Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[muen/linux.git] / drivers / clk / mmp / clk-of-mmp2.c
1 /*
2  * mmp2 clock framework source file
3  *
4  * Copyright (C) 2012 Marvell
5  * Chao Xie <xiechao.mail@gmail.com>
6  *
7  * This file is licensed under the terms of the GNU General Public
8  * License version 2. This program is licensed "as is" without any
9  * warranty of any kind, whether express or implied.
10  */
11
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/spinlock.h>
15 #include <linux/io.h>
16 #include <linux/delay.h>
17 #include <linux/err.h>
18 #include <linux/of_address.h>
19
20 #include <dt-bindings/clock/marvell,mmp2.h>
21
22 #include "clk.h"
23 #include "reset.h"
24
25 #define APBC_RTC        0x0
26 #define APBC_TWSI0      0x4
27 #define APBC_TWSI1      0x8
28 #define APBC_TWSI2      0xc
29 #define APBC_TWSI3      0x10
30 #define APBC_TWSI4      0x7c
31 #define APBC_TWSI5      0x80
32 #define APBC_KPC        0x18
33 #define APBC_TIMER      0x24
34 #define APBC_UART0      0x2c
35 #define APBC_UART1      0x30
36 #define APBC_UART2      0x34
37 #define APBC_UART3      0x88
38 #define APBC_GPIO       0x38
39 #define APBC_PWM0       0x3c
40 #define APBC_PWM1       0x40
41 #define APBC_PWM2       0x44
42 #define APBC_PWM3       0x48
43 #define APBC_SSP0       0x50
44 #define APBC_SSP1       0x54
45 #define APBC_SSP2       0x58
46 #define APBC_SSP3       0x5c
47 #define APMU_SDH0       0x54
48 #define APMU_SDH1       0x58
49 #define APMU_SDH2       0xe8
50 #define APMU_SDH3       0xec
51 #define APMU_USB        0x5c
52 #define APMU_DISP0      0x4c
53 #define APMU_DISP1      0x110
54 #define APMU_CCIC0      0x50
55 #define APMU_CCIC1      0xf4
56 #define APMU_SP         0x68
57 #define MPMU_UART_PLL   0x14
58
59 struct mmp2_clk_unit {
60         struct mmp_clk_unit unit;
61         void __iomem *mpmu_base;
62         void __iomem *apmu_base;
63         void __iomem *apbc_base;
64 };
65
66 static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
67         {MMP2_CLK_CLK32, "clk32", NULL, 0, 32768},
68         {MMP2_CLK_VCTCXO, "vctcxo", NULL, 0, 26000000},
69         {MMP2_CLK_PLL1, "pll1", NULL, 0, 800000000},
70         {MMP2_CLK_PLL2, "pll2", NULL, 0, 960000000},
71         {MMP2_CLK_USB_PLL, "usb_pll", NULL, 0, 480000000},
72 };
73
74 static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
75         {MMP2_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0},
76         {MMP2_CLK_PLL1_4, "pll1_4", "pll1_2", 1, 2, 0},
77         {MMP2_CLK_PLL1_8, "pll1_8", "pll1_4", 1, 2, 0},
78         {MMP2_CLK_PLL1_16, "pll1_16", "pll1_8", 1, 2, 0},
79         {MMP2_CLK_PLL1_20, "pll1_20", "pll1_4", 1, 5, 0},
80         {MMP2_CLK_PLL1_3, "pll1_3", "pll1", 1, 3, 0},
81         {MMP2_CLK_PLL1_6, "pll1_6", "pll1_3", 1, 2, 0},
82         {MMP2_CLK_PLL1_12, "pll1_12", "pll1_6", 1, 2, 0},
83         {MMP2_CLK_PLL2_2, "pll2_2", "pll2", 1, 2, 0},
84         {MMP2_CLK_PLL2_4, "pll2_4", "pll2_2", 1, 2, 0},
85         {MMP2_CLK_PLL2_8, "pll2_8", "pll2_4", 1, 2, 0},
86         {MMP2_CLK_PLL2_16, "pll2_16", "pll2_8", 1, 2, 0},
87         {MMP2_CLK_PLL2_3, "pll2_3", "pll2", 1, 3, 0},
88         {MMP2_CLK_PLL2_6, "pll2_6", "pll2_3", 1, 2, 0},
89         {MMP2_CLK_PLL2_12, "pll2_12", "pll2_6", 1, 2, 0},
90         {MMP2_CLK_VCTCXO_2, "vctcxo_2", "vctcxo", 1, 2, 0},
91         {MMP2_CLK_VCTCXO_4, "vctcxo_4", "vctcxo_2", 1, 2, 0},
92 };
93
94 static struct mmp_clk_factor_masks uart_factor_masks = {
95         .factor = 2,
96         .num_mask = 0x1fff,
97         .den_mask = 0x1fff,
98         .num_shift = 16,
99         .den_shift = 0,
100 };
101
102 static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
103         {.num = 8125, .den = 1536},     /*14.745MHZ */
104         {.num = 3521, .den = 689},      /*19.23MHZ */
105 };
106
107 static void mmp2_pll_init(struct mmp2_clk_unit *pxa_unit)
108 {
109         struct clk *clk;
110         struct mmp_clk_unit *unit = &pxa_unit->unit;
111
112         mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
113                                         ARRAY_SIZE(fixed_rate_clks));
114
115         mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
116                                         ARRAY_SIZE(fixed_factor_clks));
117
118         clk = mmp_clk_register_factor("uart_pll", "pll1_4",
119                                 CLK_SET_RATE_PARENT,
120                                 pxa_unit->mpmu_base + MPMU_UART_PLL,
121                                 &uart_factor_masks, uart_factor_tbl,
122                                 ARRAY_SIZE(uart_factor_tbl), NULL);
123         mmp_clk_add(unit, MMP2_CLK_UART_PLL, clk);
124 }
125
126 static DEFINE_SPINLOCK(uart0_lock);
127 static DEFINE_SPINLOCK(uart1_lock);
128 static DEFINE_SPINLOCK(uart2_lock);
129 static const char *uart_parent_names[] = {"uart_pll", "vctcxo"};
130
131 static DEFINE_SPINLOCK(ssp0_lock);
132 static DEFINE_SPINLOCK(ssp1_lock);
133 static DEFINE_SPINLOCK(ssp2_lock);
134 static DEFINE_SPINLOCK(ssp3_lock);
135 static const char *ssp_parent_names[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"};
136
137 static DEFINE_SPINLOCK(timer_lock);
138 static const char *timer_parent_names[] = {"clk32", "vctcxo_2", "vctcxo_4", "vctcxo"};
139
140 static DEFINE_SPINLOCK(reset_lock);
141
142 static struct mmp_param_mux_clk apbc_mux_clks[] = {
143         {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
144         {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
145         {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2, 4, 3, 0, &uart2_lock},
146         {0, "uart3_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART3, 4, 3, 0, &uart2_lock},
147         {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4, 3, 0, &ssp0_lock},
148         {0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4, 3, 0, &ssp1_lock},
149         {0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP2, 4, 3, 0, &ssp2_lock},
150         {0, "ssp3_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP3, 4, 3, 0, &ssp3_lock},
151         {0, "timer_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TIMER, 4, 3, 0, &timer_lock},
152 };
153
154 static struct mmp_param_gate_clk apbc_gate_clks[] = {
155         {MMP2_CLK_TWSI0, "twsi0_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x7, 0x3, 0x0, 0, &reset_lock},
156         {MMP2_CLK_TWSI1, "twsi1_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI1, 0x7, 0x3, 0x0, 0, &reset_lock},
157         {MMP2_CLK_TWSI2, "twsi2_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI2, 0x7, 0x3, 0x0, 0, &reset_lock},
158         {MMP2_CLK_TWSI3, "twsi3_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI3, 0x7, 0x3, 0x0, 0, &reset_lock},
159         {MMP2_CLK_TWSI4, "twsi4_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI4, 0x7, 0x3, 0x0, 0, &reset_lock},
160         {MMP2_CLK_TWSI5, "twsi5_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI5, 0x7, 0x3, 0x0, 0, &reset_lock},
161         {MMP2_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x7, 0x3, 0x0, 0, &reset_lock},
162         {MMP2_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x7, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock},
163         {MMP2_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x87, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock},
164         {MMP2_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x7, 0x3, 0x0, 0, &reset_lock},
165         {MMP2_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x7, 0x3, 0x0, 0, &reset_lock},
166         {MMP2_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x7, 0x3, 0x0, 0, &reset_lock},
167         {MMP2_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x7, 0x3, 0x0, 0, &reset_lock},
168         /* The gate clocks has mux parent. */
169         {MMP2_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x7, 0x3, 0x0, 0, &uart0_lock},
170         {MMP2_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x7, 0x3, 0x0, 0, &uart1_lock},
171         {MMP2_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBC_UART2, 0x7, 0x3, 0x0, 0, &uart2_lock},
172         {MMP2_CLK_UART3, "uart3_clk", "uart3_mux", CLK_SET_RATE_PARENT, APBC_UART3, 0x7, 0x3, 0x0, 0, &uart2_lock},
173         {MMP2_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x7, 0x3, 0x0, 0, &ssp0_lock},
174         {MMP2_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x7, 0x3, 0x0, 0, &ssp1_lock},
175         {MMP2_CLK_SSP2, "ssp2_clk", "ssp2_mux", CLK_SET_RATE_PARENT, APBC_SSP2, 0x7, 0x3, 0x0, 0, &ssp2_lock},
176         {MMP2_CLK_SSP3, "ssp3_clk", "ssp3_mux", CLK_SET_RATE_PARENT, APBC_SSP3, 0x7, 0x3, 0x0, 0, &ssp3_lock},
177         {MMP2_CLK_TIMER, "timer_clk", "timer_mux", CLK_SET_RATE_PARENT, APBC_TIMER, 0x7, 0x3, 0x0, 0, &timer_lock},
178 };
179
180 static void mmp2_apb_periph_clk_init(struct mmp2_clk_unit *pxa_unit)
181 {
182         struct mmp_clk_unit *unit = &pxa_unit->unit;
183
184         mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base,
185                                 ARRAY_SIZE(apbc_mux_clks));
186
187         mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base,
188                                 ARRAY_SIZE(apbc_gate_clks));
189 }
190
191 static DEFINE_SPINLOCK(sdh_lock);
192 static const char *sdh_parent_names[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
193 static struct mmp_clk_mix_config sdh_mix_config = {
194         .reg_info = DEFINE_MIX_REG_INFO(4, 10, 2, 8, 32),
195 };
196
197 static DEFINE_SPINLOCK(usb_lock);
198
199 static DEFINE_SPINLOCK(disp0_lock);
200 static DEFINE_SPINLOCK(disp1_lock);
201 static const char *disp_parent_names[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
202
203 static DEFINE_SPINLOCK(ccic0_lock);
204 static DEFINE_SPINLOCK(ccic1_lock);
205 static const char *ccic_parent_names[] = {"pll1_2", "pll1_16", "vctcxo"};
206 static struct mmp_clk_mix_config ccic0_mix_config = {
207         .reg_info = DEFINE_MIX_REG_INFO(4, 17, 2, 6, 32),
208 };
209 static struct mmp_clk_mix_config ccic1_mix_config = {
210         .reg_info = DEFINE_MIX_REG_INFO(4, 16, 2, 6, 32),
211 };
212
213 static DEFINE_SPINLOCK(sp_lock);
214
215 static struct mmp_param_mux_clk apmu_mux_clks[] = {
216         {MMP2_CLK_DISP0_MUX, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 2, 0, &disp0_lock},
217         {MMP2_CLK_DISP1_MUX, "disp1_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP1, 6, 2, 0, &disp1_lock},
218 };
219
220 static struct mmp_param_div_clk apmu_div_clks[] = {
221         {0, "disp0_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 8, 4, 0, &disp0_lock},
222         {0, "disp0_sphy_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 15, 5, 0, &disp0_lock},
223         {0, "disp1_div", "disp1_mux", CLK_SET_RATE_PARENT, APMU_DISP1, 8, 4, 0, &disp1_lock},
224         {0, "ccic0_sphy_div", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
225         {0, "ccic1_sphy_div", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 10, 5, 0, &ccic1_lock},
226 };
227
228 static struct mmp_param_gate_clk apmu_gate_clks[] = {
229         {MMP2_CLK_USB, "usb_clk", "usb_pll", 0, APMU_USB, 0x9, 0x9, 0x0, 0, &usb_lock},
230         /* The gate clocks has mux parent. */
231         {MMP2_CLK_SDH0, "sdh0_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
232         {MMP2_CLK_SDH1, "sdh1_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
233         {MMP2_CLK_SDH2, "sdh2_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH2, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
234         {MMP2_CLK_SDH3, "sdh3_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH3, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
235         {MMP2_CLK_DISP0, "disp0_clk", "disp0_div", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1b, 0x1b, 0x0, 0, &disp0_lock},
236         {MMP2_CLK_DISP0_SPHY, "disp0_sphy_clk", "disp0_sphy_div", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1024, 0x1024, 0x0, 0, &disp0_lock},
237         {MMP2_CLK_DISP1, "disp1_clk", "disp1_div", CLK_SET_RATE_PARENT, APMU_DISP1, 0x1b, 0x1b, 0x0, 0, &disp1_lock},
238         {MMP2_CLK_CCIC_ARBITER, "ccic_arbiter", "vctcxo", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1800, 0x1800, 0x0, 0, &ccic0_lock},
239         {MMP2_CLK_CCIC0, "ccic0_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock},
240         {MMP2_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock},
241         {MMP2_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, 0x300, 0x0, 0, &ccic0_lock},
242         {MMP2_CLK_CCIC1, "ccic1_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x1b, 0x1b, 0x0, 0, &ccic1_lock},
243         {MMP2_CLK_CCIC1_PHY, "ccic1_phy_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x24, 0x24, 0x0, 0, &ccic1_lock},
244         {MMP2_CLK_CCIC1_SPHY, "ccic1_sphy_clk", "ccic1_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x300, 0x300, 0x0, 0, &ccic1_lock},
245         {MMP2_CLK_SP, "sp_clk", NULL, CLK_SET_RATE_PARENT, APMU_SP, 0x1b, 0x1b, 0x0, 0, &sp_lock},
246 };
247
248 static void mmp2_axi_periph_clk_init(struct mmp2_clk_unit *pxa_unit)
249 {
250         struct clk *clk;
251         struct mmp_clk_unit *unit = &pxa_unit->unit;
252
253         sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_SDH0;
254         clk = mmp_clk_register_mix(NULL, "sdh_mix_clk", sdh_parent_names,
255                                         ARRAY_SIZE(sdh_parent_names),
256                                         CLK_SET_RATE_PARENT,
257                                         &sdh_mix_config, &sdh_lock);
258
259         ccic0_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_CCIC0;
260         clk = mmp_clk_register_mix(NULL, "ccic0_mix_clk", ccic_parent_names,
261                                         ARRAY_SIZE(ccic_parent_names),
262                                         CLK_SET_RATE_PARENT,
263                                         &ccic0_mix_config, &ccic0_lock);
264         mmp_clk_add(unit, MMP2_CLK_CCIC0_MIX, clk);
265
266         ccic1_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_CCIC1;
267         clk = mmp_clk_register_mix(NULL, "ccic1_mix_clk", ccic_parent_names,
268                                         ARRAY_SIZE(ccic_parent_names),
269                                         CLK_SET_RATE_PARENT,
270                                         &ccic1_mix_config, &ccic1_lock);
271         mmp_clk_add(unit, MMP2_CLK_CCIC1_MIX, clk);
272
273         mmp_register_mux_clks(unit, apmu_mux_clks, pxa_unit->apmu_base,
274                                 ARRAY_SIZE(apmu_mux_clks));
275
276         mmp_register_div_clks(unit, apmu_div_clks, pxa_unit->apmu_base,
277                                 ARRAY_SIZE(apmu_div_clks));
278
279         mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base,
280                                 ARRAY_SIZE(apmu_gate_clks));
281 }
282
283 static void mmp2_clk_reset_init(struct device_node *np,
284                                 struct mmp2_clk_unit *pxa_unit)
285 {
286         struct mmp_clk_reset_cell *cells;
287         int i, nr_resets;
288
289         nr_resets = ARRAY_SIZE(apbc_gate_clks);
290         cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL);
291         if (!cells)
292                 return;
293
294         for (i = 0; i < nr_resets; i++) {
295                 cells[i].clk_id = apbc_gate_clks[i].id;
296                 cells[i].reg = pxa_unit->apbc_base + apbc_gate_clks[i].offset;
297                 cells[i].flags = 0;
298                 cells[i].lock = apbc_gate_clks[i].lock;
299                 cells[i].bits = 0x4;
300         }
301
302         mmp_clk_reset_register(np, cells, nr_resets);
303 }
304
305 static void __init mmp2_clk_init(struct device_node *np)
306 {
307         struct mmp2_clk_unit *pxa_unit;
308
309         pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
310         if (!pxa_unit)
311                 return;
312
313         pxa_unit->mpmu_base = of_iomap(np, 0);
314         if (!pxa_unit->mpmu_base) {
315                 pr_err("failed to map mpmu registers\n");
316                 goto free_memory;
317         }
318
319         pxa_unit->apmu_base = of_iomap(np, 1);
320         if (!pxa_unit->apmu_base) {
321                 pr_err("failed to map apmu registers\n");
322                 goto unmap_mpmu_region;
323         }
324
325         pxa_unit->apbc_base = of_iomap(np, 2);
326         if (!pxa_unit->apbc_base) {
327                 pr_err("failed to map apbc registers\n");
328                 goto unmap_apmu_region;
329         }
330
331         mmp_clk_init(np, &pxa_unit->unit, MMP2_NR_CLKS);
332
333         mmp2_pll_init(pxa_unit);
334
335         mmp2_apb_periph_clk_init(pxa_unit);
336
337         mmp2_axi_periph_clk_init(pxa_unit);
338
339         mmp2_clk_reset_init(np, pxa_unit);
340
341         return;
342
343 unmap_apmu_region:
344         iounmap(pxa_unit->apmu_base);
345 unmap_mpmu_region:
346         iounmap(pxa_unit->mpmu_base);
347 free_memory:
348         kfree(pxa_unit);
349 }
350
351 CLK_OF_DECLARE(mmp2_clk, "marvell,mmp2-clock", mmp2_clk_init);