cpufreq: intel_pstate: constify attribute_group structures
[muen/linux.git] / drivers / cpufreq / intel_pstate.c
1 /*
2  * intel_pstate.c: Native P state management for Intel processors
3  *
4  * (C) Copyright 2012 Intel Corporation
5  * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License
9  * as published by the Free Software Foundation; version 2
10  * of the License.
11  */
12
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
15 #include <linux/kernel.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/module.h>
18 #include <linux/ktime.h>
19 #include <linux/hrtimer.h>
20 #include <linux/tick.h>
21 #include <linux/slab.h>
22 #include <linux/sched/cpufreq.h>
23 #include <linux/list.h>
24 #include <linux/cpu.h>
25 #include <linux/cpufreq.h>
26 #include <linux/sysfs.h>
27 #include <linux/types.h>
28 #include <linux/fs.h>
29 #include <linux/debugfs.h>
30 #include <linux/acpi.h>
31 #include <linux/vmalloc.h>
32 #include <trace/events/power.h>
33
34 #include <asm/div64.h>
35 #include <asm/msr.h>
36 #include <asm/cpu_device_id.h>
37 #include <asm/cpufeature.h>
38 #include <asm/intel-family.h>
39
40 #define INTEL_PSTATE_DEFAULT_SAMPLING_INTERVAL  (10 * NSEC_PER_MSEC)
41 #define INTEL_PSTATE_HWP_SAMPLING_INTERVAL      (50 * NSEC_PER_MSEC)
42
43 #define INTEL_CPUFREQ_TRANSITION_LATENCY        20000
44 #define INTEL_CPUFREQ_TRANSITION_DELAY          500
45
46 #ifdef CONFIG_ACPI
47 #include <acpi/processor.h>
48 #include <acpi/cppc_acpi.h>
49 #endif
50
51 #define FRAC_BITS 8
52 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
53 #define fp_toint(X) ((X) >> FRAC_BITS)
54
55 #define EXT_BITS 6
56 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
57 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
58 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
59
60 static inline int32_t mul_fp(int32_t x, int32_t y)
61 {
62         return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
63 }
64
65 static inline int32_t div_fp(s64 x, s64 y)
66 {
67         return div64_s64((int64_t)x << FRAC_BITS, y);
68 }
69
70 static inline int ceiling_fp(int32_t x)
71 {
72         int mask, ret;
73
74         ret = fp_toint(x);
75         mask = (1 << FRAC_BITS) - 1;
76         if (x & mask)
77                 ret += 1;
78         return ret;
79 }
80
81 static inline int32_t percent_fp(int percent)
82 {
83         return div_fp(percent, 100);
84 }
85
86 static inline u64 mul_ext_fp(u64 x, u64 y)
87 {
88         return (x * y) >> EXT_FRAC_BITS;
89 }
90
91 static inline u64 div_ext_fp(u64 x, u64 y)
92 {
93         return div64_u64(x << EXT_FRAC_BITS, y);
94 }
95
96 static inline int32_t percent_ext_fp(int percent)
97 {
98         return div_ext_fp(percent, 100);
99 }
100
101 /**
102  * struct sample -      Store performance sample
103  * @core_avg_perf:      Ratio of APERF/MPERF which is the actual average
104  *                      performance during last sample period
105  * @busy_scaled:        Scaled busy value which is used to calculate next
106  *                      P state. This can be different than core_avg_perf
107  *                      to account for cpu idle period
108  * @aperf:              Difference of actual performance frequency clock count
109  *                      read from APERF MSR between last and current sample
110  * @mperf:              Difference of maximum performance frequency clock count
111  *                      read from MPERF MSR between last and current sample
112  * @tsc:                Difference of time stamp counter between last and
113  *                      current sample
114  * @time:               Current time from scheduler
115  *
116  * This structure is used in the cpudata structure to store performance sample
117  * data for choosing next P State.
118  */
119 struct sample {
120         int32_t core_avg_perf;
121         int32_t busy_scaled;
122         u64 aperf;
123         u64 mperf;
124         u64 tsc;
125         u64 time;
126 };
127
128 /**
129  * struct pstate_data - Store P state data
130  * @current_pstate:     Current requested P state
131  * @min_pstate:         Min P state possible for this platform
132  * @max_pstate:         Max P state possible for this platform
133  * @max_pstate_physical:This is physical Max P state for a processor
134  *                      This can be higher than the max_pstate which can
135  *                      be limited by platform thermal design power limits
136  * @scaling:            Scaling factor to  convert frequency to cpufreq
137  *                      frequency units
138  * @turbo_pstate:       Max Turbo P state possible for this platform
139  * @max_freq:           @max_pstate frequency in cpufreq units
140  * @turbo_freq:         @turbo_pstate frequency in cpufreq units
141  *
142  * Stores the per cpu model P state limits and current P state.
143  */
144 struct pstate_data {
145         int     current_pstate;
146         int     min_pstate;
147         int     max_pstate;
148         int     max_pstate_physical;
149         int     scaling;
150         int     turbo_pstate;
151         unsigned int max_freq;
152         unsigned int turbo_freq;
153 };
154
155 /**
156  * struct vid_data -    Stores voltage information data
157  * @min:                VID data for this platform corresponding to
158  *                      the lowest P state
159  * @max:                VID data corresponding to the highest P State.
160  * @turbo:              VID data for turbo P state
161  * @ratio:              Ratio of (vid max - vid min) /
162  *                      (max P state - Min P State)
163  *
164  * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
165  * This data is used in Atom platforms, where in addition to target P state,
166  * the voltage data needs to be specified to select next P State.
167  */
168 struct vid_data {
169         int min;
170         int max;
171         int turbo;
172         int32_t ratio;
173 };
174
175 /**
176  * struct _pid -        Stores PID data
177  * @setpoint:           Target set point for busyness or performance
178  * @integral:           Storage for accumulated error values
179  * @p_gain:             PID proportional gain
180  * @i_gain:             PID integral gain
181  * @d_gain:             PID derivative gain
182  * @deadband:           PID deadband
183  * @last_err:           Last error storage for integral part of PID calculation
184  *
185  * Stores PID coefficients and last error for PID controller.
186  */
187 struct _pid {
188         int setpoint;
189         int32_t integral;
190         int32_t p_gain;
191         int32_t i_gain;
192         int32_t d_gain;
193         int deadband;
194         int32_t last_err;
195 };
196
197 /**
198  * struct global_params - Global parameters, mostly tunable via sysfs.
199  * @no_turbo:           Whether or not to use turbo P-states.
200  * @turbo_disabled:     Whethet or not turbo P-states are available at all,
201  *                      based on the MSR_IA32_MISC_ENABLE value and whether or
202  *                      not the maximum reported turbo P-state is different from
203  *                      the maximum reported non-turbo one.
204  * @min_perf_pct:       Minimum capacity limit in percent of the maximum turbo
205  *                      P-state capacity.
206  * @max_perf_pct:       Maximum capacity limit in percent of the maximum turbo
207  *                      P-state capacity.
208  */
209 struct global_params {
210         bool no_turbo;
211         bool turbo_disabled;
212         int max_perf_pct;
213         int min_perf_pct;
214 };
215
216 /**
217  * struct cpudata -     Per CPU instance data storage
218  * @cpu:                CPU number for this instance data
219  * @policy:             CPUFreq policy value
220  * @update_util:        CPUFreq utility callback information
221  * @update_util_set:    CPUFreq utility callback is set
222  * @iowait_boost:       iowait-related boost fraction
223  * @last_update:        Time of the last update.
224  * @pstate:             Stores P state limits for this CPU
225  * @vid:                Stores VID limits for this CPU
226  * @pid:                Stores PID parameters for this CPU
227  * @last_sample_time:   Last Sample time
228  * @prev_aperf:         Last APERF value read from APERF MSR
229  * @prev_mperf:         Last MPERF value read from MPERF MSR
230  * @prev_tsc:           Last timestamp counter (TSC) value
231  * @prev_cummulative_iowait: IO Wait time difference from last and
232  *                      current sample
233  * @sample:             Storage for storing last Sample data
234  * @min_perf:           Minimum capacity limit as a fraction of the maximum
235  *                      turbo P-state capacity.
236  * @max_perf:           Maximum capacity limit as a fraction of the maximum
237  *                      turbo P-state capacity.
238  * @acpi_perf_data:     Stores ACPI perf information read from _PSS
239  * @valid_pss_table:    Set to true for valid ACPI _PSS entries found
240  * @epp_powersave:      Last saved HWP energy performance preference
241  *                      (EPP) or energy performance bias (EPB),
242  *                      when policy switched to performance
243  * @epp_policy:         Last saved policy used to set EPP/EPB
244  * @epp_default:        Power on default HWP energy performance
245  *                      preference/bias
246  * @epp_saved:          Saved EPP/EPB during system suspend or CPU offline
247  *                      operation
248  *
249  * This structure stores per CPU instance data for all CPUs.
250  */
251 struct cpudata {
252         int cpu;
253
254         unsigned int policy;
255         struct update_util_data update_util;
256         bool   update_util_set;
257
258         struct pstate_data pstate;
259         struct vid_data vid;
260         struct _pid pid;
261
262         u64     last_update;
263         u64     last_sample_time;
264         u64     prev_aperf;
265         u64     prev_mperf;
266         u64     prev_tsc;
267         u64     prev_cummulative_iowait;
268         struct sample sample;
269         int32_t min_perf;
270         int32_t max_perf;
271 #ifdef CONFIG_ACPI
272         struct acpi_processor_performance acpi_perf_data;
273         bool valid_pss_table;
274 #endif
275         unsigned int iowait_boost;
276         s16 epp_powersave;
277         s16 epp_policy;
278         s16 epp_default;
279         s16 epp_saved;
280 };
281
282 static struct cpudata **all_cpu_data;
283
284 /**
285  * struct pstate_adjust_policy - Stores static PID configuration data
286  * @sample_rate_ms:     PID calculation sample rate in ms
287  * @sample_rate_ns:     Sample rate calculation in ns
288  * @deadband:           PID deadband
289  * @setpoint:           PID Setpoint
290  * @p_gain_pct:         PID proportional gain
291  * @i_gain_pct:         PID integral gain
292  * @d_gain_pct:         PID derivative gain
293  *
294  * Stores per CPU model static PID configuration data.
295  */
296 struct pstate_adjust_policy {
297         int sample_rate_ms;
298         s64 sample_rate_ns;
299         int deadband;
300         int setpoint;
301         int p_gain_pct;
302         int d_gain_pct;
303         int i_gain_pct;
304 };
305
306 /**
307  * struct pstate_funcs - Per CPU model specific callbacks
308  * @get_max:            Callback to get maximum non turbo effective P state
309  * @get_max_physical:   Callback to get maximum non turbo physical P state
310  * @get_min:            Callback to get minimum P state
311  * @get_turbo:          Callback to get turbo P state
312  * @get_scaling:        Callback to get frequency scaling factor
313  * @get_val:            Callback to convert P state to actual MSR write value
314  * @get_vid:            Callback to get VID data for Atom platforms
315  * @update_util:        Active mode utilization update callback.
316  *
317  * Core and Atom CPU models have different way to get P State limits. This
318  * structure is used to store those callbacks.
319  */
320 struct pstate_funcs {
321         int (*get_max)(void);
322         int (*get_max_physical)(void);
323         int (*get_min)(void);
324         int (*get_turbo)(void);
325         int (*get_scaling)(void);
326         u64 (*get_val)(struct cpudata*, int pstate);
327         void (*get_vid)(struct cpudata *);
328         void (*update_util)(struct update_util_data *data, u64 time,
329                             unsigned int flags);
330 };
331
332 static struct pstate_funcs pstate_funcs __read_mostly;
333 static struct pstate_adjust_policy pid_params __read_mostly = {
334         .sample_rate_ms = 10,
335         .sample_rate_ns = 10 * NSEC_PER_MSEC,
336         .deadband = 0,
337         .setpoint = 97,
338         .p_gain_pct = 20,
339         .d_gain_pct = 0,
340         .i_gain_pct = 0,
341 };
342
343 static int hwp_active __read_mostly;
344 static bool per_cpu_limits __read_mostly;
345
346 static struct cpufreq_driver *intel_pstate_driver __read_mostly;
347
348 #ifdef CONFIG_ACPI
349 static bool acpi_ppc;
350 #endif
351
352 static struct global_params global;
353
354 static DEFINE_MUTEX(intel_pstate_driver_lock);
355 static DEFINE_MUTEX(intel_pstate_limits_lock);
356
357 #ifdef CONFIG_ACPI
358
359 static bool intel_pstate_get_ppc_enable_status(void)
360 {
361         if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
362             acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
363                 return true;
364
365         return acpi_ppc;
366 }
367
368 #ifdef CONFIG_ACPI_CPPC_LIB
369
370 /* The work item is needed to avoid CPU hotplug locking issues */
371 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
372 {
373         sched_set_itmt_support();
374 }
375
376 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
377
378 static void intel_pstate_set_itmt_prio(int cpu)
379 {
380         struct cppc_perf_caps cppc_perf;
381         static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
382         int ret;
383
384         ret = cppc_get_perf_caps(cpu, &cppc_perf);
385         if (ret)
386                 return;
387
388         /*
389          * The priorities can be set regardless of whether or not
390          * sched_set_itmt_support(true) has been called and it is valid to
391          * update them at any time after it has been called.
392          */
393         sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
394
395         if (max_highest_perf <= min_highest_perf) {
396                 if (cppc_perf.highest_perf > max_highest_perf)
397                         max_highest_perf = cppc_perf.highest_perf;
398
399                 if (cppc_perf.highest_perf < min_highest_perf)
400                         min_highest_perf = cppc_perf.highest_perf;
401
402                 if (max_highest_perf > min_highest_perf) {
403                         /*
404                          * This code can be run during CPU online under the
405                          * CPU hotplug locks, so sched_set_itmt_support()
406                          * cannot be called from here.  Queue up a work item
407                          * to invoke it.
408                          */
409                         schedule_work(&sched_itmt_work);
410                 }
411         }
412 }
413 #else
414 static void intel_pstate_set_itmt_prio(int cpu)
415 {
416 }
417 #endif
418
419 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
420 {
421         struct cpudata *cpu;
422         int ret;
423         int i;
424
425         if (hwp_active) {
426                 intel_pstate_set_itmt_prio(policy->cpu);
427                 return;
428         }
429
430         if (!intel_pstate_get_ppc_enable_status())
431                 return;
432
433         cpu = all_cpu_data[policy->cpu];
434
435         ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
436                                                   policy->cpu);
437         if (ret)
438                 return;
439
440         /*
441          * Check if the control value in _PSS is for PERF_CTL MSR, which should
442          * guarantee that the states returned by it map to the states in our
443          * list directly.
444          */
445         if (cpu->acpi_perf_data.control_register.space_id !=
446                                                 ACPI_ADR_SPACE_FIXED_HARDWARE)
447                 goto err;
448
449         /*
450          * If there is only one entry _PSS, simply ignore _PSS and continue as
451          * usual without taking _PSS into account
452          */
453         if (cpu->acpi_perf_data.state_count < 2)
454                 goto err;
455
456         pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
457         for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
458                 pr_debug("     %cP%d: %u MHz, %u mW, 0x%x\n",
459                          (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
460                          (u32) cpu->acpi_perf_data.states[i].core_frequency,
461                          (u32) cpu->acpi_perf_data.states[i].power,
462                          (u32) cpu->acpi_perf_data.states[i].control);
463         }
464
465         /*
466          * The _PSS table doesn't contain whole turbo frequency range.
467          * This just contains +1 MHZ above the max non turbo frequency,
468          * with control value corresponding to max turbo ratio. But
469          * when cpufreq set policy is called, it will call with this
470          * max frequency, which will cause a reduced performance as
471          * this driver uses real max turbo frequency as the max
472          * frequency. So correct this frequency in _PSS table to
473          * correct max turbo frequency based on the turbo state.
474          * Also need to convert to MHz as _PSS freq is in MHz.
475          */
476         if (!global.turbo_disabled)
477                 cpu->acpi_perf_data.states[0].core_frequency =
478                                         policy->cpuinfo.max_freq / 1000;
479         cpu->valid_pss_table = true;
480         pr_debug("_PPC limits will be enforced\n");
481
482         return;
483
484  err:
485         cpu->valid_pss_table = false;
486         acpi_processor_unregister_performance(policy->cpu);
487 }
488
489 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
490 {
491         struct cpudata *cpu;
492
493         cpu = all_cpu_data[policy->cpu];
494         if (!cpu->valid_pss_table)
495                 return;
496
497         acpi_processor_unregister_performance(policy->cpu);
498 }
499 #else
500 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
501 {
502 }
503
504 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
505 {
506 }
507 #endif
508
509 static signed int pid_calc(struct _pid *pid, int32_t busy)
510 {
511         signed int result;
512         int32_t pterm, dterm, fp_error;
513         int32_t integral_limit;
514
515         fp_error = pid->setpoint - busy;
516
517         if (abs(fp_error) <= pid->deadband)
518                 return 0;
519
520         pterm = mul_fp(pid->p_gain, fp_error);
521
522         pid->integral += fp_error;
523
524         /*
525          * We limit the integral here so that it will never
526          * get higher than 30.  This prevents it from becoming
527          * too large an input over long periods of time and allows
528          * it to get factored out sooner.
529          *
530          * The value of 30 was chosen through experimentation.
531          */
532         integral_limit = int_tofp(30);
533         if (pid->integral > integral_limit)
534                 pid->integral = integral_limit;
535         if (pid->integral < -integral_limit)
536                 pid->integral = -integral_limit;
537
538         dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);
539         pid->last_err = fp_error;
540
541         result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;
542         result = result + (1 << (FRAC_BITS-1));
543         return (signed int)fp_toint(result);
544 }
545
546 static inline void intel_pstate_pid_reset(struct cpudata *cpu)
547 {
548         struct _pid *pid = &cpu->pid;
549
550         pid->p_gain = percent_fp(pid_params.p_gain_pct);
551         pid->d_gain = percent_fp(pid_params.d_gain_pct);
552         pid->i_gain = percent_fp(pid_params.i_gain_pct);
553         pid->setpoint = int_tofp(pid_params.setpoint);
554         pid->last_err  = pid->setpoint - int_tofp(100);
555         pid->deadband  = int_tofp(pid_params.deadband);
556         pid->integral  = 0;
557 }
558
559 static inline void update_turbo_state(void)
560 {
561         u64 misc_en;
562         struct cpudata *cpu;
563
564         cpu = all_cpu_data[0];
565         rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
566         global.turbo_disabled =
567                 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
568                  cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
569 }
570
571 static int min_perf_pct_min(void)
572 {
573         struct cpudata *cpu = all_cpu_data[0];
574         int turbo_pstate = cpu->pstate.turbo_pstate;
575
576         return turbo_pstate ?
577                 DIV_ROUND_UP(cpu->pstate.min_pstate * 100, turbo_pstate) : 0;
578 }
579
580 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
581 {
582         u64 epb;
583         int ret;
584
585         if (!static_cpu_has(X86_FEATURE_EPB))
586                 return -ENXIO;
587
588         ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
589         if (ret)
590                 return (s16)ret;
591
592         return (s16)(epb & 0x0f);
593 }
594
595 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
596 {
597         s16 epp;
598
599         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
600                 /*
601                  * When hwp_req_data is 0, means that caller didn't read
602                  * MSR_HWP_REQUEST, so need to read and get EPP.
603                  */
604                 if (!hwp_req_data) {
605                         epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
606                                             &hwp_req_data);
607                         if (epp)
608                                 return epp;
609                 }
610                 epp = (hwp_req_data >> 24) & 0xff;
611         } else {
612                 /* When there is no EPP present, HWP uses EPB settings */
613                 epp = intel_pstate_get_epb(cpu_data);
614         }
615
616         return epp;
617 }
618
619 static int intel_pstate_set_epb(int cpu, s16 pref)
620 {
621         u64 epb;
622         int ret;
623
624         if (!static_cpu_has(X86_FEATURE_EPB))
625                 return -ENXIO;
626
627         ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
628         if (ret)
629                 return ret;
630
631         epb = (epb & ~0x0f) | pref;
632         wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
633
634         return 0;
635 }
636
637 /*
638  * EPP/EPB display strings corresponding to EPP index in the
639  * energy_perf_strings[]
640  *      index           String
641  *-------------------------------------
642  *      0               default
643  *      1               performance
644  *      2               balance_performance
645  *      3               balance_power
646  *      4               power
647  */
648 static const char * const energy_perf_strings[] = {
649         "default",
650         "performance",
651         "balance_performance",
652         "balance_power",
653         "power",
654         NULL
655 };
656
657 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
658 {
659         s16 epp;
660         int index = -EINVAL;
661
662         epp = intel_pstate_get_epp(cpu_data, 0);
663         if (epp < 0)
664                 return epp;
665
666         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
667                 /*
668                  * Range:
669                  *      0x00-0x3F       :       Performance
670                  *      0x40-0x7F       :       Balance performance
671                  *      0x80-0xBF       :       Balance power
672                  *      0xC0-0xFF       :       Power
673                  * The EPP is a 8 bit value, but our ranges restrict the
674                  * value which can be set. Here only using top two bits
675                  * effectively.
676                  */
677                 index = (epp >> 6) + 1;
678         } else if (static_cpu_has(X86_FEATURE_EPB)) {
679                 /*
680                  * Range:
681                  *      0x00-0x03       :       Performance
682                  *      0x04-0x07       :       Balance performance
683                  *      0x08-0x0B       :       Balance power
684                  *      0x0C-0x0F       :       Power
685                  * The EPB is a 4 bit value, but our ranges restrict the
686                  * value which can be set. Here only using top two bits
687                  * effectively.
688                  */
689                 index = (epp >> 2) + 1;
690         }
691
692         return index;
693 }
694
695 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
696                                               int pref_index)
697 {
698         int epp = -EINVAL;
699         int ret;
700
701         if (!pref_index)
702                 epp = cpu_data->epp_default;
703
704         mutex_lock(&intel_pstate_limits_lock);
705
706         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
707                 u64 value;
708
709                 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value);
710                 if (ret)
711                         goto return_pref;
712
713                 value &= ~GENMASK_ULL(31, 24);
714
715                 /*
716                  * If epp is not default, convert from index into
717                  * energy_perf_strings to epp value, by shifting 6
718                  * bits left to use only top two bits in epp.
719                  * The resultant epp need to shifted by 24 bits to
720                  * epp position in MSR_HWP_REQUEST.
721                  */
722                 if (epp == -EINVAL)
723                         epp = (pref_index - 1) << 6;
724
725                 value |= (u64)epp << 24;
726                 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
727         } else {
728                 if (epp == -EINVAL)
729                         epp = (pref_index - 1) << 2;
730                 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
731         }
732 return_pref:
733         mutex_unlock(&intel_pstate_limits_lock);
734
735         return ret;
736 }
737
738 static ssize_t show_energy_performance_available_preferences(
739                                 struct cpufreq_policy *policy, char *buf)
740 {
741         int i = 0;
742         int ret = 0;
743
744         while (energy_perf_strings[i] != NULL)
745                 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
746
747         ret += sprintf(&buf[ret], "\n");
748
749         return ret;
750 }
751
752 cpufreq_freq_attr_ro(energy_performance_available_preferences);
753
754 static ssize_t store_energy_performance_preference(
755                 struct cpufreq_policy *policy, const char *buf, size_t count)
756 {
757         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
758         char str_preference[21];
759         int ret, i = 0;
760
761         ret = sscanf(buf, "%20s", str_preference);
762         if (ret != 1)
763                 return -EINVAL;
764
765         while (energy_perf_strings[i] != NULL) {
766                 if (!strcmp(str_preference, energy_perf_strings[i])) {
767                         intel_pstate_set_energy_pref_index(cpu_data, i);
768                         return count;
769                 }
770                 ++i;
771         }
772
773         return -EINVAL;
774 }
775
776 static ssize_t show_energy_performance_preference(
777                                 struct cpufreq_policy *policy, char *buf)
778 {
779         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
780         int preference;
781
782         preference = intel_pstate_get_energy_pref_index(cpu_data);
783         if (preference < 0)
784                 return preference;
785
786         return  sprintf(buf, "%s\n", energy_perf_strings[preference]);
787 }
788
789 cpufreq_freq_attr_rw(energy_performance_preference);
790
791 static struct freq_attr *hwp_cpufreq_attrs[] = {
792         &energy_performance_preference,
793         &energy_performance_available_preferences,
794         NULL,
795 };
796
797 static void intel_pstate_hwp_set(unsigned int cpu)
798 {
799         struct cpudata *cpu_data = all_cpu_data[cpu];
800         int min, hw_min, max, hw_max;
801         u64 value, cap;
802         s16 epp;
803
804         rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
805         hw_min = HWP_LOWEST_PERF(cap);
806         if (global.no_turbo)
807                 hw_max = HWP_GUARANTEED_PERF(cap);
808         else
809                 hw_max = HWP_HIGHEST_PERF(cap);
810
811         max = fp_ext_toint(hw_max * cpu_data->max_perf);
812         if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
813                 min = max;
814         else
815                 min = fp_ext_toint(hw_max * cpu_data->min_perf);
816
817         rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
818
819         value &= ~HWP_MIN_PERF(~0L);
820         value |= HWP_MIN_PERF(min);
821
822         value &= ~HWP_MAX_PERF(~0L);
823         value |= HWP_MAX_PERF(max);
824
825         if (cpu_data->epp_policy == cpu_data->policy)
826                 goto skip_epp;
827
828         cpu_data->epp_policy = cpu_data->policy;
829
830         if (cpu_data->epp_saved >= 0) {
831                 epp = cpu_data->epp_saved;
832                 cpu_data->epp_saved = -EINVAL;
833                 goto update_epp;
834         }
835
836         if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
837                 epp = intel_pstate_get_epp(cpu_data, value);
838                 cpu_data->epp_powersave = epp;
839                 /* If EPP read was failed, then don't try to write */
840                 if (epp < 0)
841                         goto skip_epp;
842
843                 epp = 0;
844         } else {
845                 /* skip setting EPP, when saved value is invalid */
846                 if (cpu_data->epp_powersave < 0)
847                         goto skip_epp;
848
849                 /*
850                  * No need to restore EPP when it is not zero. This
851                  * means:
852                  *  - Policy is not changed
853                  *  - user has manually changed
854                  *  - Error reading EPB
855                  */
856                 epp = intel_pstate_get_epp(cpu_data, value);
857                 if (epp)
858                         goto skip_epp;
859
860                 epp = cpu_data->epp_powersave;
861         }
862 update_epp:
863         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
864                 value &= ~GENMASK_ULL(31, 24);
865                 value |= (u64)epp << 24;
866         } else {
867                 intel_pstate_set_epb(cpu, epp);
868         }
869 skip_epp:
870         wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
871 }
872
873 static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
874 {
875         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
876
877         if (!hwp_active)
878                 return 0;
879
880         cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
881
882         return 0;
883 }
884
885 static int intel_pstate_resume(struct cpufreq_policy *policy)
886 {
887         if (!hwp_active)
888                 return 0;
889
890         mutex_lock(&intel_pstate_limits_lock);
891
892         all_cpu_data[policy->cpu]->epp_policy = 0;
893         intel_pstate_hwp_set(policy->cpu);
894
895         mutex_unlock(&intel_pstate_limits_lock);
896
897         return 0;
898 }
899
900 static void intel_pstate_update_policies(void)
901 {
902         int cpu;
903
904         for_each_possible_cpu(cpu)
905                 cpufreq_update_policy(cpu);
906 }
907
908 /************************** debugfs begin ************************/
909 static int pid_param_set(void *data, u64 val)
910 {
911         unsigned int cpu;
912
913         *(u32 *)data = val;
914         pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC;
915         for_each_possible_cpu(cpu)
916                 if (all_cpu_data[cpu])
917                         intel_pstate_pid_reset(all_cpu_data[cpu]);
918
919         return 0;
920 }
921
922 static int pid_param_get(void *data, u64 *val)
923 {
924         *val = *(u32 *)data;
925         return 0;
926 }
927 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n");
928
929 static struct dentry *debugfs_parent;
930
931 struct pid_param {
932         char *name;
933         void *value;
934         struct dentry *dentry;
935 };
936
937 static struct pid_param pid_files[] = {
938         {"sample_rate_ms", &pid_params.sample_rate_ms, },
939         {"d_gain_pct", &pid_params.d_gain_pct, },
940         {"i_gain_pct", &pid_params.i_gain_pct, },
941         {"deadband", &pid_params.deadband, },
942         {"setpoint", &pid_params.setpoint, },
943         {"p_gain_pct", &pid_params.p_gain_pct, },
944         {NULL, NULL, }
945 };
946
947 static void intel_pstate_debug_expose_params(void)
948 {
949         int i;
950
951         debugfs_parent = debugfs_create_dir("pstate_snb", NULL);
952         if (IS_ERR_OR_NULL(debugfs_parent))
953                 return;
954
955         for (i = 0; pid_files[i].name; i++) {
956                 struct dentry *dentry;
957
958                 dentry = debugfs_create_file(pid_files[i].name, 0660,
959                                              debugfs_parent, pid_files[i].value,
960                                              &fops_pid_param);
961                 if (!IS_ERR(dentry))
962                         pid_files[i].dentry = dentry;
963         }
964 }
965
966 static void intel_pstate_debug_hide_params(void)
967 {
968         int i;
969
970         if (IS_ERR_OR_NULL(debugfs_parent))
971                 return;
972
973         for (i = 0; pid_files[i].name; i++) {
974                 debugfs_remove(pid_files[i].dentry);
975                 pid_files[i].dentry = NULL;
976         }
977
978         debugfs_remove(debugfs_parent);
979         debugfs_parent = NULL;
980 }
981
982 /************************** debugfs end ************************/
983
984 /************************** sysfs begin ************************/
985 #define show_one(file_name, object)                                     \
986         static ssize_t show_##file_name                                 \
987         (struct kobject *kobj, struct attribute *attr, char *buf)       \
988         {                                                               \
989                 return sprintf(buf, "%u\n", global.object);             \
990         }
991
992 static ssize_t intel_pstate_show_status(char *buf);
993 static int intel_pstate_update_status(const char *buf, size_t size);
994
995 static ssize_t show_status(struct kobject *kobj,
996                            struct attribute *attr, char *buf)
997 {
998         ssize_t ret;
999
1000         mutex_lock(&intel_pstate_driver_lock);
1001         ret = intel_pstate_show_status(buf);
1002         mutex_unlock(&intel_pstate_driver_lock);
1003
1004         return ret;
1005 }
1006
1007 static ssize_t store_status(struct kobject *a, struct attribute *b,
1008                             const char *buf, size_t count)
1009 {
1010         char *p = memchr(buf, '\n', count);
1011         int ret;
1012
1013         mutex_lock(&intel_pstate_driver_lock);
1014         ret = intel_pstate_update_status(buf, p ? p - buf : count);
1015         mutex_unlock(&intel_pstate_driver_lock);
1016
1017         return ret < 0 ? ret : count;
1018 }
1019
1020 static ssize_t show_turbo_pct(struct kobject *kobj,
1021                                 struct attribute *attr, char *buf)
1022 {
1023         struct cpudata *cpu;
1024         int total, no_turbo, turbo_pct;
1025         uint32_t turbo_fp;
1026
1027         mutex_lock(&intel_pstate_driver_lock);
1028
1029         if (!intel_pstate_driver) {
1030                 mutex_unlock(&intel_pstate_driver_lock);
1031                 return -EAGAIN;
1032         }
1033
1034         cpu = all_cpu_data[0];
1035
1036         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1037         no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
1038         turbo_fp = div_fp(no_turbo, total);
1039         turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1040
1041         mutex_unlock(&intel_pstate_driver_lock);
1042
1043         return sprintf(buf, "%u\n", turbo_pct);
1044 }
1045
1046 static ssize_t show_num_pstates(struct kobject *kobj,
1047                                 struct attribute *attr, char *buf)
1048 {
1049         struct cpudata *cpu;
1050         int total;
1051
1052         mutex_lock(&intel_pstate_driver_lock);
1053
1054         if (!intel_pstate_driver) {
1055                 mutex_unlock(&intel_pstate_driver_lock);
1056                 return -EAGAIN;
1057         }
1058
1059         cpu = all_cpu_data[0];
1060         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1061
1062         mutex_unlock(&intel_pstate_driver_lock);
1063
1064         return sprintf(buf, "%u\n", total);
1065 }
1066
1067 static ssize_t show_no_turbo(struct kobject *kobj,
1068                              struct attribute *attr, char *buf)
1069 {
1070         ssize_t ret;
1071
1072         mutex_lock(&intel_pstate_driver_lock);
1073
1074         if (!intel_pstate_driver) {
1075                 mutex_unlock(&intel_pstate_driver_lock);
1076                 return -EAGAIN;
1077         }
1078
1079         update_turbo_state();
1080         if (global.turbo_disabled)
1081                 ret = sprintf(buf, "%u\n", global.turbo_disabled);
1082         else
1083                 ret = sprintf(buf, "%u\n", global.no_turbo);
1084
1085         mutex_unlock(&intel_pstate_driver_lock);
1086
1087         return ret;
1088 }
1089
1090 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
1091                               const char *buf, size_t count)
1092 {
1093         unsigned int input;
1094         int ret;
1095
1096         ret = sscanf(buf, "%u", &input);
1097         if (ret != 1)
1098                 return -EINVAL;
1099
1100         mutex_lock(&intel_pstate_driver_lock);
1101
1102         if (!intel_pstate_driver) {
1103                 mutex_unlock(&intel_pstate_driver_lock);
1104                 return -EAGAIN;
1105         }
1106
1107         mutex_lock(&intel_pstate_limits_lock);
1108
1109         update_turbo_state();
1110         if (global.turbo_disabled) {
1111                 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
1112                 mutex_unlock(&intel_pstate_limits_lock);
1113                 mutex_unlock(&intel_pstate_driver_lock);
1114                 return -EPERM;
1115         }
1116
1117         global.no_turbo = clamp_t(int, input, 0, 1);
1118
1119         if (global.no_turbo) {
1120                 struct cpudata *cpu = all_cpu_data[0];
1121                 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
1122
1123                 /* Squash the global minimum into the permitted range. */
1124                 if (global.min_perf_pct > pct)
1125                         global.min_perf_pct = pct;
1126         }
1127
1128         mutex_unlock(&intel_pstate_limits_lock);
1129
1130         intel_pstate_update_policies();
1131
1132         mutex_unlock(&intel_pstate_driver_lock);
1133
1134         return count;
1135 }
1136
1137 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
1138                                   const char *buf, size_t count)
1139 {
1140         unsigned int input;
1141         int ret;
1142
1143         ret = sscanf(buf, "%u", &input);
1144         if (ret != 1)
1145                 return -EINVAL;
1146
1147         mutex_lock(&intel_pstate_driver_lock);
1148
1149         if (!intel_pstate_driver) {
1150                 mutex_unlock(&intel_pstate_driver_lock);
1151                 return -EAGAIN;
1152         }
1153
1154         mutex_lock(&intel_pstate_limits_lock);
1155
1156         global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
1157
1158         mutex_unlock(&intel_pstate_limits_lock);
1159
1160         intel_pstate_update_policies();
1161
1162         mutex_unlock(&intel_pstate_driver_lock);
1163
1164         return count;
1165 }
1166
1167 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
1168                                   const char *buf, size_t count)
1169 {
1170         unsigned int input;
1171         int ret;
1172
1173         ret = sscanf(buf, "%u", &input);
1174         if (ret != 1)
1175                 return -EINVAL;
1176
1177         mutex_lock(&intel_pstate_driver_lock);
1178
1179         if (!intel_pstate_driver) {
1180                 mutex_unlock(&intel_pstate_driver_lock);
1181                 return -EAGAIN;
1182         }
1183
1184         mutex_lock(&intel_pstate_limits_lock);
1185
1186         global.min_perf_pct = clamp_t(int, input,
1187                                       min_perf_pct_min(), global.max_perf_pct);
1188
1189         mutex_unlock(&intel_pstate_limits_lock);
1190
1191         intel_pstate_update_policies();
1192
1193         mutex_unlock(&intel_pstate_driver_lock);
1194
1195         return count;
1196 }
1197
1198 show_one(max_perf_pct, max_perf_pct);
1199 show_one(min_perf_pct, min_perf_pct);
1200
1201 define_one_global_rw(status);
1202 define_one_global_rw(no_turbo);
1203 define_one_global_rw(max_perf_pct);
1204 define_one_global_rw(min_perf_pct);
1205 define_one_global_ro(turbo_pct);
1206 define_one_global_ro(num_pstates);
1207
1208 static struct attribute *intel_pstate_attributes[] = {
1209         &status.attr,
1210         &no_turbo.attr,
1211         &turbo_pct.attr,
1212         &num_pstates.attr,
1213         NULL
1214 };
1215
1216 static const struct attribute_group intel_pstate_attr_group = {
1217         .attrs = intel_pstate_attributes,
1218 };
1219
1220 static void __init intel_pstate_sysfs_expose_params(void)
1221 {
1222         struct kobject *intel_pstate_kobject;
1223         int rc;
1224
1225         intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1226                                                 &cpu_subsys.dev_root->kobj);
1227         if (WARN_ON(!intel_pstate_kobject))
1228                 return;
1229
1230         rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1231         if (WARN_ON(rc))
1232                 return;
1233
1234         /*
1235          * If per cpu limits are enforced there are no global limits, so
1236          * return without creating max/min_perf_pct attributes
1237          */
1238         if (per_cpu_limits)
1239                 return;
1240
1241         rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1242         WARN_ON(rc);
1243
1244         rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1245         WARN_ON(rc);
1246
1247 }
1248 /************************** sysfs end ************************/
1249
1250 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1251 {
1252         /* First disable HWP notification interrupt as we don't process them */
1253         if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
1254                 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1255
1256         wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1257         cpudata->epp_policy = 0;
1258         if (cpudata->epp_default == -EINVAL)
1259                 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1260 }
1261
1262 #define MSR_IA32_POWER_CTL_BIT_EE       19
1263
1264 /* Disable energy efficiency optimization */
1265 static void intel_pstate_disable_ee(int cpu)
1266 {
1267         u64 power_ctl;
1268         int ret;
1269
1270         ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl);
1271         if (ret)
1272                 return;
1273
1274         if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) {
1275                 pr_info("Disabling energy efficiency optimization\n");
1276                 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1277                 wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl);
1278         }
1279 }
1280
1281 static int atom_get_min_pstate(void)
1282 {
1283         u64 value;
1284
1285         rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1286         return (value >> 8) & 0x7F;
1287 }
1288
1289 static int atom_get_max_pstate(void)
1290 {
1291         u64 value;
1292
1293         rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1294         return (value >> 16) & 0x7F;
1295 }
1296
1297 static int atom_get_turbo_pstate(void)
1298 {
1299         u64 value;
1300
1301         rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1302         return value & 0x7F;
1303 }
1304
1305 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1306 {
1307         u64 val;
1308         int32_t vid_fp;
1309         u32 vid;
1310
1311         val = (u64)pstate << 8;
1312         if (global.no_turbo && !global.turbo_disabled)
1313                 val |= (u64)1 << 32;
1314
1315         vid_fp = cpudata->vid.min + mul_fp(
1316                 int_tofp(pstate - cpudata->pstate.min_pstate),
1317                 cpudata->vid.ratio);
1318
1319         vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1320         vid = ceiling_fp(vid_fp);
1321
1322         if (pstate > cpudata->pstate.max_pstate)
1323                 vid = cpudata->vid.turbo;
1324
1325         return val | vid;
1326 }
1327
1328 static int silvermont_get_scaling(void)
1329 {
1330         u64 value;
1331         int i;
1332         /* Defined in Table 35-6 from SDM (Sept 2015) */
1333         static int silvermont_freq_table[] = {
1334                 83300, 100000, 133300, 116700, 80000};
1335
1336         rdmsrl(MSR_FSB_FREQ, value);
1337         i = value & 0x7;
1338         WARN_ON(i > 4);
1339
1340         return silvermont_freq_table[i];
1341 }
1342
1343 static int airmont_get_scaling(void)
1344 {
1345         u64 value;
1346         int i;
1347         /* Defined in Table 35-10 from SDM (Sept 2015) */
1348         static int airmont_freq_table[] = {
1349                 83300, 100000, 133300, 116700, 80000,
1350                 93300, 90000, 88900, 87500};
1351
1352         rdmsrl(MSR_FSB_FREQ, value);
1353         i = value & 0xF;
1354         WARN_ON(i > 8);
1355
1356         return airmont_freq_table[i];
1357 }
1358
1359 static void atom_get_vid(struct cpudata *cpudata)
1360 {
1361         u64 value;
1362
1363         rdmsrl(MSR_ATOM_CORE_VIDS, value);
1364         cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1365         cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1366         cpudata->vid.ratio = div_fp(
1367                 cpudata->vid.max - cpudata->vid.min,
1368                 int_tofp(cpudata->pstate.max_pstate -
1369                         cpudata->pstate.min_pstate));
1370
1371         rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1372         cpudata->vid.turbo = value & 0x7f;
1373 }
1374
1375 static int core_get_min_pstate(void)
1376 {
1377         u64 value;
1378
1379         rdmsrl(MSR_PLATFORM_INFO, value);
1380         return (value >> 40) & 0xFF;
1381 }
1382
1383 static int core_get_max_pstate_physical(void)
1384 {
1385         u64 value;
1386
1387         rdmsrl(MSR_PLATFORM_INFO, value);
1388         return (value >> 8) & 0xFF;
1389 }
1390
1391 static int core_get_tdp_ratio(u64 plat_info)
1392 {
1393         /* Check how many TDP levels present */
1394         if (plat_info & 0x600000000) {
1395                 u64 tdp_ctrl;
1396                 u64 tdp_ratio;
1397                 int tdp_msr;
1398                 int err;
1399
1400                 /* Get the TDP level (0, 1, 2) to get ratios */
1401                 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1402                 if (err)
1403                         return err;
1404
1405                 /* TDP MSR are continuous starting at 0x648 */
1406                 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1407                 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1408                 if (err)
1409                         return err;
1410
1411                 /* For level 1 and 2, bits[23:16] contain the ratio */
1412                 if (tdp_ctrl & 0x03)
1413                         tdp_ratio >>= 16;
1414
1415                 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1416                 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1417
1418                 return (int)tdp_ratio;
1419         }
1420
1421         return -ENXIO;
1422 }
1423
1424 static int core_get_max_pstate(void)
1425 {
1426         u64 tar;
1427         u64 plat_info;
1428         int max_pstate;
1429         int tdp_ratio;
1430         int err;
1431
1432         rdmsrl(MSR_PLATFORM_INFO, plat_info);
1433         max_pstate = (plat_info >> 8) & 0xFF;
1434
1435         tdp_ratio = core_get_tdp_ratio(plat_info);
1436         if (tdp_ratio <= 0)
1437                 return max_pstate;
1438
1439         if (hwp_active) {
1440                 /* Turbo activation ratio is not used on HWP platforms */
1441                 return tdp_ratio;
1442         }
1443
1444         err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1445         if (!err) {
1446                 int tar_levels;
1447
1448                 /* Do some sanity checking for safety */
1449                 tar_levels = tar & 0xff;
1450                 if (tdp_ratio - 1 == tar_levels) {
1451                         max_pstate = tar_levels;
1452                         pr_debug("max_pstate=TAC %x\n", max_pstate);
1453                 }
1454         }
1455
1456         return max_pstate;
1457 }
1458
1459 static int core_get_turbo_pstate(void)
1460 {
1461         u64 value;
1462         int nont, ret;
1463
1464         rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1465         nont = core_get_max_pstate();
1466         ret = (value) & 255;
1467         if (ret <= nont)
1468                 ret = nont;
1469         return ret;
1470 }
1471
1472 static inline int core_get_scaling(void)
1473 {
1474         return 100000;
1475 }
1476
1477 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1478 {
1479         u64 val;
1480
1481         val = (u64)pstate << 8;
1482         if (global.no_turbo && !global.turbo_disabled)
1483                 val |= (u64)1 << 32;
1484
1485         return val;
1486 }
1487
1488 static int knl_get_turbo_pstate(void)
1489 {
1490         u64 value;
1491         int nont, ret;
1492
1493         rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1494         nont = core_get_max_pstate();
1495         ret = (((value) >> 8) & 0xFF);
1496         if (ret <= nont)
1497                 ret = nont;
1498         return ret;
1499 }
1500
1501 static int intel_pstate_get_base_pstate(struct cpudata *cpu)
1502 {
1503         return global.no_turbo || global.turbo_disabled ?
1504                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1505 }
1506
1507 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1508 {
1509         trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1510         cpu->pstate.current_pstate = pstate;
1511         /*
1512          * Generally, there is no guarantee that this code will always run on
1513          * the CPU being updated, so force the register update to run on the
1514          * right CPU.
1515          */
1516         wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1517                       pstate_funcs.get_val(cpu, pstate));
1518 }
1519
1520 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1521 {
1522         intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1523 }
1524
1525 static void intel_pstate_max_within_limits(struct cpudata *cpu)
1526 {
1527         int pstate;
1528
1529         update_turbo_state();
1530         pstate = intel_pstate_get_base_pstate(cpu);
1531         pstate = max(cpu->pstate.min_pstate,
1532                      fp_ext_toint(pstate * cpu->max_perf));
1533         intel_pstate_set_pstate(cpu, pstate);
1534 }
1535
1536 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1537 {
1538         cpu->pstate.min_pstate = pstate_funcs.get_min();
1539         cpu->pstate.max_pstate = pstate_funcs.get_max();
1540         cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
1541         cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
1542         cpu->pstate.scaling = pstate_funcs.get_scaling();
1543         cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1544         cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1545
1546         if (pstate_funcs.get_vid)
1547                 pstate_funcs.get_vid(cpu);
1548
1549         intel_pstate_set_min_pstate(cpu);
1550 }
1551
1552 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
1553 {
1554         struct sample *sample = &cpu->sample;
1555
1556         sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
1557 }
1558
1559 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
1560 {
1561         u64 aperf, mperf;
1562         unsigned long flags;
1563         u64 tsc;
1564
1565         local_irq_save(flags);
1566         rdmsrl(MSR_IA32_APERF, aperf);
1567         rdmsrl(MSR_IA32_MPERF, mperf);
1568         tsc = rdtsc();
1569         if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
1570                 local_irq_restore(flags);
1571                 return false;
1572         }
1573         local_irq_restore(flags);
1574
1575         cpu->last_sample_time = cpu->sample.time;
1576         cpu->sample.time = time;
1577         cpu->sample.aperf = aperf;
1578         cpu->sample.mperf = mperf;
1579         cpu->sample.tsc =  tsc;
1580         cpu->sample.aperf -= cpu->prev_aperf;
1581         cpu->sample.mperf -= cpu->prev_mperf;
1582         cpu->sample.tsc -= cpu->prev_tsc;
1583
1584         cpu->prev_aperf = aperf;
1585         cpu->prev_mperf = mperf;
1586         cpu->prev_tsc = tsc;
1587         /*
1588          * First time this function is invoked in a given cycle, all of the
1589          * previous sample data fields are equal to zero or stale and they must
1590          * be populated with meaningful numbers for things to work, so assume
1591          * that sample.time will always be reset before setting the utilization
1592          * update hook and make the caller skip the sample then.
1593          */
1594         if (cpu->last_sample_time) {
1595                 intel_pstate_calc_avg_perf(cpu);
1596                 return true;
1597         }
1598         return false;
1599 }
1600
1601 static inline int32_t get_avg_frequency(struct cpudata *cpu)
1602 {
1603         return mul_ext_fp(cpu->sample.core_avg_perf,
1604                           cpu->pstate.max_pstate_physical * cpu->pstate.scaling);
1605 }
1606
1607 static inline int32_t get_avg_pstate(struct cpudata *cpu)
1608 {
1609         return mul_ext_fp(cpu->pstate.max_pstate_physical,
1610                           cpu->sample.core_avg_perf);
1611 }
1612
1613 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu)
1614 {
1615         struct sample *sample = &cpu->sample;
1616         int32_t busy_frac, boost;
1617         int target, avg_pstate;
1618
1619         if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE)
1620                 return cpu->pstate.turbo_pstate;
1621
1622         busy_frac = div_fp(sample->mperf, sample->tsc);
1623
1624         boost = cpu->iowait_boost;
1625         cpu->iowait_boost >>= 1;
1626
1627         if (busy_frac < boost)
1628                 busy_frac = boost;
1629
1630         sample->busy_scaled = busy_frac * 100;
1631
1632         target = global.no_turbo || global.turbo_disabled ?
1633                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1634         target += target >> 2;
1635         target = mul_fp(target, busy_frac);
1636         if (target < cpu->pstate.min_pstate)
1637                 target = cpu->pstate.min_pstate;
1638
1639         /*
1640          * If the average P-state during the previous cycle was higher than the
1641          * current target, add 50% of the difference to the target to reduce
1642          * possible performance oscillations and offset possible performance
1643          * loss related to moving the workload from one CPU to another within
1644          * a package/module.
1645          */
1646         avg_pstate = get_avg_pstate(cpu);
1647         if (avg_pstate > target)
1648                 target += (avg_pstate - target) >> 1;
1649
1650         return target;
1651 }
1652
1653 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu)
1654 {
1655         int32_t perf_scaled, max_pstate, current_pstate, sample_ratio;
1656         u64 duration_ns;
1657
1658         if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE)
1659                 return cpu->pstate.turbo_pstate;
1660
1661         /*
1662          * perf_scaled is the ratio of the average P-state during the last
1663          * sampling period to the P-state requested last time (in percent).
1664          *
1665          * That measures the system's response to the previous P-state
1666          * selection.
1667          */
1668         max_pstate = cpu->pstate.max_pstate_physical;
1669         current_pstate = cpu->pstate.current_pstate;
1670         perf_scaled = mul_ext_fp(cpu->sample.core_avg_perf,
1671                                div_fp(100 * max_pstate, current_pstate));
1672
1673         /*
1674          * Since our utilization update callback will not run unless we are
1675          * in C0, check if the actual elapsed time is significantly greater (3x)
1676          * than our sample interval.  If it is, then we were idle for a long
1677          * enough period of time to adjust our performance metric.
1678          */
1679         duration_ns = cpu->sample.time - cpu->last_sample_time;
1680         if ((s64)duration_ns > pid_params.sample_rate_ns * 3) {
1681                 sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns);
1682                 perf_scaled = mul_fp(perf_scaled, sample_ratio);
1683         } else {
1684                 sample_ratio = div_fp(100 * cpu->sample.mperf, cpu->sample.tsc);
1685                 if (sample_ratio < int_tofp(1))
1686                         perf_scaled = 0;
1687         }
1688
1689         cpu->sample.busy_scaled = perf_scaled;
1690         return cpu->pstate.current_pstate - pid_calc(&cpu->pid, perf_scaled);
1691 }
1692
1693 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
1694 {
1695         int max_pstate = intel_pstate_get_base_pstate(cpu);
1696         int min_pstate;
1697
1698         min_pstate = max(cpu->pstate.min_pstate,
1699                          fp_ext_toint(max_pstate * cpu->min_perf));
1700         max_pstate = max(min_pstate, fp_ext_toint(max_pstate * cpu->max_perf));
1701         return clamp_t(int, pstate, min_pstate, max_pstate);
1702 }
1703
1704 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1705 {
1706         if (pstate == cpu->pstate.current_pstate)
1707                 return;
1708
1709         cpu->pstate.current_pstate = pstate;
1710         wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1711 }
1712
1713 static void intel_pstate_adjust_pstate(struct cpudata *cpu, int target_pstate)
1714 {
1715         int from = cpu->pstate.current_pstate;
1716         struct sample *sample;
1717
1718         update_turbo_state();
1719
1720         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1721         trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
1722         intel_pstate_update_pstate(cpu, target_pstate);
1723
1724         sample = &cpu->sample;
1725         trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
1726                 fp_toint(sample->busy_scaled),
1727                 from,
1728                 cpu->pstate.current_pstate,
1729                 sample->mperf,
1730                 sample->aperf,
1731                 sample->tsc,
1732                 get_avg_frequency(cpu),
1733                 fp_toint(cpu->iowait_boost * 100));
1734 }
1735
1736 static void intel_pstate_update_util_hwp(struct update_util_data *data,
1737                                          u64 time, unsigned int flags)
1738 {
1739         struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1740         u64 delta_ns = time - cpu->sample.time;
1741
1742         if ((s64)delta_ns >= INTEL_PSTATE_HWP_SAMPLING_INTERVAL)
1743                 intel_pstate_sample(cpu, time);
1744 }
1745
1746 static void intel_pstate_update_util_pid(struct update_util_data *data,
1747                                          u64 time, unsigned int flags)
1748 {
1749         struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1750         u64 delta_ns = time - cpu->sample.time;
1751
1752         if ((s64)delta_ns < pid_params.sample_rate_ns)
1753                 return;
1754
1755         if (intel_pstate_sample(cpu, time)) {
1756                 int target_pstate;
1757
1758                 target_pstate = get_target_pstate_use_performance(cpu);
1759                 intel_pstate_adjust_pstate(cpu, target_pstate);
1760         }
1761 }
1762
1763 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
1764                                      unsigned int flags)
1765 {
1766         struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1767         u64 delta_ns;
1768
1769         if (flags & SCHED_CPUFREQ_IOWAIT) {
1770                 cpu->iowait_boost = int_tofp(1);
1771         } else if (cpu->iowait_boost) {
1772                 /* Clear iowait_boost if the CPU may have been idle. */
1773                 delta_ns = time - cpu->last_update;
1774                 if (delta_ns > TICK_NSEC)
1775                         cpu->iowait_boost = 0;
1776         }
1777         cpu->last_update = time;
1778         delta_ns = time - cpu->sample.time;
1779         if ((s64)delta_ns < INTEL_PSTATE_DEFAULT_SAMPLING_INTERVAL)
1780                 return;
1781
1782         if (intel_pstate_sample(cpu, time)) {
1783                 int target_pstate;
1784
1785                 target_pstate = get_target_pstate_use_cpu_load(cpu);
1786                 intel_pstate_adjust_pstate(cpu, target_pstate);
1787         }
1788 }
1789
1790 static struct pstate_funcs core_funcs = {
1791         .get_max = core_get_max_pstate,
1792         .get_max_physical = core_get_max_pstate_physical,
1793         .get_min = core_get_min_pstate,
1794         .get_turbo = core_get_turbo_pstate,
1795         .get_scaling = core_get_scaling,
1796         .get_val = core_get_val,
1797         .update_util = intel_pstate_update_util_pid,
1798 };
1799
1800 static const struct pstate_funcs silvermont_funcs = {
1801         .get_max = atom_get_max_pstate,
1802         .get_max_physical = atom_get_max_pstate,
1803         .get_min = atom_get_min_pstate,
1804         .get_turbo = atom_get_turbo_pstate,
1805         .get_val = atom_get_val,
1806         .get_scaling = silvermont_get_scaling,
1807         .get_vid = atom_get_vid,
1808         .update_util = intel_pstate_update_util,
1809 };
1810
1811 static const struct pstate_funcs airmont_funcs = {
1812         .get_max = atom_get_max_pstate,
1813         .get_max_physical = atom_get_max_pstate,
1814         .get_min = atom_get_min_pstate,
1815         .get_turbo = atom_get_turbo_pstate,
1816         .get_val = atom_get_val,
1817         .get_scaling = airmont_get_scaling,
1818         .get_vid = atom_get_vid,
1819         .update_util = intel_pstate_update_util,
1820 };
1821
1822 static const struct pstate_funcs knl_funcs = {
1823         .get_max = core_get_max_pstate,
1824         .get_max_physical = core_get_max_pstate_physical,
1825         .get_min = core_get_min_pstate,
1826         .get_turbo = knl_get_turbo_pstate,
1827         .get_scaling = core_get_scaling,
1828         .get_val = core_get_val,
1829         .update_util = intel_pstate_update_util_pid,
1830 };
1831
1832 static const struct pstate_funcs bxt_funcs = {
1833         .get_max = core_get_max_pstate,
1834         .get_max_physical = core_get_max_pstate_physical,
1835         .get_min = core_get_min_pstate,
1836         .get_turbo = core_get_turbo_pstate,
1837         .get_scaling = core_get_scaling,
1838         .get_val = core_get_val,
1839         .update_util = intel_pstate_update_util,
1840 };
1841
1842 #define ICPU(model, policy) \
1843         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1844                         (unsigned long)&policy }
1845
1846 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
1847         ICPU(INTEL_FAM6_SANDYBRIDGE,            core_funcs),
1848         ICPU(INTEL_FAM6_SANDYBRIDGE_X,          core_funcs),
1849         ICPU(INTEL_FAM6_ATOM_SILVERMONT1,       silvermont_funcs),
1850         ICPU(INTEL_FAM6_IVYBRIDGE,              core_funcs),
1851         ICPU(INTEL_FAM6_HASWELL_CORE,           core_funcs),
1852         ICPU(INTEL_FAM6_BROADWELL_CORE,         core_funcs),
1853         ICPU(INTEL_FAM6_IVYBRIDGE_X,            core_funcs),
1854         ICPU(INTEL_FAM6_HASWELL_X,              core_funcs),
1855         ICPU(INTEL_FAM6_HASWELL_ULT,            core_funcs),
1856         ICPU(INTEL_FAM6_HASWELL_GT3E,           core_funcs),
1857         ICPU(INTEL_FAM6_BROADWELL_GT3E,         core_funcs),
1858         ICPU(INTEL_FAM6_ATOM_AIRMONT,           airmont_funcs),
1859         ICPU(INTEL_FAM6_SKYLAKE_MOBILE,         core_funcs),
1860         ICPU(INTEL_FAM6_BROADWELL_X,            core_funcs),
1861         ICPU(INTEL_FAM6_SKYLAKE_DESKTOP,        core_funcs),
1862         ICPU(INTEL_FAM6_BROADWELL_XEON_D,       core_funcs),
1863         ICPU(INTEL_FAM6_XEON_PHI_KNL,           knl_funcs),
1864         ICPU(INTEL_FAM6_XEON_PHI_KNM,           knl_funcs),
1865         ICPU(INTEL_FAM6_ATOM_GOLDMONT,          bxt_funcs),
1866         ICPU(INTEL_FAM6_ATOM_GEMINI_LAKE,       bxt_funcs),
1867         {}
1868 };
1869 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1870
1871 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
1872         ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
1873         ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
1874         ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
1875         {}
1876 };
1877
1878 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
1879         ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_funcs),
1880         {}
1881 };
1882
1883 static bool pid_in_use(void);
1884
1885 static int intel_pstate_init_cpu(unsigned int cpunum)
1886 {
1887         struct cpudata *cpu;
1888
1889         cpu = all_cpu_data[cpunum];
1890
1891         if (!cpu) {
1892                 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
1893                 if (!cpu)
1894                         return -ENOMEM;
1895
1896                 all_cpu_data[cpunum] = cpu;
1897
1898                 cpu->epp_default = -EINVAL;
1899                 cpu->epp_powersave = -EINVAL;
1900                 cpu->epp_saved = -EINVAL;
1901         }
1902
1903         cpu = all_cpu_data[cpunum];
1904
1905         cpu->cpu = cpunum;
1906
1907         if (hwp_active) {
1908                 const struct x86_cpu_id *id;
1909
1910                 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
1911                 if (id)
1912                         intel_pstate_disable_ee(cpunum);
1913
1914                 intel_pstate_hwp_enable(cpu);
1915         } else if (pid_in_use()) {
1916                 intel_pstate_pid_reset(cpu);
1917         }
1918
1919         intel_pstate_get_cpu_pstates(cpu);
1920
1921         pr_debug("controlling: cpu %d\n", cpunum);
1922
1923         return 0;
1924 }
1925
1926 static unsigned int intel_pstate_get(unsigned int cpu_num)
1927 {
1928         struct cpudata *cpu = all_cpu_data[cpu_num];
1929
1930         return cpu ? get_avg_frequency(cpu) : 0;
1931 }
1932
1933 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
1934 {
1935         struct cpudata *cpu = all_cpu_data[cpu_num];
1936
1937         if (cpu->update_util_set)
1938                 return;
1939
1940         /* Prevent intel_pstate_update_util() from using stale data. */
1941         cpu->sample.time = 0;
1942         cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
1943                                      pstate_funcs.update_util);
1944         cpu->update_util_set = true;
1945 }
1946
1947 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
1948 {
1949         struct cpudata *cpu_data = all_cpu_data[cpu];
1950
1951         if (!cpu_data->update_util_set)
1952                 return;
1953
1954         cpufreq_remove_update_util_hook(cpu);
1955         cpu_data->update_util_set = false;
1956         synchronize_sched();
1957 }
1958
1959 static int intel_pstate_get_max_freq(struct cpudata *cpu)
1960 {
1961         return global.turbo_disabled || global.no_turbo ?
1962                         cpu->pstate.max_freq : cpu->pstate.turbo_freq;
1963 }
1964
1965 static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
1966                                             struct cpudata *cpu)
1967 {
1968         int max_freq = intel_pstate_get_max_freq(cpu);
1969         int32_t max_policy_perf, min_policy_perf;
1970
1971         max_policy_perf = div_ext_fp(policy->max, max_freq);
1972         max_policy_perf = clamp_t(int32_t, max_policy_perf, 0, int_ext_tofp(1));
1973         if (policy->max == policy->min) {
1974                 min_policy_perf = max_policy_perf;
1975         } else {
1976                 min_policy_perf = div_ext_fp(policy->min, max_freq);
1977                 min_policy_perf = clamp_t(int32_t, min_policy_perf,
1978                                           0, max_policy_perf);
1979         }
1980
1981         /* Normalize user input to [min_perf, max_perf] */
1982         if (per_cpu_limits) {
1983                 cpu->min_perf = min_policy_perf;
1984                 cpu->max_perf = max_policy_perf;
1985         } else {
1986                 int32_t global_min, global_max;
1987
1988                 /* Global limits are in percent of the maximum turbo P-state. */
1989                 global_max = percent_ext_fp(global.max_perf_pct);
1990                 global_min = percent_ext_fp(global.min_perf_pct);
1991                 if (max_freq != cpu->pstate.turbo_freq) {
1992                         int32_t turbo_factor;
1993
1994                         turbo_factor = div_ext_fp(cpu->pstate.turbo_pstate,
1995                                                   cpu->pstate.max_pstate);
1996                         global_min = mul_ext_fp(global_min, turbo_factor);
1997                         global_max = mul_ext_fp(global_max, turbo_factor);
1998                 }
1999                 global_min = clamp_t(int32_t, global_min, 0, global_max);
2000
2001                 cpu->min_perf = max(min_policy_perf, global_min);
2002                 cpu->min_perf = min(cpu->min_perf, max_policy_perf);
2003                 cpu->max_perf = min(max_policy_perf, global_max);
2004                 cpu->max_perf = max(min_policy_perf, cpu->max_perf);
2005
2006                 /* Make sure min_perf <= max_perf */
2007                 cpu->min_perf = min(cpu->min_perf, cpu->max_perf);
2008         }
2009
2010         cpu->max_perf = round_up(cpu->max_perf, EXT_FRAC_BITS);
2011         cpu->min_perf = round_up(cpu->min_perf, EXT_FRAC_BITS);
2012
2013         pr_debug("cpu:%d max_perf_pct:%d min_perf_pct:%d\n", policy->cpu,
2014                  fp_ext_toint(cpu->max_perf * 100),
2015                  fp_ext_toint(cpu->min_perf * 100));
2016 }
2017
2018 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2019 {
2020         struct cpudata *cpu;
2021
2022         if (!policy->cpuinfo.max_freq)
2023                 return -ENODEV;
2024
2025         pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2026                  policy->cpuinfo.max_freq, policy->max);
2027
2028         cpu = all_cpu_data[policy->cpu];
2029         cpu->policy = policy->policy;
2030
2031         mutex_lock(&intel_pstate_limits_lock);
2032
2033         intel_pstate_update_perf_limits(policy, cpu);
2034
2035         if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2036                 /*
2037                  * NOHZ_FULL CPUs need this as the governor callback may not
2038                  * be invoked on them.
2039                  */
2040                 intel_pstate_clear_update_util_hook(policy->cpu);
2041                 intel_pstate_max_within_limits(cpu);
2042         }
2043
2044         intel_pstate_set_update_util_hook(policy->cpu);
2045
2046         if (hwp_active)
2047                 intel_pstate_hwp_set(policy->cpu);
2048
2049         mutex_unlock(&intel_pstate_limits_lock);
2050
2051         return 0;
2052 }
2053
2054 static void intel_pstate_adjust_policy_max(struct cpufreq_policy *policy,
2055                                          struct cpudata *cpu)
2056 {
2057         if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2058             policy->max < policy->cpuinfo.max_freq &&
2059             policy->max > cpu->pstate.max_freq) {
2060                 pr_debug("policy->max > max non turbo frequency\n");
2061                 policy->max = policy->cpuinfo.max_freq;
2062         }
2063 }
2064
2065 static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
2066 {
2067         struct cpudata *cpu = all_cpu_data[policy->cpu];
2068
2069         update_turbo_state();
2070         cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2071                                      intel_pstate_get_max_freq(cpu));
2072
2073         if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
2074             policy->policy != CPUFREQ_POLICY_PERFORMANCE)
2075                 return -EINVAL;
2076
2077         intel_pstate_adjust_policy_max(policy, cpu);
2078
2079         return 0;
2080 }
2081
2082 static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)
2083 {
2084         intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);
2085 }
2086
2087 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
2088 {
2089         pr_debug("CPU %d exiting\n", policy->cpu);
2090
2091         intel_pstate_clear_update_util_hook(policy->cpu);
2092         if (hwp_active)
2093                 intel_pstate_hwp_save_state(policy);
2094         else
2095                 intel_cpufreq_stop_cpu(policy);
2096 }
2097
2098 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2099 {
2100         intel_pstate_exit_perf_limits(policy);
2101
2102         policy->fast_switch_possible = false;
2103
2104         return 0;
2105 }
2106
2107 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2108 {
2109         struct cpudata *cpu;
2110         int rc;
2111
2112         rc = intel_pstate_init_cpu(policy->cpu);
2113         if (rc)
2114                 return rc;
2115
2116         cpu = all_cpu_data[policy->cpu];
2117
2118         cpu->max_perf = int_ext_tofp(1);
2119         cpu->min_perf = 0;
2120
2121         policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
2122         policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
2123
2124         /* cpuinfo and default policy values */
2125         policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
2126         update_turbo_state();
2127         policy->cpuinfo.max_freq = global.turbo_disabled ?
2128                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2129         policy->cpuinfo.max_freq *= cpu->pstate.scaling;
2130
2131         intel_pstate_init_acpi_perf_limits(policy);
2132         cpumask_set_cpu(policy->cpu, policy->cpus);
2133
2134         policy->fast_switch_possible = true;
2135
2136         return 0;
2137 }
2138
2139 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2140 {
2141         int ret = __intel_pstate_cpu_init(policy);
2142
2143         if (ret)
2144                 return ret;
2145
2146         policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
2147         if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE))
2148                 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
2149         else
2150                 policy->policy = CPUFREQ_POLICY_POWERSAVE;
2151
2152         return 0;
2153 }
2154
2155 static struct cpufreq_driver intel_pstate = {
2156         .flags          = CPUFREQ_CONST_LOOPS,
2157         .verify         = intel_pstate_verify_policy,
2158         .setpolicy      = intel_pstate_set_policy,
2159         .suspend        = intel_pstate_hwp_save_state,
2160         .resume         = intel_pstate_resume,
2161         .get            = intel_pstate_get,
2162         .init           = intel_pstate_cpu_init,
2163         .exit           = intel_pstate_cpu_exit,
2164         .stop_cpu       = intel_pstate_stop_cpu,
2165         .name           = "intel_pstate",
2166 };
2167
2168 static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy)
2169 {
2170         struct cpudata *cpu = all_cpu_data[policy->cpu];
2171
2172         update_turbo_state();
2173         cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2174                                      intel_pstate_get_max_freq(cpu));
2175
2176         intel_pstate_adjust_policy_max(policy, cpu);
2177
2178         intel_pstate_update_perf_limits(policy, cpu);
2179
2180         return 0;
2181 }
2182
2183 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2184                                 unsigned int target_freq,
2185                                 unsigned int relation)
2186 {
2187         struct cpudata *cpu = all_cpu_data[policy->cpu];
2188         struct cpufreq_freqs freqs;
2189         int target_pstate;
2190
2191         update_turbo_state();
2192
2193         freqs.old = policy->cur;
2194         freqs.new = target_freq;
2195
2196         cpufreq_freq_transition_begin(policy, &freqs);
2197         switch (relation) {
2198         case CPUFREQ_RELATION_L:
2199                 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2200                 break;
2201         case CPUFREQ_RELATION_H:
2202                 target_pstate = freqs.new / cpu->pstate.scaling;
2203                 break;
2204         default:
2205                 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2206                 break;
2207         }
2208         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2209         if (target_pstate != cpu->pstate.current_pstate) {
2210                 cpu->pstate.current_pstate = target_pstate;
2211                 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL,
2212                               pstate_funcs.get_val(cpu, target_pstate));
2213         }
2214         freqs.new = target_pstate * cpu->pstate.scaling;
2215         cpufreq_freq_transition_end(policy, &freqs, false);
2216
2217         return 0;
2218 }
2219
2220 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2221                                               unsigned int target_freq)
2222 {
2223         struct cpudata *cpu = all_cpu_data[policy->cpu];
2224         int target_pstate;
2225
2226         update_turbo_state();
2227
2228         target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2229         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2230         intel_pstate_update_pstate(cpu, target_pstate);
2231         return target_pstate * cpu->pstate.scaling;
2232 }
2233
2234 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2235 {
2236         int ret = __intel_pstate_cpu_init(policy);
2237
2238         if (ret)
2239                 return ret;
2240
2241         policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2242         policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
2243         /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2244         policy->cur = policy->cpuinfo.min_freq;
2245
2246         return 0;
2247 }
2248
2249 static struct cpufreq_driver intel_cpufreq = {
2250         .flags          = CPUFREQ_CONST_LOOPS,
2251         .verify         = intel_cpufreq_verify_policy,
2252         .target         = intel_cpufreq_target,
2253         .fast_switch    = intel_cpufreq_fast_switch,
2254         .init           = intel_cpufreq_cpu_init,
2255         .exit           = intel_pstate_cpu_exit,
2256         .stop_cpu       = intel_cpufreq_stop_cpu,
2257         .name           = "intel_cpufreq",
2258 };
2259
2260 static struct cpufreq_driver *default_driver = &intel_pstate;
2261
2262 static bool pid_in_use(void)
2263 {
2264         return intel_pstate_driver == &intel_pstate &&
2265                 pstate_funcs.update_util == intel_pstate_update_util_pid;
2266 }
2267
2268 static void intel_pstate_driver_cleanup(void)
2269 {
2270         unsigned int cpu;
2271
2272         get_online_cpus();
2273         for_each_online_cpu(cpu) {
2274                 if (all_cpu_data[cpu]) {
2275                         if (intel_pstate_driver == &intel_pstate)
2276                                 intel_pstate_clear_update_util_hook(cpu);
2277
2278                         kfree(all_cpu_data[cpu]);
2279                         all_cpu_data[cpu] = NULL;
2280                 }
2281         }
2282         put_online_cpus();
2283         intel_pstate_driver = NULL;
2284 }
2285
2286 static int intel_pstate_register_driver(struct cpufreq_driver *driver)
2287 {
2288         int ret;
2289
2290         memset(&global, 0, sizeof(global));
2291         global.max_perf_pct = 100;
2292
2293         intel_pstate_driver = driver;
2294         ret = cpufreq_register_driver(intel_pstate_driver);
2295         if (ret) {
2296                 intel_pstate_driver_cleanup();
2297                 return ret;
2298         }
2299
2300         global.min_perf_pct = min_perf_pct_min();
2301
2302         if (pid_in_use())
2303                 intel_pstate_debug_expose_params();
2304
2305         return 0;
2306 }
2307
2308 static int intel_pstate_unregister_driver(void)
2309 {
2310         if (hwp_active)
2311                 return -EBUSY;
2312
2313         if (pid_in_use())
2314                 intel_pstate_debug_hide_params();
2315
2316         cpufreq_unregister_driver(intel_pstate_driver);
2317         intel_pstate_driver_cleanup();
2318
2319         return 0;
2320 }
2321
2322 static ssize_t intel_pstate_show_status(char *buf)
2323 {
2324         if (!intel_pstate_driver)
2325                 return sprintf(buf, "off\n");
2326
2327         return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
2328                                         "active" : "passive");
2329 }
2330
2331 static int intel_pstate_update_status(const char *buf, size_t size)
2332 {
2333         int ret;
2334
2335         if (size == 3 && !strncmp(buf, "off", size))
2336                 return intel_pstate_driver ?
2337                         intel_pstate_unregister_driver() : -EINVAL;
2338
2339         if (size == 6 && !strncmp(buf, "active", size)) {
2340                 if (intel_pstate_driver) {
2341                         if (intel_pstate_driver == &intel_pstate)
2342                                 return 0;
2343
2344                         ret = intel_pstate_unregister_driver();
2345                         if (ret)
2346                                 return ret;
2347                 }
2348
2349                 return intel_pstate_register_driver(&intel_pstate);
2350         }
2351
2352         if (size == 7 && !strncmp(buf, "passive", size)) {
2353                 if (intel_pstate_driver) {
2354                         if (intel_pstate_driver == &intel_cpufreq)
2355                                 return 0;
2356
2357                         ret = intel_pstate_unregister_driver();
2358                         if (ret)
2359                                 return ret;
2360                 }
2361
2362                 return intel_pstate_register_driver(&intel_cpufreq);
2363         }
2364
2365         return -EINVAL;
2366 }
2367
2368 static int no_load __initdata;
2369 static int no_hwp __initdata;
2370 static int hwp_only __initdata;
2371 static unsigned int force_load __initdata;
2372
2373 static int __init intel_pstate_msrs_not_valid(void)
2374 {
2375         if (!pstate_funcs.get_max() ||
2376             !pstate_funcs.get_min() ||
2377             !pstate_funcs.get_turbo())
2378                 return -ENODEV;
2379
2380         return 0;
2381 }
2382
2383 #ifdef CONFIG_ACPI
2384 static void intel_pstate_use_acpi_profile(void)
2385 {
2386         switch (acpi_gbl_FADT.preferred_profile) {
2387         case PM_MOBILE:
2388         case PM_TABLET:
2389         case PM_APPLIANCE_PC:
2390         case PM_DESKTOP:
2391         case PM_WORKSTATION:
2392                 pstate_funcs.update_util = intel_pstate_update_util;
2393         }
2394 }
2395 #else
2396 static void intel_pstate_use_acpi_profile(void)
2397 {
2398 }
2399 #endif
2400
2401 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
2402 {
2403         pstate_funcs.get_max   = funcs->get_max;
2404         pstate_funcs.get_max_physical = funcs->get_max_physical;
2405         pstate_funcs.get_min   = funcs->get_min;
2406         pstate_funcs.get_turbo = funcs->get_turbo;
2407         pstate_funcs.get_scaling = funcs->get_scaling;
2408         pstate_funcs.get_val   = funcs->get_val;
2409         pstate_funcs.get_vid   = funcs->get_vid;
2410         pstate_funcs.update_util = funcs->update_util;
2411
2412         intel_pstate_use_acpi_profile();
2413 }
2414
2415 #ifdef CONFIG_ACPI
2416
2417 static bool __init intel_pstate_no_acpi_pss(void)
2418 {
2419         int i;
2420
2421         for_each_possible_cpu(i) {
2422                 acpi_status status;
2423                 union acpi_object *pss;
2424                 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2425                 struct acpi_processor *pr = per_cpu(processors, i);
2426
2427                 if (!pr)
2428                         continue;
2429
2430                 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2431                 if (ACPI_FAILURE(status))
2432                         continue;
2433
2434                 pss = buffer.pointer;
2435                 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2436                         kfree(pss);
2437                         return false;
2438                 }
2439
2440                 kfree(pss);
2441         }
2442
2443         return true;
2444 }
2445
2446 static bool __init intel_pstate_has_acpi_ppc(void)
2447 {
2448         int i;
2449
2450         for_each_possible_cpu(i) {
2451                 struct acpi_processor *pr = per_cpu(processors, i);
2452
2453                 if (!pr)
2454                         continue;
2455                 if (acpi_has_method(pr->handle, "_PPC"))
2456                         return true;
2457         }
2458         return false;
2459 }
2460
2461 enum {
2462         PSS,
2463         PPC,
2464 };
2465
2466 struct hw_vendor_info {
2467         u16  valid;
2468         char oem_id[ACPI_OEM_ID_SIZE];
2469         char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
2470         int  oem_pwr_table;
2471 };
2472
2473 /* Hardware vendor-specific info that has its own power management modes */
2474 static struct hw_vendor_info vendor_info[] __initdata = {
2475         {1, "HP    ", "ProLiant", PSS},
2476         {1, "ORACLE", "X4-2    ", PPC},
2477         {1, "ORACLE", "X4-2L   ", PPC},
2478         {1, "ORACLE", "X4-2B   ", PPC},
2479         {1, "ORACLE", "X3-2    ", PPC},
2480         {1, "ORACLE", "X3-2L   ", PPC},
2481         {1, "ORACLE", "X3-2B   ", PPC},
2482         {1, "ORACLE", "X4470M2 ", PPC},
2483         {1, "ORACLE", "X4270M3 ", PPC},
2484         {1, "ORACLE", "X4270M2 ", PPC},
2485         {1, "ORACLE", "X4170M2 ", PPC},
2486         {1, "ORACLE", "X4170 M3", PPC},
2487         {1, "ORACLE", "X4275 M3", PPC},
2488         {1, "ORACLE", "X6-2    ", PPC},
2489         {1, "ORACLE", "Sudbury ", PPC},
2490         {0, "", ""},
2491 };
2492
2493 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
2494 {
2495         struct acpi_table_header hdr;
2496         struct hw_vendor_info *v_info;
2497         const struct x86_cpu_id *id;
2498         u64 misc_pwr;
2499
2500         id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2501         if (id) {
2502                 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
2503                 if ( misc_pwr & (1 << 8))
2504                         return true;
2505         }
2506
2507         if (acpi_disabled ||
2508             ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr)))
2509                 return false;
2510
2511         for (v_info = vendor_info; v_info->valid; v_info++) {
2512                 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) &&
2513                         !strncmp(hdr.oem_table_id, v_info->oem_table_id,
2514                                                 ACPI_OEM_TABLE_ID_SIZE))
2515                         switch (v_info->oem_pwr_table) {
2516                         case PSS:
2517                                 return intel_pstate_no_acpi_pss();
2518                         case PPC:
2519                                 return intel_pstate_has_acpi_ppc() &&
2520                                         (!force_load);
2521                         }
2522         }
2523
2524         return false;
2525 }
2526
2527 static void intel_pstate_request_control_from_smm(void)
2528 {
2529         /*
2530          * It may be unsafe to request P-states control from SMM if _PPC support
2531          * has not been enabled.
2532          */
2533         if (acpi_ppc)
2534                 acpi_processor_pstate_control();
2535 }
2536 #else /* CONFIG_ACPI not enabled */
2537 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
2538 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
2539 static inline void intel_pstate_request_control_from_smm(void) {}
2540 #endif /* CONFIG_ACPI */
2541
2542 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
2543         { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP },
2544         {}
2545 };
2546
2547 static int __init intel_pstate_init(void)
2548 {
2549         int rc;
2550
2551         if (no_load)
2552                 return -ENODEV;
2553
2554         if (x86_match_cpu(hwp_support_ids)) {
2555                 copy_cpu_funcs(&core_funcs);
2556                 if (no_hwp) {
2557                         pstate_funcs.update_util = intel_pstate_update_util;
2558                 } else {
2559                         hwp_active++;
2560                         intel_pstate.attr = hwp_cpufreq_attrs;
2561                         pstate_funcs.update_util = intel_pstate_update_util_hwp;
2562                         goto hwp_cpu_matched;
2563                 }
2564         } else {
2565                 const struct x86_cpu_id *id;
2566
2567                 id = x86_match_cpu(intel_pstate_cpu_ids);
2568                 if (!id)
2569                         return -ENODEV;
2570
2571                 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
2572         }
2573
2574         if (intel_pstate_msrs_not_valid())
2575                 return -ENODEV;
2576
2577 hwp_cpu_matched:
2578         /*
2579          * The Intel pstate driver will be ignored if the platform
2580          * firmware has its own power management modes.
2581          */
2582         if (intel_pstate_platform_pwr_mgmt_exists())
2583                 return -ENODEV;
2584
2585         if (!hwp_active && hwp_only)
2586                 return -ENOTSUPP;
2587
2588         pr_info("Intel P-state driver initializing\n");
2589
2590         all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
2591         if (!all_cpu_data)
2592                 return -ENOMEM;
2593
2594         intel_pstate_request_control_from_smm();
2595
2596         intel_pstate_sysfs_expose_params();
2597
2598         mutex_lock(&intel_pstate_driver_lock);
2599         rc = intel_pstate_register_driver(default_driver);
2600         mutex_unlock(&intel_pstate_driver_lock);
2601         if (rc)
2602                 return rc;
2603
2604         if (hwp_active)
2605                 pr_info("HWP enabled\n");
2606
2607         return 0;
2608 }
2609 device_initcall(intel_pstate_init);
2610
2611 static int __init intel_pstate_setup(char *str)
2612 {
2613         if (!str)
2614                 return -EINVAL;
2615
2616         if (!strcmp(str, "disable")) {
2617                 no_load = 1;
2618         } else if (!strcmp(str, "passive")) {
2619                 pr_info("Passive mode enabled\n");
2620                 default_driver = &intel_cpufreq;
2621                 no_hwp = 1;
2622         }
2623         if (!strcmp(str, "no_hwp")) {
2624                 pr_info("HWP disabled\n");
2625                 no_hwp = 1;
2626         }
2627         if (!strcmp(str, "force"))
2628                 force_load = 1;
2629         if (!strcmp(str, "hwp_only"))
2630                 hwp_only = 1;
2631         if (!strcmp(str, "per_cpu_perf_limits"))
2632                 per_cpu_limits = true;
2633
2634 #ifdef CONFIG_ACPI
2635         if (!strcmp(str, "support_acpi_ppc"))
2636                 acpi_ppc = true;
2637 #endif
2638
2639         return 0;
2640 }
2641 early_param("intel_pstate", intel_pstate_setup);
2642
2643 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2644 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2645 MODULE_LICENSE("GPL");