Linux v4.13-rc1
[muen/linux.git] / drivers / cpufreq / intel_pstate.c
1 /*
2  * intel_pstate.c: Native P state management for Intel processors
3  *
4  * (C) Copyright 2012 Intel Corporation
5  * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License
9  * as published by the Free Software Foundation; version 2
10  * of the License.
11  */
12
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
15 #include <linux/kernel.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/module.h>
18 #include <linux/ktime.h>
19 #include <linux/hrtimer.h>
20 #include <linux/tick.h>
21 #include <linux/slab.h>
22 #include <linux/sched/cpufreq.h>
23 #include <linux/list.h>
24 #include <linux/cpu.h>
25 #include <linux/cpufreq.h>
26 #include <linux/sysfs.h>
27 #include <linux/types.h>
28 #include <linux/fs.h>
29 #include <linux/debugfs.h>
30 #include <linux/acpi.h>
31 #include <linux/vmalloc.h>
32 #include <trace/events/power.h>
33
34 #include <asm/div64.h>
35 #include <asm/msr.h>
36 #include <asm/cpu_device_id.h>
37 #include <asm/cpufeature.h>
38 #include <asm/intel-family.h>
39
40 #define INTEL_PSTATE_DEFAULT_SAMPLING_INTERVAL  (10 * NSEC_PER_MSEC)
41 #define INTEL_PSTATE_HWP_SAMPLING_INTERVAL      (50 * NSEC_PER_MSEC)
42
43 #define INTEL_CPUFREQ_TRANSITION_LATENCY        20000
44 #define INTEL_CPUFREQ_TRANSITION_DELAY          500
45
46 #ifdef CONFIG_ACPI
47 #include <acpi/processor.h>
48 #include <acpi/cppc_acpi.h>
49 #endif
50
51 #define FRAC_BITS 8
52 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
53 #define fp_toint(X) ((X) >> FRAC_BITS)
54
55 #define EXT_BITS 6
56 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
57 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
58 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
59
60 static inline int32_t mul_fp(int32_t x, int32_t y)
61 {
62         return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
63 }
64
65 static inline int32_t div_fp(s64 x, s64 y)
66 {
67         return div64_s64((int64_t)x << FRAC_BITS, y);
68 }
69
70 static inline int ceiling_fp(int32_t x)
71 {
72         int mask, ret;
73
74         ret = fp_toint(x);
75         mask = (1 << FRAC_BITS) - 1;
76         if (x & mask)
77                 ret += 1;
78         return ret;
79 }
80
81 static inline int32_t percent_fp(int percent)
82 {
83         return div_fp(percent, 100);
84 }
85
86 static inline u64 mul_ext_fp(u64 x, u64 y)
87 {
88         return (x * y) >> EXT_FRAC_BITS;
89 }
90
91 static inline u64 div_ext_fp(u64 x, u64 y)
92 {
93         return div64_u64(x << EXT_FRAC_BITS, y);
94 }
95
96 static inline int32_t percent_ext_fp(int percent)
97 {
98         return div_ext_fp(percent, 100);
99 }
100
101 /**
102  * struct sample -      Store performance sample
103  * @core_avg_perf:      Ratio of APERF/MPERF which is the actual average
104  *                      performance during last sample period
105  * @busy_scaled:        Scaled busy value which is used to calculate next
106  *                      P state. This can be different than core_avg_perf
107  *                      to account for cpu idle period
108  * @aperf:              Difference of actual performance frequency clock count
109  *                      read from APERF MSR between last and current sample
110  * @mperf:              Difference of maximum performance frequency clock count
111  *                      read from MPERF MSR between last and current sample
112  * @tsc:                Difference of time stamp counter between last and
113  *                      current sample
114  * @time:               Current time from scheduler
115  *
116  * This structure is used in the cpudata structure to store performance sample
117  * data for choosing next P State.
118  */
119 struct sample {
120         int32_t core_avg_perf;
121         int32_t busy_scaled;
122         u64 aperf;
123         u64 mperf;
124         u64 tsc;
125         u64 time;
126 };
127
128 /**
129  * struct pstate_data - Store P state data
130  * @current_pstate:     Current requested P state
131  * @min_pstate:         Min P state possible for this platform
132  * @max_pstate:         Max P state possible for this platform
133  * @max_pstate_physical:This is physical Max P state for a processor
134  *                      This can be higher than the max_pstate which can
135  *                      be limited by platform thermal design power limits
136  * @scaling:            Scaling factor to  convert frequency to cpufreq
137  *                      frequency units
138  * @turbo_pstate:       Max Turbo P state possible for this platform
139  * @max_freq:           @max_pstate frequency in cpufreq units
140  * @turbo_freq:         @turbo_pstate frequency in cpufreq units
141  *
142  * Stores the per cpu model P state limits and current P state.
143  */
144 struct pstate_data {
145         int     current_pstate;
146         int     min_pstate;
147         int     max_pstate;
148         int     max_pstate_physical;
149         int     scaling;
150         int     turbo_pstate;
151         unsigned int max_freq;
152         unsigned int turbo_freq;
153 };
154
155 /**
156  * struct vid_data -    Stores voltage information data
157  * @min:                VID data for this platform corresponding to
158  *                      the lowest P state
159  * @max:                VID data corresponding to the highest P State.
160  * @turbo:              VID data for turbo P state
161  * @ratio:              Ratio of (vid max - vid min) /
162  *                      (max P state - Min P State)
163  *
164  * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
165  * This data is used in Atom platforms, where in addition to target P state,
166  * the voltage data needs to be specified to select next P State.
167  */
168 struct vid_data {
169         int min;
170         int max;
171         int turbo;
172         int32_t ratio;
173 };
174
175 /**
176  * struct _pid -        Stores PID data
177  * @setpoint:           Target set point for busyness or performance
178  * @integral:           Storage for accumulated error values
179  * @p_gain:             PID proportional gain
180  * @i_gain:             PID integral gain
181  * @d_gain:             PID derivative gain
182  * @deadband:           PID deadband
183  * @last_err:           Last error storage for integral part of PID calculation
184  *
185  * Stores PID coefficients and last error for PID controller.
186  */
187 struct _pid {
188         int setpoint;
189         int32_t integral;
190         int32_t p_gain;
191         int32_t i_gain;
192         int32_t d_gain;
193         int deadband;
194         int32_t last_err;
195 };
196
197 /**
198  * struct global_params - Global parameters, mostly tunable via sysfs.
199  * @no_turbo:           Whether or not to use turbo P-states.
200  * @turbo_disabled:     Whethet or not turbo P-states are available at all,
201  *                      based on the MSR_IA32_MISC_ENABLE value and whether or
202  *                      not the maximum reported turbo P-state is different from
203  *                      the maximum reported non-turbo one.
204  * @min_perf_pct:       Minimum capacity limit in percent of the maximum turbo
205  *                      P-state capacity.
206  * @max_perf_pct:       Maximum capacity limit in percent of the maximum turbo
207  *                      P-state capacity.
208  */
209 struct global_params {
210         bool no_turbo;
211         bool turbo_disabled;
212         int max_perf_pct;
213         int min_perf_pct;
214 };
215
216 /**
217  * struct cpudata -     Per CPU instance data storage
218  * @cpu:                CPU number for this instance data
219  * @policy:             CPUFreq policy value
220  * @update_util:        CPUFreq utility callback information
221  * @update_util_set:    CPUFreq utility callback is set
222  * @iowait_boost:       iowait-related boost fraction
223  * @last_update:        Time of the last update.
224  * @pstate:             Stores P state limits for this CPU
225  * @vid:                Stores VID limits for this CPU
226  * @pid:                Stores PID parameters for this CPU
227  * @last_sample_time:   Last Sample time
228  * @prev_aperf:         Last APERF value read from APERF MSR
229  * @prev_mperf:         Last MPERF value read from MPERF MSR
230  * @prev_tsc:           Last timestamp counter (TSC) value
231  * @prev_cummulative_iowait: IO Wait time difference from last and
232  *                      current sample
233  * @sample:             Storage for storing last Sample data
234  * @min_perf_ratio:     Minimum capacity in terms of PERF or HWP ratios
235  * @max_perf_ratio:     Maximum capacity in terms of PERF or HWP ratios
236  * @acpi_perf_data:     Stores ACPI perf information read from _PSS
237  * @valid_pss_table:    Set to true for valid ACPI _PSS entries found
238  * @epp_powersave:      Last saved HWP energy performance preference
239  *                      (EPP) or energy performance bias (EPB),
240  *                      when policy switched to performance
241  * @epp_policy:         Last saved policy used to set EPP/EPB
242  * @epp_default:        Power on default HWP energy performance
243  *                      preference/bias
244  * @epp_saved:          Saved EPP/EPB during system suspend or CPU offline
245  *                      operation
246  *
247  * This structure stores per CPU instance data for all CPUs.
248  */
249 struct cpudata {
250         int cpu;
251
252         unsigned int policy;
253         struct update_util_data update_util;
254         bool   update_util_set;
255
256         struct pstate_data pstate;
257         struct vid_data vid;
258         struct _pid pid;
259
260         u64     last_update;
261         u64     last_sample_time;
262         u64     prev_aperf;
263         u64     prev_mperf;
264         u64     prev_tsc;
265         u64     prev_cummulative_iowait;
266         struct sample sample;
267         int32_t min_perf_ratio;
268         int32_t max_perf_ratio;
269 #ifdef CONFIG_ACPI
270         struct acpi_processor_performance acpi_perf_data;
271         bool valid_pss_table;
272 #endif
273         unsigned int iowait_boost;
274         s16 epp_powersave;
275         s16 epp_policy;
276         s16 epp_default;
277         s16 epp_saved;
278 };
279
280 static struct cpudata **all_cpu_data;
281
282 /**
283  * struct pstate_adjust_policy - Stores static PID configuration data
284  * @sample_rate_ms:     PID calculation sample rate in ms
285  * @sample_rate_ns:     Sample rate calculation in ns
286  * @deadband:           PID deadband
287  * @setpoint:           PID Setpoint
288  * @p_gain_pct:         PID proportional gain
289  * @i_gain_pct:         PID integral gain
290  * @d_gain_pct:         PID derivative gain
291  *
292  * Stores per CPU model static PID configuration data.
293  */
294 struct pstate_adjust_policy {
295         int sample_rate_ms;
296         s64 sample_rate_ns;
297         int deadband;
298         int setpoint;
299         int p_gain_pct;
300         int d_gain_pct;
301         int i_gain_pct;
302 };
303
304 /**
305  * struct pstate_funcs - Per CPU model specific callbacks
306  * @get_max:            Callback to get maximum non turbo effective P state
307  * @get_max_physical:   Callback to get maximum non turbo physical P state
308  * @get_min:            Callback to get minimum P state
309  * @get_turbo:          Callback to get turbo P state
310  * @get_scaling:        Callback to get frequency scaling factor
311  * @get_val:            Callback to convert P state to actual MSR write value
312  * @get_vid:            Callback to get VID data for Atom platforms
313  * @update_util:        Active mode utilization update callback.
314  *
315  * Core and Atom CPU models have different way to get P State limits. This
316  * structure is used to store those callbacks.
317  */
318 struct pstate_funcs {
319         int (*get_max)(void);
320         int (*get_max_physical)(void);
321         int (*get_min)(void);
322         int (*get_turbo)(void);
323         int (*get_scaling)(void);
324         u64 (*get_val)(struct cpudata*, int pstate);
325         void (*get_vid)(struct cpudata *);
326         void (*update_util)(struct update_util_data *data, u64 time,
327                             unsigned int flags);
328 };
329
330 static struct pstate_funcs pstate_funcs __read_mostly;
331 static struct pstate_adjust_policy pid_params __read_mostly = {
332         .sample_rate_ms = 10,
333         .sample_rate_ns = 10 * NSEC_PER_MSEC,
334         .deadband = 0,
335         .setpoint = 97,
336         .p_gain_pct = 20,
337         .d_gain_pct = 0,
338         .i_gain_pct = 0,
339 };
340
341 static int hwp_active __read_mostly;
342 static bool per_cpu_limits __read_mostly;
343
344 static struct cpufreq_driver *intel_pstate_driver __read_mostly;
345
346 #ifdef CONFIG_ACPI
347 static bool acpi_ppc;
348 #endif
349
350 static struct global_params global;
351
352 static DEFINE_MUTEX(intel_pstate_driver_lock);
353 static DEFINE_MUTEX(intel_pstate_limits_lock);
354
355 #ifdef CONFIG_ACPI
356
357 static bool intel_pstate_get_ppc_enable_status(void)
358 {
359         if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
360             acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
361                 return true;
362
363         return acpi_ppc;
364 }
365
366 #ifdef CONFIG_ACPI_CPPC_LIB
367
368 /* The work item is needed to avoid CPU hotplug locking issues */
369 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
370 {
371         sched_set_itmt_support();
372 }
373
374 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
375
376 static void intel_pstate_set_itmt_prio(int cpu)
377 {
378         struct cppc_perf_caps cppc_perf;
379         static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
380         int ret;
381
382         ret = cppc_get_perf_caps(cpu, &cppc_perf);
383         if (ret)
384                 return;
385
386         /*
387          * The priorities can be set regardless of whether or not
388          * sched_set_itmt_support(true) has been called and it is valid to
389          * update them at any time after it has been called.
390          */
391         sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
392
393         if (max_highest_perf <= min_highest_perf) {
394                 if (cppc_perf.highest_perf > max_highest_perf)
395                         max_highest_perf = cppc_perf.highest_perf;
396
397                 if (cppc_perf.highest_perf < min_highest_perf)
398                         min_highest_perf = cppc_perf.highest_perf;
399
400                 if (max_highest_perf > min_highest_perf) {
401                         /*
402                          * This code can be run during CPU online under the
403                          * CPU hotplug locks, so sched_set_itmt_support()
404                          * cannot be called from here.  Queue up a work item
405                          * to invoke it.
406                          */
407                         schedule_work(&sched_itmt_work);
408                 }
409         }
410 }
411 #else
412 static void intel_pstate_set_itmt_prio(int cpu)
413 {
414 }
415 #endif
416
417 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
418 {
419         struct cpudata *cpu;
420         int ret;
421         int i;
422
423         if (hwp_active) {
424                 intel_pstate_set_itmt_prio(policy->cpu);
425                 return;
426         }
427
428         if (!intel_pstate_get_ppc_enable_status())
429                 return;
430
431         cpu = all_cpu_data[policy->cpu];
432
433         ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
434                                                   policy->cpu);
435         if (ret)
436                 return;
437
438         /*
439          * Check if the control value in _PSS is for PERF_CTL MSR, which should
440          * guarantee that the states returned by it map to the states in our
441          * list directly.
442          */
443         if (cpu->acpi_perf_data.control_register.space_id !=
444                                                 ACPI_ADR_SPACE_FIXED_HARDWARE)
445                 goto err;
446
447         /*
448          * If there is only one entry _PSS, simply ignore _PSS and continue as
449          * usual without taking _PSS into account
450          */
451         if (cpu->acpi_perf_data.state_count < 2)
452                 goto err;
453
454         pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
455         for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
456                 pr_debug("     %cP%d: %u MHz, %u mW, 0x%x\n",
457                          (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
458                          (u32) cpu->acpi_perf_data.states[i].core_frequency,
459                          (u32) cpu->acpi_perf_data.states[i].power,
460                          (u32) cpu->acpi_perf_data.states[i].control);
461         }
462
463         /*
464          * The _PSS table doesn't contain whole turbo frequency range.
465          * This just contains +1 MHZ above the max non turbo frequency,
466          * with control value corresponding to max turbo ratio. But
467          * when cpufreq set policy is called, it will call with this
468          * max frequency, which will cause a reduced performance as
469          * this driver uses real max turbo frequency as the max
470          * frequency. So correct this frequency in _PSS table to
471          * correct max turbo frequency based on the turbo state.
472          * Also need to convert to MHz as _PSS freq is in MHz.
473          */
474         if (!global.turbo_disabled)
475                 cpu->acpi_perf_data.states[0].core_frequency =
476                                         policy->cpuinfo.max_freq / 1000;
477         cpu->valid_pss_table = true;
478         pr_debug("_PPC limits will be enforced\n");
479
480         return;
481
482  err:
483         cpu->valid_pss_table = false;
484         acpi_processor_unregister_performance(policy->cpu);
485 }
486
487 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
488 {
489         struct cpudata *cpu;
490
491         cpu = all_cpu_data[policy->cpu];
492         if (!cpu->valid_pss_table)
493                 return;
494
495         acpi_processor_unregister_performance(policy->cpu);
496 }
497 #else
498 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
499 {
500 }
501
502 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
503 {
504 }
505 #endif
506
507 static signed int pid_calc(struct _pid *pid, int32_t busy)
508 {
509         signed int result;
510         int32_t pterm, dterm, fp_error;
511         int32_t integral_limit;
512
513         fp_error = pid->setpoint - busy;
514
515         if (abs(fp_error) <= pid->deadband)
516                 return 0;
517
518         pterm = mul_fp(pid->p_gain, fp_error);
519
520         pid->integral += fp_error;
521
522         /*
523          * We limit the integral here so that it will never
524          * get higher than 30.  This prevents it from becoming
525          * too large an input over long periods of time and allows
526          * it to get factored out sooner.
527          *
528          * The value of 30 was chosen through experimentation.
529          */
530         integral_limit = int_tofp(30);
531         if (pid->integral > integral_limit)
532                 pid->integral = integral_limit;
533         if (pid->integral < -integral_limit)
534                 pid->integral = -integral_limit;
535
536         dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);
537         pid->last_err = fp_error;
538
539         result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;
540         result = result + (1 << (FRAC_BITS-1));
541         return (signed int)fp_toint(result);
542 }
543
544 static inline void intel_pstate_pid_reset(struct cpudata *cpu)
545 {
546         struct _pid *pid = &cpu->pid;
547
548         pid->p_gain = percent_fp(pid_params.p_gain_pct);
549         pid->d_gain = percent_fp(pid_params.d_gain_pct);
550         pid->i_gain = percent_fp(pid_params.i_gain_pct);
551         pid->setpoint = int_tofp(pid_params.setpoint);
552         pid->last_err  = pid->setpoint - int_tofp(100);
553         pid->deadband  = int_tofp(pid_params.deadband);
554         pid->integral  = 0;
555 }
556
557 static inline void update_turbo_state(void)
558 {
559         u64 misc_en;
560         struct cpudata *cpu;
561
562         cpu = all_cpu_data[0];
563         rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
564         global.turbo_disabled =
565                 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
566                  cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
567 }
568
569 static int min_perf_pct_min(void)
570 {
571         struct cpudata *cpu = all_cpu_data[0];
572         int turbo_pstate = cpu->pstate.turbo_pstate;
573
574         return turbo_pstate ?
575                 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
576 }
577
578 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
579 {
580         u64 epb;
581         int ret;
582
583         if (!static_cpu_has(X86_FEATURE_EPB))
584                 return -ENXIO;
585
586         ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
587         if (ret)
588                 return (s16)ret;
589
590         return (s16)(epb & 0x0f);
591 }
592
593 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
594 {
595         s16 epp;
596
597         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
598                 /*
599                  * When hwp_req_data is 0, means that caller didn't read
600                  * MSR_HWP_REQUEST, so need to read and get EPP.
601                  */
602                 if (!hwp_req_data) {
603                         epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
604                                             &hwp_req_data);
605                         if (epp)
606                                 return epp;
607                 }
608                 epp = (hwp_req_data >> 24) & 0xff;
609         } else {
610                 /* When there is no EPP present, HWP uses EPB settings */
611                 epp = intel_pstate_get_epb(cpu_data);
612         }
613
614         return epp;
615 }
616
617 static int intel_pstate_set_epb(int cpu, s16 pref)
618 {
619         u64 epb;
620         int ret;
621
622         if (!static_cpu_has(X86_FEATURE_EPB))
623                 return -ENXIO;
624
625         ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
626         if (ret)
627                 return ret;
628
629         epb = (epb & ~0x0f) | pref;
630         wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
631
632         return 0;
633 }
634
635 /*
636  * EPP/EPB display strings corresponding to EPP index in the
637  * energy_perf_strings[]
638  *      index           String
639  *-------------------------------------
640  *      0               default
641  *      1               performance
642  *      2               balance_performance
643  *      3               balance_power
644  *      4               power
645  */
646 static const char * const energy_perf_strings[] = {
647         "default",
648         "performance",
649         "balance_performance",
650         "balance_power",
651         "power",
652         NULL
653 };
654 static const unsigned int epp_values[] = {
655         HWP_EPP_PERFORMANCE,
656         HWP_EPP_BALANCE_PERFORMANCE,
657         HWP_EPP_BALANCE_POWERSAVE,
658         HWP_EPP_POWERSAVE
659 };
660
661 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
662 {
663         s16 epp;
664         int index = -EINVAL;
665
666         epp = intel_pstate_get_epp(cpu_data, 0);
667         if (epp < 0)
668                 return epp;
669
670         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
671                 if (epp == HWP_EPP_PERFORMANCE)
672                         return 1;
673                 if (epp <= HWP_EPP_BALANCE_PERFORMANCE)
674                         return 2;
675                 if (epp <= HWP_EPP_BALANCE_POWERSAVE)
676                         return 3;
677                 else
678                         return 4;
679         } else if (static_cpu_has(X86_FEATURE_EPB)) {
680                 /*
681                  * Range:
682                  *      0x00-0x03       :       Performance
683                  *      0x04-0x07       :       Balance performance
684                  *      0x08-0x0B       :       Balance power
685                  *      0x0C-0x0F       :       Power
686                  * The EPB is a 4 bit value, but our ranges restrict the
687                  * value which can be set. Here only using top two bits
688                  * effectively.
689                  */
690                 index = (epp >> 2) + 1;
691         }
692
693         return index;
694 }
695
696 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
697                                               int pref_index)
698 {
699         int epp = -EINVAL;
700         int ret;
701
702         if (!pref_index)
703                 epp = cpu_data->epp_default;
704
705         mutex_lock(&intel_pstate_limits_lock);
706
707         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
708                 u64 value;
709
710                 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value);
711                 if (ret)
712                         goto return_pref;
713
714                 value &= ~GENMASK_ULL(31, 24);
715
716                 if (epp == -EINVAL)
717                         epp = epp_values[pref_index - 1];
718
719                 value |= (u64)epp << 24;
720                 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
721         } else {
722                 if (epp == -EINVAL)
723                         epp = (pref_index - 1) << 2;
724                 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
725         }
726 return_pref:
727         mutex_unlock(&intel_pstate_limits_lock);
728
729         return ret;
730 }
731
732 static ssize_t show_energy_performance_available_preferences(
733                                 struct cpufreq_policy *policy, char *buf)
734 {
735         int i = 0;
736         int ret = 0;
737
738         while (energy_perf_strings[i] != NULL)
739                 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
740
741         ret += sprintf(&buf[ret], "\n");
742
743         return ret;
744 }
745
746 cpufreq_freq_attr_ro(energy_performance_available_preferences);
747
748 static ssize_t store_energy_performance_preference(
749                 struct cpufreq_policy *policy, const char *buf, size_t count)
750 {
751         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
752         char str_preference[21];
753         int ret, i = 0;
754
755         ret = sscanf(buf, "%20s", str_preference);
756         if (ret != 1)
757                 return -EINVAL;
758
759         while (energy_perf_strings[i] != NULL) {
760                 if (!strcmp(str_preference, energy_perf_strings[i])) {
761                         intel_pstate_set_energy_pref_index(cpu_data, i);
762                         return count;
763                 }
764                 ++i;
765         }
766
767         return -EINVAL;
768 }
769
770 static ssize_t show_energy_performance_preference(
771                                 struct cpufreq_policy *policy, char *buf)
772 {
773         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
774         int preference;
775
776         preference = intel_pstate_get_energy_pref_index(cpu_data);
777         if (preference < 0)
778                 return preference;
779
780         return  sprintf(buf, "%s\n", energy_perf_strings[preference]);
781 }
782
783 cpufreq_freq_attr_rw(energy_performance_preference);
784
785 static struct freq_attr *hwp_cpufreq_attrs[] = {
786         &energy_performance_preference,
787         &energy_performance_available_preferences,
788         NULL,
789 };
790
791 static void intel_pstate_get_hwp_max(unsigned int cpu, int *phy_max,
792                                      int *current_max)
793 {
794         u64 cap;
795
796         rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
797         if (global.no_turbo)
798                 *current_max = HWP_GUARANTEED_PERF(cap);
799         else
800                 *current_max = HWP_HIGHEST_PERF(cap);
801
802         *phy_max = HWP_HIGHEST_PERF(cap);
803 }
804
805 static void intel_pstate_hwp_set(unsigned int cpu)
806 {
807         struct cpudata *cpu_data = all_cpu_data[cpu];
808         int max, min;
809         u64 value;
810         s16 epp;
811
812         max = cpu_data->max_perf_ratio;
813         min = cpu_data->min_perf_ratio;
814
815         if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
816                 min = max;
817
818         rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
819
820         value &= ~HWP_MIN_PERF(~0L);
821         value |= HWP_MIN_PERF(min);
822
823         value &= ~HWP_MAX_PERF(~0L);
824         value |= HWP_MAX_PERF(max);
825
826         if (cpu_data->epp_policy == cpu_data->policy)
827                 goto skip_epp;
828
829         cpu_data->epp_policy = cpu_data->policy;
830
831         if (cpu_data->epp_saved >= 0) {
832                 epp = cpu_data->epp_saved;
833                 cpu_data->epp_saved = -EINVAL;
834                 goto update_epp;
835         }
836
837         if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
838                 epp = intel_pstate_get_epp(cpu_data, value);
839                 cpu_data->epp_powersave = epp;
840                 /* If EPP read was failed, then don't try to write */
841                 if (epp < 0)
842                         goto skip_epp;
843
844                 epp = 0;
845         } else {
846                 /* skip setting EPP, when saved value is invalid */
847                 if (cpu_data->epp_powersave < 0)
848                         goto skip_epp;
849
850                 /*
851                  * No need to restore EPP when it is not zero. This
852                  * means:
853                  *  - Policy is not changed
854                  *  - user has manually changed
855                  *  - Error reading EPB
856                  */
857                 epp = intel_pstate_get_epp(cpu_data, value);
858                 if (epp)
859                         goto skip_epp;
860
861                 epp = cpu_data->epp_powersave;
862         }
863 update_epp:
864         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
865                 value &= ~GENMASK_ULL(31, 24);
866                 value |= (u64)epp << 24;
867         } else {
868                 intel_pstate_set_epb(cpu, epp);
869         }
870 skip_epp:
871         wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
872 }
873
874 static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
875 {
876         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
877
878         if (!hwp_active)
879                 return 0;
880
881         cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
882
883         return 0;
884 }
885
886 static int intel_pstate_resume(struct cpufreq_policy *policy)
887 {
888         if (!hwp_active)
889                 return 0;
890
891         mutex_lock(&intel_pstate_limits_lock);
892
893         all_cpu_data[policy->cpu]->epp_policy = 0;
894         intel_pstate_hwp_set(policy->cpu);
895
896         mutex_unlock(&intel_pstate_limits_lock);
897
898         return 0;
899 }
900
901 static void intel_pstate_update_policies(void)
902 {
903         int cpu;
904
905         for_each_possible_cpu(cpu)
906                 cpufreq_update_policy(cpu);
907 }
908
909 /************************** debugfs begin ************************/
910 static int pid_param_set(void *data, u64 val)
911 {
912         unsigned int cpu;
913
914         *(u32 *)data = val;
915         pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC;
916         for_each_possible_cpu(cpu)
917                 if (all_cpu_data[cpu])
918                         intel_pstate_pid_reset(all_cpu_data[cpu]);
919
920         return 0;
921 }
922
923 static int pid_param_get(void *data, u64 *val)
924 {
925         *val = *(u32 *)data;
926         return 0;
927 }
928 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n");
929
930 static struct dentry *debugfs_parent;
931
932 struct pid_param {
933         char *name;
934         void *value;
935         struct dentry *dentry;
936 };
937
938 static struct pid_param pid_files[] = {
939         {"sample_rate_ms", &pid_params.sample_rate_ms, },
940         {"d_gain_pct", &pid_params.d_gain_pct, },
941         {"i_gain_pct", &pid_params.i_gain_pct, },
942         {"deadband", &pid_params.deadband, },
943         {"setpoint", &pid_params.setpoint, },
944         {"p_gain_pct", &pid_params.p_gain_pct, },
945         {NULL, NULL, }
946 };
947
948 static void intel_pstate_debug_expose_params(void)
949 {
950         int i;
951
952         debugfs_parent = debugfs_create_dir("pstate_snb", NULL);
953         if (IS_ERR_OR_NULL(debugfs_parent))
954                 return;
955
956         for (i = 0; pid_files[i].name; i++) {
957                 struct dentry *dentry;
958
959                 dentry = debugfs_create_file(pid_files[i].name, 0660,
960                                              debugfs_parent, pid_files[i].value,
961                                              &fops_pid_param);
962                 if (!IS_ERR(dentry))
963                         pid_files[i].dentry = dentry;
964         }
965 }
966
967 static void intel_pstate_debug_hide_params(void)
968 {
969         int i;
970
971         if (IS_ERR_OR_NULL(debugfs_parent))
972                 return;
973
974         for (i = 0; pid_files[i].name; i++) {
975                 debugfs_remove(pid_files[i].dentry);
976                 pid_files[i].dentry = NULL;
977         }
978
979         debugfs_remove(debugfs_parent);
980         debugfs_parent = NULL;
981 }
982
983 /************************** debugfs end ************************/
984
985 /************************** sysfs begin ************************/
986 #define show_one(file_name, object)                                     \
987         static ssize_t show_##file_name                                 \
988         (struct kobject *kobj, struct attribute *attr, char *buf)       \
989         {                                                               \
990                 return sprintf(buf, "%u\n", global.object);             \
991         }
992
993 static ssize_t intel_pstate_show_status(char *buf);
994 static int intel_pstate_update_status(const char *buf, size_t size);
995
996 static ssize_t show_status(struct kobject *kobj,
997                            struct attribute *attr, char *buf)
998 {
999         ssize_t ret;
1000
1001         mutex_lock(&intel_pstate_driver_lock);
1002         ret = intel_pstate_show_status(buf);
1003         mutex_unlock(&intel_pstate_driver_lock);
1004
1005         return ret;
1006 }
1007
1008 static ssize_t store_status(struct kobject *a, struct attribute *b,
1009                             const char *buf, size_t count)
1010 {
1011         char *p = memchr(buf, '\n', count);
1012         int ret;
1013
1014         mutex_lock(&intel_pstate_driver_lock);
1015         ret = intel_pstate_update_status(buf, p ? p - buf : count);
1016         mutex_unlock(&intel_pstate_driver_lock);
1017
1018         return ret < 0 ? ret : count;
1019 }
1020
1021 static ssize_t show_turbo_pct(struct kobject *kobj,
1022                                 struct attribute *attr, char *buf)
1023 {
1024         struct cpudata *cpu;
1025         int total, no_turbo, turbo_pct;
1026         uint32_t turbo_fp;
1027
1028         mutex_lock(&intel_pstate_driver_lock);
1029
1030         if (!intel_pstate_driver) {
1031                 mutex_unlock(&intel_pstate_driver_lock);
1032                 return -EAGAIN;
1033         }
1034
1035         cpu = all_cpu_data[0];
1036
1037         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1038         no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
1039         turbo_fp = div_fp(no_turbo, total);
1040         turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1041
1042         mutex_unlock(&intel_pstate_driver_lock);
1043
1044         return sprintf(buf, "%u\n", turbo_pct);
1045 }
1046
1047 static ssize_t show_num_pstates(struct kobject *kobj,
1048                                 struct attribute *attr, char *buf)
1049 {
1050         struct cpudata *cpu;
1051         int total;
1052
1053         mutex_lock(&intel_pstate_driver_lock);
1054
1055         if (!intel_pstate_driver) {
1056                 mutex_unlock(&intel_pstate_driver_lock);
1057                 return -EAGAIN;
1058         }
1059
1060         cpu = all_cpu_data[0];
1061         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1062
1063         mutex_unlock(&intel_pstate_driver_lock);
1064
1065         return sprintf(buf, "%u\n", total);
1066 }
1067
1068 static ssize_t show_no_turbo(struct kobject *kobj,
1069                              struct attribute *attr, char *buf)
1070 {
1071         ssize_t ret;
1072
1073         mutex_lock(&intel_pstate_driver_lock);
1074
1075         if (!intel_pstate_driver) {
1076                 mutex_unlock(&intel_pstate_driver_lock);
1077                 return -EAGAIN;
1078         }
1079
1080         update_turbo_state();
1081         if (global.turbo_disabled)
1082                 ret = sprintf(buf, "%u\n", global.turbo_disabled);
1083         else
1084                 ret = sprintf(buf, "%u\n", global.no_turbo);
1085
1086         mutex_unlock(&intel_pstate_driver_lock);
1087
1088         return ret;
1089 }
1090
1091 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
1092                               const char *buf, size_t count)
1093 {
1094         unsigned int input;
1095         int ret;
1096
1097         ret = sscanf(buf, "%u", &input);
1098         if (ret != 1)
1099                 return -EINVAL;
1100
1101         mutex_lock(&intel_pstate_driver_lock);
1102
1103         if (!intel_pstate_driver) {
1104                 mutex_unlock(&intel_pstate_driver_lock);
1105                 return -EAGAIN;
1106         }
1107
1108         mutex_lock(&intel_pstate_limits_lock);
1109
1110         update_turbo_state();
1111         if (global.turbo_disabled) {
1112                 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
1113                 mutex_unlock(&intel_pstate_limits_lock);
1114                 mutex_unlock(&intel_pstate_driver_lock);
1115                 return -EPERM;
1116         }
1117
1118         global.no_turbo = clamp_t(int, input, 0, 1);
1119
1120         if (global.no_turbo) {
1121                 struct cpudata *cpu = all_cpu_data[0];
1122                 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
1123
1124                 /* Squash the global minimum into the permitted range. */
1125                 if (global.min_perf_pct > pct)
1126                         global.min_perf_pct = pct;
1127         }
1128
1129         mutex_unlock(&intel_pstate_limits_lock);
1130
1131         intel_pstate_update_policies();
1132
1133         mutex_unlock(&intel_pstate_driver_lock);
1134
1135         return count;
1136 }
1137
1138 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
1139                                   const char *buf, size_t count)
1140 {
1141         unsigned int input;
1142         int ret;
1143
1144         ret = sscanf(buf, "%u", &input);
1145         if (ret != 1)
1146                 return -EINVAL;
1147
1148         mutex_lock(&intel_pstate_driver_lock);
1149
1150         if (!intel_pstate_driver) {
1151                 mutex_unlock(&intel_pstate_driver_lock);
1152                 return -EAGAIN;
1153         }
1154
1155         mutex_lock(&intel_pstate_limits_lock);
1156
1157         global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
1158
1159         mutex_unlock(&intel_pstate_limits_lock);
1160
1161         intel_pstate_update_policies();
1162
1163         mutex_unlock(&intel_pstate_driver_lock);
1164
1165         return count;
1166 }
1167
1168 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
1169                                   const char *buf, size_t count)
1170 {
1171         unsigned int input;
1172         int ret;
1173
1174         ret = sscanf(buf, "%u", &input);
1175         if (ret != 1)
1176                 return -EINVAL;
1177
1178         mutex_lock(&intel_pstate_driver_lock);
1179
1180         if (!intel_pstate_driver) {
1181                 mutex_unlock(&intel_pstate_driver_lock);
1182                 return -EAGAIN;
1183         }
1184
1185         mutex_lock(&intel_pstate_limits_lock);
1186
1187         global.min_perf_pct = clamp_t(int, input,
1188                                       min_perf_pct_min(), global.max_perf_pct);
1189
1190         mutex_unlock(&intel_pstate_limits_lock);
1191
1192         intel_pstate_update_policies();
1193
1194         mutex_unlock(&intel_pstate_driver_lock);
1195
1196         return count;
1197 }
1198
1199 show_one(max_perf_pct, max_perf_pct);
1200 show_one(min_perf_pct, min_perf_pct);
1201
1202 define_one_global_rw(status);
1203 define_one_global_rw(no_turbo);
1204 define_one_global_rw(max_perf_pct);
1205 define_one_global_rw(min_perf_pct);
1206 define_one_global_ro(turbo_pct);
1207 define_one_global_ro(num_pstates);
1208
1209 static struct attribute *intel_pstate_attributes[] = {
1210         &status.attr,
1211         &no_turbo.attr,
1212         &turbo_pct.attr,
1213         &num_pstates.attr,
1214         NULL
1215 };
1216
1217 static const struct attribute_group intel_pstate_attr_group = {
1218         .attrs = intel_pstate_attributes,
1219 };
1220
1221 static void __init intel_pstate_sysfs_expose_params(void)
1222 {
1223         struct kobject *intel_pstate_kobject;
1224         int rc;
1225
1226         intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1227                                                 &cpu_subsys.dev_root->kobj);
1228         if (WARN_ON(!intel_pstate_kobject))
1229                 return;
1230
1231         rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1232         if (WARN_ON(rc))
1233                 return;
1234
1235         /*
1236          * If per cpu limits are enforced there are no global limits, so
1237          * return without creating max/min_perf_pct attributes
1238          */
1239         if (per_cpu_limits)
1240                 return;
1241
1242         rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1243         WARN_ON(rc);
1244
1245         rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1246         WARN_ON(rc);
1247
1248 }
1249 /************************** sysfs end ************************/
1250
1251 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1252 {
1253         /* First disable HWP notification interrupt as we don't process them */
1254         if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
1255                 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1256
1257         wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1258         cpudata->epp_policy = 0;
1259         if (cpudata->epp_default == -EINVAL)
1260                 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1261 }
1262
1263 #define MSR_IA32_POWER_CTL_BIT_EE       19
1264
1265 /* Disable energy efficiency optimization */
1266 static void intel_pstate_disable_ee(int cpu)
1267 {
1268         u64 power_ctl;
1269         int ret;
1270
1271         ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl);
1272         if (ret)
1273                 return;
1274
1275         if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) {
1276                 pr_info("Disabling energy efficiency optimization\n");
1277                 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1278                 wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl);
1279         }
1280 }
1281
1282 static int atom_get_min_pstate(void)
1283 {
1284         u64 value;
1285
1286         rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1287         return (value >> 8) & 0x7F;
1288 }
1289
1290 static int atom_get_max_pstate(void)
1291 {
1292         u64 value;
1293
1294         rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1295         return (value >> 16) & 0x7F;
1296 }
1297
1298 static int atom_get_turbo_pstate(void)
1299 {
1300         u64 value;
1301
1302         rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1303         return value & 0x7F;
1304 }
1305
1306 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1307 {
1308         u64 val;
1309         int32_t vid_fp;
1310         u32 vid;
1311
1312         val = (u64)pstate << 8;
1313         if (global.no_turbo && !global.turbo_disabled)
1314                 val |= (u64)1 << 32;
1315
1316         vid_fp = cpudata->vid.min + mul_fp(
1317                 int_tofp(pstate - cpudata->pstate.min_pstate),
1318                 cpudata->vid.ratio);
1319
1320         vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1321         vid = ceiling_fp(vid_fp);
1322
1323         if (pstate > cpudata->pstate.max_pstate)
1324                 vid = cpudata->vid.turbo;
1325
1326         return val | vid;
1327 }
1328
1329 static int silvermont_get_scaling(void)
1330 {
1331         u64 value;
1332         int i;
1333         /* Defined in Table 35-6 from SDM (Sept 2015) */
1334         static int silvermont_freq_table[] = {
1335                 83300, 100000, 133300, 116700, 80000};
1336
1337         rdmsrl(MSR_FSB_FREQ, value);
1338         i = value & 0x7;
1339         WARN_ON(i > 4);
1340
1341         return silvermont_freq_table[i];
1342 }
1343
1344 static int airmont_get_scaling(void)
1345 {
1346         u64 value;
1347         int i;
1348         /* Defined in Table 35-10 from SDM (Sept 2015) */
1349         static int airmont_freq_table[] = {
1350                 83300, 100000, 133300, 116700, 80000,
1351                 93300, 90000, 88900, 87500};
1352
1353         rdmsrl(MSR_FSB_FREQ, value);
1354         i = value & 0xF;
1355         WARN_ON(i > 8);
1356
1357         return airmont_freq_table[i];
1358 }
1359
1360 static void atom_get_vid(struct cpudata *cpudata)
1361 {
1362         u64 value;
1363
1364         rdmsrl(MSR_ATOM_CORE_VIDS, value);
1365         cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1366         cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1367         cpudata->vid.ratio = div_fp(
1368                 cpudata->vid.max - cpudata->vid.min,
1369                 int_tofp(cpudata->pstate.max_pstate -
1370                         cpudata->pstate.min_pstate));
1371
1372         rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1373         cpudata->vid.turbo = value & 0x7f;
1374 }
1375
1376 static int core_get_min_pstate(void)
1377 {
1378         u64 value;
1379
1380         rdmsrl(MSR_PLATFORM_INFO, value);
1381         return (value >> 40) & 0xFF;
1382 }
1383
1384 static int core_get_max_pstate_physical(void)
1385 {
1386         u64 value;
1387
1388         rdmsrl(MSR_PLATFORM_INFO, value);
1389         return (value >> 8) & 0xFF;
1390 }
1391
1392 static int core_get_tdp_ratio(u64 plat_info)
1393 {
1394         /* Check how many TDP levels present */
1395         if (plat_info & 0x600000000) {
1396                 u64 tdp_ctrl;
1397                 u64 tdp_ratio;
1398                 int tdp_msr;
1399                 int err;
1400
1401                 /* Get the TDP level (0, 1, 2) to get ratios */
1402                 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1403                 if (err)
1404                         return err;
1405
1406                 /* TDP MSR are continuous starting at 0x648 */
1407                 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1408                 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1409                 if (err)
1410                         return err;
1411
1412                 /* For level 1 and 2, bits[23:16] contain the ratio */
1413                 if (tdp_ctrl & 0x03)
1414                         tdp_ratio >>= 16;
1415
1416                 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1417                 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1418
1419                 return (int)tdp_ratio;
1420         }
1421
1422         return -ENXIO;
1423 }
1424
1425 static int core_get_max_pstate(void)
1426 {
1427         u64 tar;
1428         u64 plat_info;
1429         int max_pstate;
1430         int tdp_ratio;
1431         int err;
1432
1433         rdmsrl(MSR_PLATFORM_INFO, plat_info);
1434         max_pstate = (plat_info >> 8) & 0xFF;
1435
1436         tdp_ratio = core_get_tdp_ratio(plat_info);
1437         if (tdp_ratio <= 0)
1438                 return max_pstate;
1439
1440         if (hwp_active) {
1441                 /* Turbo activation ratio is not used on HWP platforms */
1442                 return tdp_ratio;
1443         }
1444
1445         err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1446         if (!err) {
1447                 int tar_levels;
1448
1449                 /* Do some sanity checking for safety */
1450                 tar_levels = tar & 0xff;
1451                 if (tdp_ratio - 1 == tar_levels) {
1452                         max_pstate = tar_levels;
1453                         pr_debug("max_pstate=TAC %x\n", max_pstate);
1454                 }
1455         }
1456
1457         return max_pstate;
1458 }
1459
1460 static int core_get_turbo_pstate(void)
1461 {
1462         u64 value;
1463         int nont, ret;
1464
1465         rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1466         nont = core_get_max_pstate();
1467         ret = (value) & 255;
1468         if (ret <= nont)
1469                 ret = nont;
1470         return ret;
1471 }
1472
1473 static inline int core_get_scaling(void)
1474 {
1475         return 100000;
1476 }
1477
1478 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1479 {
1480         u64 val;
1481
1482         val = (u64)pstate << 8;
1483         if (global.no_turbo && !global.turbo_disabled)
1484                 val |= (u64)1 << 32;
1485
1486         return val;
1487 }
1488
1489 static int knl_get_turbo_pstate(void)
1490 {
1491         u64 value;
1492         int nont, ret;
1493
1494         rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1495         nont = core_get_max_pstate();
1496         ret = (((value) >> 8) & 0xFF);
1497         if (ret <= nont)
1498                 ret = nont;
1499         return ret;
1500 }
1501
1502 static int intel_pstate_get_base_pstate(struct cpudata *cpu)
1503 {
1504         return global.no_turbo || global.turbo_disabled ?
1505                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1506 }
1507
1508 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1509 {
1510         trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1511         cpu->pstate.current_pstate = pstate;
1512         /*
1513          * Generally, there is no guarantee that this code will always run on
1514          * the CPU being updated, so force the register update to run on the
1515          * right CPU.
1516          */
1517         wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1518                       pstate_funcs.get_val(cpu, pstate));
1519 }
1520
1521 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1522 {
1523         intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1524 }
1525
1526 static void intel_pstate_max_within_limits(struct cpudata *cpu)
1527 {
1528         int pstate;
1529
1530         update_turbo_state();
1531         pstate = intel_pstate_get_base_pstate(cpu);
1532         pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
1533         intel_pstate_set_pstate(cpu, pstate);
1534 }
1535
1536 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1537 {
1538         cpu->pstate.min_pstate = pstate_funcs.get_min();
1539         cpu->pstate.max_pstate = pstate_funcs.get_max();
1540         cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
1541         cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
1542         cpu->pstate.scaling = pstate_funcs.get_scaling();
1543         cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1544         cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1545
1546         if (pstate_funcs.get_vid)
1547                 pstate_funcs.get_vid(cpu);
1548
1549         intel_pstate_set_min_pstate(cpu);
1550 }
1551
1552 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
1553 {
1554         struct sample *sample = &cpu->sample;
1555
1556         sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
1557 }
1558
1559 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
1560 {
1561         u64 aperf, mperf;
1562         unsigned long flags;
1563         u64 tsc;
1564
1565         local_irq_save(flags);
1566         rdmsrl(MSR_IA32_APERF, aperf);
1567         rdmsrl(MSR_IA32_MPERF, mperf);
1568         tsc = rdtsc();
1569         if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
1570                 local_irq_restore(flags);
1571                 return false;
1572         }
1573         local_irq_restore(flags);
1574
1575         cpu->last_sample_time = cpu->sample.time;
1576         cpu->sample.time = time;
1577         cpu->sample.aperf = aperf;
1578         cpu->sample.mperf = mperf;
1579         cpu->sample.tsc =  tsc;
1580         cpu->sample.aperf -= cpu->prev_aperf;
1581         cpu->sample.mperf -= cpu->prev_mperf;
1582         cpu->sample.tsc -= cpu->prev_tsc;
1583
1584         cpu->prev_aperf = aperf;
1585         cpu->prev_mperf = mperf;
1586         cpu->prev_tsc = tsc;
1587         /*
1588          * First time this function is invoked in a given cycle, all of the
1589          * previous sample data fields are equal to zero or stale and they must
1590          * be populated with meaningful numbers for things to work, so assume
1591          * that sample.time will always be reset before setting the utilization
1592          * update hook and make the caller skip the sample then.
1593          */
1594         if (cpu->last_sample_time) {
1595                 intel_pstate_calc_avg_perf(cpu);
1596                 return true;
1597         }
1598         return false;
1599 }
1600
1601 static inline int32_t get_avg_frequency(struct cpudata *cpu)
1602 {
1603         return mul_ext_fp(cpu->sample.core_avg_perf,
1604                           cpu->pstate.max_pstate_physical * cpu->pstate.scaling);
1605 }
1606
1607 static inline int32_t get_avg_pstate(struct cpudata *cpu)
1608 {
1609         return mul_ext_fp(cpu->pstate.max_pstate_physical,
1610                           cpu->sample.core_avg_perf);
1611 }
1612
1613 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu)
1614 {
1615         struct sample *sample = &cpu->sample;
1616         int32_t busy_frac, boost;
1617         int target, avg_pstate;
1618
1619         busy_frac = div_fp(sample->mperf, sample->tsc);
1620
1621         boost = cpu->iowait_boost;
1622         cpu->iowait_boost >>= 1;
1623
1624         if (busy_frac < boost)
1625                 busy_frac = boost;
1626
1627         sample->busy_scaled = busy_frac * 100;
1628
1629         target = global.no_turbo || global.turbo_disabled ?
1630                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1631         target += target >> 2;
1632         target = mul_fp(target, busy_frac);
1633         if (target < cpu->pstate.min_pstate)
1634                 target = cpu->pstate.min_pstate;
1635
1636         /*
1637          * If the average P-state during the previous cycle was higher than the
1638          * current target, add 50% of the difference to the target to reduce
1639          * possible performance oscillations and offset possible performance
1640          * loss related to moving the workload from one CPU to another within
1641          * a package/module.
1642          */
1643         avg_pstate = get_avg_pstate(cpu);
1644         if (avg_pstate > target)
1645                 target += (avg_pstate - target) >> 1;
1646
1647         return target;
1648 }
1649
1650 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu)
1651 {
1652         int32_t perf_scaled, max_pstate, current_pstate, sample_ratio;
1653         u64 duration_ns;
1654
1655         /*
1656          * perf_scaled is the ratio of the average P-state during the last
1657          * sampling period to the P-state requested last time (in percent).
1658          *
1659          * That measures the system's response to the previous P-state
1660          * selection.
1661          */
1662         max_pstate = cpu->pstate.max_pstate_physical;
1663         current_pstate = cpu->pstate.current_pstate;
1664         perf_scaled = mul_ext_fp(cpu->sample.core_avg_perf,
1665                                div_fp(100 * max_pstate, current_pstate));
1666
1667         /*
1668          * Since our utilization update callback will not run unless we are
1669          * in C0, check if the actual elapsed time is significantly greater (3x)
1670          * than our sample interval.  If it is, then we were idle for a long
1671          * enough period of time to adjust our performance metric.
1672          */
1673         duration_ns = cpu->sample.time - cpu->last_sample_time;
1674         if ((s64)duration_ns > pid_params.sample_rate_ns * 3) {
1675                 sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns);
1676                 perf_scaled = mul_fp(perf_scaled, sample_ratio);
1677         } else {
1678                 sample_ratio = div_fp(100 * cpu->sample.mperf, cpu->sample.tsc);
1679                 if (sample_ratio < int_tofp(1))
1680                         perf_scaled = 0;
1681         }
1682
1683         cpu->sample.busy_scaled = perf_scaled;
1684         return cpu->pstate.current_pstate - pid_calc(&cpu->pid, perf_scaled);
1685 }
1686
1687 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
1688 {
1689         int max_pstate = intel_pstate_get_base_pstate(cpu);
1690         int min_pstate;
1691
1692         min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
1693         max_pstate = max(min_pstate, cpu->max_perf_ratio);
1694         return clamp_t(int, pstate, min_pstate, max_pstate);
1695 }
1696
1697 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1698 {
1699         if (pstate == cpu->pstate.current_pstate)
1700                 return;
1701
1702         cpu->pstate.current_pstate = pstate;
1703         wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1704 }
1705
1706 static void intel_pstate_adjust_pstate(struct cpudata *cpu, int target_pstate)
1707 {
1708         int from = cpu->pstate.current_pstate;
1709         struct sample *sample;
1710
1711         update_turbo_state();
1712
1713         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1714         trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
1715         intel_pstate_update_pstate(cpu, target_pstate);
1716
1717         sample = &cpu->sample;
1718         trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
1719                 fp_toint(sample->busy_scaled),
1720                 from,
1721                 cpu->pstate.current_pstate,
1722                 sample->mperf,
1723                 sample->aperf,
1724                 sample->tsc,
1725                 get_avg_frequency(cpu),
1726                 fp_toint(cpu->iowait_boost * 100));
1727 }
1728
1729 static void intel_pstate_update_util_pid(struct update_util_data *data,
1730                                          u64 time, unsigned int flags)
1731 {
1732         struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1733         u64 delta_ns = time - cpu->sample.time;
1734
1735         if ((s64)delta_ns < pid_params.sample_rate_ns)
1736                 return;
1737
1738         if (intel_pstate_sample(cpu, time)) {
1739                 int target_pstate;
1740
1741                 target_pstate = get_target_pstate_use_performance(cpu);
1742                 intel_pstate_adjust_pstate(cpu, target_pstate);
1743         }
1744 }
1745
1746 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
1747                                      unsigned int flags)
1748 {
1749         struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1750         u64 delta_ns;
1751
1752         if (flags & SCHED_CPUFREQ_IOWAIT) {
1753                 cpu->iowait_boost = int_tofp(1);
1754         } else if (cpu->iowait_boost) {
1755                 /* Clear iowait_boost if the CPU may have been idle. */
1756                 delta_ns = time - cpu->last_update;
1757                 if (delta_ns > TICK_NSEC)
1758                         cpu->iowait_boost = 0;
1759         }
1760         cpu->last_update = time;
1761         delta_ns = time - cpu->sample.time;
1762         if ((s64)delta_ns < INTEL_PSTATE_DEFAULT_SAMPLING_INTERVAL)
1763                 return;
1764
1765         if (intel_pstate_sample(cpu, time)) {
1766                 int target_pstate;
1767
1768                 target_pstate = get_target_pstate_use_cpu_load(cpu);
1769                 intel_pstate_adjust_pstate(cpu, target_pstate);
1770         }
1771 }
1772
1773 static struct pstate_funcs core_funcs = {
1774         .get_max = core_get_max_pstate,
1775         .get_max_physical = core_get_max_pstate_physical,
1776         .get_min = core_get_min_pstate,
1777         .get_turbo = core_get_turbo_pstate,
1778         .get_scaling = core_get_scaling,
1779         .get_val = core_get_val,
1780         .update_util = intel_pstate_update_util_pid,
1781 };
1782
1783 static const struct pstate_funcs silvermont_funcs = {
1784         .get_max = atom_get_max_pstate,
1785         .get_max_physical = atom_get_max_pstate,
1786         .get_min = atom_get_min_pstate,
1787         .get_turbo = atom_get_turbo_pstate,
1788         .get_val = atom_get_val,
1789         .get_scaling = silvermont_get_scaling,
1790         .get_vid = atom_get_vid,
1791         .update_util = intel_pstate_update_util,
1792 };
1793
1794 static const struct pstate_funcs airmont_funcs = {
1795         .get_max = atom_get_max_pstate,
1796         .get_max_physical = atom_get_max_pstate,
1797         .get_min = atom_get_min_pstate,
1798         .get_turbo = atom_get_turbo_pstate,
1799         .get_val = atom_get_val,
1800         .get_scaling = airmont_get_scaling,
1801         .get_vid = atom_get_vid,
1802         .update_util = intel_pstate_update_util,
1803 };
1804
1805 static const struct pstate_funcs knl_funcs = {
1806         .get_max = core_get_max_pstate,
1807         .get_max_physical = core_get_max_pstate_physical,
1808         .get_min = core_get_min_pstate,
1809         .get_turbo = knl_get_turbo_pstate,
1810         .get_scaling = core_get_scaling,
1811         .get_val = core_get_val,
1812         .update_util = intel_pstate_update_util_pid,
1813 };
1814
1815 static const struct pstate_funcs bxt_funcs = {
1816         .get_max = core_get_max_pstate,
1817         .get_max_physical = core_get_max_pstate_physical,
1818         .get_min = core_get_min_pstate,
1819         .get_turbo = core_get_turbo_pstate,
1820         .get_scaling = core_get_scaling,
1821         .get_val = core_get_val,
1822         .update_util = intel_pstate_update_util,
1823 };
1824
1825 #define ICPU(model, policy) \
1826         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1827                         (unsigned long)&policy }
1828
1829 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
1830         ICPU(INTEL_FAM6_SANDYBRIDGE,            core_funcs),
1831         ICPU(INTEL_FAM6_SANDYBRIDGE_X,          core_funcs),
1832         ICPU(INTEL_FAM6_ATOM_SILVERMONT1,       silvermont_funcs),
1833         ICPU(INTEL_FAM6_IVYBRIDGE,              core_funcs),
1834         ICPU(INTEL_FAM6_HASWELL_CORE,           core_funcs),
1835         ICPU(INTEL_FAM6_BROADWELL_CORE,         core_funcs),
1836         ICPU(INTEL_FAM6_IVYBRIDGE_X,            core_funcs),
1837         ICPU(INTEL_FAM6_HASWELL_X,              core_funcs),
1838         ICPU(INTEL_FAM6_HASWELL_ULT,            core_funcs),
1839         ICPU(INTEL_FAM6_HASWELL_GT3E,           core_funcs),
1840         ICPU(INTEL_FAM6_BROADWELL_GT3E,         core_funcs),
1841         ICPU(INTEL_FAM6_ATOM_AIRMONT,           airmont_funcs),
1842         ICPU(INTEL_FAM6_SKYLAKE_MOBILE,         core_funcs),
1843         ICPU(INTEL_FAM6_BROADWELL_X,            core_funcs),
1844         ICPU(INTEL_FAM6_SKYLAKE_DESKTOP,        core_funcs),
1845         ICPU(INTEL_FAM6_BROADWELL_XEON_D,       core_funcs),
1846         ICPU(INTEL_FAM6_XEON_PHI_KNL,           knl_funcs),
1847         ICPU(INTEL_FAM6_XEON_PHI_KNM,           knl_funcs),
1848         ICPU(INTEL_FAM6_ATOM_GOLDMONT,          bxt_funcs),
1849         ICPU(INTEL_FAM6_ATOM_GEMINI_LAKE,       bxt_funcs),
1850         {}
1851 };
1852 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1853
1854 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
1855         ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
1856         ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
1857         ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
1858         {}
1859 };
1860
1861 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
1862         ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_funcs),
1863         {}
1864 };
1865
1866 static bool pid_in_use(void);
1867
1868 static int intel_pstate_init_cpu(unsigned int cpunum)
1869 {
1870         struct cpudata *cpu;
1871
1872         cpu = all_cpu_data[cpunum];
1873
1874         if (!cpu) {
1875                 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
1876                 if (!cpu)
1877                         return -ENOMEM;
1878
1879                 all_cpu_data[cpunum] = cpu;
1880
1881                 cpu->epp_default = -EINVAL;
1882                 cpu->epp_powersave = -EINVAL;
1883                 cpu->epp_saved = -EINVAL;
1884         }
1885
1886         cpu = all_cpu_data[cpunum];
1887
1888         cpu->cpu = cpunum;
1889
1890         if (hwp_active) {
1891                 const struct x86_cpu_id *id;
1892
1893                 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
1894                 if (id)
1895                         intel_pstate_disable_ee(cpunum);
1896
1897                 intel_pstate_hwp_enable(cpu);
1898         } else if (pid_in_use()) {
1899                 intel_pstate_pid_reset(cpu);
1900         }
1901
1902         intel_pstate_get_cpu_pstates(cpu);
1903
1904         pr_debug("controlling: cpu %d\n", cpunum);
1905
1906         return 0;
1907 }
1908
1909 static unsigned int intel_pstate_get(unsigned int cpu_num)
1910 {
1911         struct cpudata *cpu = all_cpu_data[cpu_num];
1912
1913         return cpu ? get_avg_frequency(cpu) : 0;
1914 }
1915
1916 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
1917 {
1918         struct cpudata *cpu = all_cpu_data[cpu_num];
1919
1920         if (hwp_active)
1921                 return;
1922
1923         if (cpu->update_util_set)
1924                 return;
1925
1926         /* Prevent intel_pstate_update_util() from using stale data. */
1927         cpu->sample.time = 0;
1928         cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
1929                                      pstate_funcs.update_util);
1930         cpu->update_util_set = true;
1931 }
1932
1933 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
1934 {
1935         struct cpudata *cpu_data = all_cpu_data[cpu];
1936
1937         if (!cpu_data->update_util_set)
1938                 return;
1939
1940         cpufreq_remove_update_util_hook(cpu);
1941         cpu_data->update_util_set = false;
1942         synchronize_sched();
1943 }
1944
1945 static int intel_pstate_get_max_freq(struct cpudata *cpu)
1946 {
1947         return global.turbo_disabled || global.no_turbo ?
1948                         cpu->pstate.max_freq : cpu->pstate.turbo_freq;
1949 }
1950
1951 static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
1952                                             struct cpudata *cpu)
1953 {
1954         int max_freq = intel_pstate_get_max_freq(cpu);
1955         int32_t max_policy_perf, min_policy_perf;
1956         int max_state, turbo_max;
1957
1958         /*
1959          * HWP needs some special consideration, because on BDX the
1960          * HWP_REQUEST uses abstract value to represent performance
1961          * rather than pure ratios.
1962          */
1963         if (hwp_active) {
1964                 intel_pstate_get_hwp_max(cpu->cpu, &turbo_max, &max_state);
1965         } else {
1966                 max_state = intel_pstate_get_base_pstate(cpu);
1967                 turbo_max = cpu->pstate.turbo_pstate;
1968         }
1969
1970         max_policy_perf = max_state * policy->max / max_freq;
1971         if (policy->max == policy->min) {
1972                 min_policy_perf = max_policy_perf;
1973         } else {
1974                 min_policy_perf = max_state * policy->min / max_freq;
1975                 min_policy_perf = clamp_t(int32_t, min_policy_perf,
1976                                           0, max_policy_perf);
1977         }
1978
1979         pr_debug("cpu:%d max_state %d min_policy_perf:%d max_policy_perf:%d\n",
1980                  policy->cpu, max_state,
1981                  min_policy_perf, max_policy_perf);
1982
1983         /* Normalize user input to [min_perf, max_perf] */
1984         if (per_cpu_limits) {
1985                 cpu->min_perf_ratio = min_policy_perf;
1986                 cpu->max_perf_ratio = max_policy_perf;
1987         } else {
1988                 int32_t global_min, global_max;
1989
1990                 /* Global limits are in percent of the maximum turbo P-state. */
1991                 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
1992                 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
1993                 global_min = clamp_t(int32_t, global_min, 0, global_max);
1994
1995                 pr_debug("cpu:%d global_min:%d global_max:%d\n", policy->cpu,
1996                          global_min, global_max);
1997
1998                 cpu->min_perf_ratio = max(min_policy_perf, global_min);
1999                 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
2000                 cpu->max_perf_ratio = min(max_policy_perf, global_max);
2001                 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
2002
2003                 /* Make sure min_perf <= max_perf */
2004                 cpu->min_perf_ratio = min(cpu->min_perf_ratio,
2005                                           cpu->max_perf_ratio);
2006
2007         }
2008         pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", policy->cpu,
2009                  cpu->max_perf_ratio,
2010                  cpu->min_perf_ratio);
2011 }
2012
2013 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2014 {
2015         struct cpudata *cpu;
2016
2017         if (!policy->cpuinfo.max_freq)
2018                 return -ENODEV;
2019
2020         pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2021                  policy->cpuinfo.max_freq, policy->max);
2022
2023         cpu = all_cpu_data[policy->cpu];
2024         cpu->policy = policy->policy;
2025
2026         mutex_lock(&intel_pstate_limits_lock);
2027
2028         intel_pstate_update_perf_limits(policy, cpu);
2029
2030         if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2031                 /*
2032                  * NOHZ_FULL CPUs need this as the governor callback may not
2033                  * be invoked on them.
2034                  */
2035                 intel_pstate_clear_update_util_hook(policy->cpu);
2036                 intel_pstate_max_within_limits(cpu);
2037         } else {
2038                 intel_pstate_set_update_util_hook(policy->cpu);
2039         }
2040
2041         if (hwp_active)
2042                 intel_pstate_hwp_set(policy->cpu);
2043
2044         mutex_unlock(&intel_pstate_limits_lock);
2045
2046         return 0;
2047 }
2048
2049 static void intel_pstate_adjust_policy_max(struct cpufreq_policy *policy,
2050                                          struct cpudata *cpu)
2051 {
2052         if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2053             policy->max < policy->cpuinfo.max_freq &&
2054             policy->max > cpu->pstate.max_freq) {
2055                 pr_debug("policy->max > max non turbo frequency\n");
2056                 policy->max = policy->cpuinfo.max_freq;
2057         }
2058 }
2059
2060 static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
2061 {
2062         struct cpudata *cpu = all_cpu_data[policy->cpu];
2063
2064         update_turbo_state();
2065         cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2066                                      intel_pstate_get_max_freq(cpu));
2067
2068         if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
2069             policy->policy != CPUFREQ_POLICY_PERFORMANCE)
2070                 return -EINVAL;
2071
2072         intel_pstate_adjust_policy_max(policy, cpu);
2073
2074         return 0;
2075 }
2076
2077 static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)
2078 {
2079         intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);
2080 }
2081
2082 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
2083 {
2084         pr_debug("CPU %d exiting\n", policy->cpu);
2085
2086         intel_pstate_clear_update_util_hook(policy->cpu);
2087         if (hwp_active)
2088                 intel_pstate_hwp_save_state(policy);
2089         else
2090                 intel_cpufreq_stop_cpu(policy);
2091 }
2092
2093 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2094 {
2095         intel_pstate_exit_perf_limits(policy);
2096
2097         policy->fast_switch_possible = false;
2098
2099         return 0;
2100 }
2101
2102 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2103 {
2104         struct cpudata *cpu;
2105         int rc;
2106
2107         rc = intel_pstate_init_cpu(policy->cpu);
2108         if (rc)
2109                 return rc;
2110
2111         cpu = all_cpu_data[policy->cpu];
2112
2113         cpu->max_perf_ratio = 0xFF;
2114         cpu->min_perf_ratio = 0;
2115
2116         policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
2117         policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
2118
2119         /* cpuinfo and default policy values */
2120         policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
2121         update_turbo_state();
2122         policy->cpuinfo.max_freq = global.turbo_disabled ?
2123                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2124         policy->cpuinfo.max_freq *= cpu->pstate.scaling;
2125
2126         intel_pstate_init_acpi_perf_limits(policy);
2127         cpumask_set_cpu(policy->cpu, policy->cpus);
2128
2129         policy->fast_switch_possible = true;
2130
2131         return 0;
2132 }
2133
2134 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2135 {
2136         int ret = __intel_pstate_cpu_init(policy);
2137
2138         if (ret)
2139                 return ret;
2140
2141         policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
2142         if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE))
2143                 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
2144         else
2145                 policy->policy = CPUFREQ_POLICY_POWERSAVE;
2146
2147         return 0;
2148 }
2149
2150 static struct cpufreq_driver intel_pstate = {
2151         .flags          = CPUFREQ_CONST_LOOPS,
2152         .verify         = intel_pstate_verify_policy,
2153         .setpolicy      = intel_pstate_set_policy,
2154         .suspend        = intel_pstate_hwp_save_state,
2155         .resume         = intel_pstate_resume,
2156         .get            = intel_pstate_get,
2157         .init           = intel_pstate_cpu_init,
2158         .exit           = intel_pstate_cpu_exit,
2159         .stop_cpu       = intel_pstate_stop_cpu,
2160         .name           = "intel_pstate",
2161 };
2162
2163 static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy)
2164 {
2165         struct cpudata *cpu = all_cpu_data[policy->cpu];
2166
2167         update_turbo_state();
2168         cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2169                                      intel_pstate_get_max_freq(cpu));
2170
2171         intel_pstate_adjust_policy_max(policy, cpu);
2172
2173         intel_pstate_update_perf_limits(policy, cpu);
2174
2175         return 0;
2176 }
2177
2178 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2179                                 unsigned int target_freq,
2180                                 unsigned int relation)
2181 {
2182         struct cpudata *cpu = all_cpu_data[policy->cpu];
2183         struct cpufreq_freqs freqs;
2184         int target_pstate;
2185
2186         update_turbo_state();
2187
2188         freqs.old = policy->cur;
2189         freqs.new = target_freq;
2190
2191         cpufreq_freq_transition_begin(policy, &freqs);
2192         switch (relation) {
2193         case CPUFREQ_RELATION_L:
2194                 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2195                 break;
2196         case CPUFREQ_RELATION_H:
2197                 target_pstate = freqs.new / cpu->pstate.scaling;
2198                 break;
2199         default:
2200                 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2201                 break;
2202         }
2203         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2204         if (target_pstate != cpu->pstate.current_pstate) {
2205                 cpu->pstate.current_pstate = target_pstate;
2206                 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL,
2207                               pstate_funcs.get_val(cpu, target_pstate));
2208         }
2209         freqs.new = target_pstate * cpu->pstate.scaling;
2210         cpufreq_freq_transition_end(policy, &freqs, false);
2211
2212         return 0;
2213 }
2214
2215 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2216                                               unsigned int target_freq)
2217 {
2218         struct cpudata *cpu = all_cpu_data[policy->cpu];
2219         int target_pstate;
2220
2221         update_turbo_state();
2222
2223         target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2224         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2225         intel_pstate_update_pstate(cpu, target_pstate);
2226         return target_pstate * cpu->pstate.scaling;
2227 }
2228
2229 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2230 {
2231         int ret = __intel_pstate_cpu_init(policy);
2232
2233         if (ret)
2234                 return ret;
2235
2236         policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2237         policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
2238         /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2239         policy->cur = policy->cpuinfo.min_freq;
2240
2241         return 0;
2242 }
2243
2244 static struct cpufreq_driver intel_cpufreq = {
2245         .flags          = CPUFREQ_CONST_LOOPS,
2246         .verify         = intel_cpufreq_verify_policy,
2247         .target         = intel_cpufreq_target,
2248         .fast_switch    = intel_cpufreq_fast_switch,
2249         .init           = intel_cpufreq_cpu_init,
2250         .exit           = intel_pstate_cpu_exit,
2251         .stop_cpu       = intel_cpufreq_stop_cpu,
2252         .name           = "intel_cpufreq",
2253 };
2254
2255 static struct cpufreq_driver *default_driver = &intel_pstate;
2256
2257 static bool pid_in_use(void)
2258 {
2259         return intel_pstate_driver == &intel_pstate &&
2260                 pstate_funcs.update_util == intel_pstate_update_util_pid;
2261 }
2262
2263 static void intel_pstate_driver_cleanup(void)
2264 {
2265         unsigned int cpu;
2266
2267         get_online_cpus();
2268         for_each_online_cpu(cpu) {
2269                 if (all_cpu_data[cpu]) {
2270                         if (intel_pstate_driver == &intel_pstate)
2271                                 intel_pstate_clear_update_util_hook(cpu);
2272
2273                         kfree(all_cpu_data[cpu]);
2274                         all_cpu_data[cpu] = NULL;
2275                 }
2276         }
2277         put_online_cpus();
2278         intel_pstate_driver = NULL;
2279 }
2280
2281 static int intel_pstate_register_driver(struct cpufreq_driver *driver)
2282 {
2283         int ret;
2284
2285         memset(&global, 0, sizeof(global));
2286         global.max_perf_pct = 100;
2287
2288         intel_pstate_driver = driver;
2289         ret = cpufreq_register_driver(intel_pstate_driver);
2290         if (ret) {
2291                 intel_pstate_driver_cleanup();
2292                 return ret;
2293         }
2294
2295         global.min_perf_pct = min_perf_pct_min();
2296
2297         if (pid_in_use())
2298                 intel_pstate_debug_expose_params();
2299
2300         return 0;
2301 }
2302
2303 static int intel_pstate_unregister_driver(void)
2304 {
2305         if (hwp_active)
2306                 return -EBUSY;
2307
2308         if (pid_in_use())
2309                 intel_pstate_debug_hide_params();
2310
2311         cpufreq_unregister_driver(intel_pstate_driver);
2312         intel_pstate_driver_cleanup();
2313
2314         return 0;
2315 }
2316
2317 static ssize_t intel_pstate_show_status(char *buf)
2318 {
2319         if (!intel_pstate_driver)
2320                 return sprintf(buf, "off\n");
2321
2322         return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
2323                                         "active" : "passive");
2324 }
2325
2326 static int intel_pstate_update_status(const char *buf, size_t size)
2327 {
2328         int ret;
2329
2330         if (size == 3 && !strncmp(buf, "off", size))
2331                 return intel_pstate_driver ?
2332                         intel_pstate_unregister_driver() : -EINVAL;
2333
2334         if (size == 6 && !strncmp(buf, "active", size)) {
2335                 if (intel_pstate_driver) {
2336                         if (intel_pstate_driver == &intel_pstate)
2337                                 return 0;
2338
2339                         ret = intel_pstate_unregister_driver();
2340                         if (ret)
2341                                 return ret;
2342                 }
2343
2344                 return intel_pstate_register_driver(&intel_pstate);
2345         }
2346
2347         if (size == 7 && !strncmp(buf, "passive", size)) {
2348                 if (intel_pstate_driver) {
2349                         if (intel_pstate_driver == &intel_cpufreq)
2350                                 return 0;
2351
2352                         ret = intel_pstate_unregister_driver();
2353                         if (ret)
2354                                 return ret;
2355                 }
2356
2357                 return intel_pstate_register_driver(&intel_cpufreq);
2358         }
2359
2360         return -EINVAL;
2361 }
2362
2363 static int no_load __initdata;
2364 static int no_hwp __initdata;
2365 static int hwp_only __initdata;
2366 static unsigned int force_load __initdata;
2367
2368 static int __init intel_pstate_msrs_not_valid(void)
2369 {
2370         if (!pstate_funcs.get_max() ||
2371             !pstate_funcs.get_min() ||
2372             !pstate_funcs.get_turbo())
2373                 return -ENODEV;
2374
2375         return 0;
2376 }
2377
2378 #ifdef CONFIG_ACPI
2379 static void intel_pstate_use_acpi_profile(void)
2380 {
2381         switch (acpi_gbl_FADT.preferred_profile) {
2382         case PM_MOBILE:
2383         case PM_TABLET:
2384         case PM_APPLIANCE_PC:
2385         case PM_DESKTOP:
2386         case PM_WORKSTATION:
2387                 pstate_funcs.update_util = intel_pstate_update_util;
2388         }
2389 }
2390 #else
2391 static void intel_pstate_use_acpi_profile(void)
2392 {
2393 }
2394 #endif
2395
2396 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
2397 {
2398         pstate_funcs.get_max   = funcs->get_max;
2399         pstate_funcs.get_max_physical = funcs->get_max_physical;
2400         pstate_funcs.get_min   = funcs->get_min;
2401         pstate_funcs.get_turbo = funcs->get_turbo;
2402         pstate_funcs.get_scaling = funcs->get_scaling;
2403         pstate_funcs.get_val   = funcs->get_val;
2404         pstate_funcs.get_vid   = funcs->get_vid;
2405         pstate_funcs.update_util = funcs->update_util;
2406
2407         intel_pstate_use_acpi_profile();
2408 }
2409
2410 #ifdef CONFIG_ACPI
2411
2412 static bool __init intel_pstate_no_acpi_pss(void)
2413 {
2414         int i;
2415
2416         for_each_possible_cpu(i) {
2417                 acpi_status status;
2418                 union acpi_object *pss;
2419                 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2420                 struct acpi_processor *pr = per_cpu(processors, i);
2421
2422                 if (!pr)
2423                         continue;
2424
2425                 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2426                 if (ACPI_FAILURE(status))
2427                         continue;
2428
2429                 pss = buffer.pointer;
2430                 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2431                         kfree(pss);
2432                         return false;
2433                 }
2434
2435                 kfree(pss);
2436         }
2437
2438         return true;
2439 }
2440
2441 static bool __init intel_pstate_has_acpi_ppc(void)
2442 {
2443         int i;
2444
2445         for_each_possible_cpu(i) {
2446                 struct acpi_processor *pr = per_cpu(processors, i);
2447
2448                 if (!pr)
2449                         continue;
2450                 if (acpi_has_method(pr->handle, "_PPC"))
2451                         return true;
2452         }
2453         return false;
2454 }
2455
2456 enum {
2457         PSS,
2458         PPC,
2459 };
2460
2461 struct hw_vendor_info {
2462         u16  valid;
2463         char oem_id[ACPI_OEM_ID_SIZE];
2464         char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
2465         int  oem_pwr_table;
2466 };
2467
2468 /* Hardware vendor-specific info that has its own power management modes */
2469 static struct hw_vendor_info vendor_info[] __initdata = {
2470         {1, "HP    ", "ProLiant", PSS},
2471         {1, "ORACLE", "X4-2    ", PPC},
2472         {1, "ORACLE", "X4-2L   ", PPC},
2473         {1, "ORACLE", "X4-2B   ", PPC},
2474         {1, "ORACLE", "X3-2    ", PPC},
2475         {1, "ORACLE", "X3-2L   ", PPC},
2476         {1, "ORACLE", "X3-2B   ", PPC},
2477         {1, "ORACLE", "X4470M2 ", PPC},
2478         {1, "ORACLE", "X4270M3 ", PPC},
2479         {1, "ORACLE", "X4270M2 ", PPC},
2480         {1, "ORACLE", "X4170M2 ", PPC},
2481         {1, "ORACLE", "X4170 M3", PPC},
2482         {1, "ORACLE", "X4275 M3", PPC},
2483         {1, "ORACLE", "X6-2    ", PPC},
2484         {1, "ORACLE", "Sudbury ", PPC},
2485         {0, "", ""},
2486 };
2487
2488 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
2489 {
2490         struct acpi_table_header hdr;
2491         struct hw_vendor_info *v_info;
2492         const struct x86_cpu_id *id;
2493         u64 misc_pwr;
2494
2495         id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2496         if (id) {
2497                 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
2498                 if ( misc_pwr & (1 << 8))
2499                         return true;
2500         }
2501
2502         if (acpi_disabled ||
2503             ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr)))
2504                 return false;
2505
2506         for (v_info = vendor_info; v_info->valid; v_info++) {
2507                 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) &&
2508                         !strncmp(hdr.oem_table_id, v_info->oem_table_id,
2509                                                 ACPI_OEM_TABLE_ID_SIZE))
2510                         switch (v_info->oem_pwr_table) {
2511                         case PSS:
2512                                 return intel_pstate_no_acpi_pss();
2513                         case PPC:
2514                                 return intel_pstate_has_acpi_ppc() &&
2515                                         (!force_load);
2516                         }
2517         }
2518
2519         return false;
2520 }
2521
2522 static void intel_pstate_request_control_from_smm(void)
2523 {
2524         /*
2525          * It may be unsafe to request P-states control from SMM if _PPC support
2526          * has not been enabled.
2527          */
2528         if (acpi_ppc)
2529                 acpi_processor_pstate_control();
2530 }
2531 #else /* CONFIG_ACPI not enabled */
2532 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
2533 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
2534 static inline void intel_pstate_request_control_from_smm(void) {}
2535 #endif /* CONFIG_ACPI */
2536
2537 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
2538         { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP },
2539         {}
2540 };
2541
2542 static int __init intel_pstate_init(void)
2543 {
2544         int rc;
2545
2546         if (no_load)
2547                 return -ENODEV;
2548
2549         if (x86_match_cpu(hwp_support_ids)) {
2550                 copy_cpu_funcs(&core_funcs);
2551                 if (no_hwp) {
2552                         pstate_funcs.update_util = intel_pstate_update_util;
2553                 } else {
2554                         hwp_active++;
2555                         intel_pstate.attr = hwp_cpufreq_attrs;
2556                         goto hwp_cpu_matched;
2557                 }
2558         } else {
2559                 const struct x86_cpu_id *id;
2560
2561                 id = x86_match_cpu(intel_pstate_cpu_ids);
2562                 if (!id)
2563                         return -ENODEV;
2564
2565                 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
2566         }
2567
2568         if (intel_pstate_msrs_not_valid())
2569                 return -ENODEV;
2570
2571 hwp_cpu_matched:
2572         /*
2573          * The Intel pstate driver will be ignored if the platform
2574          * firmware has its own power management modes.
2575          */
2576         if (intel_pstate_platform_pwr_mgmt_exists())
2577                 return -ENODEV;
2578
2579         if (!hwp_active && hwp_only)
2580                 return -ENOTSUPP;
2581
2582         pr_info("Intel P-state driver initializing\n");
2583
2584         all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
2585         if (!all_cpu_data)
2586                 return -ENOMEM;
2587
2588         intel_pstate_request_control_from_smm();
2589
2590         intel_pstate_sysfs_expose_params();
2591
2592         mutex_lock(&intel_pstate_driver_lock);
2593         rc = intel_pstate_register_driver(default_driver);
2594         mutex_unlock(&intel_pstate_driver_lock);
2595         if (rc)
2596                 return rc;
2597
2598         if (hwp_active)
2599                 pr_info("HWP enabled\n");
2600
2601         return 0;
2602 }
2603 device_initcall(intel_pstate_init);
2604
2605 static int __init intel_pstate_setup(char *str)
2606 {
2607         if (!str)
2608                 return -EINVAL;
2609
2610         if (!strcmp(str, "disable")) {
2611                 no_load = 1;
2612         } else if (!strcmp(str, "passive")) {
2613                 pr_info("Passive mode enabled\n");
2614                 default_driver = &intel_cpufreq;
2615                 no_hwp = 1;
2616         }
2617         if (!strcmp(str, "no_hwp")) {
2618                 pr_info("HWP disabled\n");
2619                 no_hwp = 1;
2620         }
2621         if (!strcmp(str, "force"))
2622                 force_load = 1;
2623         if (!strcmp(str, "hwp_only"))
2624                 hwp_only = 1;
2625         if (!strcmp(str, "per_cpu_perf_limits"))
2626                 per_cpu_limits = true;
2627
2628 #ifdef CONFIG_ACPI
2629         if (!strcmp(str, "support_acpi_ppc"))
2630                 acpi_ppc = true;
2631 #endif
2632
2633         return 0;
2634 }
2635 early_param("intel_pstate", intel_pstate_setup);
2636
2637 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2638 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2639 MODULE_LICENSE("GPL");