Merge tag 'pm-5.1-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael...
[muen/linux.git] / drivers / cpufreq / intel_pstate.c
1 /*
2  * intel_pstate.c: Native P state management for Intel processors
3  *
4  * (C) Copyright 2012 Intel Corporation
5  * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License
9  * as published by the Free Software Foundation; version 2
10  * of the License.
11  */
12
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
15 #include <linux/kernel.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/module.h>
18 #include <linux/ktime.h>
19 #include <linux/hrtimer.h>
20 #include <linux/tick.h>
21 #include <linux/slab.h>
22 #include <linux/sched/cpufreq.h>
23 #include <linux/list.h>
24 #include <linux/cpu.h>
25 #include <linux/cpufreq.h>
26 #include <linux/sysfs.h>
27 #include <linux/types.h>
28 #include <linux/fs.h>
29 #include <linux/acpi.h>
30 #include <linux/vmalloc.h>
31 #include <trace/events/power.h>
32
33 #include <asm/div64.h>
34 #include <asm/msr.h>
35 #include <asm/cpu_device_id.h>
36 #include <asm/cpufeature.h>
37 #include <asm/intel-family.h>
38
39 #define INTEL_PSTATE_SAMPLING_INTERVAL  (10 * NSEC_PER_MSEC)
40
41 #define INTEL_CPUFREQ_TRANSITION_LATENCY        20000
42 #define INTEL_CPUFREQ_TRANSITION_DELAY          500
43
44 #ifdef CONFIG_ACPI
45 #include <acpi/processor.h>
46 #include <acpi/cppc_acpi.h>
47 #endif
48
49 #define FRAC_BITS 8
50 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
51 #define fp_toint(X) ((X) >> FRAC_BITS)
52
53 #define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3))
54
55 #define EXT_BITS 6
56 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
57 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
58 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
59
60 static inline int32_t mul_fp(int32_t x, int32_t y)
61 {
62         return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
63 }
64
65 static inline int32_t div_fp(s64 x, s64 y)
66 {
67         return div64_s64((int64_t)x << FRAC_BITS, y);
68 }
69
70 static inline int ceiling_fp(int32_t x)
71 {
72         int mask, ret;
73
74         ret = fp_toint(x);
75         mask = (1 << FRAC_BITS) - 1;
76         if (x & mask)
77                 ret += 1;
78         return ret;
79 }
80
81 static inline int32_t percent_fp(int percent)
82 {
83         return div_fp(percent, 100);
84 }
85
86 static inline u64 mul_ext_fp(u64 x, u64 y)
87 {
88         return (x * y) >> EXT_FRAC_BITS;
89 }
90
91 static inline u64 div_ext_fp(u64 x, u64 y)
92 {
93         return div64_u64(x << EXT_FRAC_BITS, y);
94 }
95
96 static inline int32_t percent_ext_fp(int percent)
97 {
98         return div_ext_fp(percent, 100);
99 }
100
101 /**
102  * struct sample -      Store performance sample
103  * @core_avg_perf:      Ratio of APERF/MPERF which is the actual average
104  *                      performance during last sample period
105  * @busy_scaled:        Scaled busy value which is used to calculate next
106  *                      P state. This can be different than core_avg_perf
107  *                      to account for cpu idle period
108  * @aperf:              Difference of actual performance frequency clock count
109  *                      read from APERF MSR between last and current sample
110  * @mperf:              Difference of maximum performance frequency clock count
111  *                      read from MPERF MSR between last and current sample
112  * @tsc:                Difference of time stamp counter between last and
113  *                      current sample
114  * @time:               Current time from scheduler
115  *
116  * This structure is used in the cpudata structure to store performance sample
117  * data for choosing next P State.
118  */
119 struct sample {
120         int32_t core_avg_perf;
121         int32_t busy_scaled;
122         u64 aperf;
123         u64 mperf;
124         u64 tsc;
125         u64 time;
126 };
127
128 /**
129  * struct pstate_data - Store P state data
130  * @current_pstate:     Current requested P state
131  * @min_pstate:         Min P state possible for this platform
132  * @max_pstate:         Max P state possible for this platform
133  * @max_pstate_physical:This is physical Max P state for a processor
134  *                      This can be higher than the max_pstate which can
135  *                      be limited by platform thermal design power limits
136  * @scaling:            Scaling factor to  convert frequency to cpufreq
137  *                      frequency units
138  * @turbo_pstate:       Max Turbo P state possible for this platform
139  * @max_freq:           @max_pstate frequency in cpufreq units
140  * @turbo_freq:         @turbo_pstate frequency in cpufreq units
141  *
142  * Stores the per cpu model P state limits and current P state.
143  */
144 struct pstate_data {
145         int     current_pstate;
146         int     min_pstate;
147         int     max_pstate;
148         int     max_pstate_physical;
149         int     scaling;
150         int     turbo_pstate;
151         unsigned int max_freq;
152         unsigned int turbo_freq;
153 };
154
155 /**
156  * struct vid_data -    Stores voltage information data
157  * @min:                VID data for this platform corresponding to
158  *                      the lowest P state
159  * @max:                VID data corresponding to the highest P State.
160  * @turbo:              VID data for turbo P state
161  * @ratio:              Ratio of (vid max - vid min) /
162  *                      (max P state - Min P State)
163  *
164  * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
165  * This data is used in Atom platforms, where in addition to target P state,
166  * the voltage data needs to be specified to select next P State.
167  */
168 struct vid_data {
169         int min;
170         int max;
171         int turbo;
172         int32_t ratio;
173 };
174
175 /**
176  * struct global_params - Global parameters, mostly tunable via sysfs.
177  * @no_turbo:           Whether or not to use turbo P-states.
178  * @turbo_disabled:     Whethet or not turbo P-states are available at all,
179  *                      based on the MSR_IA32_MISC_ENABLE value and whether or
180  *                      not the maximum reported turbo P-state is different from
181  *                      the maximum reported non-turbo one.
182  * @min_perf_pct:       Minimum capacity limit in percent of the maximum turbo
183  *                      P-state capacity.
184  * @max_perf_pct:       Maximum capacity limit in percent of the maximum turbo
185  *                      P-state capacity.
186  */
187 struct global_params {
188         bool no_turbo;
189         bool turbo_disabled;
190         int max_perf_pct;
191         int min_perf_pct;
192 };
193
194 /**
195  * struct cpudata -     Per CPU instance data storage
196  * @cpu:                CPU number for this instance data
197  * @policy:             CPUFreq policy value
198  * @update_util:        CPUFreq utility callback information
199  * @update_util_set:    CPUFreq utility callback is set
200  * @iowait_boost:       iowait-related boost fraction
201  * @last_update:        Time of the last update.
202  * @pstate:             Stores P state limits for this CPU
203  * @vid:                Stores VID limits for this CPU
204  * @last_sample_time:   Last Sample time
205  * @aperf_mperf_shift:  Number of clock cycles after aperf, merf is incremented
206  *                      This shift is a multiplier to mperf delta to
207  *                      calculate CPU busy.
208  * @prev_aperf:         Last APERF value read from APERF MSR
209  * @prev_mperf:         Last MPERF value read from MPERF MSR
210  * @prev_tsc:           Last timestamp counter (TSC) value
211  * @prev_cummulative_iowait: IO Wait time difference from last and
212  *                      current sample
213  * @sample:             Storage for storing last Sample data
214  * @min_perf_ratio:     Minimum capacity in terms of PERF or HWP ratios
215  * @max_perf_ratio:     Maximum capacity in terms of PERF or HWP ratios
216  * @acpi_perf_data:     Stores ACPI perf information read from _PSS
217  * @valid_pss_table:    Set to true for valid ACPI _PSS entries found
218  * @epp_powersave:      Last saved HWP energy performance preference
219  *                      (EPP) or energy performance bias (EPB),
220  *                      when policy switched to performance
221  * @epp_policy:         Last saved policy used to set EPP/EPB
222  * @epp_default:        Power on default HWP energy performance
223  *                      preference/bias
224  * @epp_saved:          Saved EPP/EPB during system suspend or CPU offline
225  *                      operation
226  * @hwp_req_cached:     Cached value of the last HWP Request MSR
227  * @hwp_cap_cached:     Cached value of the last HWP Capabilities MSR
228  * @last_io_update:     Last time when IO wake flag was set
229  * @sched_flags:        Store scheduler flags for possible cross CPU update
230  * @hwp_boost_min:      Last HWP boosted min performance
231  *
232  * This structure stores per CPU instance data for all CPUs.
233  */
234 struct cpudata {
235         int cpu;
236
237         unsigned int policy;
238         struct update_util_data update_util;
239         bool   update_util_set;
240
241         struct pstate_data pstate;
242         struct vid_data vid;
243
244         u64     last_update;
245         u64     last_sample_time;
246         u64     aperf_mperf_shift;
247         u64     prev_aperf;
248         u64     prev_mperf;
249         u64     prev_tsc;
250         u64     prev_cummulative_iowait;
251         struct sample sample;
252         int32_t min_perf_ratio;
253         int32_t max_perf_ratio;
254 #ifdef CONFIG_ACPI
255         struct acpi_processor_performance acpi_perf_data;
256         bool valid_pss_table;
257 #endif
258         unsigned int iowait_boost;
259         s16 epp_powersave;
260         s16 epp_policy;
261         s16 epp_default;
262         s16 epp_saved;
263         u64 hwp_req_cached;
264         u64 hwp_cap_cached;
265         u64 last_io_update;
266         unsigned int sched_flags;
267         u32 hwp_boost_min;
268 };
269
270 static struct cpudata **all_cpu_data;
271
272 /**
273  * struct pstate_funcs - Per CPU model specific callbacks
274  * @get_max:            Callback to get maximum non turbo effective P state
275  * @get_max_physical:   Callback to get maximum non turbo physical P state
276  * @get_min:            Callback to get minimum P state
277  * @get_turbo:          Callback to get turbo P state
278  * @get_scaling:        Callback to get frequency scaling factor
279  * @get_val:            Callback to convert P state to actual MSR write value
280  * @get_vid:            Callback to get VID data for Atom platforms
281  *
282  * Core and Atom CPU models have different way to get P State limits. This
283  * structure is used to store those callbacks.
284  */
285 struct pstate_funcs {
286         int (*get_max)(void);
287         int (*get_max_physical)(void);
288         int (*get_min)(void);
289         int (*get_turbo)(void);
290         int (*get_scaling)(void);
291         int (*get_aperf_mperf_shift)(void);
292         u64 (*get_val)(struct cpudata*, int pstate);
293         void (*get_vid)(struct cpudata *);
294 };
295
296 static struct pstate_funcs pstate_funcs __read_mostly;
297
298 static int hwp_active __read_mostly;
299 static int hwp_mode_bdw __read_mostly;
300 static bool per_cpu_limits __read_mostly;
301 static bool hwp_boost __read_mostly;
302
303 static struct cpufreq_driver *intel_pstate_driver __read_mostly;
304
305 #ifdef CONFIG_ACPI
306 static bool acpi_ppc;
307 #endif
308
309 static struct global_params global;
310
311 static DEFINE_MUTEX(intel_pstate_driver_lock);
312 static DEFINE_MUTEX(intel_pstate_limits_lock);
313
314 #ifdef CONFIG_ACPI
315
316 static bool intel_pstate_acpi_pm_profile_server(void)
317 {
318         if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
319             acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
320                 return true;
321
322         return false;
323 }
324
325 static bool intel_pstate_get_ppc_enable_status(void)
326 {
327         if (intel_pstate_acpi_pm_profile_server())
328                 return true;
329
330         return acpi_ppc;
331 }
332
333 #ifdef CONFIG_ACPI_CPPC_LIB
334
335 /* The work item is needed to avoid CPU hotplug locking issues */
336 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
337 {
338         sched_set_itmt_support();
339 }
340
341 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
342
343 static void intel_pstate_set_itmt_prio(int cpu)
344 {
345         struct cppc_perf_caps cppc_perf;
346         static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
347         int ret;
348
349         ret = cppc_get_perf_caps(cpu, &cppc_perf);
350         if (ret)
351                 return;
352
353         /*
354          * The priorities can be set regardless of whether or not
355          * sched_set_itmt_support(true) has been called and it is valid to
356          * update them at any time after it has been called.
357          */
358         sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
359
360         if (max_highest_perf <= min_highest_perf) {
361                 if (cppc_perf.highest_perf > max_highest_perf)
362                         max_highest_perf = cppc_perf.highest_perf;
363
364                 if (cppc_perf.highest_perf < min_highest_perf)
365                         min_highest_perf = cppc_perf.highest_perf;
366
367                 if (max_highest_perf > min_highest_perf) {
368                         /*
369                          * This code can be run during CPU online under the
370                          * CPU hotplug locks, so sched_set_itmt_support()
371                          * cannot be called from here.  Queue up a work item
372                          * to invoke it.
373                          */
374                         schedule_work(&sched_itmt_work);
375                 }
376         }
377 }
378
379 static int intel_pstate_get_cppc_guranteed(int cpu)
380 {
381         struct cppc_perf_caps cppc_perf;
382         int ret;
383
384         ret = cppc_get_perf_caps(cpu, &cppc_perf);
385         if (ret)
386                 return ret;
387
388         return cppc_perf.guaranteed_perf;
389 }
390
391 #else /* CONFIG_ACPI_CPPC_LIB */
392 static void intel_pstate_set_itmt_prio(int cpu)
393 {
394 }
395 #endif /* CONFIG_ACPI_CPPC_LIB */
396
397 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
398 {
399         struct cpudata *cpu;
400         int ret;
401         int i;
402
403         if (hwp_active) {
404                 intel_pstate_set_itmt_prio(policy->cpu);
405                 return;
406         }
407
408         if (!intel_pstate_get_ppc_enable_status())
409                 return;
410
411         cpu = all_cpu_data[policy->cpu];
412
413         ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
414                                                   policy->cpu);
415         if (ret)
416                 return;
417
418         /*
419          * Check if the control value in _PSS is for PERF_CTL MSR, which should
420          * guarantee that the states returned by it map to the states in our
421          * list directly.
422          */
423         if (cpu->acpi_perf_data.control_register.space_id !=
424                                                 ACPI_ADR_SPACE_FIXED_HARDWARE)
425                 goto err;
426
427         /*
428          * If there is only one entry _PSS, simply ignore _PSS and continue as
429          * usual without taking _PSS into account
430          */
431         if (cpu->acpi_perf_data.state_count < 2)
432                 goto err;
433
434         pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
435         for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
436                 pr_debug("     %cP%d: %u MHz, %u mW, 0x%x\n",
437                          (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
438                          (u32) cpu->acpi_perf_data.states[i].core_frequency,
439                          (u32) cpu->acpi_perf_data.states[i].power,
440                          (u32) cpu->acpi_perf_data.states[i].control);
441         }
442
443         /*
444          * The _PSS table doesn't contain whole turbo frequency range.
445          * This just contains +1 MHZ above the max non turbo frequency,
446          * with control value corresponding to max turbo ratio. But
447          * when cpufreq set policy is called, it will call with this
448          * max frequency, which will cause a reduced performance as
449          * this driver uses real max turbo frequency as the max
450          * frequency. So correct this frequency in _PSS table to
451          * correct max turbo frequency based on the turbo state.
452          * Also need to convert to MHz as _PSS freq is in MHz.
453          */
454         if (!global.turbo_disabled)
455                 cpu->acpi_perf_data.states[0].core_frequency =
456                                         policy->cpuinfo.max_freq / 1000;
457         cpu->valid_pss_table = true;
458         pr_debug("_PPC limits will be enforced\n");
459
460         return;
461
462  err:
463         cpu->valid_pss_table = false;
464         acpi_processor_unregister_performance(policy->cpu);
465 }
466
467 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
468 {
469         struct cpudata *cpu;
470
471         cpu = all_cpu_data[policy->cpu];
472         if (!cpu->valid_pss_table)
473                 return;
474
475         acpi_processor_unregister_performance(policy->cpu);
476 }
477 #else /* CONFIG_ACPI */
478 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
479 {
480 }
481
482 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
483 {
484 }
485
486 static inline bool intel_pstate_acpi_pm_profile_server(void)
487 {
488         return false;
489 }
490 #endif /* CONFIG_ACPI */
491
492 #ifndef CONFIG_ACPI_CPPC_LIB
493 static int intel_pstate_get_cppc_guranteed(int cpu)
494 {
495         return -ENOTSUPP;
496 }
497 #endif /* CONFIG_ACPI_CPPC_LIB */
498
499 static inline void update_turbo_state(void)
500 {
501         u64 misc_en;
502         struct cpudata *cpu;
503
504         cpu = all_cpu_data[0];
505         rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
506         global.turbo_disabled =
507                 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
508                  cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
509 }
510
511 static int min_perf_pct_min(void)
512 {
513         struct cpudata *cpu = all_cpu_data[0];
514         int turbo_pstate = cpu->pstate.turbo_pstate;
515
516         return turbo_pstate ?
517                 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
518 }
519
520 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
521 {
522         u64 epb;
523         int ret;
524
525         if (!static_cpu_has(X86_FEATURE_EPB))
526                 return -ENXIO;
527
528         ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
529         if (ret)
530                 return (s16)ret;
531
532         return (s16)(epb & 0x0f);
533 }
534
535 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
536 {
537         s16 epp;
538
539         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
540                 /*
541                  * When hwp_req_data is 0, means that caller didn't read
542                  * MSR_HWP_REQUEST, so need to read and get EPP.
543                  */
544                 if (!hwp_req_data) {
545                         epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
546                                             &hwp_req_data);
547                         if (epp)
548                                 return epp;
549                 }
550                 epp = (hwp_req_data >> 24) & 0xff;
551         } else {
552                 /* When there is no EPP present, HWP uses EPB settings */
553                 epp = intel_pstate_get_epb(cpu_data);
554         }
555
556         return epp;
557 }
558
559 static int intel_pstate_set_epb(int cpu, s16 pref)
560 {
561         u64 epb;
562         int ret;
563
564         if (!static_cpu_has(X86_FEATURE_EPB))
565                 return -ENXIO;
566
567         ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
568         if (ret)
569                 return ret;
570
571         epb = (epb & ~0x0f) | pref;
572         wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
573
574         return 0;
575 }
576
577 /*
578  * EPP/EPB display strings corresponding to EPP index in the
579  * energy_perf_strings[]
580  *      index           String
581  *-------------------------------------
582  *      0               default
583  *      1               performance
584  *      2               balance_performance
585  *      3               balance_power
586  *      4               power
587  */
588 static const char * const energy_perf_strings[] = {
589         "default",
590         "performance",
591         "balance_performance",
592         "balance_power",
593         "power",
594         NULL
595 };
596 static const unsigned int epp_values[] = {
597         HWP_EPP_PERFORMANCE,
598         HWP_EPP_BALANCE_PERFORMANCE,
599         HWP_EPP_BALANCE_POWERSAVE,
600         HWP_EPP_POWERSAVE
601 };
602
603 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
604 {
605         s16 epp;
606         int index = -EINVAL;
607
608         epp = intel_pstate_get_epp(cpu_data, 0);
609         if (epp < 0)
610                 return epp;
611
612         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
613                 if (epp == HWP_EPP_PERFORMANCE)
614                         return 1;
615                 if (epp <= HWP_EPP_BALANCE_PERFORMANCE)
616                         return 2;
617                 if (epp <= HWP_EPP_BALANCE_POWERSAVE)
618                         return 3;
619                 else
620                         return 4;
621         } else if (static_cpu_has(X86_FEATURE_EPB)) {
622                 /*
623                  * Range:
624                  *      0x00-0x03       :       Performance
625                  *      0x04-0x07       :       Balance performance
626                  *      0x08-0x0B       :       Balance power
627                  *      0x0C-0x0F       :       Power
628                  * The EPB is a 4 bit value, but our ranges restrict the
629                  * value which can be set. Here only using top two bits
630                  * effectively.
631                  */
632                 index = (epp >> 2) + 1;
633         }
634
635         return index;
636 }
637
638 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
639                                               int pref_index)
640 {
641         int epp = -EINVAL;
642         int ret;
643
644         if (!pref_index)
645                 epp = cpu_data->epp_default;
646
647         mutex_lock(&intel_pstate_limits_lock);
648
649         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
650                 u64 value;
651
652                 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value);
653                 if (ret)
654                         goto return_pref;
655
656                 value &= ~GENMASK_ULL(31, 24);
657
658                 if (epp == -EINVAL)
659                         epp = epp_values[pref_index - 1];
660
661                 value |= (u64)epp << 24;
662                 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
663         } else {
664                 if (epp == -EINVAL)
665                         epp = (pref_index - 1) << 2;
666                 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
667         }
668 return_pref:
669         mutex_unlock(&intel_pstate_limits_lock);
670
671         return ret;
672 }
673
674 static ssize_t show_energy_performance_available_preferences(
675                                 struct cpufreq_policy *policy, char *buf)
676 {
677         int i = 0;
678         int ret = 0;
679
680         while (energy_perf_strings[i] != NULL)
681                 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
682
683         ret += sprintf(&buf[ret], "\n");
684
685         return ret;
686 }
687
688 cpufreq_freq_attr_ro(energy_performance_available_preferences);
689
690 static ssize_t store_energy_performance_preference(
691                 struct cpufreq_policy *policy, const char *buf, size_t count)
692 {
693         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
694         char str_preference[21];
695         int ret;
696
697         ret = sscanf(buf, "%20s", str_preference);
698         if (ret != 1)
699                 return -EINVAL;
700
701         ret = match_string(energy_perf_strings, -1, str_preference);
702         if (ret < 0)
703                 return ret;
704
705         intel_pstate_set_energy_pref_index(cpu_data, ret);
706         return count;
707 }
708
709 static ssize_t show_energy_performance_preference(
710                                 struct cpufreq_policy *policy, char *buf)
711 {
712         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
713         int preference;
714
715         preference = intel_pstate_get_energy_pref_index(cpu_data);
716         if (preference < 0)
717                 return preference;
718
719         return  sprintf(buf, "%s\n", energy_perf_strings[preference]);
720 }
721
722 cpufreq_freq_attr_rw(energy_performance_preference);
723
724 static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf)
725 {
726         struct cpudata *cpu;
727         u64 cap;
728         int ratio;
729
730         ratio = intel_pstate_get_cppc_guranteed(policy->cpu);
731         if (ratio <= 0) {
732                 rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap);
733                 ratio = HWP_GUARANTEED_PERF(cap);
734         }
735
736         cpu = all_cpu_data[policy->cpu];
737
738         return sprintf(buf, "%d\n", ratio * cpu->pstate.scaling);
739 }
740
741 cpufreq_freq_attr_ro(base_frequency);
742
743 static struct freq_attr *hwp_cpufreq_attrs[] = {
744         &energy_performance_preference,
745         &energy_performance_available_preferences,
746         &base_frequency,
747         NULL,
748 };
749
750 static void intel_pstate_get_hwp_max(unsigned int cpu, int *phy_max,
751                                      int *current_max)
752 {
753         u64 cap;
754
755         rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
756         WRITE_ONCE(all_cpu_data[cpu]->hwp_cap_cached, cap);
757         if (global.no_turbo)
758                 *current_max = HWP_GUARANTEED_PERF(cap);
759         else
760                 *current_max = HWP_HIGHEST_PERF(cap);
761
762         *phy_max = HWP_HIGHEST_PERF(cap);
763 }
764
765 static void intel_pstate_hwp_set(unsigned int cpu)
766 {
767         struct cpudata *cpu_data = all_cpu_data[cpu];
768         int max, min;
769         u64 value;
770         s16 epp;
771
772         max = cpu_data->max_perf_ratio;
773         min = cpu_data->min_perf_ratio;
774
775         if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
776                 min = max;
777
778         rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
779
780         value &= ~HWP_MIN_PERF(~0L);
781         value |= HWP_MIN_PERF(min);
782
783         value &= ~HWP_MAX_PERF(~0L);
784         value |= HWP_MAX_PERF(max);
785
786         if (cpu_data->epp_policy == cpu_data->policy)
787                 goto skip_epp;
788
789         cpu_data->epp_policy = cpu_data->policy;
790
791         if (cpu_data->epp_saved >= 0) {
792                 epp = cpu_data->epp_saved;
793                 cpu_data->epp_saved = -EINVAL;
794                 goto update_epp;
795         }
796
797         if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
798                 epp = intel_pstate_get_epp(cpu_data, value);
799                 cpu_data->epp_powersave = epp;
800                 /* If EPP read was failed, then don't try to write */
801                 if (epp < 0)
802                         goto skip_epp;
803
804                 epp = 0;
805         } else {
806                 /* skip setting EPP, when saved value is invalid */
807                 if (cpu_data->epp_powersave < 0)
808                         goto skip_epp;
809
810                 /*
811                  * No need to restore EPP when it is not zero. This
812                  * means:
813                  *  - Policy is not changed
814                  *  - user has manually changed
815                  *  - Error reading EPB
816                  */
817                 epp = intel_pstate_get_epp(cpu_data, value);
818                 if (epp)
819                         goto skip_epp;
820
821                 epp = cpu_data->epp_powersave;
822         }
823 update_epp:
824         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
825                 value &= ~GENMASK_ULL(31, 24);
826                 value |= (u64)epp << 24;
827         } else {
828                 intel_pstate_set_epb(cpu, epp);
829         }
830 skip_epp:
831         WRITE_ONCE(cpu_data->hwp_req_cached, value);
832         wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
833 }
834
835 static void intel_pstate_hwp_force_min_perf(int cpu)
836 {
837         u64 value;
838         int min_perf;
839
840         value = all_cpu_data[cpu]->hwp_req_cached;
841         value &= ~GENMASK_ULL(31, 0);
842         min_perf = HWP_LOWEST_PERF(all_cpu_data[cpu]->hwp_cap_cached);
843
844         /* Set hwp_max = hwp_min */
845         value |= HWP_MAX_PERF(min_perf);
846         value |= HWP_MIN_PERF(min_perf);
847
848         /* Set EPP/EPB to min */
849         if (static_cpu_has(X86_FEATURE_HWP_EPP))
850                 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE);
851         else
852                 intel_pstate_set_epb(cpu, HWP_EPP_BALANCE_POWERSAVE);
853
854         wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
855 }
856
857 static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
858 {
859         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
860
861         if (!hwp_active)
862                 return 0;
863
864         cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
865
866         return 0;
867 }
868
869 static void intel_pstate_hwp_enable(struct cpudata *cpudata);
870
871 static int intel_pstate_resume(struct cpufreq_policy *policy)
872 {
873         if (!hwp_active)
874                 return 0;
875
876         mutex_lock(&intel_pstate_limits_lock);
877
878         if (policy->cpu == 0)
879                 intel_pstate_hwp_enable(all_cpu_data[policy->cpu]);
880
881         all_cpu_data[policy->cpu]->epp_policy = 0;
882         intel_pstate_hwp_set(policy->cpu);
883
884         mutex_unlock(&intel_pstate_limits_lock);
885
886         return 0;
887 }
888
889 static void intel_pstate_update_policies(void)
890 {
891         int cpu;
892
893         for_each_possible_cpu(cpu)
894                 cpufreq_update_policy(cpu);
895 }
896
897 /************************** sysfs begin ************************/
898 #define show_one(file_name, object)                                     \
899         static ssize_t show_##file_name                                 \
900         (struct kobject *kobj, struct kobj_attribute *attr, char *buf)  \
901         {                                                               \
902                 return sprintf(buf, "%u\n", global.object);             \
903         }
904
905 static ssize_t intel_pstate_show_status(char *buf);
906 static int intel_pstate_update_status(const char *buf, size_t size);
907
908 static ssize_t show_status(struct kobject *kobj,
909                            struct kobj_attribute *attr, char *buf)
910 {
911         ssize_t ret;
912
913         mutex_lock(&intel_pstate_driver_lock);
914         ret = intel_pstate_show_status(buf);
915         mutex_unlock(&intel_pstate_driver_lock);
916
917         return ret;
918 }
919
920 static ssize_t store_status(struct kobject *a, struct kobj_attribute *b,
921                             const char *buf, size_t count)
922 {
923         char *p = memchr(buf, '\n', count);
924         int ret;
925
926         mutex_lock(&intel_pstate_driver_lock);
927         ret = intel_pstate_update_status(buf, p ? p - buf : count);
928         mutex_unlock(&intel_pstate_driver_lock);
929
930         return ret < 0 ? ret : count;
931 }
932
933 static ssize_t show_turbo_pct(struct kobject *kobj,
934                                 struct kobj_attribute *attr, char *buf)
935 {
936         struct cpudata *cpu;
937         int total, no_turbo, turbo_pct;
938         uint32_t turbo_fp;
939
940         mutex_lock(&intel_pstate_driver_lock);
941
942         if (!intel_pstate_driver) {
943                 mutex_unlock(&intel_pstate_driver_lock);
944                 return -EAGAIN;
945         }
946
947         cpu = all_cpu_data[0];
948
949         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
950         no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
951         turbo_fp = div_fp(no_turbo, total);
952         turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
953
954         mutex_unlock(&intel_pstate_driver_lock);
955
956         return sprintf(buf, "%u\n", turbo_pct);
957 }
958
959 static ssize_t show_num_pstates(struct kobject *kobj,
960                                 struct kobj_attribute *attr, char *buf)
961 {
962         struct cpudata *cpu;
963         int total;
964
965         mutex_lock(&intel_pstate_driver_lock);
966
967         if (!intel_pstate_driver) {
968                 mutex_unlock(&intel_pstate_driver_lock);
969                 return -EAGAIN;
970         }
971
972         cpu = all_cpu_data[0];
973         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
974
975         mutex_unlock(&intel_pstate_driver_lock);
976
977         return sprintf(buf, "%u\n", total);
978 }
979
980 static ssize_t show_no_turbo(struct kobject *kobj,
981                              struct kobj_attribute *attr, char *buf)
982 {
983         ssize_t ret;
984
985         mutex_lock(&intel_pstate_driver_lock);
986
987         if (!intel_pstate_driver) {
988                 mutex_unlock(&intel_pstate_driver_lock);
989                 return -EAGAIN;
990         }
991
992         update_turbo_state();
993         if (global.turbo_disabled)
994                 ret = sprintf(buf, "%u\n", global.turbo_disabled);
995         else
996                 ret = sprintf(buf, "%u\n", global.no_turbo);
997
998         mutex_unlock(&intel_pstate_driver_lock);
999
1000         return ret;
1001 }
1002
1003 static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b,
1004                               const char *buf, size_t count)
1005 {
1006         unsigned int input;
1007         int ret;
1008
1009         ret = sscanf(buf, "%u", &input);
1010         if (ret != 1)
1011                 return -EINVAL;
1012
1013         mutex_lock(&intel_pstate_driver_lock);
1014
1015         if (!intel_pstate_driver) {
1016                 mutex_unlock(&intel_pstate_driver_lock);
1017                 return -EAGAIN;
1018         }
1019
1020         mutex_lock(&intel_pstate_limits_lock);
1021
1022         update_turbo_state();
1023         if (global.turbo_disabled) {
1024                 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
1025                 mutex_unlock(&intel_pstate_limits_lock);
1026                 mutex_unlock(&intel_pstate_driver_lock);
1027                 return -EPERM;
1028         }
1029
1030         global.no_turbo = clamp_t(int, input, 0, 1);
1031
1032         if (global.no_turbo) {
1033                 struct cpudata *cpu = all_cpu_data[0];
1034                 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
1035
1036                 /* Squash the global minimum into the permitted range. */
1037                 if (global.min_perf_pct > pct)
1038                         global.min_perf_pct = pct;
1039         }
1040
1041         mutex_unlock(&intel_pstate_limits_lock);
1042
1043         intel_pstate_update_policies();
1044
1045         mutex_unlock(&intel_pstate_driver_lock);
1046
1047         return count;
1048 }
1049
1050 static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b,
1051                                   const char *buf, size_t count)
1052 {
1053         unsigned int input;
1054         int ret;
1055
1056         ret = sscanf(buf, "%u", &input);
1057         if (ret != 1)
1058                 return -EINVAL;
1059
1060         mutex_lock(&intel_pstate_driver_lock);
1061
1062         if (!intel_pstate_driver) {
1063                 mutex_unlock(&intel_pstate_driver_lock);
1064                 return -EAGAIN;
1065         }
1066
1067         mutex_lock(&intel_pstate_limits_lock);
1068
1069         global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
1070
1071         mutex_unlock(&intel_pstate_limits_lock);
1072
1073         intel_pstate_update_policies();
1074
1075         mutex_unlock(&intel_pstate_driver_lock);
1076
1077         return count;
1078 }
1079
1080 static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b,
1081                                   const char *buf, size_t count)
1082 {
1083         unsigned int input;
1084         int ret;
1085
1086         ret = sscanf(buf, "%u", &input);
1087         if (ret != 1)
1088                 return -EINVAL;
1089
1090         mutex_lock(&intel_pstate_driver_lock);
1091
1092         if (!intel_pstate_driver) {
1093                 mutex_unlock(&intel_pstate_driver_lock);
1094                 return -EAGAIN;
1095         }
1096
1097         mutex_lock(&intel_pstate_limits_lock);
1098
1099         global.min_perf_pct = clamp_t(int, input,
1100                                       min_perf_pct_min(), global.max_perf_pct);
1101
1102         mutex_unlock(&intel_pstate_limits_lock);
1103
1104         intel_pstate_update_policies();
1105
1106         mutex_unlock(&intel_pstate_driver_lock);
1107
1108         return count;
1109 }
1110
1111 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj,
1112                                 struct kobj_attribute *attr, char *buf)
1113 {
1114         return sprintf(buf, "%u\n", hwp_boost);
1115 }
1116
1117 static ssize_t store_hwp_dynamic_boost(struct kobject *a,
1118                                        struct kobj_attribute *b,
1119                                        const char *buf, size_t count)
1120 {
1121         unsigned int input;
1122         int ret;
1123
1124         ret = kstrtouint(buf, 10, &input);
1125         if (ret)
1126                 return ret;
1127
1128         mutex_lock(&intel_pstate_driver_lock);
1129         hwp_boost = !!input;
1130         intel_pstate_update_policies();
1131         mutex_unlock(&intel_pstate_driver_lock);
1132
1133         return count;
1134 }
1135
1136 show_one(max_perf_pct, max_perf_pct);
1137 show_one(min_perf_pct, min_perf_pct);
1138
1139 define_one_global_rw(status);
1140 define_one_global_rw(no_turbo);
1141 define_one_global_rw(max_perf_pct);
1142 define_one_global_rw(min_perf_pct);
1143 define_one_global_ro(turbo_pct);
1144 define_one_global_ro(num_pstates);
1145 define_one_global_rw(hwp_dynamic_boost);
1146
1147 static struct attribute *intel_pstate_attributes[] = {
1148         &status.attr,
1149         &no_turbo.attr,
1150         &turbo_pct.attr,
1151         &num_pstates.attr,
1152         NULL
1153 };
1154
1155 static const struct attribute_group intel_pstate_attr_group = {
1156         .attrs = intel_pstate_attributes,
1157 };
1158
1159 static void __init intel_pstate_sysfs_expose_params(void)
1160 {
1161         struct kobject *intel_pstate_kobject;
1162         int rc;
1163
1164         intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1165                                                 &cpu_subsys.dev_root->kobj);
1166         if (WARN_ON(!intel_pstate_kobject))
1167                 return;
1168
1169         rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1170         if (WARN_ON(rc))
1171                 return;
1172
1173         /*
1174          * If per cpu limits are enforced there are no global limits, so
1175          * return without creating max/min_perf_pct attributes
1176          */
1177         if (per_cpu_limits)
1178                 return;
1179
1180         rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1181         WARN_ON(rc);
1182
1183         rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1184         WARN_ON(rc);
1185
1186         if (hwp_active) {
1187                 rc = sysfs_create_file(intel_pstate_kobject,
1188                                        &hwp_dynamic_boost.attr);
1189                 WARN_ON(rc);
1190         }
1191 }
1192 /************************** sysfs end ************************/
1193
1194 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1195 {
1196         /* First disable HWP notification interrupt as we don't process them */
1197         if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
1198                 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1199
1200         wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1201         cpudata->epp_policy = 0;
1202         if (cpudata->epp_default == -EINVAL)
1203                 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1204 }
1205
1206 #define MSR_IA32_POWER_CTL_BIT_EE       19
1207
1208 /* Disable energy efficiency optimization */
1209 static void intel_pstate_disable_ee(int cpu)
1210 {
1211         u64 power_ctl;
1212         int ret;
1213
1214         ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl);
1215         if (ret)
1216                 return;
1217
1218         if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) {
1219                 pr_info("Disabling energy efficiency optimization\n");
1220                 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1221                 wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl);
1222         }
1223 }
1224
1225 static int atom_get_min_pstate(void)
1226 {
1227         u64 value;
1228
1229         rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1230         return (value >> 8) & 0x7F;
1231 }
1232
1233 static int atom_get_max_pstate(void)
1234 {
1235         u64 value;
1236
1237         rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1238         return (value >> 16) & 0x7F;
1239 }
1240
1241 static int atom_get_turbo_pstate(void)
1242 {
1243         u64 value;
1244
1245         rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1246         return value & 0x7F;
1247 }
1248
1249 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1250 {
1251         u64 val;
1252         int32_t vid_fp;
1253         u32 vid;
1254
1255         val = (u64)pstate << 8;
1256         if (global.no_turbo && !global.turbo_disabled)
1257                 val |= (u64)1 << 32;
1258
1259         vid_fp = cpudata->vid.min + mul_fp(
1260                 int_tofp(pstate - cpudata->pstate.min_pstate),
1261                 cpudata->vid.ratio);
1262
1263         vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1264         vid = ceiling_fp(vid_fp);
1265
1266         if (pstate > cpudata->pstate.max_pstate)
1267                 vid = cpudata->vid.turbo;
1268
1269         return val | vid;
1270 }
1271
1272 static int silvermont_get_scaling(void)
1273 {
1274         u64 value;
1275         int i;
1276         /* Defined in Table 35-6 from SDM (Sept 2015) */
1277         static int silvermont_freq_table[] = {
1278                 83300, 100000, 133300, 116700, 80000};
1279
1280         rdmsrl(MSR_FSB_FREQ, value);
1281         i = value & 0x7;
1282         WARN_ON(i > 4);
1283
1284         return silvermont_freq_table[i];
1285 }
1286
1287 static int airmont_get_scaling(void)
1288 {
1289         u64 value;
1290         int i;
1291         /* Defined in Table 35-10 from SDM (Sept 2015) */
1292         static int airmont_freq_table[] = {
1293                 83300, 100000, 133300, 116700, 80000,
1294                 93300, 90000, 88900, 87500};
1295
1296         rdmsrl(MSR_FSB_FREQ, value);
1297         i = value & 0xF;
1298         WARN_ON(i > 8);
1299
1300         return airmont_freq_table[i];
1301 }
1302
1303 static void atom_get_vid(struct cpudata *cpudata)
1304 {
1305         u64 value;
1306
1307         rdmsrl(MSR_ATOM_CORE_VIDS, value);
1308         cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1309         cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1310         cpudata->vid.ratio = div_fp(
1311                 cpudata->vid.max - cpudata->vid.min,
1312                 int_tofp(cpudata->pstate.max_pstate -
1313                         cpudata->pstate.min_pstate));
1314
1315         rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1316         cpudata->vid.turbo = value & 0x7f;
1317 }
1318
1319 static int core_get_min_pstate(void)
1320 {
1321         u64 value;
1322
1323         rdmsrl(MSR_PLATFORM_INFO, value);
1324         return (value >> 40) & 0xFF;
1325 }
1326
1327 static int core_get_max_pstate_physical(void)
1328 {
1329         u64 value;
1330
1331         rdmsrl(MSR_PLATFORM_INFO, value);
1332         return (value >> 8) & 0xFF;
1333 }
1334
1335 static int core_get_tdp_ratio(u64 plat_info)
1336 {
1337         /* Check how many TDP levels present */
1338         if (plat_info & 0x600000000) {
1339                 u64 tdp_ctrl;
1340                 u64 tdp_ratio;
1341                 int tdp_msr;
1342                 int err;
1343
1344                 /* Get the TDP level (0, 1, 2) to get ratios */
1345                 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1346                 if (err)
1347                         return err;
1348
1349                 /* TDP MSR are continuous starting at 0x648 */
1350                 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1351                 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1352                 if (err)
1353                         return err;
1354
1355                 /* For level 1 and 2, bits[23:16] contain the ratio */
1356                 if (tdp_ctrl & 0x03)
1357                         tdp_ratio >>= 16;
1358
1359                 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1360                 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1361
1362                 return (int)tdp_ratio;
1363         }
1364
1365         return -ENXIO;
1366 }
1367
1368 static int core_get_max_pstate(void)
1369 {
1370         u64 tar;
1371         u64 plat_info;
1372         int max_pstate;
1373         int tdp_ratio;
1374         int err;
1375
1376         rdmsrl(MSR_PLATFORM_INFO, plat_info);
1377         max_pstate = (plat_info >> 8) & 0xFF;
1378
1379         tdp_ratio = core_get_tdp_ratio(plat_info);
1380         if (tdp_ratio <= 0)
1381                 return max_pstate;
1382
1383         if (hwp_active) {
1384                 /* Turbo activation ratio is not used on HWP platforms */
1385                 return tdp_ratio;
1386         }
1387
1388         err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1389         if (!err) {
1390                 int tar_levels;
1391
1392                 /* Do some sanity checking for safety */
1393                 tar_levels = tar & 0xff;
1394                 if (tdp_ratio - 1 == tar_levels) {
1395                         max_pstate = tar_levels;
1396                         pr_debug("max_pstate=TAC %x\n", max_pstate);
1397                 }
1398         }
1399
1400         return max_pstate;
1401 }
1402
1403 static int core_get_turbo_pstate(void)
1404 {
1405         u64 value;
1406         int nont, ret;
1407
1408         rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1409         nont = core_get_max_pstate();
1410         ret = (value) & 255;
1411         if (ret <= nont)
1412                 ret = nont;
1413         return ret;
1414 }
1415
1416 static inline int core_get_scaling(void)
1417 {
1418         return 100000;
1419 }
1420
1421 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1422 {
1423         u64 val;
1424
1425         val = (u64)pstate << 8;
1426         if (global.no_turbo && !global.turbo_disabled)
1427                 val |= (u64)1 << 32;
1428
1429         return val;
1430 }
1431
1432 static int knl_get_aperf_mperf_shift(void)
1433 {
1434         return 10;
1435 }
1436
1437 static int knl_get_turbo_pstate(void)
1438 {
1439         u64 value;
1440         int nont, ret;
1441
1442         rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1443         nont = core_get_max_pstate();
1444         ret = (((value) >> 8) & 0xFF);
1445         if (ret <= nont)
1446                 ret = nont;
1447         return ret;
1448 }
1449
1450 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1451 {
1452         trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1453         cpu->pstate.current_pstate = pstate;
1454         /*
1455          * Generally, there is no guarantee that this code will always run on
1456          * the CPU being updated, so force the register update to run on the
1457          * right CPU.
1458          */
1459         wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1460                       pstate_funcs.get_val(cpu, pstate));
1461 }
1462
1463 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1464 {
1465         intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1466 }
1467
1468 static void intel_pstate_max_within_limits(struct cpudata *cpu)
1469 {
1470         int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
1471
1472         update_turbo_state();
1473         intel_pstate_set_pstate(cpu, pstate);
1474 }
1475
1476 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1477 {
1478         cpu->pstate.min_pstate = pstate_funcs.get_min();
1479         cpu->pstate.max_pstate = pstate_funcs.get_max();
1480         cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
1481         cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
1482         cpu->pstate.scaling = pstate_funcs.get_scaling();
1483         cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1484
1485         if (hwp_active && !hwp_mode_bdw) {
1486                 unsigned int phy_max, current_max;
1487
1488                 intel_pstate_get_hwp_max(cpu->cpu, &phy_max, &current_max);
1489                 cpu->pstate.turbo_freq = phy_max * cpu->pstate.scaling;
1490         } else {
1491                 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1492         }
1493
1494         if (pstate_funcs.get_aperf_mperf_shift)
1495                 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
1496
1497         if (pstate_funcs.get_vid)
1498                 pstate_funcs.get_vid(cpu);
1499
1500         intel_pstate_set_min_pstate(cpu);
1501 }
1502
1503 /*
1504  * Long hold time will keep high perf limits for long time,
1505  * which negatively impacts perf/watt for some workloads,
1506  * like specpower. 3ms is based on experiements on some
1507  * workoads.
1508  */
1509 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC;
1510
1511 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu)
1512 {
1513         u64 hwp_req = READ_ONCE(cpu->hwp_req_cached);
1514         u32 max_limit = (hwp_req & 0xff00) >> 8;
1515         u32 min_limit = (hwp_req & 0xff);
1516         u32 boost_level1;
1517
1518         /*
1519          * Cases to consider (User changes via sysfs or boot time):
1520          * If, P0 (Turbo max) = P1 (Guaranteed max) = min:
1521          *      No boost, return.
1522          * If, P0 (Turbo max) > P1 (Guaranteed max) = min:
1523          *     Should result in one level boost only for P0.
1524          * If, P0 (Turbo max) = P1 (Guaranteed max) > min:
1525          *     Should result in two level boost:
1526          *         (min + p1)/2 and P1.
1527          * If, P0 (Turbo max) > P1 (Guaranteed max) > min:
1528          *     Should result in three level boost:
1529          *        (min + p1)/2, P1 and P0.
1530          */
1531
1532         /* If max and min are equal or already at max, nothing to boost */
1533         if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit)
1534                 return;
1535
1536         if (!cpu->hwp_boost_min)
1537                 cpu->hwp_boost_min = min_limit;
1538
1539         /* level at half way mark between min and guranteed */
1540         boost_level1 = (HWP_GUARANTEED_PERF(cpu->hwp_cap_cached) + min_limit) >> 1;
1541
1542         if (cpu->hwp_boost_min < boost_level1)
1543                 cpu->hwp_boost_min = boost_level1;
1544         else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(cpu->hwp_cap_cached))
1545                 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(cpu->hwp_cap_cached);
1546         else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(cpu->hwp_cap_cached) &&
1547                  max_limit != HWP_GUARANTEED_PERF(cpu->hwp_cap_cached))
1548                 cpu->hwp_boost_min = max_limit;
1549         else
1550                 return;
1551
1552         hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min;
1553         wrmsrl(MSR_HWP_REQUEST, hwp_req);
1554         cpu->last_update = cpu->sample.time;
1555 }
1556
1557 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu)
1558 {
1559         if (cpu->hwp_boost_min) {
1560                 bool expired;
1561
1562                 /* Check if we are idle for hold time to boost down */
1563                 expired = time_after64(cpu->sample.time, cpu->last_update +
1564                                        hwp_boost_hold_time_ns);
1565                 if (expired) {
1566                         wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached);
1567                         cpu->hwp_boost_min = 0;
1568                 }
1569         }
1570         cpu->last_update = cpu->sample.time;
1571 }
1572
1573 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu,
1574                                                       u64 time)
1575 {
1576         cpu->sample.time = time;
1577
1578         if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) {
1579                 bool do_io = false;
1580
1581                 cpu->sched_flags = 0;
1582                 /*
1583                  * Set iowait_boost flag and update time. Since IO WAIT flag
1584                  * is set all the time, we can't just conclude that there is
1585                  * some IO bound activity is scheduled on this CPU with just
1586                  * one occurrence. If we receive at least two in two
1587                  * consecutive ticks, then we treat as boost candidate.
1588                  */
1589                 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC))
1590                         do_io = true;
1591
1592                 cpu->last_io_update = time;
1593
1594                 if (do_io)
1595                         intel_pstate_hwp_boost_up(cpu);
1596
1597         } else {
1598                 intel_pstate_hwp_boost_down(cpu);
1599         }
1600 }
1601
1602 static inline void intel_pstate_update_util_hwp(struct update_util_data *data,
1603                                                 u64 time, unsigned int flags)
1604 {
1605         struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1606
1607         cpu->sched_flags |= flags;
1608
1609         if (smp_processor_id() == cpu->cpu)
1610                 intel_pstate_update_util_hwp_local(cpu, time);
1611 }
1612
1613 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
1614 {
1615         struct sample *sample = &cpu->sample;
1616
1617         sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
1618 }
1619
1620 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
1621 {
1622         u64 aperf, mperf;
1623         unsigned long flags;
1624         u64 tsc;
1625
1626         local_irq_save(flags);
1627         rdmsrl(MSR_IA32_APERF, aperf);
1628         rdmsrl(MSR_IA32_MPERF, mperf);
1629         tsc = rdtsc();
1630         if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
1631                 local_irq_restore(flags);
1632                 return false;
1633         }
1634         local_irq_restore(flags);
1635
1636         cpu->last_sample_time = cpu->sample.time;
1637         cpu->sample.time = time;
1638         cpu->sample.aperf = aperf;
1639         cpu->sample.mperf = mperf;
1640         cpu->sample.tsc =  tsc;
1641         cpu->sample.aperf -= cpu->prev_aperf;
1642         cpu->sample.mperf -= cpu->prev_mperf;
1643         cpu->sample.tsc -= cpu->prev_tsc;
1644
1645         cpu->prev_aperf = aperf;
1646         cpu->prev_mperf = mperf;
1647         cpu->prev_tsc = tsc;
1648         /*
1649          * First time this function is invoked in a given cycle, all of the
1650          * previous sample data fields are equal to zero or stale and they must
1651          * be populated with meaningful numbers for things to work, so assume
1652          * that sample.time will always be reset before setting the utilization
1653          * update hook and make the caller skip the sample then.
1654          */
1655         if (cpu->last_sample_time) {
1656                 intel_pstate_calc_avg_perf(cpu);
1657                 return true;
1658         }
1659         return false;
1660 }
1661
1662 static inline int32_t get_avg_frequency(struct cpudata *cpu)
1663 {
1664         return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz);
1665 }
1666
1667 static inline int32_t get_avg_pstate(struct cpudata *cpu)
1668 {
1669         return mul_ext_fp(cpu->pstate.max_pstate_physical,
1670                           cpu->sample.core_avg_perf);
1671 }
1672
1673 static inline int32_t get_target_pstate(struct cpudata *cpu)
1674 {
1675         struct sample *sample = &cpu->sample;
1676         int32_t busy_frac;
1677         int target, avg_pstate;
1678
1679         busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
1680                            sample->tsc);
1681
1682         if (busy_frac < cpu->iowait_boost)
1683                 busy_frac = cpu->iowait_boost;
1684
1685         sample->busy_scaled = busy_frac * 100;
1686
1687         target = global.no_turbo || global.turbo_disabled ?
1688                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1689         target += target >> 2;
1690         target = mul_fp(target, busy_frac);
1691         if (target < cpu->pstate.min_pstate)
1692                 target = cpu->pstate.min_pstate;
1693
1694         /*
1695          * If the average P-state during the previous cycle was higher than the
1696          * current target, add 50% of the difference to the target to reduce
1697          * possible performance oscillations and offset possible performance
1698          * loss related to moving the workload from one CPU to another within
1699          * a package/module.
1700          */
1701         avg_pstate = get_avg_pstate(cpu);
1702         if (avg_pstate > target)
1703                 target += (avg_pstate - target) >> 1;
1704
1705         return target;
1706 }
1707
1708 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
1709 {
1710         int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
1711         int max_pstate = max(min_pstate, cpu->max_perf_ratio);
1712
1713         return clamp_t(int, pstate, min_pstate, max_pstate);
1714 }
1715
1716 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1717 {
1718         if (pstate == cpu->pstate.current_pstate)
1719                 return;
1720
1721         cpu->pstate.current_pstate = pstate;
1722         wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1723 }
1724
1725 static void intel_pstate_adjust_pstate(struct cpudata *cpu)
1726 {
1727         int from = cpu->pstate.current_pstate;
1728         struct sample *sample;
1729         int target_pstate;
1730
1731         update_turbo_state();
1732
1733         target_pstate = get_target_pstate(cpu);
1734         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1735         trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
1736         intel_pstate_update_pstate(cpu, target_pstate);
1737
1738         sample = &cpu->sample;
1739         trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
1740                 fp_toint(sample->busy_scaled),
1741                 from,
1742                 cpu->pstate.current_pstate,
1743                 sample->mperf,
1744                 sample->aperf,
1745                 sample->tsc,
1746                 get_avg_frequency(cpu),
1747                 fp_toint(cpu->iowait_boost * 100));
1748 }
1749
1750 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
1751                                      unsigned int flags)
1752 {
1753         struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1754         u64 delta_ns;
1755
1756         /* Don't allow remote callbacks */
1757         if (smp_processor_id() != cpu->cpu)
1758                 return;
1759
1760         delta_ns = time - cpu->last_update;
1761         if (flags & SCHED_CPUFREQ_IOWAIT) {
1762                 /* Start over if the CPU may have been idle. */
1763                 if (delta_ns > TICK_NSEC) {
1764                         cpu->iowait_boost = ONE_EIGHTH_FP;
1765                 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) {
1766                         cpu->iowait_boost <<= 1;
1767                         if (cpu->iowait_boost > int_tofp(1))
1768                                 cpu->iowait_boost = int_tofp(1);
1769                 } else {
1770                         cpu->iowait_boost = ONE_EIGHTH_FP;
1771                 }
1772         } else if (cpu->iowait_boost) {
1773                 /* Clear iowait_boost if the CPU may have been idle. */
1774                 if (delta_ns > TICK_NSEC)
1775                         cpu->iowait_boost = 0;
1776                 else
1777                         cpu->iowait_boost >>= 1;
1778         }
1779         cpu->last_update = time;
1780         delta_ns = time - cpu->sample.time;
1781         if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL)
1782                 return;
1783
1784         if (intel_pstate_sample(cpu, time))
1785                 intel_pstate_adjust_pstate(cpu);
1786 }
1787
1788 static struct pstate_funcs core_funcs = {
1789         .get_max = core_get_max_pstate,
1790         .get_max_physical = core_get_max_pstate_physical,
1791         .get_min = core_get_min_pstate,
1792         .get_turbo = core_get_turbo_pstate,
1793         .get_scaling = core_get_scaling,
1794         .get_val = core_get_val,
1795 };
1796
1797 static const struct pstate_funcs silvermont_funcs = {
1798         .get_max = atom_get_max_pstate,
1799         .get_max_physical = atom_get_max_pstate,
1800         .get_min = atom_get_min_pstate,
1801         .get_turbo = atom_get_turbo_pstate,
1802         .get_val = atom_get_val,
1803         .get_scaling = silvermont_get_scaling,
1804         .get_vid = atom_get_vid,
1805 };
1806
1807 static const struct pstate_funcs airmont_funcs = {
1808         .get_max = atom_get_max_pstate,
1809         .get_max_physical = atom_get_max_pstate,
1810         .get_min = atom_get_min_pstate,
1811         .get_turbo = atom_get_turbo_pstate,
1812         .get_val = atom_get_val,
1813         .get_scaling = airmont_get_scaling,
1814         .get_vid = atom_get_vid,
1815 };
1816
1817 static const struct pstate_funcs knl_funcs = {
1818         .get_max = core_get_max_pstate,
1819         .get_max_physical = core_get_max_pstate_physical,
1820         .get_min = core_get_min_pstate,
1821         .get_turbo = knl_get_turbo_pstate,
1822         .get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
1823         .get_scaling = core_get_scaling,
1824         .get_val = core_get_val,
1825 };
1826
1827 #define ICPU(model, policy) \
1828         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1829                         (unsigned long)&policy }
1830
1831 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
1832         ICPU(INTEL_FAM6_SANDYBRIDGE,            core_funcs),
1833         ICPU(INTEL_FAM6_SANDYBRIDGE_X,          core_funcs),
1834         ICPU(INTEL_FAM6_ATOM_SILVERMONT,        silvermont_funcs),
1835         ICPU(INTEL_FAM6_IVYBRIDGE,              core_funcs),
1836         ICPU(INTEL_FAM6_HASWELL_CORE,           core_funcs),
1837         ICPU(INTEL_FAM6_BROADWELL_CORE,         core_funcs),
1838         ICPU(INTEL_FAM6_IVYBRIDGE_X,            core_funcs),
1839         ICPU(INTEL_FAM6_HASWELL_X,              core_funcs),
1840         ICPU(INTEL_FAM6_HASWELL_ULT,            core_funcs),
1841         ICPU(INTEL_FAM6_HASWELL_GT3E,           core_funcs),
1842         ICPU(INTEL_FAM6_BROADWELL_GT3E,         core_funcs),
1843         ICPU(INTEL_FAM6_ATOM_AIRMONT,           airmont_funcs),
1844         ICPU(INTEL_FAM6_SKYLAKE_MOBILE,         core_funcs),
1845         ICPU(INTEL_FAM6_BROADWELL_X,            core_funcs),
1846         ICPU(INTEL_FAM6_SKYLAKE_DESKTOP,        core_funcs),
1847         ICPU(INTEL_FAM6_BROADWELL_XEON_D,       core_funcs),
1848         ICPU(INTEL_FAM6_XEON_PHI_KNL,           knl_funcs),
1849         ICPU(INTEL_FAM6_XEON_PHI_KNM,           knl_funcs),
1850         ICPU(INTEL_FAM6_ATOM_GOLDMONT,          core_funcs),
1851         ICPU(INTEL_FAM6_ATOM_GOLDMONT_PLUS,     core_funcs),
1852         ICPU(INTEL_FAM6_SKYLAKE_X,              core_funcs),
1853         {}
1854 };
1855 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1856
1857 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
1858         ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
1859         ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
1860         ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
1861         {}
1862 };
1863
1864 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
1865         ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_funcs),
1866         {}
1867 };
1868
1869 static const struct x86_cpu_id intel_pstate_hwp_boost_ids[] = {
1870         ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
1871         ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_funcs),
1872         {}
1873 };
1874
1875 static int intel_pstate_init_cpu(unsigned int cpunum)
1876 {
1877         struct cpudata *cpu;
1878
1879         cpu = all_cpu_data[cpunum];
1880
1881         if (!cpu) {
1882                 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
1883                 if (!cpu)
1884                         return -ENOMEM;
1885
1886                 all_cpu_data[cpunum] = cpu;
1887
1888                 cpu->epp_default = -EINVAL;
1889                 cpu->epp_powersave = -EINVAL;
1890                 cpu->epp_saved = -EINVAL;
1891         }
1892
1893         cpu = all_cpu_data[cpunum];
1894
1895         cpu->cpu = cpunum;
1896
1897         if (hwp_active) {
1898                 const struct x86_cpu_id *id;
1899
1900                 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
1901                 if (id)
1902                         intel_pstate_disable_ee(cpunum);
1903
1904                 intel_pstate_hwp_enable(cpu);
1905
1906                 id = x86_match_cpu(intel_pstate_hwp_boost_ids);
1907                 if (id && intel_pstate_acpi_pm_profile_server())
1908                         hwp_boost = true;
1909         }
1910
1911         intel_pstate_get_cpu_pstates(cpu);
1912
1913         pr_debug("controlling: cpu %d\n", cpunum);
1914
1915         return 0;
1916 }
1917
1918 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
1919 {
1920         struct cpudata *cpu = all_cpu_data[cpu_num];
1921
1922         if (hwp_active && !hwp_boost)
1923                 return;
1924
1925         if (cpu->update_util_set)
1926                 return;
1927
1928         /* Prevent intel_pstate_update_util() from using stale data. */
1929         cpu->sample.time = 0;
1930         cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
1931                                      (hwp_active ?
1932                                       intel_pstate_update_util_hwp :
1933                                       intel_pstate_update_util));
1934         cpu->update_util_set = true;
1935 }
1936
1937 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
1938 {
1939         struct cpudata *cpu_data = all_cpu_data[cpu];
1940
1941         if (!cpu_data->update_util_set)
1942                 return;
1943
1944         cpufreq_remove_update_util_hook(cpu);
1945         cpu_data->update_util_set = false;
1946         synchronize_rcu();
1947 }
1948
1949 static int intel_pstate_get_max_freq(struct cpudata *cpu)
1950 {
1951         return global.turbo_disabled || global.no_turbo ?
1952                         cpu->pstate.max_freq : cpu->pstate.turbo_freq;
1953 }
1954
1955 static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
1956                                             struct cpudata *cpu)
1957 {
1958         int max_freq = intel_pstate_get_max_freq(cpu);
1959         int32_t max_policy_perf, min_policy_perf;
1960         int max_state, turbo_max;
1961
1962         /*
1963          * HWP needs some special consideration, because on BDX the
1964          * HWP_REQUEST uses abstract value to represent performance
1965          * rather than pure ratios.
1966          */
1967         if (hwp_active) {
1968                 intel_pstate_get_hwp_max(cpu->cpu, &turbo_max, &max_state);
1969         } else {
1970                 max_state = global.no_turbo || global.turbo_disabled ?
1971                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1972                 turbo_max = cpu->pstate.turbo_pstate;
1973         }
1974
1975         max_policy_perf = max_state * policy->max / max_freq;
1976         if (policy->max == policy->min) {
1977                 min_policy_perf = max_policy_perf;
1978         } else {
1979                 min_policy_perf = max_state * policy->min / max_freq;
1980                 min_policy_perf = clamp_t(int32_t, min_policy_perf,
1981                                           0, max_policy_perf);
1982         }
1983
1984         pr_debug("cpu:%d max_state %d min_policy_perf:%d max_policy_perf:%d\n",
1985                  policy->cpu, max_state,
1986                  min_policy_perf, max_policy_perf);
1987
1988         /* Normalize user input to [min_perf, max_perf] */
1989         if (per_cpu_limits) {
1990                 cpu->min_perf_ratio = min_policy_perf;
1991                 cpu->max_perf_ratio = max_policy_perf;
1992         } else {
1993                 int32_t global_min, global_max;
1994
1995                 /* Global limits are in percent of the maximum turbo P-state. */
1996                 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
1997                 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
1998                 global_min = clamp_t(int32_t, global_min, 0, global_max);
1999
2000                 pr_debug("cpu:%d global_min:%d global_max:%d\n", policy->cpu,
2001                          global_min, global_max);
2002
2003                 cpu->min_perf_ratio = max(min_policy_perf, global_min);
2004                 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
2005                 cpu->max_perf_ratio = min(max_policy_perf, global_max);
2006                 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
2007
2008                 /* Make sure min_perf <= max_perf */
2009                 cpu->min_perf_ratio = min(cpu->min_perf_ratio,
2010                                           cpu->max_perf_ratio);
2011
2012         }
2013         pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", policy->cpu,
2014                  cpu->max_perf_ratio,
2015                  cpu->min_perf_ratio);
2016 }
2017
2018 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2019 {
2020         struct cpudata *cpu;
2021
2022         if (!policy->cpuinfo.max_freq)
2023                 return -ENODEV;
2024
2025         pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2026                  policy->cpuinfo.max_freq, policy->max);
2027
2028         cpu = all_cpu_data[policy->cpu];
2029         cpu->policy = policy->policy;
2030
2031         mutex_lock(&intel_pstate_limits_lock);
2032
2033         intel_pstate_update_perf_limits(policy, cpu);
2034
2035         if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2036                 /*
2037                  * NOHZ_FULL CPUs need this as the governor callback may not
2038                  * be invoked on them.
2039                  */
2040                 intel_pstate_clear_update_util_hook(policy->cpu);
2041                 intel_pstate_max_within_limits(cpu);
2042         } else {
2043                 intel_pstate_set_update_util_hook(policy->cpu);
2044         }
2045
2046         if (hwp_active) {
2047                 /*
2048                  * When hwp_boost was active before and dynamically it
2049                  * was turned off, in that case we need to clear the
2050                  * update util hook.
2051                  */
2052                 if (!hwp_boost)
2053                         intel_pstate_clear_update_util_hook(policy->cpu);
2054                 intel_pstate_hwp_set(policy->cpu);
2055         }
2056
2057         mutex_unlock(&intel_pstate_limits_lock);
2058
2059         return 0;
2060 }
2061
2062 static void intel_pstate_adjust_policy_max(struct cpufreq_policy *policy,
2063                                          struct cpudata *cpu)
2064 {
2065         if (!hwp_active &&
2066             cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2067             policy->max < policy->cpuinfo.max_freq &&
2068             policy->max > cpu->pstate.max_freq) {
2069                 pr_debug("policy->max > max non turbo frequency\n");
2070                 policy->max = policy->cpuinfo.max_freq;
2071         }
2072 }
2073
2074 static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
2075 {
2076         struct cpudata *cpu = all_cpu_data[policy->cpu];
2077
2078         update_turbo_state();
2079         cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2080                                      intel_pstate_get_max_freq(cpu));
2081
2082         if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
2083             policy->policy != CPUFREQ_POLICY_PERFORMANCE)
2084                 return -EINVAL;
2085
2086         intel_pstate_adjust_policy_max(policy, cpu);
2087
2088         return 0;
2089 }
2090
2091 static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)
2092 {
2093         intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);
2094 }
2095
2096 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
2097 {
2098         pr_debug("CPU %d exiting\n", policy->cpu);
2099
2100         intel_pstate_clear_update_util_hook(policy->cpu);
2101         if (hwp_active) {
2102                 intel_pstate_hwp_save_state(policy);
2103                 intel_pstate_hwp_force_min_perf(policy->cpu);
2104         } else {
2105                 intel_cpufreq_stop_cpu(policy);
2106         }
2107 }
2108
2109 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2110 {
2111         intel_pstate_exit_perf_limits(policy);
2112
2113         policy->fast_switch_possible = false;
2114
2115         return 0;
2116 }
2117
2118 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2119 {
2120         struct cpudata *cpu;
2121         int rc;
2122
2123         rc = intel_pstate_init_cpu(policy->cpu);
2124         if (rc)
2125                 return rc;
2126
2127         cpu = all_cpu_data[policy->cpu];
2128
2129         cpu->max_perf_ratio = 0xFF;
2130         cpu->min_perf_ratio = 0;
2131
2132         policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
2133         policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
2134
2135         /* cpuinfo and default policy values */
2136         policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
2137         update_turbo_state();
2138         policy->cpuinfo.max_freq = global.turbo_disabled ?
2139                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2140         policy->cpuinfo.max_freq *= cpu->pstate.scaling;
2141
2142         if (hwp_active) {
2143                 unsigned int max_freq;
2144
2145                 max_freq = global.turbo_disabled ?
2146                         cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2147                 if (max_freq < policy->cpuinfo.max_freq)
2148                         policy->cpuinfo.max_freq = max_freq;
2149         }
2150
2151         intel_pstate_init_acpi_perf_limits(policy);
2152
2153         policy->fast_switch_possible = true;
2154
2155         return 0;
2156 }
2157
2158 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2159 {
2160         int ret = __intel_pstate_cpu_init(policy);
2161
2162         if (ret)
2163                 return ret;
2164
2165         if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE))
2166                 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
2167         else
2168                 policy->policy = CPUFREQ_POLICY_POWERSAVE;
2169
2170         return 0;
2171 }
2172
2173 static struct cpufreq_driver intel_pstate = {
2174         .flags          = CPUFREQ_CONST_LOOPS,
2175         .verify         = intel_pstate_verify_policy,
2176         .setpolicy      = intel_pstate_set_policy,
2177         .suspend        = intel_pstate_hwp_save_state,
2178         .resume         = intel_pstate_resume,
2179         .init           = intel_pstate_cpu_init,
2180         .exit           = intel_pstate_cpu_exit,
2181         .stop_cpu       = intel_pstate_stop_cpu,
2182         .name           = "intel_pstate",
2183 };
2184
2185 static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy)
2186 {
2187         struct cpudata *cpu = all_cpu_data[policy->cpu];
2188
2189         update_turbo_state();
2190         cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2191                                      intel_pstate_get_max_freq(cpu));
2192
2193         intel_pstate_adjust_policy_max(policy, cpu);
2194
2195         intel_pstate_update_perf_limits(policy, cpu);
2196
2197         return 0;
2198 }
2199
2200 /* Use of trace in passive mode:
2201  *
2202  * In passive mode the trace core_busy field (also known as the
2203  * performance field, and lablelled as such on the graphs; also known as
2204  * core_avg_perf) is not needed and so is re-assigned to indicate if the
2205  * driver call was via the normal or fast switch path. Various graphs
2206  * output from the intel_pstate_tracer.py utility that include core_busy
2207  * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%,
2208  * so we use 10 to indicate the the normal path through the driver, and
2209  * 90 to indicate the fast switch path through the driver.
2210  * The scaled_busy field is not used, and is set to 0.
2211  */
2212
2213 #define INTEL_PSTATE_TRACE_TARGET 10
2214 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90
2215
2216 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate)
2217 {
2218         struct sample *sample;
2219
2220         if (!trace_pstate_sample_enabled())
2221                 return;
2222
2223         if (!intel_pstate_sample(cpu, ktime_get()))
2224                 return;
2225
2226         sample = &cpu->sample;
2227         trace_pstate_sample(trace_type,
2228                 0,
2229                 old_pstate,
2230                 cpu->pstate.current_pstate,
2231                 sample->mperf,
2232                 sample->aperf,
2233                 sample->tsc,
2234                 get_avg_frequency(cpu),
2235                 fp_toint(cpu->iowait_boost * 100));
2236 }
2237
2238 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2239                                 unsigned int target_freq,
2240                                 unsigned int relation)
2241 {
2242         struct cpudata *cpu = all_cpu_data[policy->cpu];
2243         struct cpufreq_freqs freqs;
2244         int target_pstate, old_pstate;
2245
2246         update_turbo_state();
2247
2248         freqs.old = policy->cur;
2249         freqs.new = target_freq;
2250
2251         cpufreq_freq_transition_begin(policy, &freqs);
2252         switch (relation) {
2253         case CPUFREQ_RELATION_L:
2254                 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2255                 break;
2256         case CPUFREQ_RELATION_H:
2257                 target_pstate = freqs.new / cpu->pstate.scaling;
2258                 break;
2259         default:
2260                 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2261                 break;
2262         }
2263         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2264         old_pstate = cpu->pstate.current_pstate;
2265         if (target_pstate != cpu->pstate.current_pstate) {
2266                 cpu->pstate.current_pstate = target_pstate;
2267                 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL,
2268                               pstate_funcs.get_val(cpu, target_pstate));
2269         }
2270         freqs.new = target_pstate * cpu->pstate.scaling;
2271         intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_TARGET, old_pstate);
2272         cpufreq_freq_transition_end(policy, &freqs, false);
2273
2274         return 0;
2275 }
2276
2277 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2278                                               unsigned int target_freq)
2279 {
2280         struct cpudata *cpu = all_cpu_data[policy->cpu];
2281         int target_pstate, old_pstate;
2282
2283         update_turbo_state();
2284
2285         target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2286         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2287         old_pstate = cpu->pstate.current_pstate;
2288         intel_pstate_update_pstate(cpu, target_pstate);
2289         intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate);
2290         return target_pstate * cpu->pstate.scaling;
2291 }
2292
2293 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2294 {
2295         int ret = __intel_pstate_cpu_init(policy);
2296
2297         if (ret)
2298                 return ret;
2299
2300         policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2301         policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
2302         /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2303         policy->cur = policy->cpuinfo.min_freq;
2304
2305         return 0;
2306 }
2307
2308 static struct cpufreq_driver intel_cpufreq = {
2309         .flags          = CPUFREQ_CONST_LOOPS,
2310         .verify         = intel_cpufreq_verify_policy,
2311         .target         = intel_cpufreq_target,
2312         .fast_switch    = intel_cpufreq_fast_switch,
2313         .init           = intel_cpufreq_cpu_init,
2314         .exit           = intel_pstate_cpu_exit,
2315         .stop_cpu       = intel_cpufreq_stop_cpu,
2316         .name           = "intel_cpufreq",
2317 };
2318
2319 static struct cpufreq_driver *default_driver = &intel_pstate;
2320
2321 static void intel_pstate_driver_cleanup(void)
2322 {
2323         unsigned int cpu;
2324
2325         get_online_cpus();
2326         for_each_online_cpu(cpu) {
2327                 if (all_cpu_data[cpu]) {
2328                         if (intel_pstate_driver == &intel_pstate)
2329                                 intel_pstate_clear_update_util_hook(cpu);
2330
2331                         kfree(all_cpu_data[cpu]);
2332                         all_cpu_data[cpu] = NULL;
2333                 }
2334         }
2335         put_online_cpus();
2336         intel_pstate_driver = NULL;
2337 }
2338
2339 static int intel_pstate_register_driver(struct cpufreq_driver *driver)
2340 {
2341         int ret;
2342
2343         memset(&global, 0, sizeof(global));
2344         global.max_perf_pct = 100;
2345
2346         intel_pstate_driver = driver;
2347         ret = cpufreq_register_driver(intel_pstate_driver);
2348         if (ret) {
2349                 intel_pstate_driver_cleanup();
2350                 return ret;
2351         }
2352
2353         global.min_perf_pct = min_perf_pct_min();
2354
2355         return 0;
2356 }
2357
2358 static int intel_pstate_unregister_driver(void)
2359 {
2360         if (hwp_active)
2361                 return -EBUSY;
2362
2363         cpufreq_unregister_driver(intel_pstate_driver);
2364         intel_pstate_driver_cleanup();
2365
2366         return 0;
2367 }
2368
2369 static ssize_t intel_pstate_show_status(char *buf)
2370 {
2371         if (!intel_pstate_driver)
2372                 return sprintf(buf, "off\n");
2373
2374         return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
2375                                         "active" : "passive");
2376 }
2377
2378 static int intel_pstate_update_status(const char *buf, size_t size)
2379 {
2380         int ret;
2381
2382         if (size == 3 && !strncmp(buf, "off", size))
2383                 return intel_pstate_driver ?
2384                         intel_pstate_unregister_driver() : -EINVAL;
2385
2386         if (size == 6 && !strncmp(buf, "active", size)) {
2387                 if (intel_pstate_driver) {
2388                         if (intel_pstate_driver == &intel_pstate)
2389                                 return 0;
2390
2391                         ret = intel_pstate_unregister_driver();
2392                         if (ret)
2393                                 return ret;
2394                 }
2395
2396                 return intel_pstate_register_driver(&intel_pstate);
2397         }
2398
2399         if (size == 7 && !strncmp(buf, "passive", size)) {
2400                 if (intel_pstate_driver) {
2401                         if (intel_pstate_driver == &intel_cpufreq)
2402                                 return 0;
2403
2404                         ret = intel_pstate_unregister_driver();
2405                         if (ret)
2406                                 return ret;
2407                 }
2408
2409                 return intel_pstate_register_driver(&intel_cpufreq);
2410         }
2411
2412         return -EINVAL;
2413 }
2414
2415 static int no_load __initdata;
2416 static int no_hwp __initdata;
2417 static int hwp_only __initdata;
2418 static unsigned int force_load __initdata;
2419
2420 static int __init intel_pstate_msrs_not_valid(void)
2421 {
2422         if (!pstate_funcs.get_max() ||
2423             !pstate_funcs.get_min() ||
2424             !pstate_funcs.get_turbo())
2425                 return -ENODEV;
2426
2427         return 0;
2428 }
2429
2430 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
2431 {
2432         pstate_funcs.get_max   = funcs->get_max;
2433         pstate_funcs.get_max_physical = funcs->get_max_physical;
2434         pstate_funcs.get_min   = funcs->get_min;
2435         pstate_funcs.get_turbo = funcs->get_turbo;
2436         pstate_funcs.get_scaling = funcs->get_scaling;
2437         pstate_funcs.get_val   = funcs->get_val;
2438         pstate_funcs.get_vid   = funcs->get_vid;
2439         pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
2440 }
2441
2442 #ifdef CONFIG_ACPI
2443
2444 static bool __init intel_pstate_no_acpi_pss(void)
2445 {
2446         int i;
2447
2448         for_each_possible_cpu(i) {
2449                 acpi_status status;
2450                 union acpi_object *pss;
2451                 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2452                 struct acpi_processor *pr = per_cpu(processors, i);
2453
2454                 if (!pr)
2455                         continue;
2456
2457                 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2458                 if (ACPI_FAILURE(status))
2459                         continue;
2460
2461                 pss = buffer.pointer;
2462                 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2463                         kfree(pss);
2464                         return false;
2465                 }
2466
2467                 kfree(pss);
2468         }
2469
2470         pr_debug("ACPI _PSS not found\n");
2471         return true;
2472 }
2473
2474 static bool __init intel_pstate_no_acpi_pcch(void)
2475 {
2476         acpi_status status;
2477         acpi_handle handle;
2478
2479         status = acpi_get_handle(NULL, "\\_SB", &handle);
2480         if (ACPI_FAILURE(status))
2481                 goto not_found;
2482
2483         if (acpi_has_method(handle, "PCCH"))
2484                 return false;
2485
2486 not_found:
2487         pr_debug("ACPI PCCH not found\n");
2488         return true;
2489 }
2490
2491 static bool __init intel_pstate_has_acpi_ppc(void)
2492 {
2493         int i;
2494
2495         for_each_possible_cpu(i) {
2496                 struct acpi_processor *pr = per_cpu(processors, i);
2497
2498                 if (!pr)
2499                         continue;
2500                 if (acpi_has_method(pr->handle, "_PPC"))
2501                         return true;
2502         }
2503         pr_debug("ACPI _PPC not found\n");
2504         return false;
2505 }
2506
2507 enum {
2508         PSS,
2509         PPC,
2510 };
2511
2512 /* Hardware vendor-specific info that has its own power management modes */
2513 static struct acpi_platform_list plat_info[] __initdata = {
2514         {"HP    ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, 0, PSS},
2515         {"ORACLE", "X4-2    ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2516         {"ORACLE", "X4-2L   ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2517         {"ORACLE", "X4-2B   ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2518         {"ORACLE", "X3-2    ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2519         {"ORACLE", "X3-2L   ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2520         {"ORACLE", "X3-2B   ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2521         {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2522         {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2523         {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2524         {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2525         {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2526         {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2527         {"ORACLE", "X6-2    ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2528         {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2529         { } /* End */
2530 };
2531
2532 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
2533 {
2534         const struct x86_cpu_id *id;
2535         u64 misc_pwr;
2536         int idx;
2537
2538         id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2539         if (id) {
2540                 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
2541                 if (misc_pwr & (1 << 8)) {
2542                         pr_debug("Bit 8 in the MISC_PWR_MGMT MSR set\n");
2543                         return true;
2544                 }
2545         }
2546
2547         idx = acpi_match_platform_list(plat_info);
2548         if (idx < 0)
2549                 return false;
2550
2551         switch (plat_info[idx].data) {
2552         case PSS:
2553                 if (!intel_pstate_no_acpi_pss())
2554                         return false;
2555
2556                 return intel_pstate_no_acpi_pcch();
2557         case PPC:
2558                 return intel_pstate_has_acpi_ppc() && !force_load;
2559         }
2560
2561         return false;
2562 }
2563
2564 static void intel_pstate_request_control_from_smm(void)
2565 {
2566         /*
2567          * It may be unsafe to request P-states control from SMM if _PPC support
2568          * has not been enabled.
2569          */
2570         if (acpi_ppc)
2571                 acpi_processor_pstate_control();
2572 }
2573 #else /* CONFIG_ACPI not enabled */
2574 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
2575 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
2576 static inline void intel_pstate_request_control_from_smm(void) {}
2577 #endif /* CONFIG_ACPI */
2578
2579 #define INTEL_PSTATE_HWP_BROADWELL      0x01
2580
2581 #define ICPU_HWP(model, hwp_mode) \
2582         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_HWP, hwp_mode }
2583
2584 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
2585         ICPU_HWP(INTEL_FAM6_BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL),
2586         ICPU_HWP(INTEL_FAM6_BROADWELL_XEON_D, INTEL_PSTATE_HWP_BROADWELL),
2587         ICPU_HWP(X86_MODEL_ANY, 0),
2588         {}
2589 };
2590
2591 static int __init intel_pstate_init(void)
2592 {
2593         const struct x86_cpu_id *id;
2594         int rc;
2595
2596         if (no_load)
2597                 return -ENODEV;
2598
2599         id = x86_match_cpu(hwp_support_ids);
2600         if (id) {
2601                 copy_cpu_funcs(&core_funcs);
2602                 if (!no_hwp) {
2603                         hwp_active++;
2604                         hwp_mode_bdw = id->driver_data;
2605                         intel_pstate.attr = hwp_cpufreq_attrs;
2606                         goto hwp_cpu_matched;
2607                 }
2608         } else {
2609                 id = x86_match_cpu(intel_pstate_cpu_ids);
2610                 if (!id) {
2611                         pr_info("CPU ID not supported\n");
2612                         return -ENODEV;
2613                 }
2614
2615                 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
2616         }
2617
2618         if (intel_pstate_msrs_not_valid()) {
2619                 pr_info("Invalid MSRs\n");
2620                 return -ENODEV;
2621         }
2622
2623 hwp_cpu_matched:
2624         /*
2625          * The Intel pstate driver will be ignored if the platform
2626          * firmware has its own power management modes.
2627          */
2628         if (intel_pstate_platform_pwr_mgmt_exists()) {
2629                 pr_info("P-states controlled by the platform\n");
2630                 return -ENODEV;
2631         }
2632
2633         if (!hwp_active && hwp_only)
2634                 return -ENOTSUPP;
2635
2636         pr_info("Intel P-state driver initializing\n");
2637
2638         all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus()));
2639         if (!all_cpu_data)
2640                 return -ENOMEM;
2641
2642         intel_pstate_request_control_from_smm();
2643
2644         intel_pstate_sysfs_expose_params();
2645
2646         mutex_lock(&intel_pstate_driver_lock);
2647         rc = intel_pstate_register_driver(default_driver);
2648         mutex_unlock(&intel_pstate_driver_lock);
2649         if (rc)
2650                 return rc;
2651
2652         if (hwp_active)
2653                 pr_info("HWP enabled\n");
2654
2655         return 0;
2656 }
2657 device_initcall(intel_pstate_init);
2658
2659 static int __init intel_pstate_setup(char *str)
2660 {
2661         if (!str)
2662                 return -EINVAL;
2663
2664         if (!strcmp(str, "disable")) {
2665                 no_load = 1;
2666         } else if (!strcmp(str, "passive")) {
2667                 pr_info("Passive mode enabled\n");
2668                 default_driver = &intel_cpufreq;
2669                 no_hwp = 1;
2670         }
2671         if (!strcmp(str, "no_hwp")) {
2672                 pr_info("HWP disabled\n");
2673                 no_hwp = 1;
2674         }
2675         if (!strcmp(str, "force"))
2676                 force_load = 1;
2677         if (!strcmp(str, "hwp_only"))
2678                 hwp_only = 1;
2679         if (!strcmp(str, "per_cpu_perf_limits"))
2680                 per_cpu_limits = true;
2681
2682 #ifdef CONFIG_ACPI
2683         if (!strcmp(str, "support_acpi_ppc"))
2684                 acpi_ppc = true;
2685 #endif
2686
2687         return 0;
2688 }
2689 early_param("intel_pstate", intel_pstate_setup);
2690
2691 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2692 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2693 MODULE_LICENSE("GPL");