Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
[muen/linux.git] / drivers / crypto / ixp4xx_crypto.c
1 /*
2  * Intel IXP4xx NPE-C crypto driver
3  *
4  * Copyright (C) 2008 Christian Hohnstaedt <chohnstaedt@innominate.com>
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms of version 2 of the GNU General Public License
8  * as published by the Free Software Foundation.
9  *
10  */
11
12 #include <linux/platform_device.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/dmapool.h>
15 #include <linux/crypto.h>
16 #include <linux/kernel.h>
17 #include <linux/rtnetlink.h>
18 #include <linux/interrupt.h>
19 #include <linux/spinlock.h>
20 #include <linux/gfp.h>
21 #include <linux/module.h>
22
23 #include <crypto/ctr.h>
24 #include <crypto/des.h>
25 #include <crypto/aes.h>
26 #include <crypto/hmac.h>
27 #include <crypto/sha.h>
28 #include <crypto/algapi.h>
29 #include <crypto/internal/aead.h>
30 #include <crypto/authenc.h>
31 #include <crypto/scatterwalk.h>
32
33 #include <mach/npe.h>
34 #include <mach/qmgr.h>
35
36 #define MAX_KEYLEN 32
37
38 /* hash: cfgword + 2 * digestlen; crypt: keylen + cfgword */
39 #define NPE_CTX_LEN 80
40 #define AES_BLOCK128 16
41
42 #define NPE_OP_HASH_VERIFY   0x01
43 #define NPE_OP_CCM_ENABLE    0x04
44 #define NPE_OP_CRYPT_ENABLE  0x08
45 #define NPE_OP_HASH_ENABLE   0x10
46 #define NPE_OP_NOT_IN_PLACE  0x20
47 #define NPE_OP_HMAC_DISABLE  0x40
48 #define NPE_OP_CRYPT_ENCRYPT 0x80
49
50 #define NPE_OP_CCM_GEN_MIC   0xcc
51 #define NPE_OP_HASH_GEN_ICV  0x50
52 #define NPE_OP_ENC_GEN_KEY   0xc9
53
54 #define MOD_ECB     0x0000
55 #define MOD_CTR     0x1000
56 #define MOD_CBC_ENC 0x2000
57 #define MOD_CBC_DEC 0x3000
58 #define MOD_CCM_ENC 0x4000
59 #define MOD_CCM_DEC 0x5000
60
61 #define KEYLEN_128  4
62 #define KEYLEN_192  6
63 #define KEYLEN_256  8
64
65 #define CIPH_DECR   0x0000
66 #define CIPH_ENCR   0x0400
67
68 #define MOD_DES     0x0000
69 #define MOD_TDEA2   0x0100
70 #define MOD_3DES   0x0200
71 #define MOD_AES     0x0800
72 #define MOD_AES128  (0x0800 | KEYLEN_128)
73 #define MOD_AES192  (0x0900 | KEYLEN_192)
74 #define MOD_AES256  (0x0a00 | KEYLEN_256)
75
76 #define MAX_IVLEN   16
77 #define NPE_ID      2  /* NPE C */
78 #define NPE_QLEN    16
79 /* Space for registering when the first
80  * NPE_QLEN crypt_ctl are busy */
81 #define NPE_QLEN_TOTAL 64
82
83 #define SEND_QID    29
84 #define RECV_QID    30
85
86 #define CTL_FLAG_UNUSED         0x0000
87 #define CTL_FLAG_USED           0x1000
88 #define CTL_FLAG_PERFORM_ABLK   0x0001
89 #define CTL_FLAG_GEN_ICV        0x0002
90 #define CTL_FLAG_GEN_REVAES     0x0004
91 #define CTL_FLAG_PERFORM_AEAD   0x0008
92 #define CTL_FLAG_MASK           0x000f
93
94 #define HMAC_PAD_BLOCKLEN SHA1_BLOCK_SIZE
95
96 #define MD5_DIGEST_SIZE   16
97
98 struct buffer_desc {
99         u32 phys_next;
100 #ifdef __ARMEB__
101         u16 buf_len;
102         u16 pkt_len;
103 #else
104         u16 pkt_len;
105         u16 buf_len;
106 #endif
107         u32 phys_addr;
108         u32 __reserved[4];
109         struct buffer_desc *next;
110         enum dma_data_direction dir;
111 };
112
113 struct crypt_ctl {
114 #ifdef __ARMEB__
115         u8 mode;                /* NPE_OP_*  operation mode */
116         u8 init_len;
117         u16 reserved;
118 #else
119         u16 reserved;
120         u8 init_len;
121         u8 mode;                /* NPE_OP_*  operation mode */
122 #endif
123         u8 iv[MAX_IVLEN];       /* IV for CBC mode or CTR IV for CTR mode */
124         u32 icv_rev_aes;        /* icv or rev aes */
125         u32 src_buf;
126         u32 dst_buf;
127 #ifdef __ARMEB__
128         u16 auth_offs;          /* Authentication start offset */
129         u16 auth_len;           /* Authentication data length */
130         u16 crypt_offs;         /* Cryption start offset */
131         u16 crypt_len;          /* Cryption data length */
132 #else
133         u16 auth_len;           /* Authentication data length */
134         u16 auth_offs;          /* Authentication start offset */
135         u16 crypt_len;          /* Cryption data length */
136         u16 crypt_offs;         /* Cryption start offset */
137 #endif
138         u32 aadAddr;            /* Additional Auth Data Addr for CCM mode */
139         u32 crypto_ctx;         /* NPE Crypto Param structure address */
140
141         /* Used by Host: 4*4 bytes*/
142         unsigned ctl_flags;
143         union {
144                 struct ablkcipher_request *ablk_req;
145                 struct aead_request *aead_req;
146                 struct crypto_tfm *tfm;
147         } data;
148         struct buffer_desc *regist_buf;
149         u8 *regist_ptr;
150 };
151
152 struct ablk_ctx {
153         struct buffer_desc *src;
154         struct buffer_desc *dst;
155 };
156
157 struct aead_ctx {
158         struct buffer_desc *src;
159         struct buffer_desc *dst;
160         struct scatterlist ivlist;
161         /* used when the hmac is not on one sg entry */
162         u8 *hmac_virt;
163         int encrypt;
164 };
165
166 struct ix_hash_algo {
167         u32 cfgword;
168         unsigned char *icv;
169 };
170
171 struct ix_sa_dir {
172         unsigned char *npe_ctx;
173         dma_addr_t npe_ctx_phys;
174         int npe_ctx_idx;
175         u8 npe_mode;
176 };
177
178 struct ixp_ctx {
179         struct ix_sa_dir encrypt;
180         struct ix_sa_dir decrypt;
181         int authkey_len;
182         u8 authkey[MAX_KEYLEN];
183         int enckey_len;
184         u8 enckey[MAX_KEYLEN];
185         u8 salt[MAX_IVLEN];
186         u8 nonce[CTR_RFC3686_NONCE_SIZE];
187         unsigned salted;
188         atomic_t configuring;
189         struct completion completion;
190 };
191
192 struct ixp_alg {
193         struct crypto_alg crypto;
194         const struct ix_hash_algo *hash;
195         u32 cfg_enc;
196         u32 cfg_dec;
197
198         int registered;
199 };
200
201 struct ixp_aead_alg {
202         struct aead_alg crypto;
203         const struct ix_hash_algo *hash;
204         u32 cfg_enc;
205         u32 cfg_dec;
206
207         int registered;
208 };
209
210 static const struct ix_hash_algo hash_alg_md5 = {
211         .cfgword        = 0xAA010004,
212         .icv            = "\x01\x23\x45\x67\x89\xAB\xCD\xEF"
213                           "\xFE\xDC\xBA\x98\x76\x54\x32\x10",
214 };
215 static const struct ix_hash_algo hash_alg_sha1 = {
216         .cfgword        = 0x00000005,
217         .icv            = "\x67\x45\x23\x01\xEF\xCD\xAB\x89\x98\xBA"
218                           "\xDC\xFE\x10\x32\x54\x76\xC3\xD2\xE1\xF0",
219 };
220
221 static struct npe *npe_c;
222 static struct dma_pool *buffer_pool = NULL;
223 static struct dma_pool *ctx_pool = NULL;
224
225 static struct crypt_ctl *crypt_virt = NULL;
226 static dma_addr_t crypt_phys;
227
228 static int support_aes = 1;
229
230 #define DRIVER_NAME "ixp4xx_crypto"
231
232 static struct platform_device *pdev;
233
234 static inline dma_addr_t crypt_virt2phys(struct crypt_ctl *virt)
235 {
236         return crypt_phys + (virt - crypt_virt) * sizeof(struct crypt_ctl);
237 }
238
239 static inline struct crypt_ctl *crypt_phys2virt(dma_addr_t phys)
240 {
241         return crypt_virt + (phys - crypt_phys) / sizeof(struct crypt_ctl);
242 }
243
244 static inline u32 cipher_cfg_enc(struct crypto_tfm *tfm)
245 {
246         return container_of(tfm->__crt_alg, struct ixp_alg,crypto)->cfg_enc;
247 }
248
249 static inline u32 cipher_cfg_dec(struct crypto_tfm *tfm)
250 {
251         return container_of(tfm->__crt_alg, struct ixp_alg,crypto)->cfg_dec;
252 }
253
254 static inline const struct ix_hash_algo *ix_hash(struct crypto_tfm *tfm)
255 {
256         return container_of(tfm->__crt_alg, struct ixp_alg, crypto)->hash;
257 }
258
259 static int setup_crypt_desc(void)
260 {
261         struct device *dev = &pdev->dev;
262         BUILD_BUG_ON(sizeof(struct crypt_ctl) != 64);
263         crypt_virt = dma_alloc_coherent(dev,
264                                         NPE_QLEN * sizeof(struct crypt_ctl),
265                                         &crypt_phys, GFP_ATOMIC);
266         if (!crypt_virt)
267                 return -ENOMEM;
268         return 0;
269 }
270
271 static spinlock_t desc_lock;
272 static struct crypt_ctl *get_crypt_desc(void)
273 {
274         int i;
275         static int idx = 0;
276         unsigned long flags;
277
278         spin_lock_irqsave(&desc_lock, flags);
279
280         if (unlikely(!crypt_virt))
281                 setup_crypt_desc();
282         if (unlikely(!crypt_virt)) {
283                 spin_unlock_irqrestore(&desc_lock, flags);
284                 return NULL;
285         }
286         i = idx;
287         if (crypt_virt[i].ctl_flags == CTL_FLAG_UNUSED) {
288                 if (++idx >= NPE_QLEN)
289                         idx = 0;
290                 crypt_virt[i].ctl_flags = CTL_FLAG_USED;
291                 spin_unlock_irqrestore(&desc_lock, flags);
292                 return crypt_virt +i;
293         } else {
294                 spin_unlock_irqrestore(&desc_lock, flags);
295                 return NULL;
296         }
297 }
298
299 static spinlock_t emerg_lock;
300 static struct crypt_ctl *get_crypt_desc_emerg(void)
301 {
302         int i;
303         static int idx = NPE_QLEN;
304         struct crypt_ctl *desc;
305         unsigned long flags;
306
307         desc = get_crypt_desc();
308         if (desc)
309                 return desc;
310         if (unlikely(!crypt_virt))
311                 return NULL;
312
313         spin_lock_irqsave(&emerg_lock, flags);
314         i = idx;
315         if (crypt_virt[i].ctl_flags == CTL_FLAG_UNUSED) {
316                 if (++idx >= NPE_QLEN_TOTAL)
317                         idx = NPE_QLEN;
318                 crypt_virt[i].ctl_flags = CTL_FLAG_USED;
319                 spin_unlock_irqrestore(&emerg_lock, flags);
320                 return crypt_virt +i;
321         } else {
322                 spin_unlock_irqrestore(&emerg_lock, flags);
323                 return NULL;
324         }
325 }
326
327 static void free_buf_chain(struct device *dev, struct buffer_desc *buf,u32 phys)
328 {
329         while (buf) {
330                 struct buffer_desc *buf1;
331                 u32 phys1;
332
333                 buf1 = buf->next;
334                 phys1 = buf->phys_next;
335                 dma_unmap_single(dev, buf->phys_next, buf->buf_len, buf->dir);
336                 dma_pool_free(buffer_pool, buf, phys);
337                 buf = buf1;
338                 phys = phys1;
339         }
340 }
341
342 static struct tasklet_struct crypto_done_tasklet;
343
344 static void finish_scattered_hmac(struct crypt_ctl *crypt)
345 {
346         struct aead_request *req = crypt->data.aead_req;
347         struct aead_ctx *req_ctx = aead_request_ctx(req);
348         struct crypto_aead *tfm = crypto_aead_reqtfm(req);
349         int authsize = crypto_aead_authsize(tfm);
350         int decryptlen = req->assoclen + req->cryptlen - authsize;
351
352         if (req_ctx->encrypt) {
353                 scatterwalk_map_and_copy(req_ctx->hmac_virt,
354                         req->dst, decryptlen, authsize, 1);
355         }
356         dma_pool_free(buffer_pool, req_ctx->hmac_virt, crypt->icv_rev_aes);
357 }
358
359 static void one_packet(dma_addr_t phys)
360 {
361         struct device *dev = &pdev->dev;
362         struct crypt_ctl *crypt;
363         struct ixp_ctx *ctx;
364         int failed;
365
366         failed = phys & 0x1 ? -EBADMSG : 0;
367         phys &= ~0x3;
368         crypt = crypt_phys2virt(phys);
369
370         switch (crypt->ctl_flags & CTL_FLAG_MASK) {
371         case CTL_FLAG_PERFORM_AEAD: {
372                 struct aead_request *req = crypt->data.aead_req;
373                 struct aead_ctx *req_ctx = aead_request_ctx(req);
374
375                 free_buf_chain(dev, req_ctx->src, crypt->src_buf);
376                 free_buf_chain(dev, req_ctx->dst, crypt->dst_buf);
377                 if (req_ctx->hmac_virt) {
378                         finish_scattered_hmac(crypt);
379                 }
380                 req->base.complete(&req->base, failed);
381                 break;
382         }
383         case CTL_FLAG_PERFORM_ABLK: {
384                 struct ablkcipher_request *req = crypt->data.ablk_req;
385                 struct ablk_ctx *req_ctx = ablkcipher_request_ctx(req);
386
387                 if (req_ctx->dst) {
388                         free_buf_chain(dev, req_ctx->dst, crypt->dst_buf);
389                 }
390                 free_buf_chain(dev, req_ctx->src, crypt->src_buf);
391                 req->base.complete(&req->base, failed);
392                 break;
393         }
394         case CTL_FLAG_GEN_ICV:
395                 ctx = crypto_tfm_ctx(crypt->data.tfm);
396                 dma_pool_free(ctx_pool, crypt->regist_ptr,
397                                 crypt->regist_buf->phys_addr);
398                 dma_pool_free(buffer_pool, crypt->regist_buf, crypt->src_buf);
399                 if (atomic_dec_and_test(&ctx->configuring))
400                         complete(&ctx->completion);
401                 break;
402         case CTL_FLAG_GEN_REVAES:
403                 ctx = crypto_tfm_ctx(crypt->data.tfm);
404                 *(u32*)ctx->decrypt.npe_ctx &= cpu_to_be32(~CIPH_ENCR);
405                 if (atomic_dec_and_test(&ctx->configuring))
406                         complete(&ctx->completion);
407                 break;
408         default:
409                 BUG();
410         }
411         crypt->ctl_flags = CTL_FLAG_UNUSED;
412 }
413
414 static void irqhandler(void *_unused)
415 {
416         tasklet_schedule(&crypto_done_tasklet);
417 }
418
419 static void crypto_done_action(unsigned long arg)
420 {
421         int i;
422
423         for(i=0; i<4; i++) {
424                 dma_addr_t phys = qmgr_get_entry(RECV_QID);
425                 if (!phys)
426                         return;
427                 one_packet(phys);
428         }
429         tasklet_schedule(&crypto_done_tasklet);
430 }
431
432 static int init_ixp_crypto(struct device *dev)
433 {
434         int ret = -ENODEV;
435         u32 msg[2] = { 0, 0 };
436
437         if (! ( ~(*IXP4XX_EXP_CFG2) & (IXP4XX_FEATURE_HASH |
438                                 IXP4XX_FEATURE_AES | IXP4XX_FEATURE_DES))) {
439                 printk(KERN_ERR "ixp_crypto: No HW crypto available\n");
440                 return ret;
441         }
442         npe_c = npe_request(NPE_ID);
443         if (!npe_c)
444                 return ret;
445
446         if (!npe_running(npe_c)) {
447                 ret = npe_load_firmware(npe_c, npe_name(npe_c), dev);
448                 if (ret)
449                         goto npe_release;
450                 if (npe_recv_message(npe_c, msg, "STATUS_MSG"))
451                         goto npe_error;
452         } else {
453                 if (npe_send_message(npe_c, msg, "STATUS_MSG"))
454                         goto npe_error;
455
456                 if (npe_recv_message(npe_c, msg, "STATUS_MSG"))
457                         goto npe_error;
458         }
459
460         switch ((msg[1]>>16) & 0xff) {
461         case 3:
462                 printk(KERN_WARNING "Firmware of %s lacks AES support\n",
463                                 npe_name(npe_c));
464                 support_aes = 0;
465                 break;
466         case 4:
467         case 5:
468                 support_aes = 1;
469                 break;
470         default:
471                 printk(KERN_ERR "Firmware of %s lacks crypto support\n",
472                         npe_name(npe_c));
473                 ret = -ENODEV;
474                 goto npe_release;
475         }
476         /* buffer_pool will also be used to sometimes store the hmac,
477          * so assure it is large enough
478          */
479         BUILD_BUG_ON(SHA1_DIGEST_SIZE > sizeof(struct buffer_desc));
480         buffer_pool = dma_pool_create("buffer", dev,
481                         sizeof(struct buffer_desc), 32, 0);
482         ret = -ENOMEM;
483         if (!buffer_pool) {
484                 goto err;
485         }
486         ctx_pool = dma_pool_create("context", dev,
487                         NPE_CTX_LEN, 16, 0);
488         if (!ctx_pool) {
489                 goto err;
490         }
491         ret = qmgr_request_queue(SEND_QID, NPE_QLEN_TOTAL, 0, 0,
492                                  "ixp_crypto:out", NULL);
493         if (ret)
494                 goto err;
495         ret = qmgr_request_queue(RECV_QID, NPE_QLEN, 0, 0,
496                                  "ixp_crypto:in", NULL);
497         if (ret) {
498                 qmgr_release_queue(SEND_QID);
499                 goto err;
500         }
501         qmgr_set_irq(RECV_QID, QUEUE_IRQ_SRC_NOT_EMPTY, irqhandler, NULL);
502         tasklet_init(&crypto_done_tasklet, crypto_done_action, 0);
503
504         qmgr_enable_irq(RECV_QID);
505         return 0;
506
507 npe_error:
508         printk(KERN_ERR "%s not responding\n", npe_name(npe_c));
509         ret = -EIO;
510 err:
511         dma_pool_destroy(ctx_pool);
512         dma_pool_destroy(buffer_pool);
513 npe_release:
514         npe_release(npe_c);
515         return ret;
516 }
517
518 static void release_ixp_crypto(struct device *dev)
519 {
520         qmgr_disable_irq(RECV_QID);
521         tasklet_kill(&crypto_done_tasklet);
522
523         qmgr_release_queue(SEND_QID);
524         qmgr_release_queue(RECV_QID);
525
526         dma_pool_destroy(ctx_pool);
527         dma_pool_destroy(buffer_pool);
528
529         npe_release(npe_c);
530
531         if (crypt_virt) {
532                 dma_free_coherent(dev,
533                         NPE_QLEN_TOTAL * sizeof( struct crypt_ctl),
534                         crypt_virt, crypt_phys);
535         }
536 }
537
538 static void reset_sa_dir(struct ix_sa_dir *dir)
539 {
540         memset(dir->npe_ctx, 0, NPE_CTX_LEN);
541         dir->npe_ctx_idx = 0;
542         dir->npe_mode = 0;
543 }
544
545 static int init_sa_dir(struct ix_sa_dir *dir)
546 {
547         dir->npe_ctx = dma_pool_alloc(ctx_pool, GFP_KERNEL, &dir->npe_ctx_phys);
548         if (!dir->npe_ctx) {
549                 return -ENOMEM;
550         }
551         reset_sa_dir(dir);
552         return 0;
553 }
554
555 static void free_sa_dir(struct ix_sa_dir *dir)
556 {
557         memset(dir->npe_ctx, 0, NPE_CTX_LEN);
558         dma_pool_free(ctx_pool, dir->npe_ctx, dir->npe_ctx_phys);
559 }
560
561 static int init_tfm(struct crypto_tfm *tfm)
562 {
563         struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
564         int ret;
565
566         atomic_set(&ctx->configuring, 0);
567         ret = init_sa_dir(&ctx->encrypt);
568         if (ret)
569                 return ret;
570         ret = init_sa_dir(&ctx->decrypt);
571         if (ret) {
572                 free_sa_dir(&ctx->encrypt);
573         }
574         return ret;
575 }
576
577 static int init_tfm_ablk(struct crypto_tfm *tfm)
578 {
579         tfm->crt_ablkcipher.reqsize = sizeof(struct ablk_ctx);
580         return init_tfm(tfm);
581 }
582
583 static int init_tfm_aead(struct crypto_aead *tfm)
584 {
585         crypto_aead_set_reqsize(tfm, sizeof(struct aead_ctx));
586         return init_tfm(crypto_aead_tfm(tfm));
587 }
588
589 static void exit_tfm(struct crypto_tfm *tfm)
590 {
591         struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
592         free_sa_dir(&ctx->encrypt);
593         free_sa_dir(&ctx->decrypt);
594 }
595
596 static void exit_tfm_aead(struct crypto_aead *tfm)
597 {
598         exit_tfm(crypto_aead_tfm(tfm));
599 }
600
601 static int register_chain_var(struct crypto_tfm *tfm, u8 xpad, u32 target,
602                 int init_len, u32 ctx_addr, const u8 *key, int key_len)
603 {
604         struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
605         struct crypt_ctl *crypt;
606         struct buffer_desc *buf;
607         int i;
608         u8 *pad;
609         u32 pad_phys, buf_phys;
610
611         BUILD_BUG_ON(NPE_CTX_LEN < HMAC_PAD_BLOCKLEN);
612         pad = dma_pool_alloc(ctx_pool, GFP_KERNEL, &pad_phys);
613         if (!pad)
614                 return -ENOMEM;
615         buf = dma_pool_alloc(buffer_pool, GFP_KERNEL, &buf_phys);
616         if (!buf) {
617                 dma_pool_free(ctx_pool, pad, pad_phys);
618                 return -ENOMEM;
619         }
620         crypt = get_crypt_desc_emerg();
621         if (!crypt) {
622                 dma_pool_free(ctx_pool, pad, pad_phys);
623                 dma_pool_free(buffer_pool, buf, buf_phys);
624                 return -EAGAIN;
625         }
626
627         memcpy(pad, key, key_len);
628         memset(pad + key_len, 0, HMAC_PAD_BLOCKLEN - key_len);
629         for (i = 0; i < HMAC_PAD_BLOCKLEN; i++) {
630                 pad[i] ^= xpad;
631         }
632
633         crypt->data.tfm = tfm;
634         crypt->regist_ptr = pad;
635         crypt->regist_buf = buf;
636
637         crypt->auth_offs = 0;
638         crypt->auth_len = HMAC_PAD_BLOCKLEN;
639         crypt->crypto_ctx = ctx_addr;
640         crypt->src_buf = buf_phys;
641         crypt->icv_rev_aes = target;
642         crypt->mode = NPE_OP_HASH_GEN_ICV;
643         crypt->init_len = init_len;
644         crypt->ctl_flags |= CTL_FLAG_GEN_ICV;
645
646         buf->next = 0;
647         buf->buf_len = HMAC_PAD_BLOCKLEN;
648         buf->pkt_len = 0;
649         buf->phys_addr = pad_phys;
650
651         atomic_inc(&ctx->configuring);
652         qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt));
653         BUG_ON(qmgr_stat_overflow(SEND_QID));
654         return 0;
655 }
656
657 static int setup_auth(struct crypto_tfm *tfm, int encrypt, unsigned authsize,
658                 const u8 *key, int key_len, unsigned digest_len)
659 {
660         u32 itarget, otarget, npe_ctx_addr;
661         unsigned char *cinfo;
662         int init_len, ret = 0;
663         u32 cfgword;
664         struct ix_sa_dir *dir;
665         struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
666         const struct ix_hash_algo *algo;
667
668         dir = encrypt ? &ctx->encrypt : &ctx->decrypt;
669         cinfo = dir->npe_ctx + dir->npe_ctx_idx;
670         algo = ix_hash(tfm);
671
672         /* write cfg word to cryptinfo */
673         cfgword = algo->cfgword | ( authsize << 6); /* (authsize/4) << 8 */
674 #ifndef __ARMEB__
675         cfgword ^= 0xAA000000; /* change the "byte swap" flags */
676 #endif
677         *(u32*)cinfo = cpu_to_be32(cfgword);
678         cinfo += sizeof(cfgword);
679
680         /* write ICV to cryptinfo */
681         memcpy(cinfo, algo->icv, digest_len);
682         cinfo += digest_len;
683
684         itarget = dir->npe_ctx_phys + dir->npe_ctx_idx
685                                 + sizeof(algo->cfgword);
686         otarget = itarget + digest_len;
687         init_len = cinfo - (dir->npe_ctx + dir->npe_ctx_idx);
688         npe_ctx_addr = dir->npe_ctx_phys + dir->npe_ctx_idx;
689
690         dir->npe_ctx_idx += init_len;
691         dir->npe_mode |= NPE_OP_HASH_ENABLE;
692
693         if (!encrypt)
694                 dir->npe_mode |= NPE_OP_HASH_VERIFY;
695
696         ret = register_chain_var(tfm, HMAC_OPAD_VALUE, otarget,
697                         init_len, npe_ctx_addr, key, key_len);
698         if (ret)
699                 return ret;
700         return register_chain_var(tfm, HMAC_IPAD_VALUE, itarget,
701                         init_len, npe_ctx_addr, key, key_len);
702 }
703
704 static int gen_rev_aes_key(struct crypto_tfm *tfm)
705 {
706         struct crypt_ctl *crypt;
707         struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
708         struct ix_sa_dir *dir = &ctx->decrypt;
709
710         crypt = get_crypt_desc_emerg();
711         if (!crypt) {
712                 return -EAGAIN;
713         }
714         *(u32*)dir->npe_ctx |= cpu_to_be32(CIPH_ENCR);
715
716         crypt->data.tfm = tfm;
717         crypt->crypt_offs = 0;
718         crypt->crypt_len = AES_BLOCK128;
719         crypt->src_buf = 0;
720         crypt->crypto_ctx = dir->npe_ctx_phys;
721         crypt->icv_rev_aes = dir->npe_ctx_phys + sizeof(u32);
722         crypt->mode = NPE_OP_ENC_GEN_KEY;
723         crypt->init_len = dir->npe_ctx_idx;
724         crypt->ctl_flags |= CTL_FLAG_GEN_REVAES;
725
726         atomic_inc(&ctx->configuring);
727         qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt));
728         BUG_ON(qmgr_stat_overflow(SEND_QID));
729         return 0;
730 }
731
732 static int setup_cipher(struct crypto_tfm *tfm, int encrypt,
733                 const u8 *key, int key_len)
734 {
735         u8 *cinfo;
736         u32 cipher_cfg;
737         u32 keylen_cfg = 0;
738         struct ix_sa_dir *dir;
739         struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
740         u32 *flags = &tfm->crt_flags;
741
742         dir = encrypt ? &ctx->encrypt : &ctx->decrypt;
743         cinfo = dir->npe_ctx;
744
745         if (encrypt) {
746                 cipher_cfg = cipher_cfg_enc(tfm);
747                 dir->npe_mode |= NPE_OP_CRYPT_ENCRYPT;
748         } else {
749                 cipher_cfg = cipher_cfg_dec(tfm);
750         }
751         if (cipher_cfg & MOD_AES) {
752                 switch (key_len) {
753                 case 16: keylen_cfg = MOD_AES128; break;
754                 case 24: keylen_cfg = MOD_AES192; break;
755                 case 32: keylen_cfg = MOD_AES256; break;
756                 default:
757                         *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
758                         return -EINVAL;
759                 }
760                 cipher_cfg |= keylen_cfg;
761         } else if (cipher_cfg & MOD_3DES) {
762                 const u32 *K = (const u32 *)key;
763                 if (unlikely(!((K[0] ^ K[2]) | (K[1] ^ K[3])) ||
764                              !((K[2] ^ K[4]) | (K[3] ^ K[5]))))
765                 {
766                         *flags |= CRYPTO_TFM_RES_BAD_KEY_SCHED;
767                         return -EINVAL;
768                 }
769         } else {
770                 u32 tmp[DES_EXPKEY_WORDS];
771                 if (des_ekey(tmp, key) == 0) {
772                         *flags |= CRYPTO_TFM_RES_WEAK_KEY;
773                 }
774         }
775         /* write cfg word to cryptinfo */
776         *(u32*)cinfo = cpu_to_be32(cipher_cfg);
777         cinfo += sizeof(cipher_cfg);
778
779         /* write cipher key to cryptinfo */
780         memcpy(cinfo, key, key_len);
781         /* NPE wants keylen set to DES3_EDE_KEY_SIZE even for single DES */
782         if (key_len < DES3_EDE_KEY_SIZE && !(cipher_cfg & MOD_AES)) {
783                 memset(cinfo + key_len, 0, DES3_EDE_KEY_SIZE -key_len);
784                 key_len = DES3_EDE_KEY_SIZE;
785         }
786         dir->npe_ctx_idx = sizeof(cipher_cfg) + key_len;
787         dir->npe_mode |= NPE_OP_CRYPT_ENABLE;
788         if ((cipher_cfg & MOD_AES) && !encrypt) {
789                 return gen_rev_aes_key(tfm);
790         }
791         return 0;
792 }
793
794 static struct buffer_desc *chainup_buffers(struct device *dev,
795                 struct scatterlist *sg, unsigned nbytes,
796                 struct buffer_desc *buf, gfp_t flags,
797                 enum dma_data_direction dir)
798 {
799         for (; nbytes > 0; sg = sg_next(sg)) {
800                 unsigned len = min(nbytes, sg->length);
801                 struct buffer_desc *next_buf;
802                 u32 next_buf_phys;
803                 void *ptr;
804
805                 nbytes -= len;
806                 ptr = sg_virt(sg);
807                 next_buf = dma_pool_alloc(buffer_pool, flags, &next_buf_phys);
808                 if (!next_buf) {
809                         buf = NULL;
810                         break;
811                 }
812                 sg_dma_address(sg) = dma_map_single(dev, ptr, len, dir);
813                 buf->next = next_buf;
814                 buf->phys_next = next_buf_phys;
815                 buf = next_buf;
816
817                 buf->phys_addr = sg_dma_address(sg);
818                 buf->buf_len = len;
819                 buf->dir = dir;
820         }
821         buf->next = NULL;
822         buf->phys_next = 0;
823         return buf;
824 }
825
826 static int ablk_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
827                         unsigned int key_len)
828 {
829         struct ixp_ctx *ctx = crypto_ablkcipher_ctx(tfm);
830         u32 *flags = &tfm->base.crt_flags;
831         int ret;
832
833         init_completion(&ctx->completion);
834         atomic_inc(&ctx->configuring);
835
836         reset_sa_dir(&ctx->encrypt);
837         reset_sa_dir(&ctx->decrypt);
838
839         ctx->encrypt.npe_mode = NPE_OP_HMAC_DISABLE;
840         ctx->decrypt.npe_mode = NPE_OP_HMAC_DISABLE;
841
842         ret = setup_cipher(&tfm->base, 0, key, key_len);
843         if (ret)
844                 goto out;
845         ret = setup_cipher(&tfm->base, 1, key, key_len);
846         if (ret)
847                 goto out;
848
849         if (*flags & CRYPTO_TFM_RES_WEAK_KEY) {
850                 if (*flags & CRYPTO_TFM_REQ_FORBID_WEAK_KEYS) {
851                         ret = -EINVAL;
852                 } else {
853                         *flags &= ~CRYPTO_TFM_RES_WEAK_KEY;
854                 }
855         }
856 out:
857         if (!atomic_dec_and_test(&ctx->configuring))
858                 wait_for_completion(&ctx->completion);
859         return ret;
860 }
861
862 static int ablk_rfc3686_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
863                 unsigned int key_len)
864 {
865         struct ixp_ctx *ctx = crypto_ablkcipher_ctx(tfm);
866
867         /* the nonce is stored in bytes at end of key */
868         if (key_len < CTR_RFC3686_NONCE_SIZE)
869                 return -EINVAL;
870
871         memcpy(ctx->nonce, key + (key_len - CTR_RFC3686_NONCE_SIZE),
872                         CTR_RFC3686_NONCE_SIZE);
873
874         key_len -= CTR_RFC3686_NONCE_SIZE;
875         return ablk_setkey(tfm, key, key_len);
876 }
877
878 static int ablk_perform(struct ablkcipher_request *req, int encrypt)
879 {
880         struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
881         struct ixp_ctx *ctx = crypto_ablkcipher_ctx(tfm);
882         unsigned ivsize = crypto_ablkcipher_ivsize(tfm);
883         struct ix_sa_dir *dir;
884         struct crypt_ctl *crypt;
885         unsigned int nbytes = req->nbytes;
886         enum dma_data_direction src_direction = DMA_BIDIRECTIONAL;
887         struct ablk_ctx *req_ctx = ablkcipher_request_ctx(req);
888         struct buffer_desc src_hook;
889         struct device *dev = &pdev->dev;
890         gfp_t flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ?
891                                 GFP_KERNEL : GFP_ATOMIC;
892
893         if (qmgr_stat_full(SEND_QID))
894                 return -EAGAIN;
895         if (atomic_read(&ctx->configuring))
896                 return -EAGAIN;
897
898         dir = encrypt ? &ctx->encrypt : &ctx->decrypt;
899
900         crypt = get_crypt_desc();
901         if (!crypt)
902                 return -ENOMEM;
903
904         crypt->data.ablk_req = req;
905         crypt->crypto_ctx = dir->npe_ctx_phys;
906         crypt->mode = dir->npe_mode;
907         crypt->init_len = dir->npe_ctx_idx;
908
909         crypt->crypt_offs = 0;
910         crypt->crypt_len = nbytes;
911
912         BUG_ON(ivsize && !req->info);
913         memcpy(crypt->iv, req->info, ivsize);
914         if (req->src != req->dst) {
915                 struct buffer_desc dst_hook;
916                 crypt->mode |= NPE_OP_NOT_IN_PLACE;
917                 /* This was never tested by Intel
918                  * for more than one dst buffer, I think. */
919                 req_ctx->dst = NULL;
920                 if (!chainup_buffers(dev, req->dst, nbytes, &dst_hook,
921                                         flags, DMA_FROM_DEVICE))
922                         goto free_buf_dest;
923                 src_direction = DMA_TO_DEVICE;
924                 req_ctx->dst = dst_hook.next;
925                 crypt->dst_buf = dst_hook.phys_next;
926         } else {
927                 req_ctx->dst = NULL;
928         }
929         req_ctx->src = NULL;
930         if (!chainup_buffers(dev, req->src, nbytes, &src_hook,
931                                 flags, src_direction))
932                 goto free_buf_src;
933
934         req_ctx->src = src_hook.next;
935         crypt->src_buf = src_hook.phys_next;
936         crypt->ctl_flags |= CTL_FLAG_PERFORM_ABLK;
937         qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt));
938         BUG_ON(qmgr_stat_overflow(SEND_QID));
939         return -EINPROGRESS;
940
941 free_buf_src:
942         free_buf_chain(dev, req_ctx->src, crypt->src_buf);
943 free_buf_dest:
944         if (req->src != req->dst) {
945                 free_buf_chain(dev, req_ctx->dst, crypt->dst_buf);
946         }
947         crypt->ctl_flags = CTL_FLAG_UNUSED;
948         return -ENOMEM;
949 }
950
951 static int ablk_encrypt(struct ablkcipher_request *req)
952 {
953         return ablk_perform(req, 1);
954 }
955
956 static int ablk_decrypt(struct ablkcipher_request *req)
957 {
958         return ablk_perform(req, 0);
959 }
960
961 static int ablk_rfc3686_crypt(struct ablkcipher_request *req)
962 {
963         struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
964         struct ixp_ctx *ctx = crypto_ablkcipher_ctx(tfm);
965         u8 iv[CTR_RFC3686_BLOCK_SIZE];
966         u8 *info = req->info;
967         int ret;
968
969         /* set up counter block */
970         memcpy(iv, ctx->nonce, CTR_RFC3686_NONCE_SIZE);
971         memcpy(iv + CTR_RFC3686_NONCE_SIZE, info, CTR_RFC3686_IV_SIZE);
972
973         /* initialize counter portion of counter block */
974         *(__be32 *)(iv + CTR_RFC3686_NONCE_SIZE + CTR_RFC3686_IV_SIZE) =
975                 cpu_to_be32(1);
976
977         req->info = iv;
978         ret = ablk_perform(req, 1);
979         req->info = info;
980         return ret;
981 }
982
983 static int aead_perform(struct aead_request *req, int encrypt,
984                 int cryptoffset, int eff_cryptlen, u8 *iv)
985 {
986         struct crypto_aead *tfm = crypto_aead_reqtfm(req);
987         struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
988         unsigned ivsize = crypto_aead_ivsize(tfm);
989         unsigned authsize = crypto_aead_authsize(tfm);
990         struct ix_sa_dir *dir;
991         struct crypt_ctl *crypt;
992         unsigned int cryptlen;
993         struct buffer_desc *buf, src_hook;
994         struct aead_ctx *req_ctx = aead_request_ctx(req);
995         struct device *dev = &pdev->dev;
996         gfp_t flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ?
997                                 GFP_KERNEL : GFP_ATOMIC;
998         enum dma_data_direction src_direction = DMA_BIDIRECTIONAL;
999         unsigned int lastlen;
1000
1001         if (qmgr_stat_full(SEND_QID))
1002                 return -EAGAIN;
1003         if (atomic_read(&ctx->configuring))
1004                 return -EAGAIN;
1005
1006         if (encrypt) {
1007                 dir = &ctx->encrypt;
1008                 cryptlen = req->cryptlen;
1009         } else {
1010                 dir = &ctx->decrypt;
1011                 /* req->cryptlen includes the authsize when decrypting */
1012                 cryptlen = req->cryptlen -authsize;
1013                 eff_cryptlen -= authsize;
1014         }
1015         crypt = get_crypt_desc();
1016         if (!crypt)
1017                 return -ENOMEM;
1018
1019         crypt->data.aead_req = req;
1020         crypt->crypto_ctx = dir->npe_ctx_phys;
1021         crypt->mode = dir->npe_mode;
1022         crypt->init_len = dir->npe_ctx_idx;
1023
1024         crypt->crypt_offs = cryptoffset;
1025         crypt->crypt_len = eff_cryptlen;
1026
1027         crypt->auth_offs = 0;
1028         crypt->auth_len = req->assoclen + cryptlen;
1029         BUG_ON(ivsize && !req->iv);
1030         memcpy(crypt->iv, req->iv, ivsize);
1031
1032         buf = chainup_buffers(dev, req->src, crypt->auth_len,
1033                               &src_hook, flags, src_direction);
1034         req_ctx->src = src_hook.next;
1035         crypt->src_buf = src_hook.phys_next;
1036         if (!buf)
1037                 goto free_buf_src;
1038
1039         lastlen = buf->buf_len;
1040         if (lastlen >= authsize)
1041                 crypt->icv_rev_aes = buf->phys_addr +
1042                                      buf->buf_len - authsize;
1043
1044         req_ctx->dst = NULL;
1045
1046         if (req->src != req->dst) {
1047                 struct buffer_desc dst_hook;
1048
1049                 crypt->mode |= NPE_OP_NOT_IN_PLACE;
1050                 src_direction = DMA_TO_DEVICE;
1051
1052                 buf = chainup_buffers(dev, req->dst, crypt->auth_len,
1053                                       &dst_hook, flags, DMA_FROM_DEVICE);
1054                 req_ctx->dst = dst_hook.next;
1055                 crypt->dst_buf = dst_hook.phys_next;
1056
1057                 if (!buf)
1058                         goto free_buf_dst;
1059
1060                 if (encrypt) {
1061                         lastlen = buf->buf_len;
1062                         if (lastlen >= authsize)
1063                                 crypt->icv_rev_aes = buf->phys_addr +
1064                                                      buf->buf_len - authsize;
1065                 }
1066         }
1067
1068         if (unlikely(lastlen < authsize)) {
1069                 /* The 12 hmac bytes are scattered,
1070                  * we need to copy them into a safe buffer */
1071                 req_ctx->hmac_virt = dma_pool_alloc(buffer_pool, flags,
1072                                 &crypt->icv_rev_aes);
1073                 if (unlikely(!req_ctx->hmac_virt))
1074                         goto free_buf_dst;
1075                 if (!encrypt) {
1076                         scatterwalk_map_and_copy(req_ctx->hmac_virt,
1077                                 req->src, cryptlen, authsize, 0);
1078                 }
1079                 req_ctx->encrypt = encrypt;
1080         } else {
1081                 req_ctx->hmac_virt = NULL;
1082         }
1083
1084         crypt->ctl_flags |= CTL_FLAG_PERFORM_AEAD;
1085         qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt));
1086         BUG_ON(qmgr_stat_overflow(SEND_QID));
1087         return -EINPROGRESS;
1088
1089 free_buf_dst:
1090         free_buf_chain(dev, req_ctx->dst, crypt->dst_buf);
1091 free_buf_src:
1092         free_buf_chain(dev, req_ctx->src, crypt->src_buf);
1093         crypt->ctl_flags = CTL_FLAG_UNUSED;
1094         return -ENOMEM;
1095 }
1096
1097 static int aead_setup(struct crypto_aead *tfm, unsigned int authsize)
1098 {
1099         struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
1100         u32 *flags = &tfm->base.crt_flags;
1101         unsigned digest_len = crypto_aead_maxauthsize(tfm);
1102         int ret;
1103
1104         if (!ctx->enckey_len && !ctx->authkey_len)
1105                 return 0;
1106         init_completion(&ctx->completion);
1107         atomic_inc(&ctx->configuring);
1108
1109         reset_sa_dir(&ctx->encrypt);
1110         reset_sa_dir(&ctx->decrypt);
1111
1112         ret = setup_cipher(&tfm->base, 0, ctx->enckey, ctx->enckey_len);
1113         if (ret)
1114                 goto out;
1115         ret = setup_cipher(&tfm->base, 1, ctx->enckey, ctx->enckey_len);
1116         if (ret)
1117                 goto out;
1118         ret = setup_auth(&tfm->base, 0, authsize, ctx->authkey,
1119                         ctx->authkey_len, digest_len);
1120         if (ret)
1121                 goto out;
1122         ret = setup_auth(&tfm->base, 1, authsize,  ctx->authkey,
1123                         ctx->authkey_len, digest_len);
1124         if (ret)
1125                 goto out;
1126
1127         if (*flags & CRYPTO_TFM_RES_WEAK_KEY) {
1128                 if (*flags & CRYPTO_TFM_REQ_FORBID_WEAK_KEYS) {
1129                         ret = -EINVAL;
1130                         goto out;
1131                 } else {
1132                         *flags &= ~CRYPTO_TFM_RES_WEAK_KEY;
1133                 }
1134         }
1135 out:
1136         if (!atomic_dec_and_test(&ctx->configuring))
1137                 wait_for_completion(&ctx->completion);
1138         return ret;
1139 }
1140
1141 static int aead_setauthsize(struct crypto_aead *tfm, unsigned int authsize)
1142 {
1143         int max = crypto_aead_maxauthsize(tfm) >> 2;
1144
1145         if ((authsize>>2) < 1 || (authsize>>2) > max || (authsize & 3))
1146                 return -EINVAL;
1147         return aead_setup(tfm, authsize);
1148 }
1149
1150 static int aead_setkey(struct crypto_aead *tfm, const u8 *key,
1151                         unsigned int keylen)
1152 {
1153         struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
1154         struct crypto_authenc_keys keys;
1155
1156         if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
1157                 goto badkey;
1158
1159         if (keys.authkeylen > sizeof(ctx->authkey))
1160                 goto badkey;
1161
1162         if (keys.enckeylen > sizeof(ctx->enckey))
1163                 goto badkey;
1164
1165         memcpy(ctx->authkey, keys.authkey, keys.authkeylen);
1166         memcpy(ctx->enckey, keys.enckey, keys.enckeylen);
1167         ctx->authkey_len = keys.authkeylen;
1168         ctx->enckey_len = keys.enckeylen;
1169
1170         memzero_explicit(&keys, sizeof(keys));
1171         return aead_setup(tfm, crypto_aead_authsize(tfm));
1172 badkey:
1173         crypto_aead_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
1174         memzero_explicit(&keys, sizeof(keys));
1175         return -EINVAL;
1176 }
1177
1178 static int aead_encrypt(struct aead_request *req)
1179 {
1180         return aead_perform(req, 1, req->assoclen, req->cryptlen, req->iv);
1181 }
1182
1183 static int aead_decrypt(struct aead_request *req)
1184 {
1185         return aead_perform(req, 0, req->assoclen, req->cryptlen, req->iv);
1186 }
1187
1188 static struct ixp_alg ixp4xx_algos[] = {
1189 {
1190         .crypto = {
1191                 .cra_name       = "cbc(des)",
1192                 .cra_blocksize  = DES_BLOCK_SIZE,
1193                 .cra_u          = { .ablkcipher = {
1194                         .min_keysize    = DES_KEY_SIZE,
1195                         .max_keysize    = DES_KEY_SIZE,
1196                         .ivsize         = DES_BLOCK_SIZE,
1197                         }
1198                 }
1199         },
1200         .cfg_enc = CIPH_ENCR | MOD_DES | MOD_CBC_ENC | KEYLEN_192,
1201         .cfg_dec = CIPH_DECR | MOD_DES | MOD_CBC_DEC | KEYLEN_192,
1202
1203 }, {
1204         .crypto = {
1205                 .cra_name       = "ecb(des)",
1206                 .cra_blocksize  = DES_BLOCK_SIZE,
1207                 .cra_u          = { .ablkcipher = {
1208                         .min_keysize    = DES_KEY_SIZE,
1209                         .max_keysize    = DES_KEY_SIZE,
1210                         }
1211                 }
1212         },
1213         .cfg_enc = CIPH_ENCR | MOD_DES | MOD_ECB | KEYLEN_192,
1214         .cfg_dec = CIPH_DECR | MOD_DES | MOD_ECB | KEYLEN_192,
1215 }, {
1216         .crypto = {
1217                 .cra_name       = "cbc(des3_ede)",
1218                 .cra_blocksize  = DES3_EDE_BLOCK_SIZE,
1219                 .cra_u          = { .ablkcipher = {
1220                         .min_keysize    = DES3_EDE_KEY_SIZE,
1221                         .max_keysize    = DES3_EDE_KEY_SIZE,
1222                         .ivsize         = DES3_EDE_BLOCK_SIZE,
1223                         }
1224                 }
1225         },
1226         .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_CBC_ENC | KEYLEN_192,
1227         .cfg_dec = CIPH_DECR | MOD_3DES | MOD_CBC_DEC | KEYLEN_192,
1228 }, {
1229         .crypto = {
1230                 .cra_name       = "ecb(des3_ede)",
1231                 .cra_blocksize  = DES3_EDE_BLOCK_SIZE,
1232                 .cra_u          = { .ablkcipher = {
1233                         .min_keysize    = DES3_EDE_KEY_SIZE,
1234                         .max_keysize    = DES3_EDE_KEY_SIZE,
1235                         }
1236                 }
1237         },
1238         .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_ECB | KEYLEN_192,
1239         .cfg_dec = CIPH_DECR | MOD_3DES | MOD_ECB | KEYLEN_192,
1240 }, {
1241         .crypto = {
1242                 .cra_name       = "cbc(aes)",
1243                 .cra_blocksize  = AES_BLOCK_SIZE,
1244                 .cra_u          = { .ablkcipher = {
1245                         .min_keysize    = AES_MIN_KEY_SIZE,
1246                         .max_keysize    = AES_MAX_KEY_SIZE,
1247                         .ivsize         = AES_BLOCK_SIZE,
1248                         }
1249                 }
1250         },
1251         .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CBC_ENC,
1252         .cfg_dec = CIPH_DECR | MOD_AES | MOD_CBC_DEC,
1253 }, {
1254         .crypto = {
1255                 .cra_name       = "ecb(aes)",
1256                 .cra_blocksize  = AES_BLOCK_SIZE,
1257                 .cra_u          = { .ablkcipher = {
1258                         .min_keysize    = AES_MIN_KEY_SIZE,
1259                         .max_keysize    = AES_MAX_KEY_SIZE,
1260                         }
1261                 }
1262         },
1263         .cfg_enc = CIPH_ENCR | MOD_AES | MOD_ECB,
1264         .cfg_dec = CIPH_DECR | MOD_AES | MOD_ECB,
1265 }, {
1266         .crypto = {
1267                 .cra_name       = "ctr(aes)",
1268                 .cra_blocksize  = AES_BLOCK_SIZE,
1269                 .cra_u          = { .ablkcipher = {
1270                         .min_keysize    = AES_MIN_KEY_SIZE,
1271                         .max_keysize    = AES_MAX_KEY_SIZE,
1272                         .ivsize         = AES_BLOCK_SIZE,
1273                         }
1274                 }
1275         },
1276         .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CTR,
1277         .cfg_dec = CIPH_ENCR | MOD_AES | MOD_CTR,
1278 }, {
1279         .crypto = {
1280                 .cra_name       = "rfc3686(ctr(aes))",
1281                 .cra_blocksize  = AES_BLOCK_SIZE,
1282                 .cra_u          = { .ablkcipher = {
1283                         .min_keysize    = AES_MIN_KEY_SIZE,
1284                         .max_keysize    = AES_MAX_KEY_SIZE,
1285                         .ivsize         = AES_BLOCK_SIZE,
1286                         .setkey         = ablk_rfc3686_setkey,
1287                         .encrypt        = ablk_rfc3686_crypt,
1288                         .decrypt        = ablk_rfc3686_crypt }
1289                 }
1290         },
1291         .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CTR,
1292         .cfg_dec = CIPH_ENCR | MOD_AES | MOD_CTR,
1293 } };
1294
1295 static struct ixp_aead_alg ixp4xx_aeads[] = {
1296 {
1297         .crypto = {
1298                 .base = {
1299                         .cra_name       = "authenc(hmac(md5),cbc(des))",
1300                         .cra_blocksize  = DES_BLOCK_SIZE,
1301                 },
1302                 .ivsize         = DES_BLOCK_SIZE,
1303                 .maxauthsize    = MD5_DIGEST_SIZE,
1304         },
1305         .hash = &hash_alg_md5,
1306         .cfg_enc = CIPH_ENCR | MOD_DES | MOD_CBC_ENC | KEYLEN_192,
1307         .cfg_dec = CIPH_DECR | MOD_DES | MOD_CBC_DEC | KEYLEN_192,
1308 }, {
1309         .crypto = {
1310                 .base = {
1311                         .cra_name       = "authenc(hmac(md5),cbc(des3_ede))",
1312                         .cra_blocksize  = DES3_EDE_BLOCK_SIZE,
1313                 },
1314                 .ivsize         = DES3_EDE_BLOCK_SIZE,
1315                 .maxauthsize    = MD5_DIGEST_SIZE,
1316         },
1317         .hash = &hash_alg_md5,
1318         .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_CBC_ENC | KEYLEN_192,
1319         .cfg_dec = CIPH_DECR | MOD_3DES | MOD_CBC_DEC | KEYLEN_192,
1320 }, {
1321         .crypto = {
1322                 .base = {
1323                         .cra_name       = "authenc(hmac(sha1),cbc(des))",
1324                         .cra_blocksize  = DES_BLOCK_SIZE,
1325                 },
1326                         .ivsize         = DES_BLOCK_SIZE,
1327                         .maxauthsize    = SHA1_DIGEST_SIZE,
1328         },
1329         .hash = &hash_alg_sha1,
1330         .cfg_enc = CIPH_ENCR | MOD_DES | MOD_CBC_ENC | KEYLEN_192,
1331         .cfg_dec = CIPH_DECR | MOD_DES | MOD_CBC_DEC | KEYLEN_192,
1332 }, {
1333         .crypto = {
1334                 .base = {
1335                         .cra_name       = "authenc(hmac(sha1),cbc(des3_ede))",
1336                         .cra_blocksize  = DES3_EDE_BLOCK_SIZE,
1337                 },
1338                 .ivsize         = DES3_EDE_BLOCK_SIZE,
1339                 .maxauthsize    = SHA1_DIGEST_SIZE,
1340         },
1341         .hash = &hash_alg_sha1,
1342         .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_CBC_ENC | KEYLEN_192,
1343         .cfg_dec = CIPH_DECR | MOD_3DES | MOD_CBC_DEC | KEYLEN_192,
1344 }, {
1345         .crypto = {
1346                 .base = {
1347                         .cra_name       = "authenc(hmac(md5),cbc(aes))",
1348                         .cra_blocksize  = AES_BLOCK_SIZE,
1349                 },
1350                 .ivsize         = AES_BLOCK_SIZE,
1351                 .maxauthsize    = MD5_DIGEST_SIZE,
1352         },
1353         .hash = &hash_alg_md5,
1354         .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CBC_ENC,
1355         .cfg_dec = CIPH_DECR | MOD_AES | MOD_CBC_DEC,
1356 }, {
1357         .crypto = {
1358                 .base = {
1359                         .cra_name       = "authenc(hmac(sha1),cbc(aes))",
1360                         .cra_blocksize  = AES_BLOCK_SIZE,
1361                 },
1362                 .ivsize         = AES_BLOCK_SIZE,
1363                 .maxauthsize    = SHA1_DIGEST_SIZE,
1364         },
1365         .hash = &hash_alg_sha1,
1366         .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CBC_ENC,
1367         .cfg_dec = CIPH_DECR | MOD_AES | MOD_CBC_DEC,
1368 } };
1369
1370 #define IXP_POSTFIX "-ixp4xx"
1371
1372 static const struct platform_device_info ixp_dev_info __initdata = {
1373         .name           = DRIVER_NAME,
1374         .id             = 0,
1375         .dma_mask       = DMA_BIT_MASK(32),
1376 };
1377
1378 static int __init ixp_module_init(void)
1379 {
1380         int num = ARRAY_SIZE(ixp4xx_algos);
1381         int i, err;
1382
1383         pdev = platform_device_register_full(&ixp_dev_info);
1384         if (IS_ERR(pdev))
1385                 return PTR_ERR(pdev);
1386
1387         spin_lock_init(&desc_lock);
1388         spin_lock_init(&emerg_lock);
1389
1390         err = init_ixp_crypto(&pdev->dev);
1391         if (err) {
1392                 platform_device_unregister(pdev);
1393                 return err;
1394         }
1395         for (i=0; i< num; i++) {
1396                 struct crypto_alg *cra = &ixp4xx_algos[i].crypto;
1397
1398                 if (snprintf(cra->cra_driver_name, CRYPTO_MAX_ALG_NAME,
1399                         "%s"IXP_POSTFIX, cra->cra_name) >=
1400                         CRYPTO_MAX_ALG_NAME)
1401                 {
1402                         continue;
1403                 }
1404                 if (!support_aes && (ixp4xx_algos[i].cfg_enc & MOD_AES)) {
1405                         continue;
1406                 }
1407
1408                 /* block ciphers */
1409                 cra->cra_type = &crypto_ablkcipher_type;
1410                 cra->cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
1411                                  CRYPTO_ALG_KERN_DRIVER_ONLY |
1412                                  CRYPTO_ALG_ASYNC;
1413                 if (!cra->cra_ablkcipher.setkey)
1414                         cra->cra_ablkcipher.setkey = ablk_setkey;
1415                 if (!cra->cra_ablkcipher.encrypt)
1416                         cra->cra_ablkcipher.encrypt = ablk_encrypt;
1417                 if (!cra->cra_ablkcipher.decrypt)
1418                         cra->cra_ablkcipher.decrypt = ablk_decrypt;
1419                 cra->cra_init = init_tfm_ablk;
1420
1421                 cra->cra_ctxsize = sizeof(struct ixp_ctx);
1422                 cra->cra_module = THIS_MODULE;
1423                 cra->cra_alignmask = 3;
1424                 cra->cra_priority = 300;
1425                 cra->cra_exit = exit_tfm;
1426                 if (crypto_register_alg(cra))
1427                         printk(KERN_ERR "Failed to register '%s'\n",
1428                                 cra->cra_name);
1429                 else
1430                         ixp4xx_algos[i].registered = 1;
1431         }
1432
1433         for (i = 0; i < ARRAY_SIZE(ixp4xx_aeads); i++) {
1434                 struct aead_alg *cra = &ixp4xx_aeads[i].crypto;
1435
1436                 if (snprintf(cra->base.cra_driver_name, CRYPTO_MAX_ALG_NAME,
1437                              "%s"IXP_POSTFIX, cra->base.cra_name) >=
1438                     CRYPTO_MAX_ALG_NAME)
1439                         continue;
1440                 if (!support_aes && (ixp4xx_algos[i].cfg_enc & MOD_AES))
1441                         continue;
1442
1443                 /* authenc */
1444                 cra->base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1445                                       CRYPTO_ALG_ASYNC;
1446                 cra->setkey = aead_setkey;
1447                 cra->setauthsize = aead_setauthsize;
1448                 cra->encrypt = aead_encrypt;
1449                 cra->decrypt = aead_decrypt;
1450                 cra->init = init_tfm_aead;
1451                 cra->exit = exit_tfm_aead;
1452
1453                 cra->base.cra_ctxsize = sizeof(struct ixp_ctx);
1454                 cra->base.cra_module = THIS_MODULE;
1455                 cra->base.cra_alignmask = 3;
1456                 cra->base.cra_priority = 300;
1457
1458                 if (crypto_register_aead(cra))
1459                         printk(KERN_ERR "Failed to register '%s'\n",
1460                                 cra->base.cra_driver_name);
1461                 else
1462                         ixp4xx_aeads[i].registered = 1;
1463         }
1464         return 0;
1465 }
1466
1467 static void __exit ixp_module_exit(void)
1468 {
1469         int num = ARRAY_SIZE(ixp4xx_algos);
1470         int i;
1471
1472         for (i = 0; i < ARRAY_SIZE(ixp4xx_aeads); i++) {
1473                 if (ixp4xx_aeads[i].registered)
1474                         crypto_unregister_aead(&ixp4xx_aeads[i].crypto);
1475         }
1476
1477         for (i=0; i< num; i++) {
1478                 if (ixp4xx_algos[i].registered)
1479                         crypto_unregister_alg(&ixp4xx_algos[i].crypto);
1480         }
1481         release_ixp_crypto(&pdev->dev);
1482         platform_device_unregister(pdev);
1483 }
1484
1485 module_init(ixp_module_init);
1486 module_exit(ixp_module_exit);
1487
1488 MODULE_LICENSE("GPL");
1489 MODULE_AUTHOR("Christian Hohnstaedt <chohnstaedt@innominate.com>");
1490 MODULE_DESCRIPTION("IXP4xx hardware crypto");
1491