Merge tag 'mmc-v4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc
[muen/linux.git] / drivers / dma / imx-sdma.c
1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // drivers/dma/imx-sdma.c
4 //
5 // This file contains a driver for the Freescale Smart DMA engine
6 //
7 // Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
8 //
9 // Based on code from Freescale:
10 //
11 // Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
12
13 #include <linux/init.h>
14 #include <linux/iopoll.h>
15 #include <linux/module.h>
16 #include <linux/types.h>
17 #include <linux/bitops.h>
18 #include <linux/mm.h>
19 #include <linux/interrupt.h>
20 #include <linux/clk.h>
21 #include <linux/delay.h>
22 #include <linux/sched.h>
23 #include <linux/semaphore.h>
24 #include <linux/spinlock.h>
25 #include <linux/device.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/firmware.h>
28 #include <linux/slab.h>
29 #include <linux/platform_device.h>
30 #include <linux/dmaengine.h>
31 #include <linux/of.h>
32 #include <linux/of_address.h>
33 #include <linux/of_device.h>
34 #include <linux/of_dma.h>
35
36 #include <asm/irq.h>
37 #include <linux/platform_data/dma-imx-sdma.h>
38 #include <linux/platform_data/dma-imx.h>
39 #include <linux/regmap.h>
40 #include <linux/mfd/syscon.h>
41 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
42
43 #include "dmaengine.h"
44
45 /* SDMA registers */
46 #define SDMA_H_C0PTR            0x000
47 #define SDMA_H_INTR             0x004
48 #define SDMA_H_STATSTOP         0x008
49 #define SDMA_H_START            0x00c
50 #define SDMA_H_EVTOVR           0x010
51 #define SDMA_H_DSPOVR           0x014
52 #define SDMA_H_HOSTOVR          0x018
53 #define SDMA_H_EVTPEND          0x01c
54 #define SDMA_H_DSPENBL          0x020
55 #define SDMA_H_RESET            0x024
56 #define SDMA_H_EVTERR           0x028
57 #define SDMA_H_INTRMSK          0x02c
58 #define SDMA_H_PSW              0x030
59 #define SDMA_H_EVTERRDBG        0x034
60 #define SDMA_H_CONFIG           0x038
61 #define SDMA_ONCE_ENB           0x040
62 #define SDMA_ONCE_DATA          0x044
63 #define SDMA_ONCE_INSTR         0x048
64 #define SDMA_ONCE_STAT          0x04c
65 #define SDMA_ONCE_CMD           0x050
66 #define SDMA_EVT_MIRROR         0x054
67 #define SDMA_ILLINSTADDR        0x058
68 #define SDMA_CHN0ADDR           0x05c
69 #define SDMA_ONCE_RTB           0x060
70 #define SDMA_XTRIG_CONF1        0x070
71 #define SDMA_XTRIG_CONF2        0x074
72 #define SDMA_CHNENBL0_IMX35     0x200
73 #define SDMA_CHNENBL0_IMX31     0x080
74 #define SDMA_CHNPRI_0           0x100
75
76 /*
77  * Buffer descriptor status values.
78  */
79 #define BD_DONE  0x01
80 #define BD_WRAP  0x02
81 #define BD_CONT  0x04
82 #define BD_INTR  0x08
83 #define BD_RROR  0x10
84 #define BD_LAST  0x20
85 #define BD_EXTD  0x80
86
87 /*
88  * Data Node descriptor status values.
89  */
90 #define DND_END_OF_FRAME  0x80
91 #define DND_END_OF_XFER   0x40
92 #define DND_DONE          0x20
93 #define DND_UNUSED        0x01
94
95 /*
96  * IPCV2 descriptor status values.
97  */
98 #define BD_IPCV2_END_OF_FRAME  0x40
99
100 #define IPCV2_MAX_NODES        50
101 /*
102  * Error bit set in the CCB status field by the SDMA,
103  * in setbd routine, in case of a transfer error
104  */
105 #define DATA_ERROR  0x10000000
106
107 /*
108  * Buffer descriptor commands.
109  */
110 #define C0_ADDR             0x01
111 #define C0_LOAD             0x02
112 #define C0_DUMP             0x03
113 #define C0_SETCTX           0x07
114 #define C0_GETCTX           0x03
115 #define C0_SETDM            0x01
116 #define C0_SETPM            0x04
117 #define C0_GETDM            0x02
118 #define C0_GETPM            0x08
119 /*
120  * Change endianness indicator in the BD command field
121  */
122 #define CHANGE_ENDIANNESS   0x80
123
124 /*
125  *  p_2_p watermark_level description
126  *      Bits            Name                    Description
127  *      0-7             Lower WML               Lower watermark level
128  *      8               PS                      1: Pad Swallowing
129  *                                              0: No Pad Swallowing
130  *      9               PA                      1: Pad Adding
131  *                                              0: No Pad Adding
132  *      10              SPDIF                   If this bit is set both source
133  *                                              and destination are on SPBA
134  *      11              Source Bit(SP)          1: Source on SPBA
135  *                                              0: Source on AIPS
136  *      12              Destination Bit(DP)     1: Destination on SPBA
137  *                                              0: Destination on AIPS
138  *      13-15           ---------               MUST BE 0
139  *      16-23           Higher WML              HWML
140  *      24-27           N                       Total number of samples after
141  *                                              which Pad adding/Swallowing
142  *                                              must be done. It must be odd.
143  *      28              Lower WML Event(LWE)    SDMA events reg to check for
144  *                                              LWML event mask
145  *                                              0: LWE in EVENTS register
146  *                                              1: LWE in EVENTS2 register
147  *      29              Higher WML Event(HWE)   SDMA events reg to check for
148  *                                              HWML event mask
149  *                                              0: HWE in EVENTS register
150  *                                              1: HWE in EVENTS2 register
151  *      30              ---------               MUST BE 0
152  *      31              CONT                    1: Amount of samples to be
153  *                                              transferred is unknown and
154  *                                              script will keep on
155  *                                              transferring samples as long as
156  *                                              both events are detected and
157  *                                              script must be manually stopped
158  *                                              by the application
159  *                                              0: The amount of samples to be
160  *                                              transferred is equal to the
161  *                                              count field of mode word
162  */
163 #define SDMA_WATERMARK_LEVEL_LWML       0xFF
164 #define SDMA_WATERMARK_LEVEL_PS         BIT(8)
165 #define SDMA_WATERMARK_LEVEL_PA         BIT(9)
166 #define SDMA_WATERMARK_LEVEL_SPDIF      BIT(10)
167 #define SDMA_WATERMARK_LEVEL_SP         BIT(11)
168 #define SDMA_WATERMARK_LEVEL_DP         BIT(12)
169 #define SDMA_WATERMARK_LEVEL_HWML       (0xFF << 16)
170 #define SDMA_WATERMARK_LEVEL_LWE        BIT(28)
171 #define SDMA_WATERMARK_LEVEL_HWE        BIT(29)
172 #define SDMA_WATERMARK_LEVEL_CONT       BIT(31)
173
174 #define SDMA_DMA_BUSWIDTHS      (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
175                                  BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
176                                  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
177
178 #define SDMA_DMA_DIRECTIONS     (BIT(DMA_DEV_TO_MEM) | \
179                                  BIT(DMA_MEM_TO_DEV) | \
180                                  BIT(DMA_DEV_TO_DEV))
181
182 /*
183  * Mode/Count of data node descriptors - IPCv2
184  */
185 struct sdma_mode_count {
186         u32 count   : 16; /* size of the buffer pointed by this BD */
187         u32 status  :  8; /* E,R,I,C,W,D status bits stored here */
188         u32 command :  8; /* command mostly used for channel 0 */
189 };
190
191 /*
192  * Buffer descriptor
193  */
194 struct sdma_buffer_descriptor {
195         struct sdma_mode_count  mode;
196         u32 buffer_addr;        /* address of the buffer described */
197         u32 ext_buffer_addr;    /* extended buffer address */
198 } __attribute__ ((packed));
199
200 /**
201  * struct sdma_channel_control - Channel control Block
202  *
203  * @current_bd_ptr      current buffer descriptor processed
204  * @base_bd_ptr         first element of buffer descriptor array
205  * @unused              padding. The SDMA engine expects an array of 128 byte
206  *                      control blocks
207  */
208 struct sdma_channel_control {
209         u32 current_bd_ptr;
210         u32 base_bd_ptr;
211         u32 unused[2];
212 } __attribute__ ((packed));
213
214 /**
215  * struct sdma_state_registers - SDMA context for a channel
216  *
217  * @pc:         program counter
218  * @t:          test bit: status of arithmetic & test instruction
219  * @rpc:        return program counter
220  * @sf:         source fault while loading data
221  * @spc:        loop start program counter
222  * @df:         destination fault while storing data
223  * @epc:        loop end program counter
224  * @lm:         loop mode
225  */
226 struct sdma_state_registers {
227         u32 pc     :14;
228         u32 unused1: 1;
229         u32 t      : 1;
230         u32 rpc    :14;
231         u32 unused0: 1;
232         u32 sf     : 1;
233         u32 spc    :14;
234         u32 unused2: 1;
235         u32 df     : 1;
236         u32 epc    :14;
237         u32 lm     : 2;
238 } __attribute__ ((packed));
239
240 /**
241  * struct sdma_context_data - sdma context specific to a channel
242  *
243  * @channel_state:      channel state bits
244  * @gReg:               general registers
245  * @mda:                burst dma destination address register
246  * @msa:                burst dma source address register
247  * @ms:                 burst dma status register
248  * @md:                 burst dma data register
249  * @pda:                peripheral dma destination address register
250  * @psa:                peripheral dma source address register
251  * @ps:                 peripheral dma status register
252  * @pd:                 peripheral dma data register
253  * @ca:                 CRC polynomial register
254  * @cs:                 CRC accumulator register
255  * @dda:                dedicated core destination address register
256  * @dsa:                dedicated core source address register
257  * @ds:                 dedicated core status register
258  * @dd:                 dedicated core data register
259  */
260 struct sdma_context_data {
261         struct sdma_state_registers  channel_state;
262         u32  gReg[8];
263         u32  mda;
264         u32  msa;
265         u32  ms;
266         u32  md;
267         u32  pda;
268         u32  psa;
269         u32  ps;
270         u32  pd;
271         u32  ca;
272         u32  cs;
273         u32  dda;
274         u32  dsa;
275         u32  ds;
276         u32  dd;
277         u32  scratch0;
278         u32  scratch1;
279         u32  scratch2;
280         u32  scratch3;
281         u32  scratch4;
282         u32  scratch5;
283         u32  scratch6;
284         u32  scratch7;
285 } __attribute__ ((packed));
286
287 #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
288
289 struct sdma_engine;
290
291 /**
292  * struct sdma_channel - housekeeping for a SDMA channel
293  *
294  * @sdma                pointer to the SDMA engine for this channel
295  * @channel             the channel number, matches dmaengine chan_id + 1
296  * @direction           transfer type. Needed for setting SDMA script
297  * @peripheral_type     Peripheral type. Needed for setting SDMA script
298  * @event_id0           aka dma request line
299  * @event_id1           for channels that use 2 events
300  * @word_size           peripheral access size
301  * @buf_tail            ID of the buffer that was processed
302  * @buf_ptail           ID of the previous buffer that was processed
303  * @num_bd              max NUM_BD. number of descriptors currently handling
304  */
305 struct sdma_channel {
306         struct sdma_engine              *sdma;
307         unsigned int                    channel;
308         enum dma_transfer_direction             direction;
309         enum sdma_peripheral_type       peripheral_type;
310         unsigned int                    event_id0;
311         unsigned int                    event_id1;
312         enum dma_slave_buswidth         word_size;
313         unsigned int                    buf_tail;
314         unsigned int                    buf_ptail;
315         unsigned int                    num_bd;
316         unsigned int                    period_len;
317         struct sdma_buffer_descriptor   *bd;
318         dma_addr_t                      bd_phys;
319         unsigned int                    pc_from_device, pc_to_device;
320         unsigned int                    device_to_device;
321         unsigned long                   flags;
322         dma_addr_t                      per_address, per_address2;
323         unsigned long                   event_mask[2];
324         unsigned long                   watermark_level;
325         u32                             shp_addr, per_addr;
326         struct dma_chan                 chan;
327         spinlock_t                      lock;
328         struct dma_async_tx_descriptor  desc;
329         enum dma_status                 status;
330         unsigned int                    chn_count;
331         unsigned int                    chn_real_count;
332         struct tasklet_struct           tasklet;
333         struct imx_dma_data             data;
334         bool                            enabled;
335 };
336
337 #define IMX_DMA_SG_LOOP         BIT(0)
338
339 #define MAX_DMA_CHANNELS 32
340 #define MXC_SDMA_DEFAULT_PRIORITY 1
341 #define MXC_SDMA_MIN_PRIORITY 1
342 #define MXC_SDMA_MAX_PRIORITY 7
343
344 #define SDMA_FIRMWARE_MAGIC 0x414d4453
345
346 /**
347  * struct sdma_firmware_header - Layout of the firmware image
348  *
349  * @magic               "SDMA"
350  * @version_major       increased whenever layout of struct sdma_script_start_addrs
351  *                      changes.
352  * @version_minor       firmware minor version (for binary compatible changes)
353  * @script_addrs_start  offset of struct sdma_script_start_addrs in this image
354  * @num_script_addrs    Number of script addresses in this image
355  * @ram_code_start      offset of SDMA ram image in this firmware image
356  * @ram_code_size       size of SDMA ram image
357  * @script_addrs        Stores the start address of the SDMA scripts
358  *                      (in SDMA memory space)
359  */
360 struct sdma_firmware_header {
361         u32     magic;
362         u32     version_major;
363         u32     version_minor;
364         u32     script_addrs_start;
365         u32     num_script_addrs;
366         u32     ram_code_start;
367         u32     ram_code_size;
368 };
369
370 struct sdma_driver_data {
371         int chnenbl0;
372         int num_events;
373         struct sdma_script_start_addrs  *script_addrs;
374 };
375
376 struct sdma_engine {
377         struct device                   *dev;
378         struct device_dma_parameters    dma_parms;
379         struct sdma_channel             channel[MAX_DMA_CHANNELS];
380         struct sdma_channel_control     *channel_control;
381         void __iomem                    *regs;
382         struct sdma_context_data        *context;
383         dma_addr_t                      context_phys;
384         struct dma_device               dma_device;
385         struct clk                      *clk_ipg;
386         struct clk                      *clk_ahb;
387         spinlock_t                      channel_0_lock;
388         u32                             script_number;
389         struct sdma_script_start_addrs  *script_addrs;
390         const struct sdma_driver_data   *drvdata;
391         u32                             spba_start_addr;
392         u32                             spba_end_addr;
393         unsigned int                    irq;
394 };
395
396 static struct sdma_driver_data sdma_imx31 = {
397         .chnenbl0 = SDMA_CHNENBL0_IMX31,
398         .num_events = 32,
399 };
400
401 static struct sdma_script_start_addrs sdma_script_imx25 = {
402         .ap_2_ap_addr = 729,
403         .uart_2_mcu_addr = 904,
404         .per_2_app_addr = 1255,
405         .mcu_2_app_addr = 834,
406         .uartsh_2_mcu_addr = 1120,
407         .per_2_shp_addr = 1329,
408         .mcu_2_shp_addr = 1048,
409         .ata_2_mcu_addr = 1560,
410         .mcu_2_ata_addr = 1479,
411         .app_2_per_addr = 1189,
412         .app_2_mcu_addr = 770,
413         .shp_2_per_addr = 1407,
414         .shp_2_mcu_addr = 979,
415 };
416
417 static struct sdma_driver_data sdma_imx25 = {
418         .chnenbl0 = SDMA_CHNENBL0_IMX35,
419         .num_events = 48,
420         .script_addrs = &sdma_script_imx25,
421 };
422
423 static struct sdma_driver_data sdma_imx35 = {
424         .chnenbl0 = SDMA_CHNENBL0_IMX35,
425         .num_events = 48,
426 };
427
428 static struct sdma_script_start_addrs sdma_script_imx51 = {
429         .ap_2_ap_addr = 642,
430         .uart_2_mcu_addr = 817,
431         .mcu_2_app_addr = 747,
432         .mcu_2_shp_addr = 961,
433         .ata_2_mcu_addr = 1473,
434         .mcu_2_ata_addr = 1392,
435         .app_2_per_addr = 1033,
436         .app_2_mcu_addr = 683,
437         .shp_2_per_addr = 1251,
438         .shp_2_mcu_addr = 892,
439 };
440
441 static struct sdma_driver_data sdma_imx51 = {
442         .chnenbl0 = SDMA_CHNENBL0_IMX35,
443         .num_events = 48,
444         .script_addrs = &sdma_script_imx51,
445 };
446
447 static struct sdma_script_start_addrs sdma_script_imx53 = {
448         .ap_2_ap_addr = 642,
449         .app_2_mcu_addr = 683,
450         .mcu_2_app_addr = 747,
451         .uart_2_mcu_addr = 817,
452         .shp_2_mcu_addr = 891,
453         .mcu_2_shp_addr = 960,
454         .uartsh_2_mcu_addr = 1032,
455         .spdif_2_mcu_addr = 1100,
456         .mcu_2_spdif_addr = 1134,
457         .firi_2_mcu_addr = 1193,
458         .mcu_2_firi_addr = 1290,
459 };
460
461 static struct sdma_driver_data sdma_imx53 = {
462         .chnenbl0 = SDMA_CHNENBL0_IMX35,
463         .num_events = 48,
464         .script_addrs = &sdma_script_imx53,
465 };
466
467 static struct sdma_script_start_addrs sdma_script_imx6q = {
468         .ap_2_ap_addr = 642,
469         .uart_2_mcu_addr = 817,
470         .mcu_2_app_addr = 747,
471         .per_2_per_addr = 6331,
472         .uartsh_2_mcu_addr = 1032,
473         .mcu_2_shp_addr = 960,
474         .app_2_mcu_addr = 683,
475         .shp_2_mcu_addr = 891,
476         .spdif_2_mcu_addr = 1100,
477         .mcu_2_spdif_addr = 1134,
478 };
479
480 static struct sdma_driver_data sdma_imx6q = {
481         .chnenbl0 = SDMA_CHNENBL0_IMX35,
482         .num_events = 48,
483         .script_addrs = &sdma_script_imx6q,
484 };
485
486 static struct sdma_script_start_addrs sdma_script_imx7d = {
487         .ap_2_ap_addr = 644,
488         .uart_2_mcu_addr = 819,
489         .mcu_2_app_addr = 749,
490         .uartsh_2_mcu_addr = 1034,
491         .mcu_2_shp_addr = 962,
492         .app_2_mcu_addr = 685,
493         .shp_2_mcu_addr = 893,
494         .spdif_2_mcu_addr = 1102,
495         .mcu_2_spdif_addr = 1136,
496 };
497
498 static struct sdma_driver_data sdma_imx7d = {
499         .chnenbl0 = SDMA_CHNENBL0_IMX35,
500         .num_events = 48,
501         .script_addrs = &sdma_script_imx7d,
502 };
503
504 static const struct platform_device_id sdma_devtypes[] = {
505         {
506                 .name = "imx25-sdma",
507                 .driver_data = (unsigned long)&sdma_imx25,
508         }, {
509                 .name = "imx31-sdma",
510                 .driver_data = (unsigned long)&sdma_imx31,
511         }, {
512                 .name = "imx35-sdma",
513                 .driver_data = (unsigned long)&sdma_imx35,
514         }, {
515                 .name = "imx51-sdma",
516                 .driver_data = (unsigned long)&sdma_imx51,
517         }, {
518                 .name = "imx53-sdma",
519                 .driver_data = (unsigned long)&sdma_imx53,
520         }, {
521                 .name = "imx6q-sdma",
522                 .driver_data = (unsigned long)&sdma_imx6q,
523         }, {
524                 .name = "imx7d-sdma",
525                 .driver_data = (unsigned long)&sdma_imx7d,
526         }, {
527                 /* sentinel */
528         }
529 };
530 MODULE_DEVICE_TABLE(platform, sdma_devtypes);
531
532 static const struct of_device_id sdma_dt_ids[] = {
533         { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
534         { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
535         { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
536         { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
537         { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
538         { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
539         { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
540         { /* sentinel */ }
541 };
542 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
543
544 #define SDMA_H_CONFIG_DSPDMA    BIT(12) /* indicates if the DSPDMA is used */
545 #define SDMA_H_CONFIG_RTD_PINS  BIT(11) /* indicates if Real-Time Debug pins are enabled */
546 #define SDMA_H_CONFIG_ACR       BIT(4)  /* indicates if AHB freq /core freq = 2 or 1 */
547 #define SDMA_H_CONFIG_CSM       (3)       /* indicates which context switch mode is selected*/
548
549 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
550 {
551         u32 chnenbl0 = sdma->drvdata->chnenbl0;
552         return chnenbl0 + event * 4;
553 }
554
555 static int sdma_config_ownership(struct sdma_channel *sdmac,
556                 bool event_override, bool mcu_override, bool dsp_override)
557 {
558         struct sdma_engine *sdma = sdmac->sdma;
559         int channel = sdmac->channel;
560         unsigned long evt, mcu, dsp;
561
562         if (event_override && mcu_override && dsp_override)
563                 return -EINVAL;
564
565         evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
566         mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
567         dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
568
569         if (dsp_override)
570                 __clear_bit(channel, &dsp);
571         else
572                 __set_bit(channel, &dsp);
573
574         if (event_override)
575                 __clear_bit(channel, &evt);
576         else
577                 __set_bit(channel, &evt);
578
579         if (mcu_override)
580                 __clear_bit(channel, &mcu);
581         else
582                 __set_bit(channel, &mcu);
583
584         writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
585         writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
586         writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
587
588         return 0;
589 }
590
591 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
592 {
593         unsigned long flags;
594         struct sdma_channel *sdmac = &sdma->channel[channel];
595
596         writel(BIT(channel), sdma->regs + SDMA_H_START);
597
598         spin_lock_irqsave(&sdmac->lock, flags);
599         sdmac->enabled = true;
600         spin_unlock_irqrestore(&sdmac->lock, flags);
601 }
602
603 /*
604  * sdma_run_channel0 - run a channel and wait till it's done
605  */
606 static int sdma_run_channel0(struct sdma_engine *sdma)
607 {
608         int ret;
609         u32 reg;
610
611         sdma_enable_channel(sdma, 0);
612
613         ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP,
614                                                 reg, !(reg & 1), 1, 500);
615         if (ret)
616                 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
617
618         /* Set bits of CONFIG register with dynamic context switching */
619         if (readl(sdma->regs + SDMA_H_CONFIG) == 0)
620                 writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
621
622         return ret;
623 }
624
625 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
626                 u32 address)
627 {
628         struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
629         void *buf_virt;
630         dma_addr_t buf_phys;
631         int ret;
632         unsigned long flags;
633
634         buf_virt = dma_alloc_coherent(NULL,
635                         size,
636                         &buf_phys, GFP_KERNEL);
637         if (!buf_virt) {
638                 return -ENOMEM;
639         }
640
641         spin_lock_irqsave(&sdma->channel_0_lock, flags);
642
643         bd0->mode.command = C0_SETPM;
644         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
645         bd0->mode.count = size / 2;
646         bd0->buffer_addr = buf_phys;
647         bd0->ext_buffer_addr = address;
648
649         memcpy(buf_virt, buf, size);
650
651         ret = sdma_run_channel0(sdma);
652
653         spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
654
655         dma_free_coherent(NULL, size, buf_virt, buf_phys);
656
657         return ret;
658 }
659
660 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
661 {
662         struct sdma_engine *sdma = sdmac->sdma;
663         int channel = sdmac->channel;
664         unsigned long val;
665         u32 chnenbl = chnenbl_ofs(sdma, event);
666
667         val = readl_relaxed(sdma->regs + chnenbl);
668         __set_bit(channel, &val);
669         writel_relaxed(val, sdma->regs + chnenbl);
670 }
671
672 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
673 {
674         struct sdma_engine *sdma = sdmac->sdma;
675         int channel = sdmac->channel;
676         u32 chnenbl = chnenbl_ofs(sdma, event);
677         unsigned long val;
678
679         val = readl_relaxed(sdma->regs + chnenbl);
680         __clear_bit(channel, &val);
681         writel_relaxed(val, sdma->regs + chnenbl);
682 }
683
684 static void sdma_update_channel_loop(struct sdma_channel *sdmac)
685 {
686         struct sdma_buffer_descriptor *bd;
687         int error = 0;
688         enum dma_status old_status = sdmac->status;
689         unsigned long flags;
690
691         spin_lock_irqsave(&sdmac->lock, flags);
692         if (!sdmac->enabled) {
693                 spin_unlock_irqrestore(&sdmac->lock, flags);
694                 return;
695         }
696         spin_unlock_irqrestore(&sdmac->lock, flags);
697
698         /*
699          * loop mode. Iterate over descriptors, re-setup them and
700          * call callback function.
701          */
702         while (1) {
703                 bd = &sdmac->bd[sdmac->buf_tail];
704
705                 if (bd->mode.status & BD_DONE)
706                         break;
707
708                 if (bd->mode.status & BD_RROR) {
709                         bd->mode.status &= ~BD_RROR;
710                         sdmac->status = DMA_ERROR;
711                         error = -EIO;
712                 }
713
714                /*
715                 * We use bd->mode.count to calculate the residue, since contains
716                 * the number of bytes present in the current buffer descriptor.
717                 */
718
719                 sdmac->chn_real_count = bd->mode.count;
720                 bd->mode.status |= BD_DONE;
721                 bd->mode.count = sdmac->period_len;
722                 sdmac->buf_ptail = sdmac->buf_tail;
723                 sdmac->buf_tail = (sdmac->buf_tail + 1) % sdmac->num_bd;
724
725                 /*
726                  * The callback is called from the interrupt context in order
727                  * to reduce latency and to avoid the risk of altering the
728                  * SDMA transaction status by the time the client tasklet is
729                  * executed.
730                  */
731
732                 dmaengine_desc_get_callback_invoke(&sdmac->desc, NULL);
733
734                 if (error)
735                         sdmac->status = old_status;
736         }
737 }
738
739 static void mxc_sdma_handle_channel_normal(unsigned long data)
740 {
741         struct sdma_channel *sdmac = (struct sdma_channel *) data;
742         struct sdma_buffer_descriptor *bd;
743         int i, error = 0;
744
745         sdmac->chn_real_count = 0;
746         /*
747          * non loop mode. Iterate over all descriptors, collect
748          * errors and call callback function
749          */
750         for (i = 0; i < sdmac->num_bd; i++) {
751                 bd = &sdmac->bd[i];
752
753                  if (bd->mode.status & (BD_DONE | BD_RROR))
754                         error = -EIO;
755                  sdmac->chn_real_count += bd->mode.count;
756         }
757
758         if (error)
759                 sdmac->status = DMA_ERROR;
760         else
761                 sdmac->status = DMA_COMPLETE;
762
763         dma_cookie_complete(&sdmac->desc);
764
765         dmaengine_desc_get_callback_invoke(&sdmac->desc, NULL);
766 }
767
768 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
769 {
770         struct sdma_engine *sdma = dev_id;
771         unsigned long stat;
772
773         stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
774         writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
775         /* channel 0 is special and not handled here, see run_channel0() */
776         stat &= ~1;
777
778         while (stat) {
779                 int channel = fls(stat) - 1;
780                 struct sdma_channel *sdmac = &sdma->channel[channel];
781
782                 if (sdmac->flags & IMX_DMA_SG_LOOP)
783                         sdma_update_channel_loop(sdmac);
784                 else
785                         tasklet_schedule(&sdmac->tasklet);
786
787                 __clear_bit(channel, &stat);
788         }
789
790         return IRQ_HANDLED;
791 }
792
793 /*
794  * sets the pc of SDMA script according to the peripheral type
795  */
796 static void sdma_get_pc(struct sdma_channel *sdmac,
797                 enum sdma_peripheral_type peripheral_type)
798 {
799         struct sdma_engine *sdma = sdmac->sdma;
800         int per_2_emi = 0, emi_2_per = 0;
801         /*
802          * These are needed once we start to support transfers between
803          * two peripherals or memory-to-memory transfers
804          */
805         int per_2_per = 0;
806
807         sdmac->pc_from_device = 0;
808         sdmac->pc_to_device = 0;
809         sdmac->device_to_device = 0;
810
811         switch (peripheral_type) {
812         case IMX_DMATYPE_MEMORY:
813                 break;
814         case IMX_DMATYPE_DSP:
815                 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
816                 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
817                 break;
818         case IMX_DMATYPE_FIRI:
819                 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
820                 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
821                 break;
822         case IMX_DMATYPE_UART:
823                 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
824                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
825                 break;
826         case IMX_DMATYPE_UART_SP:
827                 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
828                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
829                 break;
830         case IMX_DMATYPE_ATA:
831                 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
832                 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
833                 break;
834         case IMX_DMATYPE_CSPI:
835         case IMX_DMATYPE_EXT:
836         case IMX_DMATYPE_SSI:
837         case IMX_DMATYPE_SAI:
838                 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
839                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
840                 break;
841         case IMX_DMATYPE_SSI_DUAL:
842                 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr;
843                 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr;
844                 break;
845         case IMX_DMATYPE_SSI_SP:
846         case IMX_DMATYPE_MMC:
847         case IMX_DMATYPE_SDHC:
848         case IMX_DMATYPE_CSPI_SP:
849         case IMX_DMATYPE_ESAI:
850         case IMX_DMATYPE_MSHC_SP:
851                 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
852                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
853                 break;
854         case IMX_DMATYPE_ASRC:
855                 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
856                 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
857                 per_2_per = sdma->script_addrs->per_2_per_addr;
858                 break;
859         case IMX_DMATYPE_ASRC_SP:
860                 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
861                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
862                 per_2_per = sdma->script_addrs->per_2_per_addr;
863                 break;
864         case IMX_DMATYPE_MSHC:
865                 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
866                 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
867                 break;
868         case IMX_DMATYPE_CCM:
869                 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
870                 break;
871         case IMX_DMATYPE_SPDIF:
872                 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
873                 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
874                 break;
875         case IMX_DMATYPE_IPU_MEMORY:
876                 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
877                 break;
878         default:
879                 break;
880         }
881
882         sdmac->pc_from_device = per_2_emi;
883         sdmac->pc_to_device = emi_2_per;
884         sdmac->device_to_device = per_2_per;
885 }
886
887 static int sdma_load_context(struct sdma_channel *sdmac)
888 {
889         struct sdma_engine *sdma = sdmac->sdma;
890         int channel = sdmac->channel;
891         int load_address;
892         struct sdma_context_data *context = sdma->context;
893         struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
894         int ret;
895         unsigned long flags;
896
897         if (sdmac->direction == DMA_DEV_TO_MEM)
898                 load_address = sdmac->pc_from_device;
899         else if (sdmac->direction == DMA_DEV_TO_DEV)
900                 load_address = sdmac->device_to_device;
901         else
902                 load_address = sdmac->pc_to_device;
903
904         if (load_address < 0)
905                 return load_address;
906
907         dev_dbg(sdma->dev, "load_address = %d\n", load_address);
908         dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
909         dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
910         dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
911         dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
912         dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
913
914         spin_lock_irqsave(&sdma->channel_0_lock, flags);
915
916         memset(context, 0, sizeof(*context));
917         context->channel_state.pc = load_address;
918
919         /* Send by context the event mask,base address for peripheral
920          * and watermark level
921          */
922         context->gReg[0] = sdmac->event_mask[1];
923         context->gReg[1] = sdmac->event_mask[0];
924         context->gReg[2] = sdmac->per_addr;
925         context->gReg[6] = sdmac->shp_addr;
926         context->gReg[7] = sdmac->watermark_level;
927
928         bd0->mode.command = C0_SETDM;
929         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
930         bd0->mode.count = sizeof(*context) / 4;
931         bd0->buffer_addr = sdma->context_phys;
932         bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
933         ret = sdma_run_channel0(sdma);
934
935         spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
936
937         return ret;
938 }
939
940 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
941 {
942         return container_of(chan, struct sdma_channel, chan);
943 }
944
945 static int sdma_disable_channel(struct dma_chan *chan)
946 {
947         struct sdma_channel *sdmac = to_sdma_chan(chan);
948         struct sdma_engine *sdma = sdmac->sdma;
949         int channel = sdmac->channel;
950         unsigned long flags;
951
952         writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
953         sdmac->status = DMA_ERROR;
954
955         spin_lock_irqsave(&sdmac->lock, flags);
956         sdmac->enabled = false;
957         spin_unlock_irqrestore(&sdmac->lock, flags);
958
959         return 0;
960 }
961
962 static int sdma_disable_channel_with_delay(struct dma_chan *chan)
963 {
964         sdma_disable_channel(chan);
965
966         /*
967          * According to NXP R&D team a delay of one BD SDMA cost time
968          * (maximum is 1ms) should be added after disable of the channel
969          * bit, to ensure SDMA core has really been stopped after SDMA
970          * clients call .device_terminate_all.
971          */
972         mdelay(1);
973
974         return 0;
975 }
976
977 static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
978 {
979         struct sdma_engine *sdma = sdmac->sdma;
980
981         int lwml = sdmac->watermark_level & SDMA_WATERMARK_LEVEL_LWML;
982         int hwml = (sdmac->watermark_level & SDMA_WATERMARK_LEVEL_HWML) >> 16;
983
984         set_bit(sdmac->event_id0 % 32, &sdmac->event_mask[1]);
985         set_bit(sdmac->event_id1 % 32, &sdmac->event_mask[0]);
986
987         if (sdmac->event_id0 > 31)
988                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_LWE;
989
990         if (sdmac->event_id1 > 31)
991                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_HWE;
992
993         /*
994          * If LWML(src_maxburst) > HWML(dst_maxburst), we need
995          * swap LWML and HWML of INFO(A.3.2.5.1), also need swap
996          * r0(event_mask[1]) and r1(event_mask[0]).
997          */
998         if (lwml > hwml) {
999                 sdmac->watermark_level &= ~(SDMA_WATERMARK_LEVEL_LWML |
1000                                                 SDMA_WATERMARK_LEVEL_HWML);
1001                 sdmac->watermark_level |= hwml;
1002                 sdmac->watermark_level |= lwml << 16;
1003                 swap(sdmac->event_mask[0], sdmac->event_mask[1]);
1004         }
1005
1006         if (sdmac->per_address2 >= sdma->spba_start_addr &&
1007                         sdmac->per_address2 <= sdma->spba_end_addr)
1008                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SP;
1009
1010         if (sdmac->per_address >= sdma->spba_start_addr &&
1011                         sdmac->per_address <= sdma->spba_end_addr)
1012                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP;
1013
1014         sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT;
1015 }
1016
1017 static int sdma_config_channel(struct dma_chan *chan)
1018 {
1019         struct sdma_channel *sdmac = to_sdma_chan(chan);
1020         int ret;
1021
1022         sdma_disable_channel(chan);
1023
1024         sdmac->event_mask[0] = 0;
1025         sdmac->event_mask[1] = 0;
1026         sdmac->shp_addr = 0;
1027         sdmac->per_addr = 0;
1028
1029         if (sdmac->event_id0) {
1030                 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
1031                         return -EINVAL;
1032                 sdma_event_enable(sdmac, sdmac->event_id0);
1033         }
1034
1035         if (sdmac->event_id1) {
1036                 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events)
1037                         return -EINVAL;
1038                 sdma_event_enable(sdmac, sdmac->event_id1);
1039         }
1040
1041         switch (sdmac->peripheral_type) {
1042         case IMX_DMATYPE_DSP:
1043                 sdma_config_ownership(sdmac, false, true, true);
1044                 break;
1045         case IMX_DMATYPE_MEMORY:
1046                 sdma_config_ownership(sdmac, false, true, false);
1047                 break;
1048         default:
1049                 sdma_config_ownership(sdmac, true, true, false);
1050                 break;
1051         }
1052
1053         sdma_get_pc(sdmac, sdmac->peripheral_type);
1054
1055         if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
1056                         (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
1057                 /* Handle multiple event channels differently */
1058                 if (sdmac->event_id1) {
1059                         if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP ||
1060                             sdmac->peripheral_type == IMX_DMATYPE_ASRC)
1061                                 sdma_set_watermarklevel_for_p2p(sdmac);
1062                 } else
1063                         __set_bit(sdmac->event_id0, sdmac->event_mask);
1064
1065                 /* Address */
1066                 sdmac->shp_addr = sdmac->per_address;
1067                 sdmac->per_addr = sdmac->per_address2;
1068         } else {
1069                 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
1070         }
1071
1072         ret = sdma_load_context(sdmac);
1073
1074         return ret;
1075 }
1076
1077 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
1078                 unsigned int priority)
1079 {
1080         struct sdma_engine *sdma = sdmac->sdma;
1081         int channel = sdmac->channel;
1082
1083         if (priority < MXC_SDMA_MIN_PRIORITY
1084             || priority > MXC_SDMA_MAX_PRIORITY) {
1085                 return -EINVAL;
1086         }
1087
1088         writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
1089
1090         return 0;
1091 }
1092
1093 static int sdma_request_channel(struct sdma_channel *sdmac)
1094 {
1095         struct sdma_engine *sdma = sdmac->sdma;
1096         int channel = sdmac->channel;
1097         int ret = -EBUSY;
1098
1099         sdmac->bd = dma_zalloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys,
1100                                         GFP_KERNEL);
1101         if (!sdmac->bd) {
1102                 ret = -ENOMEM;
1103                 goto out;
1104         }
1105
1106         sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
1107         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1108
1109         sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY);
1110         return 0;
1111 out:
1112
1113         return ret;
1114 }
1115
1116 static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
1117 {
1118         unsigned long flags;
1119         struct sdma_channel *sdmac = to_sdma_chan(tx->chan);
1120         dma_cookie_t cookie;
1121
1122         spin_lock_irqsave(&sdmac->lock, flags);
1123
1124         cookie = dma_cookie_assign(tx);
1125
1126         spin_unlock_irqrestore(&sdmac->lock, flags);
1127
1128         return cookie;
1129 }
1130
1131 static int sdma_alloc_chan_resources(struct dma_chan *chan)
1132 {
1133         struct sdma_channel *sdmac = to_sdma_chan(chan);
1134         struct imx_dma_data *data = chan->private;
1135         int prio, ret;
1136
1137         if (!data)
1138                 return -EINVAL;
1139
1140         switch (data->priority) {
1141         case DMA_PRIO_HIGH:
1142                 prio = 3;
1143                 break;
1144         case DMA_PRIO_MEDIUM:
1145                 prio = 2;
1146                 break;
1147         case DMA_PRIO_LOW:
1148         default:
1149                 prio = 1;
1150                 break;
1151         }
1152
1153         sdmac->peripheral_type = data->peripheral_type;
1154         sdmac->event_id0 = data->dma_request;
1155         sdmac->event_id1 = data->dma_request2;
1156
1157         ret = clk_enable(sdmac->sdma->clk_ipg);
1158         if (ret)
1159                 return ret;
1160         ret = clk_enable(sdmac->sdma->clk_ahb);
1161         if (ret)
1162                 goto disable_clk_ipg;
1163
1164         ret = sdma_request_channel(sdmac);
1165         if (ret)
1166                 goto disable_clk_ahb;
1167
1168         ret = sdma_set_channel_priority(sdmac, prio);
1169         if (ret)
1170                 goto disable_clk_ahb;
1171
1172         dma_async_tx_descriptor_init(&sdmac->desc, chan);
1173         sdmac->desc.tx_submit = sdma_tx_submit;
1174         /* txd.flags will be overwritten in prep funcs */
1175         sdmac->desc.flags = DMA_CTRL_ACK;
1176
1177         return 0;
1178
1179 disable_clk_ahb:
1180         clk_disable(sdmac->sdma->clk_ahb);
1181 disable_clk_ipg:
1182         clk_disable(sdmac->sdma->clk_ipg);
1183         return ret;
1184 }
1185
1186 static void sdma_free_chan_resources(struct dma_chan *chan)
1187 {
1188         struct sdma_channel *sdmac = to_sdma_chan(chan);
1189         struct sdma_engine *sdma = sdmac->sdma;
1190
1191         sdma_disable_channel(chan);
1192
1193         if (sdmac->event_id0)
1194                 sdma_event_disable(sdmac, sdmac->event_id0);
1195         if (sdmac->event_id1)
1196                 sdma_event_disable(sdmac, sdmac->event_id1);
1197
1198         sdmac->event_id0 = 0;
1199         sdmac->event_id1 = 0;
1200
1201         sdma_set_channel_priority(sdmac, 0);
1202
1203         dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
1204
1205         clk_disable(sdma->clk_ipg);
1206         clk_disable(sdma->clk_ahb);
1207 }
1208
1209 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
1210                 struct dma_chan *chan, struct scatterlist *sgl,
1211                 unsigned int sg_len, enum dma_transfer_direction direction,
1212                 unsigned long flags, void *context)
1213 {
1214         struct sdma_channel *sdmac = to_sdma_chan(chan);
1215         struct sdma_engine *sdma = sdmac->sdma;
1216         int ret, i, count;
1217         int channel = sdmac->channel;
1218         struct scatterlist *sg;
1219
1220         if (sdmac->status == DMA_IN_PROGRESS)
1221                 return NULL;
1222         sdmac->status = DMA_IN_PROGRESS;
1223
1224         sdmac->flags = 0;
1225
1226         sdmac->buf_tail = 0;
1227         sdmac->buf_ptail = 0;
1228         sdmac->chn_real_count = 0;
1229
1230         dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
1231                         sg_len, channel);
1232
1233         sdmac->direction = direction;
1234         ret = sdma_load_context(sdmac);
1235         if (ret)
1236                 goto err_out;
1237
1238         if (sg_len > NUM_BD) {
1239                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1240                                 channel, sg_len, NUM_BD);
1241                 ret = -EINVAL;
1242                 goto err_out;
1243         }
1244
1245         sdmac->chn_count = 0;
1246         for_each_sg(sgl, sg, sg_len, i) {
1247                 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1248                 int param;
1249
1250                 bd->buffer_addr = sg->dma_address;
1251
1252                 count = sg_dma_len(sg);
1253
1254                 if (count > 0xffff) {
1255                         dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
1256                                         channel, count, 0xffff);
1257                         ret = -EINVAL;
1258                         goto err_out;
1259                 }
1260
1261                 bd->mode.count = count;
1262                 sdmac->chn_count += count;
1263
1264                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
1265                         ret =  -EINVAL;
1266                         goto err_out;
1267                 }
1268
1269                 switch (sdmac->word_size) {
1270                 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1271                         bd->mode.command = 0;
1272                         if (count & 3 || sg->dma_address & 3)
1273                                 return NULL;
1274                         break;
1275                 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1276                         bd->mode.command = 2;
1277                         if (count & 1 || sg->dma_address & 1)
1278                                 return NULL;
1279                         break;
1280                 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1281                         bd->mode.command = 1;
1282                         break;
1283                 default:
1284                         return NULL;
1285                 }
1286
1287                 param = BD_DONE | BD_EXTD | BD_CONT;
1288
1289                 if (i + 1 == sg_len) {
1290                         param |= BD_INTR;
1291                         param |= BD_LAST;
1292                         param &= ~BD_CONT;
1293                 }
1294
1295                 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
1296                                 i, count, (u64)sg->dma_address,
1297                                 param & BD_WRAP ? "wrap" : "",
1298                                 param & BD_INTR ? " intr" : "");
1299
1300                 bd->mode.status = param;
1301         }
1302
1303         sdmac->num_bd = sg_len;
1304         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1305
1306         return &sdmac->desc;
1307 err_out:
1308         sdmac->status = DMA_ERROR;
1309         return NULL;
1310 }
1311
1312 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1313                 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1314                 size_t period_len, enum dma_transfer_direction direction,
1315                 unsigned long flags)
1316 {
1317         struct sdma_channel *sdmac = to_sdma_chan(chan);
1318         struct sdma_engine *sdma = sdmac->sdma;
1319         int num_periods = buf_len / period_len;
1320         int channel = sdmac->channel;
1321         int ret, i = 0, buf = 0;
1322
1323         dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1324
1325         if (sdmac->status == DMA_IN_PROGRESS)
1326                 return NULL;
1327
1328         sdmac->status = DMA_IN_PROGRESS;
1329
1330         sdmac->buf_tail = 0;
1331         sdmac->buf_ptail = 0;
1332         sdmac->chn_real_count = 0;
1333         sdmac->period_len = period_len;
1334
1335         sdmac->flags |= IMX_DMA_SG_LOOP;
1336         sdmac->direction = direction;
1337         ret = sdma_load_context(sdmac);
1338         if (ret)
1339                 goto err_out;
1340
1341         if (num_periods > NUM_BD) {
1342                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1343                                 channel, num_periods, NUM_BD);
1344                 goto err_out;
1345         }
1346
1347         if (period_len > 0xffff) {
1348                 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %zu > %d\n",
1349                                 channel, period_len, 0xffff);
1350                 goto err_out;
1351         }
1352
1353         while (buf < buf_len) {
1354                 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1355                 int param;
1356
1357                 bd->buffer_addr = dma_addr;
1358
1359                 bd->mode.count = period_len;
1360
1361                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1362                         goto err_out;
1363                 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1364                         bd->mode.command = 0;
1365                 else
1366                         bd->mode.command = sdmac->word_size;
1367
1368                 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1369                 if (i + 1 == num_periods)
1370                         param |= BD_WRAP;
1371
1372                 dev_dbg(sdma->dev, "entry %d: count: %zu dma: %#llx %s%s\n",
1373                                 i, period_len, (u64)dma_addr,
1374                                 param & BD_WRAP ? "wrap" : "",
1375                                 param & BD_INTR ? " intr" : "");
1376
1377                 bd->mode.status = param;
1378
1379                 dma_addr += period_len;
1380                 buf += period_len;
1381
1382                 i++;
1383         }
1384
1385         sdmac->num_bd = num_periods;
1386         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1387
1388         return &sdmac->desc;
1389 err_out:
1390         sdmac->status = DMA_ERROR;
1391         return NULL;
1392 }
1393
1394 static int sdma_config(struct dma_chan *chan,
1395                        struct dma_slave_config *dmaengine_cfg)
1396 {
1397         struct sdma_channel *sdmac = to_sdma_chan(chan);
1398
1399         if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
1400                 sdmac->per_address = dmaengine_cfg->src_addr;
1401                 sdmac->watermark_level = dmaengine_cfg->src_maxburst *
1402                         dmaengine_cfg->src_addr_width;
1403                 sdmac->word_size = dmaengine_cfg->src_addr_width;
1404         } else if (dmaengine_cfg->direction == DMA_DEV_TO_DEV) {
1405                 sdmac->per_address2 = dmaengine_cfg->src_addr;
1406                 sdmac->per_address = dmaengine_cfg->dst_addr;
1407                 sdmac->watermark_level = dmaengine_cfg->src_maxburst &
1408                         SDMA_WATERMARK_LEVEL_LWML;
1409                 sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) &
1410                         SDMA_WATERMARK_LEVEL_HWML;
1411                 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1412         } else {
1413                 sdmac->per_address = dmaengine_cfg->dst_addr;
1414                 sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
1415                         dmaengine_cfg->dst_addr_width;
1416                 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1417         }
1418         sdmac->direction = dmaengine_cfg->direction;
1419         return sdma_config_channel(chan);
1420 }
1421
1422 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1423                                       dma_cookie_t cookie,
1424                                       struct dma_tx_state *txstate)
1425 {
1426         struct sdma_channel *sdmac = to_sdma_chan(chan);
1427         u32 residue;
1428
1429         if (sdmac->flags & IMX_DMA_SG_LOOP)
1430                 residue = (sdmac->num_bd - sdmac->buf_ptail) *
1431                            sdmac->period_len - sdmac->chn_real_count;
1432         else
1433                 residue = sdmac->chn_count - sdmac->chn_real_count;
1434
1435         dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
1436                          residue);
1437
1438         return sdmac->status;
1439 }
1440
1441 static void sdma_issue_pending(struct dma_chan *chan)
1442 {
1443         struct sdma_channel *sdmac = to_sdma_chan(chan);
1444         struct sdma_engine *sdma = sdmac->sdma;
1445
1446         if (sdmac->status == DMA_IN_PROGRESS)
1447                 sdma_enable_channel(sdma, sdmac->channel);
1448 }
1449
1450 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1451 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38
1452 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 41
1453 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 42
1454
1455 static void sdma_add_scripts(struct sdma_engine *sdma,
1456                 const struct sdma_script_start_addrs *addr)
1457 {
1458         s32 *addr_arr = (u32 *)addr;
1459         s32 *saddr_arr = (u32 *)sdma->script_addrs;
1460         int i;
1461
1462         /* use the default firmware in ROM if missing external firmware */
1463         if (!sdma->script_number)
1464                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1465
1466         for (i = 0; i < sdma->script_number; i++)
1467                 if (addr_arr[i] > 0)
1468                         saddr_arr[i] = addr_arr[i];
1469 }
1470
1471 static void sdma_load_firmware(const struct firmware *fw, void *context)
1472 {
1473         struct sdma_engine *sdma = context;
1474         const struct sdma_firmware_header *header;
1475         const struct sdma_script_start_addrs *addr;
1476         unsigned short *ram_code;
1477
1478         if (!fw) {
1479                 dev_info(sdma->dev, "external firmware not found, using ROM firmware\n");
1480                 /* In this case we just use the ROM firmware. */
1481                 return;
1482         }
1483
1484         if (fw->size < sizeof(*header))
1485                 goto err_firmware;
1486
1487         header = (struct sdma_firmware_header *)fw->data;
1488
1489         if (header->magic != SDMA_FIRMWARE_MAGIC)
1490                 goto err_firmware;
1491         if (header->ram_code_start + header->ram_code_size > fw->size)
1492                 goto err_firmware;
1493         switch (header->version_major) {
1494         case 1:
1495                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1496                 break;
1497         case 2:
1498                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2;
1499                 break;
1500         case 3:
1501                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3;
1502                 break;
1503         case 4:
1504                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4;
1505                 break;
1506         default:
1507                 dev_err(sdma->dev, "unknown firmware version\n");
1508                 goto err_firmware;
1509         }
1510
1511         addr = (void *)header + header->script_addrs_start;
1512         ram_code = (void *)header + header->ram_code_start;
1513
1514         clk_enable(sdma->clk_ipg);
1515         clk_enable(sdma->clk_ahb);
1516         /* download the RAM image for SDMA */
1517         sdma_load_script(sdma, ram_code,
1518                         header->ram_code_size,
1519                         addr->ram_code_start_addr);
1520         clk_disable(sdma->clk_ipg);
1521         clk_disable(sdma->clk_ahb);
1522
1523         sdma_add_scripts(sdma, addr);
1524
1525         dev_info(sdma->dev, "loaded firmware %d.%d\n",
1526                         header->version_major,
1527                         header->version_minor);
1528
1529 err_firmware:
1530         release_firmware(fw);
1531 }
1532
1533 #define EVENT_REMAP_CELLS 3
1534
1535 static int sdma_event_remap(struct sdma_engine *sdma)
1536 {
1537         struct device_node *np = sdma->dev->of_node;
1538         struct device_node *gpr_np = of_parse_phandle(np, "gpr", 0);
1539         struct property *event_remap;
1540         struct regmap *gpr;
1541         char propname[] = "fsl,sdma-event-remap";
1542         u32 reg, val, shift, num_map, i;
1543         int ret = 0;
1544
1545         if (IS_ERR(np) || IS_ERR(gpr_np))
1546                 goto out;
1547
1548         event_remap = of_find_property(np, propname, NULL);
1549         num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0;
1550         if (!num_map) {
1551                 dev_dbg(sdma->dev, "no event needs to be remapped\n");
1552                 goto out;
1553         } else if (num_map % EVENT_REMAP_CELLS) {
1554                 dev_err(sdma->dev, "the property %s must modulo %d\n",
1555                                 propname, EVENT_REMAP_CELLS);
1556                 ret = -EINVAL;
1557                 goto out;
1558         }
1559
1560         gpr = syscon_node_to_regmap(gpr_np);
1561         if (IS_ERR(gpr)) {
1562                 dev_err(sdma->dev, "failed to get gpr regmap\n");
1563                 ret = PTR_ERR(gpr);
1564                 goto out;
1565         }
1566
1567         for (i = 0; i < num_map; i += EVENT_REMAP_CELLS) {
1568                 ret = of_property_read_u32_index(np, propname, i, &reg);
1569                 if (ret) {
1570                         dev_err(sdma->dev, "failed to read property %s index %d\n",
1571                                         propname, i);
1572                         goto out;
1573                 }
1574
1575                 ret = of_property_read_u32_index(np, propname, i + 1, &shift);
1576                 if (ret) {
1577                         dev_err(sdma->dev, "failed to read property %s index %d\n",
1578                                         propname, i + 1);
1579                         goto out;
1580                 }
1581
1582                 ret = of_property_read_u32_index(np, propname, i + 2, &val);
1583                 if (ret) {
1584                         dev_err(sdma->dev, "failed to read property %s index %d\n",
1585                                         propname, i + 2);
1586                         goto out;
1587                 }
1588
1589                 regmap_update_bits(gpr, reg, BIT(shift), val << shift);
1590         }
1591
1592 out:
1593         if (!IS_ERR(gpr_np))
1594                 of_node_put(gpr_np);
1595
1596         return ret;
1597 }
1598
1599 static int sdma_get_firmware(struct sdma_engine *sdma,
1600                 const char *fw_name)
1601 {
1602         int ret;
1603
1604         ret = request_firmware_nowait(THIS_MODULE,
1605                         FW_ACTION_HOTPLUG, fw_name, sdma->dev,
1606                         GFP_KERNEL, sdma, sdma_load_firmware);
1607
1608         return ret;
1609 }
1610
1611 static int sdma_init(struct sdma_engine *sdma)
1612 {
1613         int i, ret;
1614         dma_addr_t ccb_phys;
1615
1616         ret = clk_enable(sdma->clk_ipg);
1617         if (ret)
1618                 return ret;
1619         ret = clk_enable(sdma->clk_ahb);
1620         if (ret)
1621                 goto disable_clk_ipg;
1622
1623         /* Be sure SDMA has not started yet */
1624         writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
1625
1626         sdma->channel_control = dma_alloc_coherent(NULL,
1627                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1628                         sizeof(struct sdma_context_data),
1629                         &ccb_phys, GFP_KERNEL);
1630
1631         if (!sdma->channel_control) {
1632                 ret = -ENOMEM;
1633                 goto err_dma_alloc;
1634         }
1635
1636         sdma->context = (void *)sdma->channel_control +
1637                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1638         sdma->context_phys = ccb_phys +
1639                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1640
1641         /* Zero-out the CCB structures array just allocated */
1642         memset(sdma->channel_control, 0,
1643                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1644
1645         /* disable all channels */
1646         for (i = 0; i < sdma->drvdata->num_events; i++)
1647                 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
1648
1649         /* All channels have priority 0 */
1650         for (i = 0; i < MAX_DMA_CHANNELS; i++)
1651                 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1652
1653         ret = sdma_request_channel(&sdma->channel[0]);
1654         if (ret)
1655                 goto err_dma_alloc;
1656
1657         sdma_config_ownership(&sdma->channel[0], false, true, false);
1658
1659         /* Set Command Channel (Channel Zero) */
1660         writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
1661
1662         /* Set bits of CONFIG register but with static context switching */
1663         /* FIXME: Check whether to set ACR bit depending on clock ratios */
1664         writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
1665
1666         writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1667
1668         /* Initializes channel's priorities */
1669         sdma_set_channel_priority(&sdma->channel[0], 7);
1670
1671         clk_disable(sdma->clk_ipg);
1672         clk_disable(sdma->clk_ahb);
1673
1674         return 0;
1675
1676 err_dma_alloc:
1677         clk_disable(sdma->clk_ahb);
1678 disable_clk_ipg:
1679         clk_disable(sdma->clk_ipg);
1680         dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1681         return ret;
1682 }
1683
1684 static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param)
1685 {
1686         struct sdma_channel *sdmac = to_sdma_chan(chan);
1687         struct imx_dma_data *data = fn_param;
1688
1689         if (!imx_dma_is_general_purpose(chan))
1690                 return false;
1691
1692         sdmac->data = *data;
1693         chan->private = &sdmac->data;
1694
1695         return true;
1696 }
1697
1698 static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec,
1699                                    struct of_dma *ofdma)
1700 {
1701         struct sdma_engine *sdma = ofdma->of_dma_data;
1702         dma_cap_mask_t mask = sdma->dma_device.cap_mask;
1703         struct imx_dma_data data;
1704
1705         if (dma_spec->args_count != 3)
1706                 return NULL;
1707
1708         data.dma_request = dma_spec->args[0];
1709         data.peripheral_type = dma_spec->args[1];
1710         data.priority = dma_spec->args[2];
1711         /*
1712          * init dma_request2 to zero, which is not used by the dts.
1713          * For P2P, dma_request2 is init from dma_request_channel(),
1714          * chan->private will point to the imx_dma_data, and in
1715          * device_alloc_chan_resources(), imx_dma_data.dma_request2 will
1716          * be set to sdmac->event_id1.
1717          */
1718         data.dma_request2 = 0;
1719
1720         return dma_request_channel(mask, sdma_filter_fn, &data);
1721 }
1722
1723 static int sdma_probe(struct platform_device *pdev)
1724 {
1725         const struct of_device_id *of_id =
1726                         of_match_device(sdma_dt_ids, &pdev->dev);
1727         struct device_node *np = pdev->dev.of_node;
1728         struct device_node *spba_bus;
1729         const char *fw_name;
1730         int ret;
1731         int irq;
1732         struct resource *iores;
1733         struct resource spba_res;
1734         struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev);
1735         int i;
1736         struct sdma_engine *sdma;
1737         s32 *saddr_arr;
1738         const struct sdma_driver_data *drvdata = NULL;
1739
1740         if (of_id)
1741                 drvdata = of_id->data;
1742         else if (pdev->id_entry)
1743                 drvdata = (void *)pdev->id_entry->driver_data;
1744
1745         if (!drvdata) {
1746                 dev_err(&pdev->dev, "unable to find driver data\n");
1747                 return -EINVAL;
1748         }
1749
1750         ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1751         if (ret)
1752                 return ret;
1753
1754         sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL);
1755         if (!sdma)
1756                 return -ENOMEM;
1757
1758         spin_lock_init(&sdma->channel_0_lock);
1759
1760         sdma->dev = &pdev->dev;
1761         sdma->drvdata = drvdata;
1762
1763         irq = platform_get_irq(pdev, 0);
1764         if (irq < 0)
1765                 return irq;
1766
1767         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1768         sdma->regs = devm_ioremap_resource(&pdev->dev, iores);
1769         if (IS_ERR(sdma->regs))
1770                 return PTR_ERR(sdma->regs);
1771
1772         sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1773         if (IS_ERR(sdma->clk_ipg))
1774                 return PTR_ERR(sdma->clk_ipg);
1775
1776         sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1777         if (IS_ERR(sdma->clk_ahb))
1778                 return PTR_ERR(sdma->clk_ahb);
1779
1780         ret = clk_prepare(sdma->clk_ipg);
1781         if (ret)
1782                 return ret;
1783
1784         ret = clk_prepare(sdma->clk_ahb);
1785         if (ret)
1786                 goto err_clk;
1787
1788         ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, "sdma",
1789                                sdma);
1790         if (ret)
1791                 goto err_irq;
1792
1793         sdma->irq = irq;
1794
1795         sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
1796         if (!sdma->script_addrs) {
1797                 ret = -ENOMEM;
1798                 goto err_irq;
1799         }
1800
1801         /* initially no scripts available */
1802         saddr_arr = (s32 *)sdma->script_addrs;
1803         for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1804                 saddr_arr[i] = -EINVAL;
1805
1806         dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
1807         dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
1808
1809         INIT_LIST_HEAD(&sdma->dma_device.channels);
1810         /* Initialize channel parameters */
1811         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1812                 struct sdma_channel *sdmac = &sdma->channel[i];
1813
1814                 sdmac->sdma = sdma;
1815                 spin_lock_init(&sdmac->lock);
1816
1817                 sdmac->chan.device = &sdma->dma_device;
1818                 dma_cookie_init(&sdmac->chan);
1819                 sdmac->channel = i;
1820
1821                 tasklet_init(&sdmac->tasklet, mxc_sdma_handle_channel_normal,
1822                              (unsigned long) sdmac);
1823                 /*
1824                  * Add the channel to the DMAC list. Do not add channel 0 though
1825                  * because we need it internally in the SDMA driver. This also means
1826                  * that channel 0 in dmaengine counting matches sdma channel 1.
1827                  */
1828                 if (i)
1829                         list_add_tail(&sdmac->chan.device_node,
1830                                         &sdma->dma_device.channels);
1831         }
1832
1833         ret = sdma_init(sdma);
1834         if (ret)
1835                 goto err_init;
1836
1837         ret = sdma_event_remap(sdma);
1838         if (ret)
1839                 goto err_init;
1840
1841         if (sdma->drvdata->script_addrs)
1842                 sdma_add_scripts(sdma, sdma->drvdata->script_addrs);
1843         if (pdata && pdata->script_addrs)
1844                 sdma_add_scripts(sdma, pdata->script_addrs);
1845
1846         if (pdata) {
1847                 ret = sdma_get_firmware(sdma, pdata->fw_name);
1848                 if (ret)
1849                         dev_warn(&pdev->dev, "failed to get firmware from platform data\n");
1850         } else {
1851                 /*
1852                  * Because that device tree does not encode ROM script address,
1853                  * the RAM script in firmware is mandatory for device tree
1854                  * probe, otherwise it fails.
1855                  */
1856                 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
1857                                               &fw_name);
1858                 if (ret)
1859                         dev_warn(&pdev->dev, "failed to get firmware name\n");
1860                 else {
1861                         ret = sdma_get_firmware(sdma, fw_name);
1862                         if (ret)
1863                                 dev_warn(&pdev->dev, "failed to get firmware from device tree\n");
1864                 }
1865         }
1866
1867         sdma->dma_device.dev = &pdev->dev;
1868
1869         sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
1870         sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
1871         sdma->dma_device.device_tx_status = sdma_tx_status;
1872         sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
1873         sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
1874         sdma->dma_device.device_config = sdma_config;
1875         sdma->dma_device.device_terminate_all = sdma_disable_channel_with_delay;
1876         sdma->dma_device.src_addr_widths = SDMA_DMA_BUSWIDTHS;
1877         sdma->dma_device.dst_addr_widths = SDMA_DMA_BUSWIDTHS;
1878         sdma->dma_device.directions = SDMA_DMA_DIRECTIONS;
1879         sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
1880         sdma->dma_device.device_issue_pending = sdma_issue_pending;
1881         sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
1882         dma_set_max_seg_size(sdma->dma_device.dev, 65535);
1883
1884         platform_set_drvdata(pdev, sdma);
1885
1886         ret = dma_async_device_register(&sdma->dma_device);
1887         if (ret) {
1888                 dev_err(&pdev->dev, "unable to register\n");
1889                 goto err_init;
1890         }
1891
1892         if (np) {
1893                 ret = of_dma_controller_register(np, sdma_xlate, sdma);
1894                 if (ret) {
1895                         dev_err(&pdev->dev, "failed to register controller\n");
1896                         goto err_register;
1897                 }
1898
1899                 spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus");
1900                 ret = of_address_to_resource(spba_bus, 0, &spba_res);
1901                 if (!ret) {
1902                         sdma->spba_start_addr = spba_res.start;
1903                         sdma->spba_end_addr = spba_res.end;
1904                 }
1905                 of_node_put(spba_bus);
1906         }
1907
1908         return 0;
1909
1910 err_register:
1911         dma_async_device_unregister(&sdma->dma_device);
1912 err_init:
1913         kfree(sdma->script_addrs);
1914 err_irq:
1915         clk_unprepare(sdma->clk_ahb);
1916 err_clk:
1917         clk_unprepare(sdma->clk_ipg);
1918         return ret;
1919 }
1920
1921 static int sdma_remove(struct platform_device *pdev)
1922 {
1923         struct sdma_engine *sdma = platform_get_drvdata(pdev);
1924         int i;
1925
1926         devm_free_irq(&pdev->dev, sdma->irq, sdma);
1927         dma_async_device_unregister(&sdma->dma_device);
1928         kfree(sdma->script_addrs);
1929         clk_unprepare(sdma->clk_ahb);
1930         clk_unprepare(sdma->clk_ipg);
1931         /* Kill the tasklet */
1932         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1933                 struct sdma_channel *sdmac = &sdma->channel[i];
1934
1935                 tasklet_kill(&sdmac->tasklet);
1936         }
1937
1938         platform_set_drvdata(pdev, NULL);
1939         return 0;
1940 }
1941
1942 static struct platform_driver sdma_driver = {
1943         .driver         = {
1944                 .name   = "imx-sdma",
1945                 .of_match_table = sdma_dt_ids,
1946         },
1947         .id_table       = sdma_devtypes,
1948         .remove         = sdma_remove,
1949         .probe          = sdma_probe,
1950 };
1951
1952 module_platform_driver(sdma_driver);
1953
1954 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1955 MODULE_DESCRIPTION("i.MX SDMA driver");
1956 #if IS_ENABLED(CONFIG_SOC_IMX6Q)
1957 MODULE_FIRMWARE("imx/sdma/sdma-imx6q.bin");
1958 #endif
1959 #if IS_ENABLED(CONFIG_SOC_IMX7D)
1960 MODULE_FIRMWARE("imx/sdma/sdma-imx7d.bin");
1961 #endif
1962 MODULE_LICENSE("GPL");