drivers/dma/qcom/bam_dma.c

   1 /*
   2  * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  */
  14 /*
  15  * QCOM BAM DMA engine driver
  16  *
  17  * QCOM BAM DMA blocks are distributed amongst a number of the on-chip
  18  * peripherals on the MSM 8x74.  The configuration of the channels are dependent
  19  * on the way they are hard wired to that specific peripheral.  The peripheral
  20  * device tree entries specify the configuration of each channel.
  21  *
  22  * The DMA controller requires the use of external memory for storage of the
  23  * hardware descriptors for each channel.  The descriptor FIFO is accessed as a
  24  * circular buffer and operations are managed according to the offset within the
  25  * FIFO.  After pipe/channel reset, all of the pipe registers and internal state
  26  * are back to defaults.
  27  *
  28  * During DMA operations, we write descriptors to the FIFO, being careful to
  29  * handle wrapping and then write the last FIFO offset to that channel's
  30  * P_EVNT_REG register to kick off the transaction.  The P_SW_OFSTS register
  31  * indicates the current FIFO offset that is being processed, so there is some
  32  * indication of where the hardware is currently working.
  33  */
  34
  35 #include <linux/kernel.h>
  36 #include <linux/io.h>
  37 #include <linux/init.h>
  38 #include <linux/slab.h>
  39 #include <linux/module.h>
  40 #include <linux/interrupt.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/scatterlist.h>
  43 #include <linux/device.h>
  44 #include <linux/platform_device.h>
  45 #include <linux/of.h>
  46 #include <linux/of_address.h>
  47 #include <linux/of_irq.h>
  48 #include <linux/of_dma.h>
  49 #include <linux/circ_buf.h>
  50 #include <linux/clk.h>
  51 #include <linux/dmaengine.h>
  52 #include <linux/pm_runtime.h>
  53
  54 #include "../dmaengine.h"
  55 #include "../virt-dma.h"
  56
  57 struct bam_desc_hw {
  58         __le32 addr;            /* Buffer physical address */
  59         __le16 size;            /* Buffer size in bytes */
  60         __le16 flags;
  61 };
  62
  63 #define BAM_DMA_AUTOSUSPEND_DELAY 100
  64
  65 #define DESC_FLAG_INT BIT(15)
  66 #define DESC_FLAG_EOT BIT(14)
  67 #define DESC_FLAG_EOB BIT(13)
  68 #define DESC_FLAG_NWD BIT(12)
  69 #define DESC_FLAG_CMD BIT(11)
  70
  71 struct bam_async_desc {
  72         struct virt_dma_desc vd;
  73
  74         u32 num_desc;
  75         u32 xfer_len;
  76
  77         /* transaction flags, EOT|EOB|NWD */
  78         u16 flags;
  79
  80         struct bam_desc_hw *curr_desc;
  81
  82         /* list node for the desc in the bam_chan list of descriptors */
  83         struct list_head desc_node;
  84         enum dma_transfer_direction dir;
  85         size_t length;
  86         struct bam_desc_hw desc[0];
  87 };
  88
  89 enum bam_reg {
  90         BAM_CTRL,
  91         BAM_REVISION,
  92         BAM_NUM_PIPES,
  93         BAM_DESC_CNT_TRSHLD,
  94         BAM_IRQ_SRCS,
  95         BAM_IRQ_SRCS_MSK,
  96         BAM_IRQ_SRCS_UNMASKED,
  97         BAM_IRQ_STTS,
  98         BAM_IRQ_CLR,
  99         BAM_IRQ_EN,
 100         BAM_CNFG_BITS,
 101         BAM_IRQ_SRCS_EE,
 102         BAM_IRQ_SRCS_MSK_EE,
 103         BAM_P_CTRL,
 104         BAM_P_RST,
 105         BAM_P_HALT,
 106         BAM_P_IRQ_STTS,
 107         BAM_P_IRQ_CLR,
 108         BAM_P_IRQ_EN,
 109         BAM_P_EVNT_DEST_ADDR,
 110         BAM_P_EVNT_REG,
 111         BAM_P_SW_OFSTS,
 112         BAM_P_DATA_FIFO_ADDR,
 113         BAM_P_DESC_FIFO_ADDR,
 114         BAM_P_EVNT_GEN_TRSHLD,
 115         BAM_P_FIFO_SIZES,
 116 };
 117
 118 struct reg_offset_data {
 119         u32 base_offset;
 120         unsigned int pipe_mult, evnt_mult, ee_mult;
 121 };
 122
 123 static const struct reg_offset_data bam_v1_3_reg_info[] = {
 124         [BAM_CTRL]              = { 0x0F80, 0x00, 0x00, 0x00 },
 125         [BAM_REVISION]          = { 0x0F84, 0x00, 0x00, 0x00 },
 126         [BAM_NUM_PIPES]         = { 0x0FBC, 0x00, 0x00, 0x00 },
 127         [BAM_DESC_CNT_TRSHLD]   = { 0x0F88, 0x00, 0x00, 0x00 },
 128         [BAM_IRQ_SRCS]          = { 0x0F8C, 0x00, 0x00, 0x00 },
 129         [BAM_IRQ_SRCS_MSK]      = { 0x0F90, 0x00, 0x00, 0x00 },
 130         [BAM_IRQ_SRCS_UNMASKED] = { 0x0FB0, 0x00, 0x00, 0x00 },
 131         [BAM_IRQ_STTS]          = { 0x0F94, 0x00, 0x00, 0x00 },
 132         [BAM_IRQ_CLR]           = { 0x0F98, 0x00, 0x00, 0x00 },
 133         [BAM_IRQ_EN]            = { 0x0F9C, 0x00, 0x00, 0x00 },
 134         [BAM_CNFG_BITS]         = { 0x0FFC, 0x00, 0x00, 0x00 },
 135         [BAM_IRQ_SRCS_EE]       = { 0x1800, 0x00, 0x00, 0x80 },
 136         [BAM_IRQ_SRCS_MSK_EE]   = { 0x1804, 0x00, 0x00, 0x80 },
 137         [BAM_P_CTRL]            = { 0x0000, 0x80, 0x00, 0x00 },
 138         [BAM_P_RST]             = { 0x0004, 0x80, 0x00, 0x00 },
 139         [BAM_P_HALT]            = { 0x0008, 0x80, 0x00, 0x00 },
 140         [BAM_P_IRQ_STTS]        = { 0x0010, 0x80, 0x00, 0x00 },
 141         [BAM_P_IRQ_CLR]         = { 0x0014, 0x80, 0x00, 0x00 },
 142         [BAM_P_IRQ_EN]          = { 0x0018, 0x80, 0x00, 0x00 },
 143         [BAM_P_EVNT_DEST_ADDR]  = { 0x102C, 0x00, 0x40, 0x00 },
 144         [BAM_P_EVNT_REG]        = { 0x1018, 0x00, 0x40, 0x00 },
 145         [BAM_P_SW_OFSTS]        = { 0x1000, 0x00, 0x40, 0x00 },
 146         [BAM_P_DATA_FIFO_ADDR]  = { 0x1024, 0x00, 0x40, 0x00 },
 147         [BAM_P_DESC_FIFO_ADDR]  = { 0x101C, 0x00, 0x40, 0x00 },
 148         [BAM_P_EVNT_GEN_TRSHLD] = { 0x1028, 0x00, 0x40, 0x00 },
 149         [BAM_P_FIFO_SIZES]      = { 0x1020, 0x00, 0x40, 0x00 },
 150 };
 151
 152 static const struct reg_offset_data bam_v1_4_reg_info[] = {
 153         [BAM_CTRL]              = { 0x0000, 0x00, 0x00, 0x00 },
 154         [BAM_REVISION]          = { 0x0004, 0x00, 0x00, 0x00 },
 155         [BAM_NUM_PIPES]         = { 0x003C, 0x00, 0x00, 0x00 },
 156         [BAM_DESC_CNT_TRSHLD]   = { 0x0008, 0x00, 0x00, 0x00 },
 157         [BAM_IRQ_SRCS]          = { 0x000C, 0x00, 0x00, 0x00 },
 158         [BAM_IRQ_SRCS_MSK]      = { 0x0010, 0x00, 0x00, 0x00 },
 159         [BAM_IRQ_SRCS_UNMASKED] = { 0x0030, 0x00, 0x00, 0x00 },
 160         [BAM_IRQ_STTS]          = { 0x0014, 0x00, 0x00, 0x00 },
 161         [BAM_IRQ_CLR]           = { 0x0018, 0x00, 0x00, 0x00 },
 162         [BAM_IRQ_EN]            = { 0x001C, 0x00, 0x00, 0x00 },
 163         [BAM_CNFG_BITS]         = { 0x007C, 0x00, 0x00, 0x00 },
 164         [BAM_IRQ_SRCS_EE]       = { 0x0800, 0x00, 0x00, 0x80 },
 165         [BAM_IRQ_SRCS_MSK_EE]   = { 0x0804, 0x00, 0x00, 0x80 },
 166         [BAM_P_CTRL]            = { 0x1000, 0x1000, 0x00, 0x00 },
 167         [BAM_P_RST]             = { 0x1004, 0x1000, 0x00, 0x00 },
 168         [BAM_P_HALT]            = { 0x1008, 0x1000, 0x00, 0x00 },
 169         [BAM_P_IRQ_STTS]        = { 0x1010, 0x1000, 0x00, 0x00 },
 170         [BAM_P_IRQ_CLR]         = { 0x1014, 0x1000, 0x00, 0x00 },
 171         [BAM_P_IRQ_EN]          = { 0x1018, 0x1000, 0x00, 0x00 },
 172         [BAM_P_EVNT_DEST_ADDR]  = { 0x182C, 0x00, 0x1000, 0x00 },
 173         [BAM_P_EVNT_REG]        = { 0x1818, 0x00, 0x1000, 0x00 },
 174         [BAM_P_SW_OFSTS]        = { 0x1800, 0x00, 0x1000, 0x00 },
 175         [BAM_P_DATA_FIFO_ADDR]  = { 0x1824, 0x00, 0x1000, 0x00 },
 176         [BAM_P_DESC_FIFO_ADDR]  = { 0x181C, 0x00, 0x1000, 0x00 },
 177         [BAM_P_EVNT_GEN_TRSHLD] = { 0x1828, 0x00, 0x1000, 0x00 },
 178         [BAM_P_FIFO_SIZES]      = { 0x1820, 0x00, 0x1000, 0x00 },
 179 };
 180
 181 static const struct reg_offset_data bam_v1_7_reg_info[] = {
 182         [BAM_CTRL]              = { 0x00000, 0x00, 0x00, 0x00 },
 183         [BAM_REVISION]          = { 0x01000, 0x00, 0x00, 0x00 },
 184         [BAM_NUM_PIPES]         = { 0x01008, 0x00, 0x00, 0x00 },
 185         [BAM_DESC_CNT_TRSHLD]   = { 0x00008, 0x00, 0x00, 0x00 },
 186         [BAM_IRQ_SRCS]          = { 0x03010, 0x00, 0x00, 0x00 },
 187         [BAM_IRQ_SRCS_MSK]      = { 0x03014, 0x00, 0x00, 0x00 },
 188         [BAM_IRQ_SRCS_UNMASKED] = { 0x03018, 0x00, 0x00, 0x00 },
 189         [BAM_IRQ_STTS]          = { 0x00014, 0x00, 0x00, 0x00 },
 190         [BAM_IRQ_CLR]           = { 0x00018, 0x00, 0x00, 0x00 },
 191         [BAM_IRQ_EN]            = { 0x0001C, 0x00, 0x00, 0x00 },
 192         [BAM_CNFG_BITS]         = { 0x0007C, 0x00, 0x00, 0x00 },
 193         [BAM_IRQ_SRCS_EE]       = { 0x03000, 0x00, 0x00, 0x1000 },
 194         [BAM_IRQ_SRCS_MSK_EE]   = { 0x03004, 0x00, 0x00, 0x1000 },
 195         [BAM_P_CTRL]            = { 0x13000, 0x1000, 0x00, 0x00 },
 196         [BAM_P_RST]             = { 0x13004, 0x1000, 0x00, 0x00 },
 197         [BAM_P_HALT]            = { 0x13008, 0x1000, 0x00, 0x00 },
 198         [BAM_P_IRQ_STTS]        = { 0x13010, 0x1000, 0x00, 0x00 },
 199         [BAM_P_IRQ_CLR]         = { 0x13014, 0x1000, 0x00, 0x00 },
 200         [BAM_P_IRQ_EN]          = { 0x13018, 0x1000, 0x00, 0x00 },
 201         [BAM_P_EVNT_DEST_ADDR]  = { 0x1382C, 0x00, 0x1000, 0x00 },
 202         [BAM_P_EVNT_REG]        = { 0x13818, 0x00, 0x1000, 0x00 },
 203         [BAM_P_SW_OFSTS]        = { 0x13800, 0x00, 0x1000, 0x00 },
 204         [BAM_P_DATA_FIFO_ADDR]  = { 0x13824, 0x00, 0x1000, 0x00 },
 205         [BAM_P_DESC_FIFO_ADDR]  = { 0x1381C, 0x00, 0x1000, 0x00 },
 206         [BAM_P_EVNT_GEN_TRSHLD] = { 0x13828, 0x00, 0x1000, 0x00 },
 207         [BAM_P_FIFO_SIZES]      = { 0x13820, 0x00, 0x1000, 0x00 },
 208 };
 209
 210 /* BAM CTRL */
 211 #define BAM_SW_RST                      BIT(0)
 212 #define BAM_EN                          BIT(1)
 213 #define BAM_EN_ACCUM                    BIT(4)
 214 #define BAM_TESTBUS_SEL_SHIFT           5
 215 #define BAM_TESTBUS_SEL_MASK            0x3F
 216 #define BAM_DESC_CACHE_SEL_SHIFT        13
 217 #define BAM_DESC_CACHE_SEL_MASK         0x3
 218 #define BAM_CACHED_DESC_STORE           BIT(15)
 219 #define IBC_DISABLE                     BIT(16)
 220
 221 /* BAM REVISION */
 222 #define REVISION_SHIFT          0
 223 #define REVISION_MASK           0xFF
 224 #define NUM_EES_SHIFT           8
 225 #define NUM_EES_MASK            0xF
 226 #define CE_BUFFER_SIZE          BIT(13)
 227 #define AXI_ACTIVE              BIT(14)
 228 #define USE_VMIDMT              BIT(15)
 229 #define SECURED                 BIT(16)
 230 #define BAM_HAS_NO_BYPASS       BIT(17)
 231 #define HIGH_FREQUENCY_BAM      BIT(18)
 232 #define INACTIV_TMRS_EXST       BIT(19)
 233 #define NUM_INACTIV_TMRS        BIT(20)
 234 #define DESC_CACHE_DEPTH_SHIFT  21
 235 #define DESC_CACHE_DEPTH_1      (0 << DESC_CACHE_DEPTH_SHIFT)
 236 #define DESC_CACHE_DEPTH_2      (1 << DESC_CACHE_DEPTH_SHIFT)
 237 #define DESC_CACHE_DEPTH_3      (2 << DESC_CACHE_DEPTH_SHIFT)
 238 #define DESC_CACHE_DEPTH_4      (3 << DESC_CACHE_DEPTH_SHIFT)
 239 #define CMD_DESC_EN             BIT(23)
 240 #define INACTIV_TMR_BASE_SHIFT  24
 241 #define INACTIV_TMR_BASE_MASK   0xFF
 242
 243 /* BAM NUM PIPES */
 244 #define BAM_NUM_PIPES_SHIFT             0
 245 #define BAM_NUM_PIPES_MASK              0xFF
 246 #define PERIPH_NON_PIPE_GRP_SHIFT       16
 247 #define PERIPH_NON_PIP_GRP_MASK         0xFF
 248 #define BAM_NON_PIPE_GRP_SHIFT          24
 249 #define BAM_NON_PIPE_GRP_MASK           0xFF
 250
 251 /* BAM CNFG BITS */
 252 #define BAM_PIPE_CNFG           BIT(2)
 253 #define BAM_FULL_PIPE           BIT(11)
 254 #define BAM_NO_EXT_P_RST        BIT(12)
 255 #define BAM_IBC_DISABLE         BIT(13)
 256 #define BAM_SB_CLK_REQ          BIT(14)
 257 #define BAM_PSM_CSW_REQ         BIT(15)
 258 #define BAM_PSM_P_RES           BIT(16)
 259 #define BAM_AU_P_RES            BIT(17)
 260 #define BAM_SI_P_RES            BIT(18)
 261 #define BAM_WB_P_RES            BIT(19)
 262 #define BAM_WB_BLK_CSW          BIT(20)
 263 #define BAM_WB_CSW_ACK_IDL      BIT(21)
 264 #define BAM_WB_RETR_SVPNT       BIT(22)
 265 #define BAM_WB_DSC_AVL_P_RST    BIT(23)
 266 #define BAM_REG_P_EN            BIT(24)
 267 #define BAM_PSM_P_HD_DATA       BIT(25)
 268 #define BAM_AU_ACCUMED          BIT(26)
 269 #define BAM_CMD_ENABLE          BIT(27)
 270
 271 #define BAM_CNFG_BITS_DEFAULT   (BAM_PIPE_CNFG |        \
 272                                  BAM_NO_EXT_P_RST |     \
 273                                  BAM_IBC_DISABLE |      \
 274                                  BAM_SB_CLK_REQ |       \
 275                                  BAM_PSM_CSW_REQ |      \
 276                                  BAM_PSM_P_RES |        \
 277                                  BAM_AU_P_RES |         \
 278                                  BAM_SI_P_RES |         \
 279                                  BAM_WB_P_RES |         \
 280                                  BAM_WB_BLK_CSW |       \
 281                                  BAM_WB_CSW_ACK_IDL |   \
 282                                  BAM_WB_RETR_SVPNT |    \
 283                                  BAM_WB_DSC_AVL_P_RST | \
 284                                  BAM_REG_P_EN |         \
 285                                  BAM_PSM_P_HD_DATA |    \
 286                                  BAM_AU_ACCUMED |       \
 287                                  BAM_CMD_ENABLE)
 288
 289 /* PIPE CTRL */
 290 #define P_EN                    BIT(1)
 291 #define P_DIRECTION             BIT(3)
 292 #define P_SYS_STRM              BIT(4)
 293 #define P_SYS_MODE              BIT(5)
 294 #define P_AUTO_EOB              BIT(6)
 295 #define P_AUTO_EOB_SEL_SHIFT    7
 296 #define P_AUTO_EOB_SEL_512      (0 << P_AUTO_EOB_SEL_SHIFT)
 297 #define P_AUTO_EOB_SEL_256      (1 << P_AUTO_EOB_SEL_SHIFT)
 298 #define P_AUTO_EOB_SEL_128      (2 << P_AUTO_EOB_SEL_SHIFT)
 299 #define P_AUTO_EOB_SEL_64       (3 << P_AUTO_EOB_SEL_SHIFT)
 300 #define P_PREFETCH_LIMIT_SHIFT  9
 301 #define P_PREFETCH_LIMIT_32     (0 << P_PREFETCH_LIMIT_SHIFT)
 302 #define P_PREFETCH_LIMIT_16     (1 << P_PREFETCH_LIMIT_SHIFT)
 303 #define P_PREFETCH_LIMIT_4      (2 << P_PREFETCH_LIMIT_SHIFT)
 304 #define P_WRITE_NWD             BIT(11)
 305 #define P_LOCK_GROUP_SHIFT      16
 306 #define P_LOCK_GROUP_MASK       0x1F
 307
 308 /* BAM_DESC_CNT_TRSHLD */
 309 #define CNT_TRSHLD              0xffff
 310 #define DEFAULT_CNT_THRSHLD     0x4
 311
 312 /* BAM_IRQ_SRCS */
 313 #define BAM_IRQ                 BIT(31)
 314 #define P_IRQ                   0x7fffffff
 315
 316 /* BAM_IRQ_SRCS_MSK */
 317 #define BAM_IRQ_MSK             BAM_IRQ
 318 #define P_IRQ_MSK               P_IRQ
 319
 320 /* BAM_IRQ_STTS */
 321 #define BAM_TIMER_IRQ           BIT(4)
 322 #define BAM_EMPTY_IRQ           BIT(3)
 323 #define BAM_ERROR_IRQ           BIT(2)
 324 #define BAM_HRESP_ERR_IRQ       BIT(1)
 325
 326 /* BAM_IRQ_CLR */
 327 #define BAM_TIMER_CLR           BIT(4)
 328 #define BAM_EMPTY_CLR           BIT(3)
 329 #define BAM_ERROR_CLR           BIT(2)
 330 #define BAM_HRESP_ERR_CLR       BIT(1)
 331
 332 /* BAM_IRQ_EN */
 333 #define BAM_TIMER_EN            BIT(4)
 334 #define BAM_EMPTY_EN            BIT(3)
 335 #define BAM_ERROR_EN            BIT(2)
 336 #define BAM_HRESP_ERR_EN        BIT(1)
 337
 338 /* BAM_P_IRQ_EN */
 339 #define P_PRCSD_DESC_EN         BIT(0)
 340 #define P_TIMER_EN              BIT(1)
 341 #define P_WAKE_EN               BIT(2)
 342 #define P_OUT_OF_DESC_EN        BIT(3)
 343 #define P_ERR_EN                BIT(4)
 344 #define P_TRNSFR_END_EN         BIT(5)
 345 #define P_DEFAULT_IRQS_EN       (P_PRCSD_DESC_EN | P_ERR_EN | P_TRNSFR_END_EN)
 346
 347 /* BAM_P_SW_OFSTS */
 348 #define P_SW_OFSTS_MASK         0xffff
 349
 350 #define BAM_DESC_FIFO_SIZE      SZ_32K
 351 #define MAX_DESCRIPTORS (BAM_DESC_FIFO_SIZE / sizeof(struct bam_desc_hw) - 1)
 352 #define BAM_FIFO_SIZE   (SZ_32K - 8)
 353 #define IS_BUSY(chan)   (CIRC_SPACE(bchan->tail, bchan->head,\
 354                          MAX_DESCRIPTORS + 1) == 0)
 355
 356 struct bam_chan {
 357         struct virt_dma_chan vc;
 358
 359         struct bam_device *bdev;
 360
 361         /* configuration from device tree */
 362         u32 id;
 363
 364         /* runtime configuration */
 365         struct dma_slave_config slave;
 366
 367         /* fifo storage */
 368         struct bam_desc_hw *fifo_virt;
 369         dma_addr_t fifo_phys;
 370
 371         /* fifo markers */
 372         unsigned short head;            /* start of active descriptor entries */
 373         unsigned short tail;            /* end of active descriptor entries */
 374
 375         unsigned int initialized;       /* is the channel hw initialized? */
 376         unsigned int paused;            /* is the channel paused? */
 377         unsigned int reconfigure;       /* new slave config? */
 378         /* list of descriptors currently processed */
 379         struct list_head desc_list;
 380
 381         struct list_head node;
 382 };
 383
 384 static inline struct bam_chan *to_bam_chan(struct dma_chan *common)
 385 {
 386         return container_of(common, struct bam_chan, vc.chan);
 387 }
 388
 389 struct bam_device {
 390         void __iomem *regs;
 391         struct device *dev;
 392         struct dma_device common;
 393         struct device_dma_parameters dma_parms;
 394         struct bam_chan *channels;
 395         u32 num_channels;
 396         u32 num_ees;
 397
 398         /* execution environment ID, from DT */
 399         u32 ee;
 400         bool controlled_remotely;
 401
 402         const struct reg_offset_data *layout;
 403
 404         struct clk *bamclk;
 405         int irq;
 406
 407         /* dma start transaction tasklet */
 408         struct tasklet_struct task;
 409 };
 410
 411 /**
 412  * bam_addr - returns BAM register address
 413  * @bdev: bam device
 414  * @pipe: pipe instance (ignored when register doesn't have multiple instances)
 415  * @reg:  register enum
 416  */
 417 static inline void __iomem *bam_addr(struct bam_device *bdev, u32 pipe,
 418                 enum bam_reg reg)
 419 {
 420         const struct reg_offset_data r = bdev->layout[reg];
 421
 422         return bdev->regs + r.base_offset +
 423                 r.pipe_mult * pipe +
 424                 r.evnt_mult * pipe +
 425                 r.ee_mult * bdev->ee;
 426 }
 427
 428 /**
 429  * bam_reset_channel - Reset individual BAM DMA channel
 430  * @bchan: bam channel
 431  *
 432  * This function resets a specific BAM channel
 433  */
 434 static void bam_reset_channel(struct bam_chan *bchan)
 435 {
 436         struct bam_device *bdev = bchan->bdev;
 437
 438         lockdep_assert_held(&bchan->vc.lock);
 439
 440         /* reset channel */
 441         writel_relaxed(1, bam_addr(bdev, bchan->id, BAM_P_RST));
 442         writel_relaxed(0, bam_addr(bdev, bchan->id, BAM_P_RST));
 443
 444         /* don't allow cpu to reorder BAM register accesses done after this */
 445         wmb();
 446
 447         /* make sure hw is initialized when channel is used the first time  */
 448         bchan->initialized = 0;
 449 }
 450
 451 /**
 452  * bam_chan_init_hw - Initialize channel hardware
 453  * @bchan: bam channel
 454  *
 455  * This function resets and initializes the BAM channel
 456  */
 457 static void bam_chan_init_hw(struct bam_chan *bchan,
 458         enum dma_transfer_direction dir)
 459 {
 460         struct bam_device *bdev = bchan->bdev;
 461         u32 val;
 462
 463         /* Reset the channel to clear internal state of the FIFO */
 464         bam_reset_channel(bchan);
 465
 466         /*
 467          * write out 8 byte aligned address.  We have enough space for this
 468          * because we allocated 1 more descriptor (8 bytes) than we can use
 469          */
 470         writel_relaxed(ALIGN(bchan->fifo_phys, sizeof(struct bam_desc_hw)),
 471                         bam_addr(bdev, bchan->id, BAM_P_DESC_FIFO_ADDR));
 472         writel_relaxed(BAM_FIFO_SIZE,
 473                         bam_addr(bdev, bchan->id, BAM_P_FIFO_SIZES));
 474
 475         /* enable the per pipe interrupts, enable EOT, ERR, and INT irqs */
 476         writel_relaxed(P_DEFAULT_IRQS_EN,
 477                         bam_addr(bdev, bchan->id, BAM_P_IRQ_EN));
 478
 479         /* unmask the specific pipe and EE combo */
 480         val = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
 481         val |= BIT(bchan->id);
 482         writel_relaxed(val, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
 483
 484         /* don't allow cpu to reorder the channel enable done below */
 485         wmb();
 486
 487         /* set fixed direction and mode, then enable channel */
 488         val = P_EN | P_SYS_MODE;
 489         if (dir == DMA_DEV_TO_MEM)
 490                 val |= P_DIRECTION;
 491
 492         writel_relaxed(val, bam_addr(bdev, bchan->id, BAM_P_CTRL));
 493
 494         bchan->initialized = 1;
 495
 496         /* init FIFO pointers */
 497         bchan->head = 0;
 498         bchan->tail = 0;
 499 }
 500
 501 /**
 502  * bam_alloc_chan - Allocate channel resources for DMA channel.
 503  * @chan: specified channel
 504  *
 505  * This function allocates the FIFO descriptor memory
 506  */
 507 static int bam_alloc_chan(struct dma_chan *chan)
 508 {
 509         struct bam_chan *bchan = to_bam_chan(chan);
 510         struct bam_device *bdev = bchan->bdev;
 511
 512         if (bchan->fifo_virt)
 513                 return 0;
 514
 515         /* allocate FIFO descriptor space, but only if necessary */
 516         bchan->fifo_virt = dma_alloc_wc(bdev->dev, BAM_DESC_FIFO_SIZE,
 517                                         &bchan->fifo_phys, GFP_KERNEL);
 518
 519         if (!bchan->fifo_virt) {
 520                 dev_err(bdev->dev, "Failed to allocate desc fifo\n");
 521                 return -ENOMEM;
 522         }
 523
 524         return 0;
 525 }
 526
 527 static int bam_pm_runtime_get_sync(struct device *dev)
 528 {
 529         if (pm_runtime_enabled(dev))
 530                 return pm_runtime_get_sync(dev);
 531
 532         return 0;
 533 }
 534
 535 /**
 536  * bam_free_chan - Frees dma resources associated with specific channel
 537  * @chan: specified channel
 538  *
 539  * Free the allocated fifo descriptor memory and channel resources
 540  *
 541  */
 542 static void bam_free_chan(struct dma_chan *chan)
 543 {
 544         struct bam_chan *bchan = to_bam_chan(chan);
 545         struct bam_device *bdev = bchan->bdev;
 546         u32 val;
 547         unsigned long flags;
 548         int ret;
 549
 550         ret = bam_pm_runtime_get_sync(bdev->dev);
 551         if (ret < 0)
 552                 return;
 553
 554         vchan_free_chan_resources(to_virt_chan(chan));
 555
 556         if (!list_empty(&bchan->desc_list)) {
 557                 dev_err(bchan->bdev->dev, "Cannot free busy channel\n");
 558                 goto err;
 559         }
 560
 561         spin_lock_irqsave(&bchan->vc.lock, flags);
 562         bam_reset_channel(bchan);
 563         spin_unlock_irqrestore(&bchan->vc.lock, flags);
 564
 565         dma_free_wc(bdev->dev, BAM_DESC_FIFO_SIZE, bchan->fifo_virt,
 566                     bchan->fifo_phys);
 567         bchan->fifo_virt = NULL;
 568
 569         /* mask irq for pipe/channel */
 570         val = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
 571         val &= ~BIT(bchan->id);
 572         writel_relaxed(val, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
 573
 574         /* disable irq */
 575         writel_relaxed(0, bam_addr(bdev, bchan->id, BAM_P_IRQ_EN));
 576
 577 err:
 578         pm_runtime_mark_last_busy(bdev->dev);
 579         pm_runtime_put_autosuspend(bdev->dev);
 580 }
 581
 582 /**
 583  * bam_slave_config - set slave configuration for channel
 584  * @chan: dma channel
 585  * @cfg: slave configuration
 586  *
 587  * Sets slave configuration for channel
 588  *
 589  */
 590 static int bam_slave_config(struct dma_chan *chan,
 591                             struct dma_slave_config *cfg)
 592 {
 593         struct bam_chan *bchan = to_bam_chan(chan);
 594         unsigned long flag;
 595
 596         spin_lock_irqsave(&bchan->vc.lock, flag);
 597         memcpy(&bchan->slave, cfg, sizeof(*cfg));
 598         bchan->reconfigure = 1;
 599         spin_unlock_irqrestore(&bchan->vc.lock, flag);
 600
 601         return 0;
 602 }
 603
 604 /**
 605  * bam_prep_slave_sg - Prep slave sg transaction
 606  *
 607  * @chan: dma channel
 608  * @sgl: scatter gather list
 609  * @sg_len: length of sg
 610  * @direction: DMA transfer direction
 611  * @flags: DMA flags
 612  * @context: transfer context (unused)
 613  */
 614 static struct dma_async_tx_descriptor *bam_prep_slave_sg(struct dma_chan *chan,
 615         struct scatterlist *sgl, unsigned int sg_len,
 616         enum dma_transfer_direction direction, unsigned long flags,
 617         void *context)
 618 {
 619         struct bam_chan *bchan = to_bam_chan(chan);
 620         struct bam_device *bdev = bchan->bdev;
 621         struct bam_async_desc *async_desc;
 622         struct scatterlist *sg;
 623         u32 i;
 624         struct bam_desc_hw *desc;
 625         unsigned int num_alloc = 0;
 626
 627
 628         if (!is_slave_direction(direction)) {
 629                 dev_err(bdev->dev, "invalid dma direction\n");
 630                 return NULL;
 631         }
 632
 633         /* calculate number of required entries */
 634         for_each_sg(sgl, sg, sg_len, i)
 635                 num_alloc += DIV_ROUND_UP(sg_dma_len(sg), BAM_FIFO_SIZE);
 636
 637         /* allocate enough room to accomodate the number of entries */
 638         async_desc = kzalloc(sizeof(*async_desc) +
 639                         (num_alloc * sizeof(struct bam_desc_hw)), GFP_NOWAIT);
 640
 641         if (!async_desc)
 642                 goto err_out;
 643
 644         if (flags & DMA_PREP_FENCE)
 645                 async_desc->flags |= DESC_FLAG_NWD;
 646
 647         if (flags & DMA_PREP_INTERRUPT)
 648                 async_desc->flags |= DESC_FLAG_EOT;
 649
 650         async_desc->num_desc = num_alloc;
 651         async_desc->curr_desc = async_desc->desc;
 652         async_desc->dir = direction;
 653
 654         /* fill in temporary descriptors */
 655         desc = async_desc->desc;
 656         for_each_sg(sgl, sg, sg_len, i) {
 657                 unsigned int remainder = sg_dma_len(sg);
 658                 unsigned int curr_offset = 0;
 659
 660                 do {
 661                         if (flags & DMA_PREP_CMD)
 662                                 desc->flags |= cpu_to_le16(DESC_FLAG_CMD);
 663
 664                         desc->addr = cpu_to_le32(sg_dma_address(sg) +
 665                                                  curr_offset);
 666
 667                         if (remainder > BAM_FIFO_SIZE) {
 668                                 desc->size = cpu_to_le16(BAM_FIFO_SIZE);
 669                                 remainder -= BAM_FIFO_SIZE;
 670                                 curr_offset += BAM_FIFO_SIZE;
 671                         } else {
 672                                 desc->size = cpu_to_le16(remainder);
 673                                 remainder = 0;
 674                         }
 675
 676                         async_desc->length += desc->size;
 677                         desc++;
 678                 } while (remainder > 0);
 679         }
 680
 681         return vchan_tx_prep(&bchan->vc, &async_desc->vd, flags);
 682
 683 err_out:
 684         kfree(async_desc);
 685         return NULL;
 686 }
 687
 688 /**
 689  * bam_dma_terminate_all - terminate all transactions on a channel
 690  * @bchan: bam dma channel
 691  *
 692  * Dequeues and frees all transactions
 693  * No callbacks are done
 694  *
 695  */
 696 static int bam_dma_terminate_all(struct dma_chan *chan)
 697 {
 698         struct bam_chan *bchan = to_bam_chan(chan);
 699         struct bam_async_desc *async_desc, *tmp;
 700         unsigned long flag;
 701         LIST_HEAD(head);
 702
 703         /* remove all transactions, including active transaction */
 704         spin_lock_irqsave(&bchan->vc.lock, flag);
 705         list_for_each_entry_safe(async_desc, tmp,
 706                                  &bchan->desc_list, desc_node) {
 707                 list_add(&async_desc->vd.node, &bchan->vc.desc_issued);
 708                 list_del(&async_desc->desc_node);
 709         }
 710
 711         vchan_get_all_descriptors(&bchan->vc, &head);
 712         spin_unlock_irqrestore(&bchan->vc.lock, flag);
 713
 714         vchan_dma_desc_free_list(&bchan->vc, &head);
 715
 716         return 0;
 717 }
 718
 719 /**
 720  * bam_pause - Pause DMA channel
 721  * @chan: dma channel
 722  *
 723  */
 724 static int bam_pause(struct dma_chan *chan)
 725 {
 726         struct bam_chan *bchan = to_bam_chan(chan);
 727         struct bam_device *bdev = bchan->bdev;
 728         unsigned long flag;
 729         int ret;
 730
 731         ret = bam_pm_runtime_get_sync(bdev->dev);
 732         if (ret < 0)
 733                 return ret;
 734
 735         spin_lock_irqsave(&bchan->vc.lock, flag);
 736         writel_relaxed(1, bam_addr(bdev, bchan->id, BAM_P_HALT));
 737         bchan->paused = 1;
 738         spin_unlock_irqrestore(&bchan->vc.lock, flag);
 739         pm_runtime_mark_last_busy(bdev->dev);
 740         pm_runtime_put_autosuspend(bdev->dev);
 741
 742         return 0;
 743 }
 744
 745 /**
 746  * bam_resume - Resume DMA channel operations
 747  * @chan: dma channel
 748  *
 749  */
 750 static int bam_resume(struct dma_chan *chan)
 751 {
 752         struct bam_chan *bchan = to_bam_chan(chan);
 753         struct bam_device *bdev = bchan->bdev;
 754         unsigned long flag;
 755         int ret;
 756
 757         ret = bam_pm_runtime_get_sync(bdev->dev);
 758         if (ret < 0)
 759                 return ret;
 760
 761         spin_lock_irqsave(&bchan->vc.lock, flag);
 762         writel_relaxed(0, bam_addr(bdev, bchan->id, BAM_P_HALT));
 763         bchan->paused = 0;
 764         spin_unlock_irqrestore(&bchan->vc.lock, flag);
 765         pm_runtime_mark_last_busy(bdev->dev);
 766         pm_runtime_put_autosuspend(bdev->dev);
 767
 768         return 0;
 769 }
 770
 771 /**
 772  * process_channel_irqs - processes the channel interrupts
 773  * @bdev: bam controller
 774  *
 775  * This function processes the channel interrupts
 776  *
 777  */
 778 static u32 process_channel_irqs(struct bam_device *bdev)
 779 {
 780         u32 i, srcs, pipe_stts, offset, avail;
 781         unsigned long flags;
 782         struct bam_async_desc *async_desc, *tmp;
 783
 784         srcs = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_SRCS_EE));
 785
 786         /* return early if no pipe/channel interrupts are present */
 787         if (!(srcs & P_IRQ))
 788                 return srcs;
 789
 790         for (i = 0; i < bdev->num_channels; i++) {
 791                 struct bam_chan *bchan = &bdev->channels[i];
 792
 793                 if (!(srcs & BIT(i)))
 794                         continue;
 795
 796                 /* clear pipe irq */
 797                 pipe_stts = readl_relaxed(bam_addr(bdev, i, BAM_P_IRQ_STTS));
 798
 799                 writel_relaxed(pipe_stts, bam_addr(bdev, i, BAM_P_IRQ_CLR));
 800
 801                 spin_lock_irqsave(&bchan->vc.lock, flags);
 802
 803                 offset = readl_relaxed(bam_addr(bdev, i, BAM_P_SW_OFSTS)) &
 804                                        P_SW_OFSTS_MASK;
 805                 offset /= sizeof(struct bam_desc_hw);
 806
 807                 /* Number of bytes available to read */
 808                 avail = CIRC_CNT(offset, bchan->head, MAX_DESCRIPTORS + 1);
 809
 810                 list_for_each_entry_safe(async_desc, tmp,
 811                                          &bchan->desc_list, desc_node) {
 812                         /* Not enough data to read */
 813                         if (avail < async_desc->xfer_len)
 814                                 break;
 815
 816                         /* manage FIFO */
 817                         bchan->head += async_desc->xfer_len;
 818                         bchan->head %= MAX_DESCRIPTORS;
 819
 820                         async_desc->num_desc -= async_desc->xfer_len;
 821                         async_desc->curr_desc += async_desc->xfer_len;
 822                         avail -= async_desc->xfer_len;
 823
 824                         /*
 825                          * if complete, process cookie. Otherwise
 826                          * push back to front of desc_issued so that
 827                          * it gets restarted by the tasklet
 828                          */
 829                         if (!async_desc->num_desc) {
 830                                 vchan_cookie_complete(&async_desc->vd);
 831                         } else {
 832                                 list_add(&async_desc->vd.node,
 833                                          &bchan->vc.desc_issued);
 834                         }
 835                         list_del(&async_desc->desc_node);
 836                 }
 837
 838                 spin_unlock_irqrestore(&bchan->vc.lock, flags);
 839         }
 840
 841         return srcs;
 842 }
 843
 844 /**
 845  * bam_dma_irq - irq handler for bam controller
 846  * @irq: IRQ of interrupt
 847  * @data: callback data
 848  *
 849  * IRQ handler for the bam controller
 850  */
 851 static irqreturn_t bam_dma_irq(int irq, void *data)
 852 {
 853         struct bam_device *bdev = data;
 854         u32 clr_mask = 0, srcs = 0;
 855         int ret;
 856
 857         srcs |= process_channel_irqs(bdev);
 858
 859         /* kick off tasklet to start next dma transfer */
 860         if (srcs & P_IRQ)
 861                 tasklet_schedule(&bdev->task);
 862
 863         ret = bam_pm_runtime_get_sync(bdev->dev);
 864         if (ret < 0)
 865                 return ret;
 866
 867         if (srcs & BAM_IRQ) {
 868                 clr_mask = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_STTS));
 869
 870                 /*
 871                  * don't allow reorder of the various accesses to the BAM
 872                  * registers
 873                  */
 874                 mb();
 875
 876                 writel_relaxed(clr_mask, bam_addr(bdev, 0, BAM_IRQ_CLR));
 877         }
 878
 879         pm_runtime_mark_last_busy(bdev->dev);
 880         pm_runtime_put_autosuspend(bdev->dev);
 881
 882         return IRQ_HANDLED;
 883 }
 884
 885 /**
 886  * bam_tx_status - returns status of transaction
 887  * @chan: dma channel
 888  * @cookie: transaction cookie
 889  * @txstate: DMA transaction state
 890  *
 891  * Return status of dma transaction
 892  */
 893 static enum dma_status bam_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 894                 struct dma_tx_state *txstate)
 895 {
 896         struct bam_chan *bchan = to_bam_chan(chan);
 897         struct bam_async_desc *async_desc;
 898         struct virt_dma_desc *vd;
 899         int ret;
 900         size_t residue = 0;
 901         unsigned int i;
 902         unsigned long flags;
 903
 904         ret = dma_cookie_status(chan, cookie, txstate);
 905         if (ret == DMA_COMPLETE)
 906                 return ret;
 907
 908         if (!txstate)
 909                 return bchan->paused ? DMA_PAUSED : ret;
 910
 911         spin_lock_irqsave(&bchan->vc.lock, flags);
 912         vd = vchan_find_desc(&bchan->vc, cookie);
 913         if (vd) {
 914                 residue = container_of(vd, struct bam_async_desc, vd)->length;
 915         } else {
 916                 list_for_each_entry(async_desc, &bchan->desc_list, desc_node) {
 917                         if (async_desc->vd.tx.cookie != cookie)
 918                                 continue;
 919
 920                         for (i = 0; i < async_desc->num_desc; i++)
 921                                 residue += async_desc->curr_desc[i].size;
 922                 }
 923         }
 924
 925         spin_unlock_irqrestore(&bchan->vc.lock, flags);
 926
 927         dma_set_residue(txstate, residue);
 928
 929         if (ret == DMA_IN_PROGRESS && bchan->paused)
 930                 ret = DMA_PAUSED;
 931
 932         return ret;
 933 }
 934
 935 /**
 936  * bam_apply_new_config
 937  * @bchan: bam dma channel
 938  * @dir: DMA direction
 939  */
 940 static void bam_apply_new_config(struct bam_chan *bchan,
 941         enum dma_transfer_direction dir)
 942 {
 943         struct bam_device *bdev = bchan->bdev;
 944         u32 maxburst;
 945
 946         if (!bdev->controlled_remotely) {
 947                 if (dir == DMA_DEV_TO_MEM)
 948                         maxburst = bchan->slave.src_maxburst;
 949                 else
 950                         maxburst = bchan->slave.dst_maxburst;
 951
 952                 writel_relaxed(maxburst,
 953                                bam_addr(bdev, 0, BAM_DESC_CNT_TRSHLD));
 954         }
 955
 956         bchan->reconfigure = 0;
 957 }
 958
 959 /**
 960  * bam_start_dma - start next transaction
 961  * @bchan - bam dma channel
 962  */
 963 static void bam_start_dma(struct bam_chan *bchan)
 964 {
 965         struct virt_dma_desc *vd = vchan_next_desc(&bchan->vc);
 966         struct bam_device *bdev = bchan->bdev;
 967         struct bam_async_desc *async_desc = NULL;
 968         struct bam_desc_hw *desc;
 969         struct bam_desc_hw *fifo = PTR_ALIGN(bchan->fifo_virt,
 970                                         sizeof(struct bam_desc_hw));
 971         int ret;
 972         unsigned int avail;
 973         struct dmaengine_desc_callback cb;
 974
 975         lockdep_assert_held(&bchan->vc.lock);
 976
 977         if (!vd)
 978                 return;
 979
 980         ret = bam_pm_runtime_get_sync(bdev->dev);
 981         if (ret < 0)
 982                 return;
 983
 984         while (vd && !IS_BUSY(bchan)) {
 985                 list_del(&vd->node);
 986
 987                 async_desc = container_of(vd, struct bam_async_desc, vd);
 988
 989                 /* on first use, initialize the channel hardware */
 990                 if (!bchan->initialized)
 991                         bam_chan_init_hw(bchan, async_desc->dir);
 992
 993                 /* apply new slave config changes, if necessary */
 994                 if (bchan->reconfigure)
 995                         bam_apply_new_config(bchan, async_desc->dir);
 996
 997                 desc = async_desc->curr_desc;
 998                 avail = CIRC_SPACE(bchan->tail, bchan->head,
 999                                    MAX_DESCRIPTORS + 1);
1000
1001                 if (async_desc->num_desc > avail)
1002                         async_desc->xfer_len = avail;
1003                 else
1004                         async_desc->xfer_len = async_desc->num_desc;
1005
1006                 /* set any special flags on the last descriptor */
1007                 if (async_desc->num_desc == async_desc->xfer_len)
1008                         desc[async_desc->xfer_len - 1].flags |=
1009                                                 cpu_to_le16(async_desc->flags);
1010
1011                 vd = vchan_next_desc(&bchan->vc);
1012
1013                 dmaengine_desc_get_callback(&async_desc->vd.tx, &cb);
1014
1015                 /*
1016                  * An interrupt is generated at this desc, if
1017                  *  - FIFO is FULL.
1018                  *  - No more descriptors to add.
1019                  *  - If a callback completion was requested for this DESC,
1020                  *     In this case, BAM will deliver the completion callback
1021                  *     for this desc and continue processing the next desc.
1022                  */
1023                 if (((avail <= async_desc->xfer_len) || !vd ||
1024                      dmaengine_desc_callback_valid(&cb)) &&
1025                     !(async_desc->flags & DESC_FLAG_EOT))
1026                         desc[async_desc->xfer_len - 1].flags |=
1027                                 cpu_to_le16(DESC_FLAG_INT);
1028
1029                 if (bchan->tail + async_desc->xfer_len > MAX_DESCRIPTORS) {
1030                         u32 partial = MAX_DESCRIPTORS - bchan->tail;
1031
1032                         memcpy(&fifo[bchan->tail], desc,
1033                                partial * sizeof(struct bam_desc_hw));
1034                         memcpy(fifo, &desc[partial],
1035                                (async_desc->xfer_len - partial) *
1036                                 sizeof(struct bam_desc_hw));
1037                 } else {
1038                         memcpy(&fifo[bchan->tail], desc,
1039                                async_desc->xfer_len *
1040                                sizeof(struct bam_desc_hw));
1041                 }
1042
1043                 bchan->tail += async_desc->xfer_len;
1044                 bchan->tail %= MAX_DESCRIPTORS;
1045                 list_add_tail(&async_desc->desc_node, &bchan->desc_list);
1046         }
1047
1048         /* ensure descriptor writes and dma start not reordered */
1049         wmb();
1050         writel_relaxed(bchan->tail * sizeof(struct bam_desc_hw),
1051                         bam_addr(bdev, bchan->id, BAM_P_EVNT_REG));
1052
1053         pm_runtime_mark_last_busy(bdev->dev);
1054         pm_runtime_put_autosuspend(bdev->dev);
1055 }
1056
1057 /**
1058  * dma_tasklet - DMA IRQ tasklet
1059  * @data: tasklet argument (bam controller structure)
1060  *
1061  * Sets up next DMA operation and then processes all completed transactions
1062  */
1063 static void dma_tasklet(unsigned long data)
1064 {
1065         struct bam_device *bdev = (struct bam_device *)data;
1066         struct bam_chan *bchan;
1067         unsigned long flags;
1068         unsigned int i;
1069
1070         /* go through the channels and kick off transactions */
1071         for (i = 0; i < bdev->num_channels; i++) {
1072                 bchan = &bdev->channels[i];
1073                 spin_lock_irqsave(&bchan->vc.lock, flags);
1074
1075                 if (!list_empty(&bchan->vc.desc_issued) && !IS_BUSY(bchan))
1076                         bam_start_dma(bchan);
1077                 spin_unlock_irqrestore(&bchan->vc.lock, flags);
1078         }
1079
1080 }
1081
1082 /**
1083  * bam_issue_pending - starts pending transactions
1084  * @chan: dma channel
1085  *
1086  * Calls tasklet directly which in turn starts any pending transactions
1087  */
1088 static void bam_issue_pending(struct dma_chan *chan)
1089 {
1090         struct bam_chan *bchan = to_bam_chan(chan);
1091         unsigned long flags;
1092
1093         spin_lock_irqsave(&bchan->vc.lock, flags);
1094
1095         /* if work pending and idle, start a transaction */
1096         if (vchan_issue_pending(&bchan->vc) && !IS_BUSY(bchan))
1097                 bam_start_dma(bchan);
1098
1099         spin_unlock_irqrestore(&bchan->vc.lock, flags);
1100 }
1101
1102 /**
1103  * bam_dma_free_desc - free descriptor memory
1104  * @vd: virtual descriptor
1105  *
1106  */
1107 static void bam_dma_free_desc(struct virt_dma_desc *vd)
1108 {
1109         struct bam_async_desc *async_desc = container_of(vd,
1110                         struct bam_async_desc, vd);
1111
1112         kfree(async_desc);
1113 }
1114
1115 static struct dma_chan *bam_dma_xlate(struct of_phandle_args *dma_spec,
1116                 struct of_dma *of)
1117 {
1118         struct bam_device *bdev = container_of(of->of_dma_data,
1119                                         struct bam_device, common);
1120         unsigned int request;
1121
1122         if (dma_spec->args_count != 1)
1123                 return NULL;
1124
1125         request = dma_spec->args[0];
1126         if (request >= bdev->num_channels)
1127                 return NULL;
1128
1129         return dma_get_slave_channel(&(bdev->channels[request].vc.chan));
1130 }
1131
1132 /**
1133  * bam_init
1134  * @bdev: bam device
1135  *
1136  * Initialization helper for global bam registers
1137  */
1138 static int bam_init(struct bam_device *bdev)
1139 {
1140         u32 val;
1141
1142         /* read revision and configuration information */
1143         if (!bdev->num_ees) {
1144                 val = readl_relaxed(bam_addr(bdev, 0, BAM_REVISION));
1145                 bdev->num_ees = (val >> NUM_EES_SHIFT) & NUM_EES_MASK;
1146         }
1147
1148         /* check that configured EE is within range */
1149         if (bdev->ee >= bdev->num_ees)
1150                 return -EINVAL;
1151
1152         if (!bdev->num_channels) {
1153                 val = readl_relaxed(bam_addr(bdev, 0, BAM_NUM_PIPES));
1154                 bdev->num_channels = val & BAM_NUM_PIPES_MASK;
1155         }
1156
1157         if (bdev->controlled_remotely)
1158                 return 0;
1159
1160         /* s/w reset bam */
1161         /* after reset all pipes are disabled and idle */
1162         val = readl_relaxed(bam_addr(bdev, 0, BAM_CTRL));
1163         val |= BAM_SW_RST;
1164         writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL));
1165         val &= ~BAM_SW_RST;
1166         writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL));
1167
1168         /* make sure previous stores are visible before enabling BAM */
1169         wmb();
1170
1171         /* enable bam */
1172         val |= BAM_EN;
1173         writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL));
1174
1175         /* set descriptor threshhold, start with 4 bytes */
1176         writel_relaxed(DEFAULT_CNT_THRSHLD,
1177                         bam_addr(bdev, 0, BAM_DESC_CNT_TRSHLD));
1178
1179         /* Enable default set of h/w workarounds, ie all except BAM_FULL_PIPE */
1180         writel_relaxed(BAM_CNFG_BITS_DEFAULT, bam_addr(bdev, 0, BAM_CNFG_BITS));
1181
1182         /* enable irqs for errors */
1183         writel_relaxed(BAM_ERROR_EN | BAM_HRESP_ERR_EN,
1184                         bam_addr(bdev, 0, BAM_IRQ_EN));
1185
1186         /* unmask global bam interrupt */
1187         writel_relaxed(BAM_IRQ_MSK, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
1188
1189         return 0;
1190 }
1191
1192 static void bam_channel_init(struct bam_device *bdev, struct bam_chan *bchan,
1193         u32 index)
1194 {
1195         bchan->id = index;
1196         bchan->bdev = bdev;
1197
1198         vchan_init(&bchan->vc, &bdev->common);
1199         bchan->vc.desc_free = bam_dma_free_desc;
1200         INIT_LIST_HEAD(&bchan->desc_list);
1201 }
1202
1203 static const struct of_device_id bam_of_match[] = {
1204         { .compatible = "qcom,bam-v1.3.0", .data = &bam_v1_3_reg_info },
1205         { .compatible = "qcom,bam-v1.4.0", .data = &bam_v1_4_reg_info },
1206         { .compatible = "qcom,bam-v1.7.0", .data = &bam_v1_7_reg_info },
1207         {}
1208 };
1209
1210 MODULE_DEVICE_TABLE(of, bam_of_match);
1211
1212 static int bam_dma_probe(struct platform_device *pdev)
1213 {
1214         struct bam_device *bdev;
1215         const struct of_device_id *match;
1216         struct resource *iores;
1217         int ret, i;
1218
1219         bdev = devm_kzalloc(&pdev->dev, sizeof(*bdev), GFP_KERNEL);
1220         if (!bdev)
1221                 return -ENOMEM;
1222
1223         bdev->dev = &pdev->dev;
1224
1225         match = of_match_node(bam_of_match, pdev->dev.of_node);
1226         if (!match) {
1227                 dev_err(&pdev->dev, "Unsupported BAM module\n");
1228                 return -ENODEV;
1229         }
1230
1231         bdev->layout = match->data;
1232
1233         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1234         bdev->regs = devm_ioremap_resource(&pdev->dev, iores);
1235         if (IS_ERR(bdev->regs))
1236                 return PTR_ERR(bdev->regs);
1237
1238         bdev->irq = platform_get_irq(pdev, 0);
1239         if (bdev->irq < 0)
1240                 return bdev->irq;
1241
1242         ret = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &bdev->ee);
1243         if (ret) {
1244                 dev_err(bdev->dev, "Execution environment unspecified\n");
1245                 return ret;
1246         }
1247
1248         bdev->controlled_remotely = of_property_read_bool(pdev->dev.of_node,
1249                                                 "qcom,controlled-remotely");
1250
1251         if (bdev->controlled_remotely) {
1252                 ret = of_property_read_u32(pdev->dev.of_node, "num-channels",
1253                                            &bdev->num_channels);
1254                 if (ret)
1255                         dev_err(bdev->dev, "num-channels unspecified in dt\n");
1256
1257                 ret = of_property_read_u32(pdev->dev.of_node, "qcom,num-ees",
1258                                            &bdev->num_ees);
1259                 if (ret)
1260                         dev_err(bdev->dev, "num-ees unspecified in dt\n");
1261         }
1262
1263         bdev->bamclk = devm_clk_get(bdev->dev, "bam_clk");
1264         if (IS_ERR(bdev->bamclk)) {
1265                 if (!bdev->controlled_remotely)
1266                         return PTR_ERR(bdev->bamclk);
1267
1268                 bdev->bamclk = NULL;
1269         }
1270
1271         ret = clk_prepare_enable(bdev->bamclk);
1272         if (ret) {
1273                 dev_err(bdev->dev, "failed to prepare/enable clock\n");
1274                 return ret;
1275         }
1276
1277         ret = bam_init(bdev);
1278         if (ret)
1279                 goto err_disable_clk;
1280
1281         tasklet_init(&bdev->task, dma_tasklet, (unsigned long)bdev);
1282
1283         bdev->channels = devm_kcalloc(bdev->dev, bdev->num_channels,
1284                                 sizeof(*bdev->channels), GFP_KERNEL);
1285
1286         if (!bdev->channels) {
1287                 ret = -ENOMEM;
1288                 goto err_tasklet_kill;
1289         }
1290
1291         /* allocate and initialize channels */
1292         INIT_LIST_HEAD(&bdev->common.channels);
1293
1294         for (i = 0; i < bdev->num_channels; i++)
1295                 bam_channel_init(bdev, &bdev->channels[i], i);
1296
1297         ret = devm_request_irq(bdev->dev, bdev->irq, bam_dma_irq,
1298                         IRQF_TRIGGER_HIGH, "bam_dma", bdev);
1299         if (ret)
1300                 goto err_bam_channel_exit;
1301
1302         /* set max dma segment size */
1303         bdev->common.dev = bdev->dev;
1304         bdev->common.dev->dma_parms = &bdev->dma_parms;
1305         ret = dma_set_max_seg_size(bdev->common.dev, BAM_FIFO_SIZE);
1306         if (ret) {
1307                 dev_err(bdev->dev, "cannot set maximum segment size\n");
1308                 goto err_bam_channel_exit;
1309         }
1310
1311         platform_set_drvdata(pdev, bdev);
1312
1313         /* set capabilities */
1314         dma_cap_zero(bdev->common.cap_mask);
1315         dma_cap_set(DMA_SLAVE, bdev->common.cap_mask);
1316
1317         /* initialize dmaengine apis */
1318         bdev->common.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1319         bdev->common.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
1320         bdev->common.src_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES;
1321         bdev->common.dst_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES;
1322         bdev->common.device_alloc_chan_resources = bam_alloc_chan;
1323         bdev->common.device_free_chan_resources = bam_free_chan;
1324         bdev->common.device_prep_slave_sg = bam_prep_slave_sg;
1325         bdev->common.device_config = bam_slave_config;
1326         bdev->common.device_pause = bam_pause;
1327         bdev->common.device_resume = bam_resume;
1328         bdev->common.device_terminate_all = bam_dma_terminate_all;
1329         bdev->common.device_issue_pending = bam_issue_pending;
1330         bdev->common.device_tx_status = bam_tx_status;
1331         bdev->common.dev = bdev->dev;
1332
1333         ret = dma_async_device_register(&bdev->common);
1334         if (ret) {
1335                 dev_err(bdev->dev, "failed to register dma async device\n");
1336                 goto err_bam_channel_exit;
1337         }
1338
1339         ret = of_dma_controller_register(pdev->dev.of_node, bam_dma_xlate,
1340                                         &bdev->common);
1341         if (ret)
1342                 goto err_unregister_dma;
1343
1344         if (bdev->controlled_remotely) {
1345                 pm_runtime_disable(&pdev->dev);
1346                 return 0;
1347         }
1348
1349         pm_runtime_irq_safe(&pdev->dev);
1350         pm_runtime_set_autosuspend_delay(&pdev->dev, BAM_DMA_AUTOSUSPEND_DELAY);
1351         pm_runtime_use_autosuspend(&pdev->dev);
1352         pm_runtime_mark_last_busy(&pdev->dev);
1353         pm_runtime_set_active(&pdev->dev);
1354         pm_runtime_enable(&pdev->dev);
1355
1356         return 0;
1357
1358 err_unregister_dma:
1359         dma_async_device_unregister(&bdev->common);
1360 err_bam_channel_exit:
1361         for (i = 0; i < bdev->num_channels; i++)
1362                 tasklet_kill(&bdev->channels[i].vc.task);
1363 err_tasklet_kill:
1364         tasklet_kill(&bdev->task);
1365 err_disable_clk:
1366         clk_disable_unprepare(bdev->bamclk);
1367
1368         return ret;
1369 }
1370
1371 static int bam_dma_remove(struct platform_device *pdev)
1372 {
1373         struct bam_device *bdev = platform_get_drvdata(pdev);
1374         u32 i;
1375
1376         pm_runtime_force_suspend(&pdev->dev);
1377
1378         of_dma_controller_free(pdev->dev.of_node);
1379         dma_async_device_unregister(&bdev->common);
1380
1381         /* mask all interrupts for this execution environment */
1382         writel_relaxed(0, bam_addr(bdev, 0,  BAM_IRQ_SRCS_MSK_EE));
1383
1384         devm_free_irq(bdev->dev, bdev->irq, bdev);
1385
1386         for (i = 0; i < bdev->num_channels; i++) {
1387                 bam_dma_terminate_all(&bdev->channels[i].vc.chan);
1388                 tasklet_kill(&bdev->channels[i].vc.task);
1389
1390                 if (!bdev->channels[i].fifo_virt)
1391                         continue;
1392
1393                 dma_free_wc(bdev->dev, BAM_DESC_FIFO_SIZE,
1394                             bdev->channels[i].fifo_virt,
1395                             bdev->channels[i].fifo_phys);
1396         }
1397
1398         tasklet_kill(&bdev->task);
1399
1400         clk_disable_unprepare(bdev->bamclk);
1401
1402         return 0;
1403 }
1404
1405 static int __maybe_unused bam_dma_runtime_suspend(struct device *dev)
1406 {
1407         struct bam_device *bdev = dev_get_drvdata(dev);
1408
1409         clk_disable(bdev->bamclk);
1410
1411         return 0;
1412 }
1413
1414 static int __maybe_unused bam_dma_runtime_resume(struct device *dev)
1415 {
1416         struct bam_device *bdev = dev_get_drvdata(dev);
1417         int ret;
1418
1419         ret = clk_enable(bdev->bamclk);
1420         if (ret < 0) {
1421                 dev_err(dev, "clk_enable failed: %d\n", ret);
1422                 return ret;
1423         }
1424
1425         return 0;
1426 }
1427
1428 static int __maybe_unused bam_dma_suspend(struct device *dev)
1429 {
1430         struct bam_device *bdev = dev_get_drvdata(dev);
1431
1432         if (!bdev->controlled_remotely)
1433                 pm_runtime_force_suspend(dev);
1434
1435         clk_unprepare(bdev->bamclk);
1436
1437         return 0;
1438 }
1439
1440 static int __maybe_unused bam_dma_resume(struct device *dev)
1441 {
1442         struct bam_device *bdev = dev_get_drvdata(dev);
1443         int ret;
1444
1445         ret = clk_prepare(bdev->bamclk);
1446         if (ret)
1447                 return ret;
1448
1449         if (!bdev->controlled_remotely)
1450                 pm_runtime_force_resume(dev);
1451
1452         return 0;
1453 }
1454
1455 static const struct dev_pm_ops bam_dma_pm_ops = {
1456         SET_LATE_SYSTEM_SLEEP_PM_OPS(bam_dma_suspend, bam_dma_resume)
1457         SET_RUNTIME_PM_OPS(bam_dma_runtime_suspend, bam_dma_runtime_resume,
1458                                 NULL)
1459 };
1460
1461 static struct platform_driver bam_dma_driver = {
1462         .probe = bam_dma_probe,
1463         .remove = bam_dma_remove,
1464         .driver = {
1465                 .name = "bam-dma-engine",
1466                 .pm = &bam_dma_pm_ops,
1467                 .of_match_table = bam_of_match,
1468         },
1469 };
1470
1471 module_platform_driver(bam_dma_driver);
1472
1473 MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
1474 MODULE_DESCRIPTION("QCOM BAM DMA engine driver");
1475 MODULE_LICENSE("GPL v2");