Merge tag 'dmaengine-4.18-rc1' of git://git.infradead.org/users/vkoul/slave-dma
[muen/linux.git] / drivers / dma / ti / edma.c
1 /*
2  * TI EDMA DMA engine driver
3  *
4  * Copyright 2012 Texas Instruments
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation version 2.
9  *
10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11  * kind, whether express or implied; without even the implied warranty
12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  */
15
16 #include <linux/dmaengine.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/edma.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/list.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
27 #include <linux/of.h>
28 #include <linux/of_dma.h>
29 #include <linux/of_irq.h>
30 #include <linux/of_address.h>
31 #include <linux/of_device.h>
32 #include <linux/pm_runtime.h>
33
34 #include <linux/platform_data/edma.h>
35
36 #include "../dmaengine.h"
37 #include "../virt-dma.h"
38
39 /* Offsets matching "struct edmacc_param" */
40 #define PARM_OPT                0x00
41 #define PARM_SRC                0x04
42 #define PARM_A_B_CNT            0x08
43 #define PARM_DST                0x0c
44 #define PARM_SRC_DST_BIDX       0x10
45 #define PARM_LINK_BCNTRLD       0x14
46 #define PARM_SRC_DST_CIDX       0x18
47 #define PARM_CCNT               0x1c
48
49 #define PARM_SIZE               0x20
50
51 /* Offsets for EDMA CC global channel registers and their shadows */
52 #define SH_ER                   0x00    /* 64 bits */
53 #define SH_ECR                  0x08    /* 64 bits */
54 #define SH_ESR                  0x10    /* 64 bits */
55 #define SH_CER                  0x18    /* 64 bits */
56 #define SH_EER                  0x20    /* 64 bits */
57 #define SH_EECR                 0x28    /* 64 bits */
58 #define SH_EESR                 0x30    /* 64 bits */
59 #define SH_SER                  0x38    /* 64 bits */
60 #define SH_SECR                 0x40    /* 64 bits */
61 #define SH_IER                  0x50    /* 64 bits */
62 #define SH_IECR                 0x58    /* 64 bits */
63 #define SH_IESR                 0x60    /* 64 bits */
64 #define SH_IPR                  0x68    /* 64 bits */
65 #define SH_ICR                  0x70    /* 64 bits */
66 #define SH_IEVAL                0x78
67 #define SH_QER                  0x80
68 #define SH_QEER                 0x84
69 #define SH_QEECR                0x88
70 #define SH_QEESR                0x8c
71 #define SH_QSER                 0x90
72 #define SH_QSECR                0x94
73 #define SH_SIZE                 0x200
74
75 /* Offsets for EDMA CC global registers */
76 #define EDMA_REV                0x0000
77 #define EDMA_CCCFG              0x0004
78 #define EDMA_QCHMAP             0x0200  /* 8 registers */
79 #define EDMA_DMAQNUM            0x0240  /* 8 registers (4 on OMAP-L1xx) */
80 #define EDMA_QDMAQNUM           0x0260
81 #define EDMA_QUETCMAP           0x0280
82 #define EDMA_QUEPRI             0x0284
83 #define EDMA_EMR                0x0300  /* 64 bits */
84 #define EDMA_EMCR               0x0308  /* 64 bits */
85 #define EDMA_QEMR               0x0310
86 #define EDMA_QEMCR              0x0314
87 #define EDMA_CCERR              0x0318
88 #define EDMA_CCERRCLR           0x031c
89 #define EDMA_EEVAL              0x0320
90 #define EDMA_DRAE               0x0340  /* 4 x 64 bits*/
91 #define EDMA_QRAE               0x0380  /* 4 registers */
92 #define EDMA_QUEEVTENTRY        0x0400  /* 2 x 16 registers */
93 #define EDMA_QSTAT              0x0600  /* 2 registers */
94 #define EDMA_QWMTHRA            0x0620
95 #define EDMA_QWMTHRB            0x0624
96 #define EDMA_CCSTAT             0x0640
97
98 #define EDMA_M                  0x1000  /* global channel registers */
99 #define EDMA_ECR                0x1008
100 #define EDMA_ECRH               0x100C
101 #define EDMA_SHADOW0            0x2000  /* 4 shadow regions */
102 #define EDMA_PARM               0x4000  /* PaRAM entries */
103
104 #define PARM_OFFSET(param_no)   (EDMA_PARM + ((param_no) << 5))
105
106 #define EDMA_DCHMAP             0x0100  /* 64 registers */
107
108 /* CCCFG register */
109 #define GET_NUM_DMACH(x)        (x & 0x7) /* bits 0-2 */
110 #define GET_NUM_QDMACH(x)       ((x & 0x70) >> 4) /* bits 4-6 */
111 #define GET_NUM_PAENTRY(x)      ((x & 0x7000) >> 12) /* bits 12-14 */
112 #define GET_NUM_EVQUE(x)        ((x & 0x70000) >> 16) /* bits 16-18 */
113 #define GET_NUM_REGN(x)         ((x & 0x300000) >> 20) /* bits 20-21 */
114 #define CHMAP_EXIST             BIT(24)
115
116 /* CCSTAT register */
117 #define EDMA_CCSTAT_ACTV        BIT(4)
118
119 /*
120  * Max of 20 segments per channel to conserve PaRAM slots
121  * Also note that MAX_NR_SG should be atleast the no.of periods
122  * that are required for ASoC, otherwise DMA prep calls will
123  * fail. Today davinci-pcm is the only user of this driver and
124  * requires atleast 17 slots, so we setup the default to 20.
125  */
126 #define MAX_NR_SG               20
127 #define EDMA_MAX_SLOTS          MAX_NR_SG
128 #define EDMA_DESCRIPTORS        16
129
130 #define EDMA_CHANNEL_ANY                -1      /* for edma_alloc_channel() */
131 #define EDMA_SLOT_ANY                   -1      /* for edma_alloc_slot() */
132 #define EDMA_CONT_PARAMS_ANY             1001
133 #define EDMA_CONT_PARAMS_FIXED_EXACT     1002
134 #define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
135
136 /* PaRAM slots are laid out like this */
137 struct edmacc_param {
138         u32 opt;
139         u32 src;
140         u32 a_b_cnt;
141         u32 dst;
142         u32 src_dst_bidx;
143         u32 link_bcntrld;
144         u32 src_dst_cidx;
145         u32 ccnt;
146 } __packed;
147
148 /* fields in edmacc_param.opt */
149 #define SAM             BIT(0)
150 #define DAM             BIT(1)
151 #define SYNCDIM         BIT(2)
152 #define STATIC          BIT(3)
153 #define EDMA_FWID       (0x07 << 8)
154 #define TCCMODE         BIT(11)
155 #define EDMA_TCC(t)     ((t) << 12)
156 #define TCINTEN         BIT(20)
157 #define ITCINTEN        BIT(21)
158 #define TCCHEN          BIT(22)
159 #define ITCCHEN         BIT(23)
160
161 struct edma_pset {
162         u32                             len;
163         dma_addr_t                      addr;
164         struct edmacc_param             param;
165 };
166
167 struct edma_desc {
168         struct virt_dma_desc            vdesc;
169         struct list_head                node;
170         enum dma_transfer_direction     direction;
171         int                             cyclic;
172         int                             absync;
173         int                             pset_nr;
174         struct edma_chan                *echan;
175         int                             processed;
176
177         /*
178          * The following 4 elements are used for residue accounting.
179          *
180          * - processed_stat: the number of SG elements we have traversed
181          * so far to cover accounting. This is updated directly to processed
182          * during edma_callback and is always <= processed, because processed
183          * refers to the number of pending transfer (programmed to EDMA
184          * controller), where as processed_stat tracks number of transfers
185          * accounted for so far.
186          *
187          * - residue: The amount of bytes we have left to transfer for this desc
188          *
189          * - residue_stat: The residue in bytes of data we have covered
190          * so far for accounting. This is updated directly to residue
191          * during callbacks to keep it current.
192          *
193          * - sg_len: Tracks the length of the current intermediate transfer,
194          * this is required to update the residue during intermediate transfer
195          * completion callback.
196          */
197         int                             processed_stat;
198         u32                             sg_len;
199         u32                             residue;
200         u32                             residue_stat;
201
202         struct edma_pset                pset[0];
203 };
204
205 struct edma_cc;
206
207 struct edma_tc {
208         struct device_node              *node;
209         u16                             id;
210 };
211
212 struct edma_chan {
213         struct virt_dma_chan            vchan;
214         struct list_head                node;
215         struct edma_desc                *edesc;
216         struct edma_cc                  *ecc;
217         struct edma_tc                  *tc;
218         int                             ch_num;
219         bool                            alloced;
220         bool                            hw_triggered;
221         int                             slot[EDMA_MAX_SLOTS];
222         int                             missed;
223         struct dma_slave_config         cfg;
224 };
225
226 struct edma_cc {
227         struct device                   *dev;
228         struct edma_soc_info            *info;
229         void __iomem                    *base;
230         int                             id;
231         bool                            legacy_mode;
232
233         /* eDMA3 resource information */
234         unsigned                        num_channels;
235         unsigned                        num_qchannels;
236         unsigned                        num_region;
237         unsigned                        num_slots;
238         unsigned                        num_tc;
239         bool                            chmap_exist;
240         enum dma_event_q                default_queue;
241
242         unsigned int                    ccint;
243         unsigned int                    ccerrint;
244
245         /*
246          * The slot_inuse bit for each PaRAM slot is clear unless the slot is
247          * in use by Linux or if it is allocated to be used by DSP.
248          */
249         unsigned long *slot_inuse;
250
251         struct dma_device               dma_slave;
252         struct dma_device               *dma_memcpy;
253         struct edma_chan                *slave_chans;
254         struct edma_tc                  *tc_list;
255         int                             dummy_slot;
256 };
257
258 /* dummy param set used to (re)initialize parameter RAM slots */
259 static const struct edmacc_param dummy_paramset = {
260         .link_bcntrld = 0xffff,
261         .ccnt = 1,
262 };
263
264 #define EDMA_BINDING_LEGACY     0
265 #define EDMA_BINDING_TPCC       1
266 static const u32 edma_binding_type[] = {
267         [EDMA_BINDING_LEGACY] = EDMA_BINDING_LEGACY,
268         [EDMA_BINDING_TPCC] = EDMA_BINDING_TPCC,
269 };
270
271 static const struct of_device_id edma_of_ids[] = {
272         {
273                 .compatible = "ti,edma3",
274                 .data = &edma_binding_type[EDMA_BINDING_LEGACY],
275         },
276         {
277                 .compatible = "ti,edma3-tpcc",
278                 .data = &edma_binding_type[EDMA_BINDING_TPCC],
279         },
280         {}
281 };
282 MODULE_DEVICE_TABLE(of, edma_of_ids);
283
284 static const struct of_device_id edma_tptc_of_ids[] = {
285         { .compatible = "ti,edma3-tptc", },
286         {}
287 };
288 MODULE_DEVICE_TABLE(of, edma_tptc_of_ids);
289
290 static inline unsigned int edma_read(struct edma_cc *ecc, int offset)
291 {
292         return (unsigned int)__raw_readl(ecc->base + offset);
293 }
294
295 static inline void edma_write(struct edma_cc *ecc, int offset, int val)
296 {
297         __raw_writel(val, ecc->base + offset);
298 }
299
300 static inline void edma_modify(struct edma_cc *ecc, int offset, unsigned and,
301                                unsigned or)
302 {
303         unsigned val = edma_read(ecc, offset);
304
305         val &= and;
306         val |= or;
307         edma_write(ecc, offset, val);
308 }
309
310 static inline void edma_and(struct edma_cc *ecc, int offset, unsigned and)
311 {
312         unsigned val = edma_read(ecc, offset);
313
314         val &= and;
315         edma_write(ecc, offset, val);
316 }
317
318 static inline void edma_or(struct edma_cc *ecc, int offset, unsigned or)
319 {
320         unsigned val = edma_read(ecc, offset);
321
322         val |= or;
323         edma_write(ecc, offset, val);
324 }
325
326 static inline unsigned int edma_read_array(struct edma_cc *ecc, int offset,
327                                            int i)
328 {
329         return edma_read(ecc, offset + (i << 2));
330 }
331
332 static inline void edma_write_array(struct edma_cc *ecc, int offset, int i,
333                                     unsigned val)
334 {
335         edma_write(ecc, offset + (i << 2), val);
336 }
337
338 static inline void edma_modify_array(struct edma_cc *ecc, int offset, int i,
339                                      unsigned and, unsigned or)
340 {
341         edma_modify(ecc, offset + (i << 2), and, or);
342 }
343
344 static inline void edma_or_array(struct edma_cc *ecc, int offset, int i,
345                                  unsigned or)
346 {
347         edma_or(ecc, offset + (i << 2), or);
348 }
349
350 static inline void edma_or_array2(struct edma_cc *ecc, int offset, int i, int j,
351                                   unsigned or)
352 {
353         edma_or(ecc, offset + ((i * 2 + j) << 2), or);
354 }
355
356 static inline void edma_write_array2(struct edma_cc *ecc, int offset, int i,
357                                      int j, unsigned val)
358 {
359         edma_write(ecc, offset + ((i * 2 + j) << 2), val);
360 }
361
362 static inline unsigned int edma_shadow0_read(struct edma_cc *ecc, int offset)
363 {
364         return edma_read(ecc, EDMA_SHADOW0 + offset);
365 }
366
367 static inline unsigned int edma_shadow0_read_array(struct edma_cc *ecc,
368                                                    int offset, int i)
369 {
370         return edma_read(ecc, EDMA_SHADOW0 + offset + (i << 2));
371 }
372
373 static inline void edma_shadow0_write(struct edma_cc *ecc, int offset,
374                                       unsigned val)
375 {
376         edma_write(ecc, EDMA_SHADOW0 + offset, val);
377 }
378
379 static inline void edma_shadow0_write_array(struct edma_cc *ecc, int offset,
380                                             int i, unsigned val)
381 {
382         edma_write(ecc, EDMA_SHADOW0 + offset + (i << 2), val);
383 }
384
385 static inline unsigned int edma_param_read(struct edma_cc *ecc, int offset,
386                                            int param_no)
387 {
388         return edma_read(ecc, EDMA_PARM + offset + (param_no << 5));
389 }
390
391 static inline void edma_param_write(struct edma_cc *ecc, int offset,
392                                     int param_no, unsigned val)
393 {
394         edma_write(ecc, EDMA_PARM + offset + (param_no << 5), val);
395 }
396
397 static inline void edma_param_modify(struct edma_cc *ecc, int offset,
398                                      int param_no, unsigned and, unsigned or)
399 {
400         edma_modify(ecc, EDMA_PARM + offset + (param_no << 5), and, or);
401 }
402
403 static inline void edma_param_and(struct edma_cc *ecc, int offset, int param_no,
404                                   unsigned and)
405 {
406         edma_and(ecc, EDMA_PARM + offset + (param_no << 5), and);
407 }
408
409 static inline void edma_param_or(struct edma_cc *ecc, int offset, int param_no,
410                                  unsigned or)
411 {
412         edma_or(ecc, EDMA_PARM + offset + (param_no << 5), or);
413 }
414
415 static inline void edma_set_bits(int offset, int len, unsigned long *p)
416 {
417         for (; len > 0; len--)
418                 set_bit(offset + (len - 1), p);
419 }
420
421 static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no,
422                                           int priority)
423 {
424         int bit = queue_no * 4;
425
426         edma_modify(ecc, EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit));
427 }
428
429 static void edma_set_chmap(struct edma_chan *echan, int slot)
430 {
431         struct edma_cc *ecc = echan->ecc;
432         int channel = EDMA_CHAN_SLOT(echan->ch_num);
433
434         if (ecc->chmap_exist) {
435                 slot = EDMA_CHAN_SLOT(slot);
436                 edma_write_array(ecc, EDMA_DCHMAP, channel, (slot << 5));
437         }
438 }
439
440 static void edma_setup_interrupt(struct edma_chan *echan, bool enable)
441 {
442         struct edma_cc *ecc = echan->ecc;
443         int channel = EDMA_CHAN_SLOT(echan->ch_num);
444
445         if (enable) {
446                 edma_shadow0_write_array(ecc, SH_ICR, channel >> 5,
447                                          BIT(channel & 0x1f));
448                 edma_shadow0_write_array(ecc, SH_IESR, channel >> 5,
449                                          BIT(channel & 0x1f));
450         } else {
451                 edma_shadow0_write_array(ecc, SH_IECR, channel >> 5,
452                                          BIT(channel & 0x1f));
453         }
454 }
455
456 /*
457  * paRAM slot management functions
458  */
459 static void edma_write_slot(struct edma_cc *ecc, unsigned slot,
460                             const struct edmacc_param *param)
461 {
462         slot = EDMA_CHAN_SLOT(slot);
463         if (slot >= ecc->num_slots)
464                 return;
465         memcpy_toio(ecc->base + PARM_OFFSET(slot), param, PARM_SIZE);
466 }
467
468 static int edma_read_slot(struct edma_cc *ecc, unsigned slot,
469                            struct edmacc_param *param)
470 {
471         slot = EDMA_CHAN_SLOT(slot);
472         if (slot >= ecc->num_slots)
473                 return -EINVAL;
474         memcpy_fromio(param, ecc->base + PARM_OFFSET(slot), PARM_SIZE);
475
476         return 0;
477 }
478
479 /**
480  * edma_alloc_slot - allocate DMA parameter RAM
481  * @ecc: pointer to edma_cc struct
482  * @slot: specific slot to allocate; negative for "any unused slot"
483  *
484  * This allocates a parameter RAM slot, initializing it to hold a
485  * dummy transfer.  Slots allocated using this routine have not been
486  * mapped to a hardware DMA channel, and will normally be used by
487  * linking to them from a slot associated with a DMA channel.
488  *
489  * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
490  * slots may be allocated on behalf of DSP firmware.
491  *
492  * Returns the number of the slot, else negative errno.
493  */
494 static int edma_alloc_slot(struct edma_cc *ecc, int slot)
495 {
496         if (slot >= 0) {
497                 slot = EDMA_CHAN_SLOT(slot);
498                 /* Requesting entry paRAM slot for a HW triggered channel. */
499                 if (ecc->chmap_exist && slot < ecc->num_channels)
500                         slot = EDMA_SLOT_ANY;
501         }
502
503         if (slot < 0) {
504                 if (ecc->chmap_exist)
505                         slot = 0;
506                 else
507                         slot = ecc->num_channels;
508                 for (;;) {
509                         slot = find_next_zero_bit(ecc->slot_inuse,
510                                                   ecc->num_slots,
511                                                   slot);
512                         if (slot == ecc->num_slots)
513                                 return -ENOMEM;
514                         if (!test_and_set_bit(slot, ecc->slot_inuse))
515                                 break;
516                 }
517         } else if (slot >= ecc->num_slots) {
518                 return -EINVAL;
519         } else if (test_and_set_bit(slot, ecc->slot_inuse)) {
520                 return -EBUSY;
521         }
522
523         edma_write_slot(ecc, slot, &dummy_paramset);
524
525         return EDMA_CTLR_CHAN(ecc->id, slot);
526 }
527
528 static void edma_free_slot(struct edma_cc *ecc, unsigned slot)
529 {
530         slot = EDMA_CHAN_SLOT(slot);
531         if (slot >= ecc->num_slots)
532                 return;
533
534         edma_write_slot(ecc, slot, &dummy_paramset);
535         clear_bit(slot, ecc->slot_inuse);
536 }
537
538 /**
539  * edma_link - link one parameter RAM slot to another
540  * @ecc: pointer to edma_cc struct
541  * @from: parameter RAM slot originating the link
542  * @to: parameter RAM slot which is the link target
543  *
544  * The originating slot should not be part of any active DMA transfer.
545  */
546 static void edma_link(struct edma_cc *ecc, unsigned from, unsigned to)
547 {
548         if (unlikely(EDMA_CTLR(from) != EDMA_CTLR(to)))
549                 dev_warn(ecc->dev, "Ignoring eDMA instance for linking\n");
550
551         from = EDMA_CHAN_SLOT(from);
552         to = EDMA_CHAN_SLOT(to);
553         if (from >= ecc->num_slots || to >= ecc->num_slots)
554                 return;
555
556         edma_param_modify(ecc, PARM_LINK_BCNTRLD, from, 0xffff0000,
557                           PARM_OFFSET(to));
558 }
559
560 /**
561  * edma_get_position - returns the current transfer point
562  * @ecc: pointer to edma_cc struct
563  * @slot: parameter RAM slot being examined
564  * @dst:  true selects the dest position, false the source
565  *
566  * Returns the position of the current active slot
567  */
568 static dma_addr_t edma_get_position(struct edma_cc *ecc, unsigned slot,
569                                     bool dst)
570 {
571         u32 offs;
572
573         slot = EDMA_CHAN_SLOT(slot);
574         offs = PARM_OFFSET(slot);
575         offs += dst ? PARM_DST : PARM_SRC;
576
577         return edma_read(ecc, offs);
578 }
579
580 /*
581  * Channels with event associations will be triggered by their hardware
582  * events, and channels without such associations will be triggered by
583  * software.  (At this writing there is no interface for using software
584  * triggers except with channels that don't support hardware triggers.)
585  */
586 static void edma_start(struct edma_chan *echan)
587 {
588         struct edma_cc *ecc = echan->ecc;
589         int channel = EDMA_CHAN_SLOT(echan->ch_num);
590         int j = (channel >> 5);
591         unsigned int mask = BIT(channel & 0x1f);
592
593         if (!echan->hw_triggered) {
594                 /* EDMA channels without event association */
595                 dev_dbg(ecc->dev, "ESR%d %08x\n", j,
596                         edma_shadow0_read_array(ecc, SH_ESR, j));
597                 edma_shadow0_write_array(ecc, SH_ESR, j, mask);
598         } else {
599                 /* EDMA channel with event association */
600                 dev_dbg(ecc->dev, "ER%d %08x\n", j,
601                         edma_shadow0_read_array(ecc, SH_ER, j));
602                 /* Clear any pending event or error */
603                 edma_write_array(ecc, EDMA_ECR, j, mask);
604                 edma_write_array(ecc, EDMA_EMCR, j, mask);
605                 /* Clear any SER */
606                 edma_shadow0_write_array(ecc, SH_SECR, j, mask);
607                 edma_shadow0_write_array(ecc, SH_EESR, j, mask);
608                 dev_dbg(ecc->dev, "EER%d %08x\n", j,
609                         edma_shadow0_read_array(ecc, SH_EER, j));
610         }
611 }
612
613 static void edma_stop(struct edma_chan *echan)
614 {
615         struct edma_cc *ecc = echan->ecc;
616         int channel = EDMA_CHAN_SLOT(echan->ch_num);
617         int j = (channel >> 5);
618         unsigned int mask = BIT(channel & 0x1f);
619
620         edma_shadow0_write_array(ecc, SH_EECR, j, mask);
621         edma_shadow0_write_array(ecc, SH_ECR, j, mask);
622         edma_shadow0_write_array(ecc, SH_SECR, j, mask);
623         edma_write_array(ecc, EDMA_EMCR, j, mask);
624
625         /* clear possibly pending completion interrupt */
626         edma_shadow0_write_array(ecc, SH_ICR, j, mask);
627
628         dev_dbg(ecc->dev, "EER%d %08x\n", j,
629                 edma_shadow0_read_array(ecc, SH_EER, j));
630
631         /* REVISIT:  consider guarding against inappropriate event
632          * chaining by overwriting with dummy_paramset.
633          */
634 }
635
636 /*
637  * Temporarily disable EDMA hardware events on the specified channel,
638  * preventing them from triggering new transfers
639  */
640 static void edma_pause(struct edma_chan *echan)
641 {
642         int channel = EDMA_CHAN_SLOT(echan->ch_num);
643         unsigned int mask = BIT(channel & 0x1f);
644
645         edma_shadow0_write_array(echan->ecc, SH_EECR, channel >> 5, mask);
646 }
647
648 /* Re-enable EDMA hardware events on the specified channel.  */
649 static void edma_resume(struct edma_chan *echan)
650 {
651         int channel = EDMA_CHAN_SLOT(echan->ch_num);
652         unsigned int mask = BIT(channel & 0x1f);
653
654         edma_shadow0_write_array(echan->ecc, SH_EESR, channel >> 5, mask);
655 }
656
657 static void edma_trigger_channel(struct edma_chan *echan)
658 {
659         struct edma_cc *ecc = echan->ecc;
660         int channel = EDMA_CHAN_SLOT(echan->ch_num);
661         unsigned int mask = BIT(channel & 0x1f);
662
663         edma_shadow0_write_array(ecc, SH_ESR, (channel >> 5), mask);
664
665         dev_dbg(ecc->dev, "ESR%d %08x\n", (channel >> 5),
666                 edma_shadow0_read_array(ecc, SH_ESR, (channel >> 5)));
667 }
668
669 static void edma_clean_channel(struct edma_chan *echan)
670 {
671         struct edma_cc *ecc = echan->ecc;
672         int channel = EDMA_CHAN_SLOT(echan->ch_num);
673         int j = (channel >> 5);
674         unsigned int mask = BIT(channel & 0x1f);
675
676         dev_dbg(ecc->dev, "EMR%d %08x\n", j, edma_read_array(ecc, EDMA_EMR, j));
677         edma_shadow0_write_array(ecc, SH_ECR, j, mask);
678         /* Clear the corresponding EMR bits */
679         edma_write_array(ecc, EDMA_EMCR, j, mask);
680         /* Clear any SER */
681         edma_shadow0_write_array(ecc, SH_SECR, j, mask);
682         edma_write(ecc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
683 }
684
685 /* Move channel to a specific event queue */
686 static void edma_assign_channel_eventq(struct edma_chan *echan,
687                                        enum dma_event_q eventq_no)
688 {
689         struct edma_cc *ecc = echan->ecc;
690         int channel = EDMA_CHAN_SLOT(echan->ch_num);
691         int bit = (channel & 0x7) * 4;
692
693         /* default to low priority queue */
694         if (eventq_no == EVENTQ_DEFAULT)
695                 eventq_no = ecc->default_queue;
696         if (eventq_no >= ecc->num_tc)
697                 return;
698
699         eventq_no &= 7;
700         edma_modify_array(ecc, EDMA_DMAQNUM, (channel >> 3), ~(0x7 << bit),
701                           eventq_no << bit);
702 }
703
704 static int edma_alloc_channel(struct edma_chan *echan,
705                               enum dma_event_q eventq_no)
706 {
707         struct edma_cc *ecc = echan->ecc;
708         int channel = EDMA_CHAN_SLOT(echan->ch_num);
709
710         /* ensure access through shadow region 0 */
711         edma_or_array2(ecc, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
712
713         /* ensure no events are pending */
714         edma_stop(echan);
715
716         edma_setup_interrupt(echan, true);
717
718         edma_assign_channel_eventq(echan, eventq_no);
719
720         return 0;
721 }
722
723 static void edma_free_channel(struct edma_chan *echan)
724 {
725         /* ensure no events are pending */
726         edma_stop(echan);
727         /* REVISIT should probably take out of shadow region 0 */
728         edma_setup_interrupt(echan, false);
729 }
730
731 static inline struct edma_cc *to_edma_cc(struct dma_device *d)
732 {
733         return container_of(d, struct edma_cc, dma_slave);
734 }
735
736 static inline struct edma_chan *to_edma_chan(struct dma_chan *c)
737 {
738         return container_of(c, struct edma_chan, vchan.chan);
739 }
740
741 static inline struct edma_desc *to_edma_desc(struct dma_async_tx_descriptor *tx)
742 {
743         return container_of(tx, struct edma_desc, vdesc.tx);
744 }
745
746 static void edma_desc_free(struct virt_dma_desc *vdesc)
747 {
748         kfree(container_of(vdesc, struct edma_desc, vdesc));
749 }
750
751 /* Dispatch a queued descriptor to the controller (caller holds lock) */
752 static void edma_execute(struct edma_chan *echan)
753 {
754         struct edma_cc *ecc = echan->ecc;
755         struct virt_dma_desc *vdesc;
756         struct edma_desc *edesc;
757         struct device *dev = echan->vchan.chan.device->dev;
758         int i, j, left, nslots;
759
760         if (!echan->edesc) {
761                 /* Setup is needed for the first transfer */
762                 vdesc = vchan_next_desc(&echan->vchan);
763                 if (!vdesc)
764                         return;
765                 list_del(&vdesc->node);
766                 echan->edesc = to_edma_desc(&vdesc->tx);
767         }
768
769         edesc = echan->edesc;
770
771         /* Find out how many left */
772         left = edesc->pset_nr - edesc->processed;
773         nslots = min(MAX_NR_SG, left);
774         edesc->sg_len = 0;
775
776         /* Write descriptor PaRAM set(s) */
777         for (i = 0; i < nslots; i++) {
778                 j = i + edesc->processed;
779                 edma_write_slot(ecc, echan->slot[i], &edesc->pset[j].param);
780                 edesc->sg_len += edesc->pset[j].len;
781                 dev_vdbg(dev,
782                          "\n pset[%d]:\n"
783                          "  chnum\t%d\n"
784                          "  slot\t%d\n"
785                          "  opt\t%08x\n"
786                          "  src\t%08x\n"
787                          "  dst\t%08x\n"
788                          "  abcnt\t%08x\n"
789                          "  ccnt\t%08x\n"
790                          "  bidx\t%08x\n"
791                          "  cidx\t%08x\n"
792                          "  lkrld\t%08x\n",
793                          j, echan->ch_num, echan->slot[i],
794                          edesc->pset[j].param.opt,
795                          edesc->pset[j].param.src,
796                          edesc->pset[j].param.dst,
797                          edesc->pset[j].param.a_b_cnt,
798                          edesc->pset[j].param.ccnt,
799                          edesc->pset[j].param.src_dst_bidx,
800                          edesc->pset[j].param.src_dst_cidx,
801                          edesc->pset[j].param.link_bcntrld);
802                 /* Link to the previous slot if not the last set */
803                 if (i != (nslots - 1))
804                         edma_link(ecc, echan->slot[i], echan->slot[i + 1]);
805         }
806
807         edesc->processed += nslots;
808
809         /*
810          * If this is either the last set in a set of SG-list transactions
811          * then setup a link to the dummy slot, this results in all future
812          * events being absorbed and that's OK because we're done
813          */
814         if (edesc->processed == edesc->pset_nr) {
815                 if (edesc->cyclic)
816                         edma_link(ecc, echan->slot[nslots - 1], echan->slot[1]);
817                 else
818                         edma_link(ecc, echan->slot[nslots - 1],
819                                   echan->ecc->dummy_slot);
820         }
821
822         if (echan->missed) {
823                 /*
824                  * This happens due to setup times between intermediate
825                  * transfers in long SG lists which have to be broken up into
826                  * transfers of MAX_NR_SG
827                  */
828                 dev_dbg(dev, "missed event on channel %d\n", echan->ch_num);
829                 edma_clean_channel(echan);
830                 edma_stop(echan);
831                 edma_start(echan);
832                 edma_trigger_channel(echan);
833                 echan->missed = 0;
834         } else if (edesc->processed <= MAX_NR_SG) {
835                 dev_dbg(dev, "first transfer starting on channel %d\n",
836                         echan->ch_num);
837                 edma_start(echan);
838         } else {
839                 dev_dbg(dev, "chan: %d: completed %d elements, resuming\n",
840                         echan->ch_num, edesc->processed);
841                 edma_resume(echan);
842         }
843 }
844
845 static int edma_terminate_all(struct dma_chan *chan)
846 {
847         struct edma_chan *echan = to_edma_chan(chan);
848         unsigned long flags;
849         LIST_HEAD(head);
850
851         spin_lock_irqsave(&echan->vchan.lock, flags);
852
853         /*
854          * Stop DMA activity: we assume the callback will not be called
855          * after edma_dma() returns (even if it does, it will see
856          * echan->edesc is NULL and exit.)
857          */
858         if (echan->edesc) {
859                 edma_stop(echan);
860                 /* Move the cyclic channel back to default queue */
861                 if (!echan->tc && echan->edesc->cyclic)
862                         edma_assign_channel_eventq(echan, EVENTQ_DEFAULT);
863
864                 vchan_terminate_vdesc(&echan->edesc->vdesc);
865                 echan->edesc = NULL;
866         }
867
868         vchan_get_all_descriptors(&echan->vchan, &head);
869         spin_unlock_irqrestore(&echan->vchan.lock, flags);
870         vchan_dma_desc_free_list(&echan->vchan, &head);
871
872         return 0;
873 }
874
875 static void edma_synchronize(struct dma_chan *chan)
876 {
877         struct edma_chan *echan = to_edma_chan(chan);
878
879         vchan_synchronize(&echan->vchan);
880 }
881
882 static int edma_slave_config(struct dma_chan *chan,
883         struct dma_slave_config *cfg)
884 {
885         struct edma_chan *echan = to_edma_chan(chan);
886
887         if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
888             cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
889                 return -EINVAL;
890
891         if (cfg->src_maxburst > chan->device->max_burst ||
892             cfg->dst_maxburst > chan->device->max_burst)
893                 return -EINVAL;
894
895         memcpy(&echan->cfg, cfg, sizeof(echan->cfg));
896
897         return 0;
898 }
899
900 static int edma_dma_pause(struct dma_chan *chan)
901 {
902         struct edma_chan *echan = to_edma_chan(chan);
903
904         if (!echan->edesc)
905                 return -EINVAL;
906
907         edma_pause(echan);
908         return 0;
909 }
910
911 static int edma_dma_resume(struct dma_chan *chan)
912 {
913         struct edma_chan *echan = to_edma_chan(chan);
914
915         edma_resume(echan);
916         return 0;
917 }
918
919 /*
920  * A PaRAM set configuration abstraction used by other modes
921  * @chan: Channel who's PaRAM set we're configuring
922  * @pset: PaRAM set to initialize and setup.
923  * @src_addr: Source address of the DMA
924  * @dst_addr: Destination address of the DMA
925  * @burst: In units of dev_width, how much to send
926  * @dev_width: How much is the dev_width
927  * @dma_length: Total length of the DMA transfer
928  * @direction: Direction of the transfer
929  */
930 static int edma_config_pset(struct dma_chan *chan, struct edma_pset *epset,
931                             dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst,
932                             unsigned int acnt, unsigned int dma_length,
933                             enum dma_transfer_direction direction)
934 {
935         struct edma_chan *echan = to_edma_chan(chan);
936         struct device *dev = chan->device->dev;
937         struct edmacc_param *param = &epset->param;
938         int bcnt, ccnt, cidx;
939         int src_bidx, dst_bidx, src_cidx, dst_cidx;
940         int absync;
941
942         /* src/dst_maxburst == 0 is the same case as src/dst_maxburst == 1 */
943         if (!burst)
944                 burst = 1;
945         /*
946          * If the maxburst is equal to the fifo width, use
947          * A-synced transfers. This allows for large contiguous
948          * buffer transfers using only one PaRAM set.
949          */
950         if (burst == 1) {
951                 /*
952                  * For the A-sync case, bcnt and ccnt are the remainder
953                  * and quotient respectively of the division of:
954                  * (dma_length / acnt) by (SZ_64K -1). This is so
955                  * that in case bcnt over flows, we have ccnt to use.
956                  * Note: In A-sync tranfer only, bcntrld is used, but it
957                  * only applies for sg_dma_len(sg) >= SZ_64K.
958                  * In this case, the best way adopted is- bccnt for the
959                  * first frame will be the remainder below. Then for
960                  * every successive frame, bcnt will be SZ_64K-1. This
961                  * is assured as bcntrld = 0xffff in end of function.
962                  */
963                 absync = false;
964                 ccnt = dma_length / acnt / (SZ_64K - 1);
965                 bcnt = dma_length / acnt - ccnt * (SZ_64K - 1);
966                 /*
967                  * If bcnt is non-zero, we have a remainder and hence an
968                  * extra frame to transfer, so increment ccnt.
969                  */
970                 if (bcnt)
971                         ccnt++;
972                 else
973                         bcnt = SZ_64K - 1;
974                 cidx = acnt;
975         } else {
976                 /*
977                  * If maxburst is greater than the fifo address_width,
978                  * use AB-synced transfers where A count is the fifo
979                  * address_width and B count is the maxburst. In this
980                  * case, we are limited to transfers of C count frames
981                  * of (address_width * maxburst) where C count is limited
982                  * to SZ_64K-1. This places an upper bound on the length
983                  * of an SG segment that can be handled.
984                  */
985                 absync = true;
986                 bcnt = burst;
987                 ccnt = dma_length / (acnt * bcnt);
988                 if (ccnt > (SZ_64K - 1)) {
989                         dev_err(dev, "Exceeded max SG segment size\n");
990                         return -EINVAL;
991                 }
992                 cidx = acnt * bcnt;
993         }
994
995         epset->len = dma_length;
996
997         if (direction == DMA_MEM_TO_DEV) {
998                 src_bidx = acnt;
999                 src_cidx = cidx;
1000                 dst_bidx = 0;
1001                 dst_cidx = 0;
1002                 epset->addr = src_addr;
1003         } else if (direction == DMA_DEV_TO_MEM)  {
1004                 src_bidx = 0;
1005                 src_cidx = 0;
1006                 dst_bidx = acnt;
1007                 dst_cidx = cidx;
1008                 epset->addr = dst_addr;
1009         } else if (direction == DMA_MEM_TO_MEM)  {
1010                 src_bidx = acnt;
1011                 src_cidx = cidx;
1012                 dst_bidx = acnt;
1013                 dst_cidx = cidx;
1014         } else {
1015                 dev_err(dev, "%s: direction not implemented yet\n", __func__);
1016                 return -EINVAL;
1017         }
1018
1019         param->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
1020         /* Configure A or AB synchronized transfers */
1021         if (absync)
1022                 param->opt |= SYNCDIM;
1023
1024         param->src = src_addr;
1025         param->dst = dst_addr;
1026
1027         param->src_dst_bidx = (dst_bidx << 16) | src_bidx;
1028         param->src_dst_cidx = (dst_cidx << 16) | src_cidx;
1029
1030         param->a_b_cnt = bcnt << 16 | acnt;
1031         param->ccnt = ccnt;
1032         /*
1033          * Only time when (bcntrld) auto reload is required is for
1034          * A-sync case, and in this case, a requirement of reload value
1035          * of SZ_64K-1 only is assured. 'link' is initially set to NULL
1036          * and then later will be populated by edma_execute.
1037          */
1038         param->link_bcntrld = 0xffffffff;
1039         return absync;
1040 }
1041
1042 static struct dma_async_tx_descriptor *edma_prep_slave_sg(
1043         struct dma_chan *chan, struct scatterlist *sgl,
1044         unsigned int sg_len, enum dma_transfer_direction direction,
1045         unsigned long tx_flags, void *context)
1046 {
1047         struct edma_chan *echan = to_edma_chan(chan);
1048         struct device *dev = chan->device->dev;
1049         struct edma_desc *edesc;
1050         dma_addr_t src_addr = 0, dst_addr = 0;
1051         enum dma_slave_buswidth dev_width;
1052         u32 burst;
1053         struct scatterlist *sg;
1054         int i, nslots, ret;
1055
1056         if (unlikely(!echan || !sgl || !sg_len))
1057                 return NULL;
1058
1059         if (direction == DMA_DEV_TO_MEM) {
1060                 src_addr = echan->cfg.src_addr;
1061                 dev_width = echan->cfg.src_addr_width;
1062                 burst = echan->cfg.src_maxburst;
1063         } else if (direction == DMA_MEM_TO_DEV) {
1064                 dst_addr = echan->cfg.dst_addr;
1065                 dev_width = echan->cfg.dst_addr_width;
1066                 burst = echan->cfg.dst_maxburst;
1067         } else {
1068                 dev_err(dev, "%s: bad direction: %d\n", __func__, direction);
1069                 return NULL;
1070         }
1071
1072         if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
1073                 dev_err(dev, "%s: Undefined slave buswidth\n", __func__);
1074                 return NULL;
1075         }
1076
1077         edesc = kzalloc(struct_size(edesc, pset, sg_len), GFP_ATOMIC);
1078         if (!edesc)
1079                 return NULL;
1080
1081         edesc->pset_nr = sg_len;
1082         edesc->residue = 0;
1083         edesc->direction = direction;
1084         edesc->echan = echan;
1085
1086         /* Allocate a PaRAM slot, if needed */
1087         nslots = min_t(unsigned, MAX_NR_SG, sg_len);
1088
1089         for (i = 0; i < nslots; i++) {
1090                 if (echan->slot[i] < 0) {
1091                         echan->slot[i] =
1092                                 edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY);
1093                         if (echan->slot[i] < 0) {
1094                                 kfree(edesc);
1095                                 dev_err(dev, "%s: Failed to allocate slot\n",
1096                                         __func__);
1097                                 return NULL;
1098                         }
1099                 }
1100         }
1101
1102         /* Configure PaRAM sets for each SG */
1103         for_each_sg(sgl, sg, sg_len, i) {
1104                 /* Get address for each SG */
1105                 if (direction == DMA_DEV_TO_MEM)
1106                         dst_addr = sg_dma_address(sg);
1107                 else
1108                         src_addr = sg_dma_address(sg);
1109
1110                 ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
1111                                        dst_addr, burst, dev_width,
1112                                        sg_dma_len(sg), direction);
1113                 if (ret < 0) {
1114                         kfree(edesc);
1115                         return NULL;
1116                 }
1117
1118                 edesc->absync = ret;
1119                 edesc->residue += sg_dma_len(sg);
1120
1121                 if (i == sg_len - 1)
1122                         /* Enable completion interrupt */
1123                         edesc->pset[i].param.opt |= TCINTEN;
1124                 else if (!((i+1) % MAX_NR_SG))
1125                         /*
1126                          * Enable early completion interrupt for the
1127                          * intermediateset. In this case the driver will be
1128                          * notified when the paRAM set is submitted to TC. This
1129                          * will allow more time to set up the next set of slots.
1130                          */
1131                         edesc->pset[i].param.opt |= (TCINTEN | TCCMODE);
1132         }
1133         edesc->residue_stat = edesc->residue;
1134
1135         return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
1136 }
1137
1138 static struct dma_async_tx_descriptor *edma_prep_dma_memcpy(
1139         struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1140         size_t len, unsigned long tx_flags)
1141 {
1142         int ret, nslots;
1143         struct edma_desc *edesc;
1144         struct device *dev = chan->device->dev;
1145         struct edma_chan *echan = to_edma_chan(chan);
1146         unsigned int width, pset_len, array_size;
1147
1148         if (unlikely(!echan || !len))
1149                 return NULL;
1150
1151         /* Align the array size (acnt block) with the transfer properties */
1152         switch (__ffs((src | dest | len))) {
1153         case 0:
1154                 array_size = SZ_32K - 1;
1155                 break;
1156         case 1:
1157                 array_size = SZ_32K - 2;
1158                 break;
1159         default:
1160                 array_size = SZ_32K - 4;
1161                 break;
1162         }
1163
1164         if (len < SZ_64K) {
1165                 /*
1166                  * Transfer size less than 64K can be handled with one paRAM
1167                  * slot and with one burst.
1168                  * ACNT = length
1169                  */
1170                 width = len;
1171                 pset_len = len;
1172                 nslots = 1;
1173         } else {
1174                 /*
1175                  * Transfer size bigger than 64K will be handled with maximum of
1176                  * two paRAM slots.
1177                  * slot1: (full_length / 32767) times 32767 bytes bursts.
1178                  *        ACNT = 32767, length1: (full_length / 32767) * 32767
1179                  * slot2: the remaining amount of data after slot1.
1180                  *        ACNT = full_length - length1, length2 = ACNT
1181                  *
1182                  * When the full_length is multibple of 32767 one slot can be
1183                  * used to complete the transfer.
1184                  */
1185                 width = array_size;
1186                 pset_len = rounddown(len, width);
1187                 /* One slot is enough for lengths multiple of (SZ_32K -1) */
1188                 if (unlikely(pset_len == len))
1189                         nslots = 1;
1190                 else
1191                         nslots = 2;
1192         }
1193
1194         edesc = kzalloc(struct_size(edesc, pset, nslots), GFP_ATOMIC);
1195         if (!edesc)
1196                 return NULL;
1197
1198         edesc->pset_nr = nslots;
1199         edesc->residue = edesc->residue_stat = len;
1200         edesc->direction = DMA_MEM_TO_MEM;
1201         edesc->echan = echan;
1202
1203         ret = edma_config_pset(chan, &edesc->pset[0], src, dest, 1,
1204                                width, pset_len, DMA_MEM_TO_MEM);
1205         if (ret < 0) {
1206                 kfree(edesc);
1207                 return NULL;
1208         }
1209
1210         edesc->absync = ret;
1211
1212         edesc->pset[0].param.opt |= ITCCHEN;
1213         if (nslots == 1) {
1214                 /* Enable transfer complete interrupt */
1215                 edesc->pset[0].param.opt |= TCINTEN;
1216         } else {
1217                 /* Enable transfer complete chaining for the first slot */
1218                 edesc->pset[0].param.opt |= TCCHEN;
1219
1220                 if (echan->slot[1] < 0) {
1221                         echan->slot[1] = edma_alloc_slot(echan->ecc,
1222                                                          EDMA_SLOT_ANY);
1223                         if (echan->slot[1] < 0) {
1224                                 kfree(edesc);
1225                                 dev_err(dev, "%s: Failed to allocate slot\n",
1226                                         __func__);
1227                                 return NULL;
1228                         }
1229                 }
1230                 dest += pset_len;
1231                 src += pset_len;
1232                 pset_len = width = len % array_size;
1233
1234                 ret = edma_config_pset(chan, &edesc->pset[1], src, dest, 1,
1235                                        width, pset_len, DMA_MEM_TO_MEM);
1236                 if (ret < 0) {
1237                         kfree(edesc);
1238                         return NULL;
1239                 }
1240
1241                 edesc->pset[1].param.opt |= ITCCHEN;
1242                 edesc->pset[1].param.opt |= TCINTEN;
1243         }
1244
1245         return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
1246 }
1247
1248 static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
1249         struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
1250         size_t period_len, enum dma_transfer_direction direction,
1251         unsigned long tx_flags)
1252 {
1253         struct edma_chan *echan = to_edma_chan(chan);
1254         struct device *dev = chan->device->dev;
1255         struct edma_desc *edesc;
1256         dma_addr_t src_addr, dst_addr;
1257         enum dma_slave_buswidth dev_width;
1258         bool use_intermediate = false;
1259         u32 burst;
1260         int i, ret, nslots;
1261
1262         if (unlikely(!echan || !buf_len || !period_len))
1263                 return NULL;
1264
1265         if (direction == DMA_DEV_TO_MEM) {
1266                 src_addr = echan->cfg.src_addr;
1267                 dst_addr = buf_addr;
1268                 dev_width = echan->cfg.src_addr_width;
1269                 burst = echan->cfg.src_maxburst;
1270         } else if (direction == DMA_MEM_TO_DEV) {
1271                 src_addr = buf_addr;
1272                 dst_addr = echan->cfg.dst_addr;
1273                 dev_width = echan->cfg.dst_addr_width;
1274                 burst = echan->cfg.dst_maxburst;
1275         } else {
1276                 dev_err(dev, "%s: bad direction: %d\n", __func__, direction);
1277                 return NULL;
1278         }
1279
1280         if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
1281                 dev_err(dev, "%s: Undefined slave buswidth\n", __func__);
1282                 return NULL;
1283         }
1284
1285         if (unlikely(buf_len % period_len)) {
1286                 dev_err(dev, "Period should be multiple of Buffer length\n");
1287                 return NULL;
1288         }
1289
1290         nslots = (buf_len / period_len) + 1;
1291
1292         /*
1293          * Cyclic DMA users such as audio cannot tolerate delays introduced
1294          * by cases where the number of periods is more than the maximum
1295          * number of SGs the EDMA driver can handle at a time. For DMA types
1296          * such as Slave SGs, such delays are tolerable and synchronized,
1297          * but the synchronization is difficult to achieve with Cyclic and
1298          * cannot be guaranteed, so we error out early.
1299          */
1300         if (nslots > MAX_NR_SG) {
1301                 /*
1302                  * If the burst and period sizes are the same, we can put
1303                  * the full buffer into a single period and activate
1304                  * intermediate interrupts. This will produce interrupts
1305                  * after each burst, which is also after each desired period.
1306                  */
1307                 if (burst == period_len) {
1308                         period_len = buf_len;
1309                         nslots = 2;
1310                         use_intermediate = true;
1311                 } else {
1312                         return NULL;
1313                 }
1314         }
1315
1316         edesc = kzalloc(struct_size(edesc, pset, nslots), GFP_ATOMIC);
1317         if (!edesc)
1318                 return NULL;
1319
1320         edesc->cyclic = 1;
1321         edesc->pset_nr = nslots;
1322         edesc->residue = edesc->residue_stat = buf_len;
1323         edesc->direction = direction;
1324         edesc->echan = echan;
1325
1326         dev_dbg(dev, "%s: channel=%d nslots=%d period_len=%zu buf_len=%zu\n",
1327                 __func__, echan->ch_num, nslots, period_len, buf_len);
1328
1329         for (i = 0; i < nslots; i++) {
1330                 /* Allocate a PaRAM slot, if needed */
1331                 if (echan->slot[i] < 0) {
1332                         echan->slot[i] =
1333                                 edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY);
1334                         if (echan->slot[i] < 0) {
1335                                 kfree(edesc);
1336                                 dev_err(dev, "%s: Failed to allocate slot\n",
1337                                         __func__);
1338                                 return NULL;
1339                         }
1340                 }
1341
1342                 if (i == nslots - 1) {
1343                         memcpy(&edesc->pset[i], &edesc->pset[0],
1344                                sizeof(edesc->pset[0]));
1345                         break;
1346                 }
1347
1348                 ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
1349                                        dst_addr, burst, dev_width, period_len,
1350                                        direction);
1351                 if (ret < 0) {
1352                         kfree(edesc);
1353                         return NULL;
1354                 }
1355
1356                 if (direction == DMA_DEV_TO_MEM)
1357                         dst_addr += period_len;
1358                 else
1359                         src_addr += period_len;
1360
1361                 dev_vdbg(dev, "%s: Configure period %d of buf:\n", __func__, i);
1362                 dev_vdbg(dev,
1363                         "\n pset[%d]:\n"
1364                         "  chnum\t%d\n"
1365                         "  slot\t%d\n"
1366                         "  opt\t%08x\n"
1367                         "  src\t%08x\n"
1368                         "  dst\t%08x\n"
1369                         "  abcnt\t%08x\n"
1370                         "  ccnt\t%08x\n"
1371                         "  bidx\t%08x\n"
1372                         "  cidx\t%08x\n"
1373                         "  lkrld\t%08x\n",
1374                         i, echan->ch_num, echan->slot[i],
1375                         edesc->pset[i].param.opt,
1376                         edesc->pset[i].param.src,
1377                         edesc->pset[i].param.dst,
1378                         edesc->pset[i].param.a_b_cnt,
1379                         edesc->pset[i].param.ccnt,
1380                         edesc->pset[i].param.src_dst_bidx,
1381                         edesc->pset[i].param.src_dst_cidx,
1382                         edesc->pset[i].param.link_bcntrld);
1383
1384                 edesc->absync = ret;
1385
1386                 /*
1387                  * Enable period interrupt only if it is requested
1388                  */
1389                 if (tx_flags & DMA_PREP_INTERRUPT) {
1390                         edesc->pset[i].param.opt |= TCINTEN;
1391
1392                         /* Also enable intermediate interrupts if necessary */
1393                         if (use_intermediate)
1394                                 edesc->pset[i].param.opt |= ITCINTEN;
1395                 }
1396         }
1397
1398         /* Place the cyclic channel to highest priority queue */
1399         if (!echan->tc)
1400                 edma_assign_channel_eventq(echan, EVENTQ_0);
1401
1402         return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
1403 }
1404
1405 static void edma_completion_handler(struct edma_chan *echan)
1406 {
1407         struct device *dev = echan->vchan.chan.device->dev;
1408         struct edma_desc *edesc;
1409
1410         spin_lock(&echan->vchan.lock);
1411         edesc = echan->edesc;
1412         if (edesc) {
1413                 if (edesc->cyclic) {
1414                         vchan_cyclic_callback(&edesc->vdesc);
1415                         spin_unlock(&echan->vchan.lock);
1416                         return;
1417                 } else if (edesc->processed == edesc->pset_nr) {
1418                         edesc->residue = 0;
1419                         edma_stop(echan);
1420                         vchan_cookie_complete(&edesc->vdesc);
1421                         echan->edesc = NULL;
1422
1423                         dev_dbg(dev, "Transfer completed on channel %d\n",
1424                                 echan->ch_num);
1425                 } else {
1426                         dev_dbg(dev, "Sub transfer completed on channel %d\n",
1427                                 echan->ch_num);
1428
1429                         edma_pause(echan);
1430
1431                         /* Update statistics for tx_status */
1432                         edesc->residue -= edesc->sg_len;
1433                         edesc->residue_stat = edesc->residue;
1434                         edesc->processed_stat = edesc->processed;
1435                 }
1436                 edma_execute(echan);
1437         }
1438
1439         spin_unlock(&echan->vchan.lock);
1440 }
1441
1442 /* eDMA interrupt handler */
1443 static irqreturn_t dma_irq_handler(int irq, void *data)
1444 {
1445         struct edma_cc *ecc = data;
1446         int ctlr;
1447         u32 sh_ier;
1448         u32 sh_ipr;
1449         u32 bank;
1450
1451         ctlr = ecc->id;
1452         if (ctlr < 0)
1453                 return IRQ_NONE;
1454
1455         dev_vdbg(ecc->dev, "dma_irq_handler\n");
1456
1457         sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 0);
1458         if (!sh_ipr) {
1459                 sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 1);
1460                 if (!sh_ipr)
1461                         return IRQ_NONE;
1462                 sh_ier = edma_shadow0_read_array(ecc, SH_IER, 1);
1463                 bank = 1;
1464         } else {
1465                 sh_ier = edma_shadow0_read_array(ecc, SH_IER, 0);
1466                 bank = 0;
1467         }
1468
1469         do {
1470                 u32 slot;
1471                 u32 channel;
1472
1473                 slot = __ffs(sh_ipr);
1474                 sh_ipr &= ~(BIT(slot));
1475
1476                 if (sh_ier & BIT(slot)) {
1477                         channel = (bank << 5) | slot;
1478                         /* Clear the corresponding IPR bits */
1479                         edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot));
1480                         edma_completion_handler(&ecc->slave_chans[channel]);
1481                 }
1482         } while (sh_ipr);
1483
1484         edma_shadow0_write(ecc, SH_IEVAL, 1);
1485         return IRQ_HANDLED;
1486 }
1487
1488 static void edma_error_handler(struct edma_chan *echan)
1489 {
1490         struct edma_cc *ecc = echan->ecc;
1491         struct device *dev = echan->vchan.chan.device->dev;
1492         struct edmacc_param p;
1493         int err;
1494
1495         if (!echan->edesc)
1496                 return;
1497
1498         spin_lock(&echan->vchan.lock);
1499
1500         err = edma_read_slot(ecc, echan->slot[0], &p);
1501
1502         /*
1503          * Issue later based on missed flag which will be sure
1504          * to happen as:
1505          * (1) we finished transmitting an intermediate slot and
1506          *     edma_execute is coming up.
1507          * (2) or we finished current transfer and issue will
1508          *     call edma_execute.
1509          *
1510          * Important note: issuing can be dangerous here and
1511          * lead to some nasty recursion when we are in a NULL
1512          * slot. So we avoid doing so and set the missed flag.
1513          */
1514         if (err || (p.a_b_cnt == 0 && p.ccnt == 0)) {
1515                 dev_dbg(dev, "Error on null slot, setting miss\n");
1516                 echan->missed = 1;
1517         } else {
1518                 /*
1519                  * The slot is already programmed but the event got
1520                  * missed, so its safe to issue it here.
1521                  */
1522                 dev_dbg(dev, "Missed event, TRIGGERING\n");
1523                 edma_clean_channel(echan);
1524                 edma_stop(echan);
1525                 edma_start(echan);
1526                 edma_trigger_channel(echan);
1527         }
1528         spin_unlock(&echan->vchan.lock);
1529 }
1530
1531 static inline bool edma_error_pending(struct edma_cc *ecc)
1532 {
1533         if (edma_read_array(ecc, EDMA_EMR, 0) ||
1534             edma_read_array(ecc, EDMA_EMR, 1) ||
1535             edma_read(ecc, EDMA_QEMR) || edma_read(ecc, EDMA_CCERR))
1536                 return true;
1537
1538         return false;
1539 }
1540
1541 /* eDMA error interrupt handler */
1542 static irqreturn_t dma_ccerr_handler(int irq, void *data)
1543 {
1544         struct edma_cc *ecc = data;
1545         int i, j;
1546         int ctlr;
1547         unsigned int cnt = 0;
1548         unsigned int val;
1549
1550         ctlr = ecc->id;
1551         if (ctlr < 0)
1552                 return IRQ_NONE;
1553
1554         dev_vdbg(ecc->dev, "dma_ccerr_handler\n");
1555
1556         if (!edma_error_pending(ecc)) {
1557                 /*
1558                  * The registers indicate no pending error event but the irq
1559                  * handler has been called.
1560                  * Ask eDMA to re-evaluate the error registers.
1561                  */
1562                 dev_err(ecc->dev, "%s: Error interrupt without error event!\n",
1563                         __func__);
1564                 edma_write(ecc, EDMA_EEVAL, 1);
1565                 return IRQ_NONE;
1566         }
1567
1568         while (1) {
1569                 /* Event missed register(s) */
1570                 for (j = 0; j < 2; j++) {
1571                         unsigned long emr;
1572
1573                         val = edma_read_array(ecc, EDMA_EMR, j);
1574                         if (!val)
1575                                 continue;
1576
1577                         dev_dbg(ecc->dev, "EMR%d 0x%08x\n", j, val);
1578                         emr = val;
1579                         for (i = find_next_bit(&emr, 32, 0); i < 32;
1580                              i = find_next_bit(&emr, 32, i + 1)) {
1581                                 int k = (j << 5) + i;
1582
1583                                 /* Clear the corresponding EMR bits */
1584                                 edma_write_array(ecc, EDMA_EMCR, j, BIT(i));
1585                                 /* Clear any SER */
1586                                 edma_shadow0_write_array(ecc, SH_SECR, j,
1587                                                          BIT(i));
1588                                 edma_error_handler(&ecc->slave_chans[k]);
1589                         }
1590                 }
1591
1592                 val = edma_read(ecc, EDMA_QEMR);
1593                 if (val) {
1594                         dev_dbg(ecc->dev, "QEMR 0x%02x\n", val);
1595                         /* Not reported, just clear the interrupt reason. */
1596                         edma_write(ecc, EDMA_QEMCR, val);
1597                         edma_shadow0_write(ecc, SH_QSECR, val);
1598                 }
1599
1600                 val = edma_read(ecc, EDMA_CCERR);
1601                 if (val) {
1602                         dev_warn(ecc->dev, "CCERR 0x%08x\n", val);
1603                         /* Not reported, just clear the interrupt reason. */
1604                         edma_write(ecc, EDMA_CCERRCLR, val);
1605                 }
1606
1607                 if (!edma_error_pending(ecc))
1608                         break;
1609                 cnt++;
1610                 if (cnt > 10)
1611                         break;
1612         }
1613         edma_write(ecc, EDMA_EEVAL, 1);
1614         return IRQ_HANDLED;
1615 }
1616
1617 /* Alloc channel resources */
1618 static int edma_alloc_chan_resources(struct dma_chan *chan)
1619 {
1620         struct edma_chan *echan = to_edma_chan(chan);
1621         struct edma_cc *ecc = echan->ecc;
1622         struct device *dev = ecc->dev;
1623         enum dma_event_q eventq_no = EVENTQ_DEFAULT;
1624         int ret;
1625
1626         if (echan->tc) {
1627                 eventq_no = echan->tc->id;
1628         } else if (ecc->tc_list) {
1629                 /* memcpy channel */
1630                 echan->tc = &ecc->tc_list[ecc->info->default_queue];
1631                 eventq_no = echan->tc->id;
1632         }
1633
1634         ret = edma_alloc_channel(echan, eventq_no);
1635         if (ret)
1636                 return ret;
1637
1638         echan->slot[0] = edma_alloc_slot(ecc, echan->ch_num);
1639         if (echan->slot[0] < 0) {
1640                 dev_err(dev, "Entry slot allocation failed for channel %u\n",
1641                         EDMA_CHAN_SLOT(echan->ch_num));
1642                 ret = echan->slot[0];
1643                 goto err_slot;
1644         }
1645
1646         /* Set up channel -> slot mapping for the entry slot */
1647         edma_set_chmap(echan, echan->slot[0]);
1648         echan->alloced = true;
1649
1650         dev_dbg(dev, "Got eDMA channel %d for virt channel %d (%s trigger)\n",
1651                 EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id,
1652                 echan->hw_triggered ? "HW" : "SW");
1653
1654         return 0;
1655
1656 err_slot:
1657         edma_free_channel(echan);
1658         return ret;
1659 }
1660
1661 /* Free channel resources */
1662 static void edma_free_chan_resources(struct dma_chan *chan)
1663 {
1664         struct edma_chan *echan = to_edma_chan(chan);
1665         struct device *dev = echan->ecc->dev;
1666         int i;
1667
1668         /* Terminate transfers */
1669         edma_stop(echan);
1670
1671         vchan_free_chan_resources(&echan->vchan);
1672
1673         /* Free EDMA PaRAM slots */
1674         for (i = 0; i < EDMA_MAX_SLOTS; i++) {
1675                 if (echan->slot[i] >= 0) {
1676                         edma_free_slot(echan->ecc, echan->slot[i]);
1677                         echan->slot[i] = -1;
1678                 }
1679         }
1680
1681         /* Set entry slot to the dummy slot */
1682         edma_set_chmap(echan, echan->ecc->dummy_slot);
1683
1684         /* Free EDMA channel */
1685         if (echan->alloced) {
1686                 edma_free_channel(echan);
1687                 echan->alloced = false;
1688         }
1689
1690         echan->tc = NULL;
1691         echan->hw_triggered = false;
1692
1693         dev_dbg(dev, "Free eDMA channel %d for virt channel %d\n",
1694                 EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id);
1695 }
1696
1697 /* Send pending descriptor to hardware */
1698 static void edma_issue_pending(struct dma_chan *chan)
1699 {
1700         struct edma_chan *echan = to_edma_chan(chan);
1701         unsigned long flags;
1702
1703         spin_lock_irqsave(&echan->vchan.lock, flags);
1704         if (vchan_issue_pending(&echan->vchan) && !echan->edesc)
1705                 edma_execute(echan);
1706         spin_unlock_irqrestore(&echan->vchan.lock, flags);
1707 }
1708
1709 /*
1710  * This limit exists to avoid a possible infinite loop when waiting for proof
1711  * that a particular transfer is completed. This limit can be hit if there
1712  * are large bursts to/from slow devices or the CPU is never able to catch
1713  * the DMA hardware idle. On an AM335x transfering 48 bytes from the UART
1714  * RX-FIFO, as many as 55 loops have been seen.
1715  */
1716 #define EDMA_MAX_TR_WAIT_LOOPS 1000
1717
1718 static u32 edma_residue(struct edma_desc *edesc)
1719 {
1720         bool dst = edesc->direction == DMA_DEV_TO_MEM;
1721         int loop_count = EDMA_MAX_TR_WAIT_LOOPS;
1722         struct edma_chan *echan = edesc->echan;
1723         struct edma_pset *pset = edesc->pset;
1724         dma_addr_t done, pos;
1725         int i;
1726
1727         /*
1728          * We always read the dst/src position from the first RamPar
1729          * pset. That's the one which is active now.
1730          */
1731         pos = edma_get_position(echan->ecc, echan->slot[0], dst);
1732
1733         /*
1734          * "pos" may represent a transfer request that is still being
1735          * processed by the EDMACC or EDMATC. We will busy wait until
1736          * any one of the situations occurs:
1737          *   1. the DMA hardware is idle
1738          *   2. a new transfer request is setup
1739          *   3. we hit the loop limit
1740          */
1741         while (edma_read(echan->ecc, EDMA_CCSTAT) & EDMA_CCSTAT_ACTV) {
1742                 /* check if a new transfer request is setup */
1743                 if (edma_get_position(echan->ecc,
1744                                       echan->slot[0], dst) != pos) {
1745                         break;
1746                 }
1747
1748                 if (!--loop_count) {
1749                         dev_dbg_ratelimited(echan->vchan.chan.device->dev,
1750                                 "%s: timeout waiting for PaRAM update\n",
1751                                 __func__);
1752                         break;
1753                 }
1754
1755                 cpu_relax();
1756         }
1757
1758         /*
1759          * Cyclic is simple. Just subtract pset[0].addr from pos.
1760          *
1761          * We never update edesc->residue in the cyclic case, so we
1762          * can tell the remaining room to the end of the circular
1763          * buffer.
1764          */
1765         if (edesc->cyclic) {
1766                 done = pos - pset->addr;
1767                 edesc->residue_stat = edesc->residue - done;
1768                 return edesc->residue_stat;
1769         }
1770
1771         /*
1772          * For SG operation we catch up with the last processed
1773          * status.
1774          */
1775         pset += edesc->processed_stat;
1776
1777         for (i = edesc->processed_stat; i < edesc->processed; i++, pset++) {
1778                 /*
1779                  * If we are inside this pset address range, we know
1780                  * this is the active one. Get the current delta and
1781                  * stop walking the psets.
1782                  */
1783                 if (pos >= pset->addr && pos < pset->addr + pset->len)
1784                         return edesc->residue_stat - (pos - pset->addr);
1785
1786                 /* Otherwise mark it done and update residue_stat. */
1787                 edesc->processed_stat++;
1788                 edesc->residue_stat -= pset->len;
1789         }
1790         return edesc->residue_stat;
1791 }
1792
1793 /* Check request completion status */
1794 static enum dma_status edma_tx_status(struct dma_chan *chan,
1795                                       dma_cookie_t cookie,
1796                                       struct dma_tx_state *txstate)
1797 {
1798         struct edma_chan *echan = to_edma_chan(chan);
1799         struct virt_dma_desc *vdesc;
1800         enum dma_status ret;
1801         unsigned long flags;
1802
1803         ret = dma_cookie_status(chan, cookie, txstate);
1804         if (ret == DMA_COMPLETE || !txstate)
1805                 return ret;
1806
1807         spin_lock_irqsave(&echan->vchan.lock, flags);
1808         if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie)
1809                 txstate->residue = edma_residue(echan->edesc);
1810         else if ((vdesc = vchan_find_desc(&echan->vchan, cookie)))
1811                 txstate->residue = to_edma_desc(&vdesc->tx)->residue;
1812         spin_unlock_irqrestore(&echan->vchan.lock, flags);
1813
1814         return ret;
1815 }
1816
1817 static bool edma_is_memcpy_channel(int ch_num, s32 *memcpy_channels)
1818 {
1819         if (!memcpy_channels)
1820                 return false;
1821         while (*memcpy_channels != -1) {
1822                 if (*memcpy_channels == ch_num)
1823                         return true;
1824                 memcpy_channels++;
1825         }
1826         return false;
1827 }
1828
1829 #define EDMA_DMA_BUSWIDTHS      (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
1830                                  BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
1831                                  BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \
1832                                  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
1833
1834 static void edma_dma_init(struct edma_cc *ecc, bool legacy_mode)
1835 {
1836         struct dma_device *s_ddev = &ecc->dma_slave;
1837         struct dma_device *m_ddev = NULL;
1838         s32 *memcpy_channels = ecc->info->memcpy_channels;
1839         int i, j;
1840
1841         dma_cap_zero(s_ddev->cap_mask);
1842         dma_cap_set(DMA_SLAVE, s_ddev->cap_mask);
1843         dma_cap_set(DMA_CYCLIC, s_ddev->cap_mask);
1844         if (ecc->legacy_mode && !memcpy_channels) {
1845                 dev_warn(ecc->dev,
1846                          "Legacy memcpy is enabled, things might not work\n");
1847
1848                 dma_cap_set(DMA_MEMCPY, s_ddev->cap_mask);
1849                 s_ddev->device_prep_dma_memcpy = edma_prep_dma_memcpy;
1850                 s_ddev->directions = BIT(DMA_MEM_TO_MEM);
1851         }
1852
1853         s_ddev->device_prep_slave_sg = edma_prep_slave_sg;
1854         s_ddev->device_prep_dma_cyclic = edma_prep_dma_cyclic;
1855         s_ddev->device_alloc_chan_resources = edma_alloc_chan_resources;
1856         s_ddev->device_free_chan_resources = edma_free_chan_resources;
1857         s_ddev->device_issue_pending = edma_issue_pending;
1858         s_ddev->device_tx_status = edma_tx_status;
1859         s_ddev->device_config = edma_slave_config;
1860         s_ddev->device_pause = edma_dma_pause;
1861         s_ddev->device_resume = edma_dma_resume;
1862         s_ddev->device_terminate_all = edma_terminate_all;
1863         s_ddev->device_synchronize = edma_synchronize;
1864
1865         s_ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS;
1866         s_ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS;
1867         s_ddev->directions |= (BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV));
1868         s_ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1869         s_ddev->max_burst = SZ_32K - 1; /* CIDX: 16bit signed */
1870
1871         s_ddev->dev = ecc->dev;
1872         INIT_LIST_HEAD(&s_ddev->channels);
1873
1874         if (memcpy_channels) {
1875                 m_ddev = devm_kzalloc(ecc->dev, sizeof(*m_ddev), GFP_KERNEL);
1876                 if (!m_ddev) {
1877                         dev_warn(ecc->dev, "memcpy is disabled due to OoM\n");
1878                         memcpy_channels = NULL;
1879                         goto ch_setup;
1880                 }
1881                 ecc->dma_memcpy = m_ddev;
1882
1883                 dma_cap_zero(m_ddev->cap_mask);
1884                 dma_cap_set(DMA_MEMCPY, m_ddev->cap_mask);
1885
1886                 m_ddev->device_prep_dma_memcpy = edma_prep_dma_memcpy;
1887                 m_ddev->device_alloc_chan_resources = edma_alloc_chan_resources;
1888                 m_ddev->device_free_chan_resources = edma_free_chan_resources;
1889                 m_ddev->device_issue_pending = edma_issue_pending;
1890                 m_ddev->device_tx_status = edma_tx_status;
1891                 m_ddev->device_config = edma_slave_config;
1892                 m_ddev->device_pause = edma_dma_pause;
1893                 m_ddev->device_resume = edma_dma_resume;
1894                 m_ddev->device_terminate_all = edma_terminate_all;
1895                 m_ddev->device_synchronize = edma_synchronize;
1896
1897                 m_ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS;
1898                 m_ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS;
1899                 m_ddev->directions = BIT(DMA_MEM_TO_MEM);
1900                 m_ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1901
1902                 m_ddev->dev = ecc->dev;
1903                 INIT_LIST_HEAD(&m_ddev->channels);
1904         } else if (!ecc->legacy_mode) {
1905                 dev_info(ecc->dev, "memcpy is disabled\n");
1906         }
1907
1908 ch_setup:
1909         for (i = 0; i < ecc->num_channels; i++) {
1910                 struct edma_chan *echan = &ecc->slave_chans[i];
1911                 echan->ch_num = EDMA_CTLR_CHAN(ecc->id, i);
1912                 echan->ecc = ecc;
1913                 echan->vchan.desc_free = edma_desc_free;
1914
1915                 if (m_ddev && edma_is_memcpy_channel(i, memcpy_channels))
1916                         vchan_init(&echan->vchan, m_ddev);
1917                 else
1918                         vchan_init(&echan->vchan, s_ddev);
1919
1920                 INIT_LIST_HEAD(&echan->node);
1921                 for (j = 0; j < EDMA_MAX_SLOTS; j++)
1922                         echan->slot[j] = -1;
1923         }
1924 }
1925
1926 static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
1927                               struct edma_cc *ecc)
1928 {
1929         int i;
1930         u32 value, cccfg;
1931         s8 (*queue_priority_map)[2];
1932
1933         /* Decode the eDMA3 configuration from CCCFG register */
1934         cccfg = edma_read(ecc, EDMA_CCCFG);
1935
1936         value = GET_NUM_REGN(cccfg);
1937         ecc->num_region = BIT(value);
1938
1939         value = GET_NUM_DMACH(cccfg);
1940         ecc->num_channels = BIT(value + 1);
1941
1942         value = GET_NUM_QDMACH(cccfg);
1943         ecc->num_qchannels = value * 2;
1944
1945         value = GET_NUM_PAENTRY(cccfg);
1946         ecc->num_slots = BIT(value + 4);
1947
1948         value = GET_NUM_EVQUE(cccfg);
1949         ecc->num_tc = value + 1;
1950
1951         ecc->chmap_exist = (cccfg & CHMAP_EXIST) ? true : false;
1952
1953         dev_dbg(dev, "eDMA3 CC HW configuration (cccfg: 0x%08x):\n", cccfg);
1954         dev_dbg(dev, "num_region: %u\n", ecc->num_region);
1955         dev_dbg(dev, "num_channels: %u\n", ecc->num_channels);
1956         dev_dbg(dev, "num_qchannels: %u\n", ecc->num_qchannels);
1957         dev_dbg(dev, "num_slots: %u\n", ecc->num_slots);
1958         dev_dbg(dev, "num_tc: %u\n", ecc->num_tc);
1959         dev_dbg(dev, "chmap_exist: %s\n", ecc->chmap_exist ? "yes" : "no");
1960
1961         /* Nothing need to be done if queue priority is provided */
1962         if (pdata->queue_priority_mapping)
1963                 return 0;
1964
1965         /*
1966          * Configure TC/queue priority as follows:
1967          * Q0 - priority 0
1968          * Q1 - priority 1
1969          * Q2 - priority 2
1970          * ...
1971          * The meaning of priority numbers: 0 highest priority, 7 lowest
1972          * priority. So Q0 is the highest priority queue and the last queue has
1973          * the lowest priority.
1974          */
1975         queue_priority_map = devm_kcalloc(dev, ecc->num_tc + 1, sizeof(s8),
1976                                           GFP_KERNEL);
1977         if (!queue_priority_map)
1978                 return -ENOMEM;
1979
1980         for (i = 0; i < ecc->num_tc; i++) {
1981                 queue_priority_map[i][0] = i;
1982                 queue_priority_map[i][1] = i;
1983         }
1984         queue_priority_map[i][0] = -1;
1985         queue_priority_map[i][1] = -1;
1986
1987         pdata->queue_priority_mapping = queue_priority_map;
1988         /* Default queue has the lowest priority */
1989         pdata->default_queue = i - 1;
1990
1991         return 0;
1992 }
1993
1994 #if IS_ENABLED(CONFIG_OF)
1995 static int edma_xbar_event_map(struct device *dev, struct edma_soc_info *pdata,
1996                                size_t sz)
1997 {
1998         const char pname[] = "ti,edma-xbar-event-map";
1999         struct resource res;
2000         void __iomem *xbar;
2001         s16 (*xbar_chans)[2];
2002         size_t nelm = sz / sizeof(s16);
2003         u32 shift, offset, mux;
2004         int ret, i;
2005
2006         xbar_chans = devm_kcalloc(dev, nelm + 2, sizeof(s16), GFP_KERNEL);
2007         if (!xbar_chans)
2008                 return -ENOMEM;
2009
2010         ret = of_address_to_resource(dev->of_node, 1, &res);
2011         if (ret)
2012                 return -ENOMEM;
2013
2014         xbar = devm_ioremap(dev, res.start, resource_size(&res));
2015         if (!xbar)
2016                 return -ENOMEM;
2017
2018         ret = of_property_read_u16_array(dev->of_node, pname, (u16 *)xbar_chans,
2019                                          nelm);
2020         if (ret)
2021                 return -EIO;
2022
2023         /* Invalidate last entry for the other user of this mess */
2024         nelm >>= 1;
2025         xbar_chans[nelm][0] = -1;
2026         xbar_chans[nelm][1] = -1;
2027
2028         for (i = 0; i < nelm; i++) {
2029                 shift = (xbar_chans[i][1] & 0x03) << 3;
2030                 offset = xbar_chans[i][1] & 0xfffffffc;
2031                 mux = readl(xbar + offset);
2032                 mux &= ~(0xff << shift);
2033                 mux |= xbar_chans[i][0] << shift;
2034                 writel(mux, (xbar + offset));
2035         }
2036
2037         pdata->xbar_chans = (const s16 (*)[2]) xbar_chans;
2038         return 0;
2039 }
2040
2041 static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
2042                                                      bool legacy_mode)
2043 {
2044         struct edma_soc_info *info;
2045         struct property *prop;
2046         int sz, ret;
2047
2048         info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL);
2049         if (!info)
2050                 return ERR_PTR(-ENOMEM);
2051
2052         if (legacy_mode) {
2053                 prop = of_find_property(dev->of_node, "ti,edma-xbar-event-map",
2054                                         &sz);
2055                 if (prop) {
2056                         ret = edma_xbar_event_map(dev, info, sz);
2057                         if (ret)
2058                                 return ERR_PTR(ret);
2059                 }
2060                 return info;
2061         }
2062
2063         /* Get the list of channels allocated to be used for memcpy */
2064         prop = of_find_property(dev->of_node, "ti,edma-memcpy-channels", &sz);
2065         if (prop) {
2066                 const char pname[] = "ti,edma-memcpy-channels";
2067                 size_t nelm = sz / sizeof(s32);
2068                 s32 *memcpy_ch;
2069
2070                 memcpy_ch = devm_kcalloc(dev, nelm + 1, sizeof(s32),
2071                                          GFP_KERNEL);
2072                 if (!memcpy_ch)
2073                         return ERR_PTR(-ENOMEM);
2074
2075                 ret = of_property_read_u32_array(dev->of_node, pname,
2076                                                  (u32 *)memcpy_ch, nelm);
2077                 if (ret)
2078                         return ERR_PTR(ret);
2079
2080                 memcpy_ch[nelm] = -1;
2081                 info->memcpy_channels = memcpy_ch;
2082         }
2083
2084         prop = of_find_property(dev->of_node, "ti,edma-reserved-slot-ranges",
2085                                 &sz);
2086         if (prop) {
2087                 const char pname[] = "ti,edma-reserved-slot-ranges";
2088                 u32 (*tmp)[2];
2089                 s16 (*rsv_slots)[2];
2090                 size_t nelm = sz / sizeof(*tmp);
2091                 struct edma_rsv_info *rsv_info;
2092                 int i;
2093
2094                 if (!nelm)
2095                         return info;
2096
2097                 tmp = kcalloc(nelm, sizeof(*tmp), GFP_KERNEL);
2098                 if (!tmp)
2099                         return ERR_PTR(-ENOMEM);
2100
2101                 rsv_info = devm_kzalloc(dev, sizeof(*rsv_info), GFP_KERNEL);
2102                 if (!rsv_info) {
2103                         kfree(tmp);
2104                         return ERR_PTR(-ENOMEM);
2105                 }
2106
2107                 rsv_slots = devm_kcalloc(dev, nelm + 1, sizeof(*rsv_slots),
2108                                          GFP_KERNEL);
2109                 if (!rsv_slots) {
2110                         kfree(tmp);
2111                         return ERR_PTR(-ENOMEM);
2112                 }
2113
2114                 ret = of_property_read_u32_array(dev->of_node, pname,
2115                                                  (u32 *)tmp, nelm * 2);
2116                 if (ret) {
2117                         kfree(tmp);
2118                         return ERR_PTR(ret);
2119                 }
2120
2121                 for (i = 0; i < nelm; i++) {
2122                         rsv_slots[i][0] = tmp[i][0];
2123                         rsv_slots[i][1] = tmp[i][1];
2124                 }
2125                 rsv_slots[nelm][0] = -1;
2126                 rsv_slots[nelm][1] = -1;
2127
2128                 info->rsv = rsv_info;
2129                 info->rsv->rsv_slots = (const s16 (*)[2])rsv_slots;
2130
2131                 kfree(tmp);
2132         }
2133
2134         return info;
2135 }
2136
2137 static struct dma_chan *of_edma_xlate(struct of_phandle_args *dma_spec,
2138                                       struct of_dma *ofdma)
2139 {
2140         struct edma_cc *ecc = ofdma->of_dma_data;
2141         struct dma_chan *chan = NULL;
2142         struct edma_chan *echan;
2143         int i;
2144
2145         if (!ecc || dma_spec->args_count < 1)
2146                 return NULL;
2147
2148         for (i = 0; i < ecc->num_channels; i++) {
2149                 echan = &ecc->slave_chans[i];
2150                 if (echan->ch_num == dma_spec->args[0]) {
2151                         chan = &echan->vchan.chan;
2152                         break;
2153                 }
2154         }
2155
2156         if (!chan)
2157                 return NULL;
2158
2159         if (echan->ecc->legacy_mode && dma_spec->args_count == 1)
2160                 goto out;
2161
2162         if (!echan->ecc->legacy_mode && dma_spec->args_count == 2 &&
2163             dma_spec->args[1] < echan->ecc->num_tc) {
2164                 echan->tc = &echan->ecc->tc_list[dma_spec->args[1]];
2165                 goto out;
2166         }
2167
2168         return NULL;
2169 out:
2170         /* The channel is going to be used as HW synchronized */
2171         echan->hw_triggered = true;
2172         return dma_get_slave_channel(chan);
2173 }
2174 #else
2175 static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
2176                                                      bool legacy_mode)
2177 {
2178         return ERR_PTR(-EINVAL);
2179 }
2180
2181 static struct dma_chan *of_edma_xlate(struct of_phandle_args *dma_spec,
2182                                       struct of_dma *ofdma)
2183 {
2184         return NULL;
2185 }
2186 #endif
2187
2188 static int edma_probe(struct platform_device *pdev)
2189 {
2190         struct edma_soc_info    *info = pdev->dev.platform_data;
2191         s8                      (*queue_priority_mapping)[2];
2192         int                     i, off, ln;
2193         const s16               (*rsv_slots)[2];
2194         const s16               (*xbar_chans)[2];
2195         int                     irq;
2196         char                    *irq_name;
2197         struct resource         *mem;
2198         struct device_node      *node = pdev->dev.of_node;
2199         struct device           *dev = &pdev->dev;
2200         struct edma_cc          *ecc;
2201         bool                    legacy_mode = true;
2202         int ret;
2203
2204         if (node) {
2205                 const struct of_device_id *match;
2206
2207                 match = of_match_node(edma_of_ids, node);
2208                 if (match && (*(u32 *)match->data) == EDMA_BINDING_TPCC)
2209                         legacy_mode = false;
2210
2211                 info = edma_setup_info_from_dt(dev, legacy_mode);
2212                 if (IS_ERR(info)) {
2213                         dev_err(dev, "failed to get DT data\n");
2214                         return PTR_ERR(info);
2215                 }
2216         }
2217
2218         if (!info)
2219                 return -ENODEV;
2220
2221         pm_runtime_enable(dev);
2222         ret = pm_runtime_get_sync(dev);
2223         if (ret < 0) {
2224                 dev_err(dev, "pm_runtime_get_sync() failed\n");
2225                 return ret;
2226         }
2227
2228         ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
2229         if (ret)
2230                 return ret;
2231
2232         ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
2233         if (!ecc)
2234                 return -ENOMEM;
2235
2236         ecc->dev = dev;
2237         ecc->id = pdev->id;
2238         ecc->legacy_mode = legacy_mode;
2239         /* When booting with DT the pdev->id is -1 */
2240         if (ecc->id < 0)
2241                 ecc->id = 0;
2242
2243         mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "edma3_cc");
2244         if (!mem) {
2245                 dev_dbg(dev, "mem resource not found, using index 0\n");
2246                 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2247                 if (!mem) {
2248                         dev_err(dev, "no mem resource?\n");
2249                         return -ENODEV;
2250                 }
2251         }
2252         ecc->base = devm_ioremap_resource(dev, mem);
2253         if (IS_ERR(ecc->base))
2254                 return PTR_ERR(ecc->base);
2255
2256         platform_set_drvdata(pdev, ecc);
2257
2258         /* Get eDMA3 configuration from IP */
2259         ret = edma_setup_from_hw(dev, info, ecc);
2260         if (ret)
2261                 return ret;
2262
2263         /* Allocate memory based on the information we got from the IP */
2264         ecc->slave_chans = devm_kcalloc(dev, ecc->num_channels,
2265                                         sizeof(*ecc->slave_chans), GFP_KERNEL);
2266         if (!ecc->slave_chans)
2267                 return -ENOMEM;
2268
2269         ecc->slot_inuse = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_slots),
2270                                        sizeof(unsigned long), GFP_KERNEL);
2271         if (!ecc->slot_inuse)
2272                 return -ENOMEM;
2273
2274         ecc->default_queue = info->default_queue;
2275
2276         for (i = 0; i < ecc->num_slots; i++)
2277                 edma_write_slot(ecc, i, &dummy_paramset);
2278
2279         if (info->rsv) {
2280                 /* Set the reserved slots in inuse list */
2281                 rsv_slots = info->rsv->rsv_slots;
2282                 if (rsv_slots) {
2283                         for (i = 0; rsv_slots[i][0] != -1; i++) {
2284                                 off = rsv_slots[i][0];
2285                                 ln = rsv_slots[i][1];
2286                                 edma_set_bits(off, ln, ecc->slot_inuse);
2287                         }
2288                 }
2289         }
2290
2291         /* Clear the xbar mapped channels in unused list */
2292         xbar_chans = info->xbar_chans;
2293         if (xbar_chans) {
2294                 for (i = 0; xbar_chans[i][1] != -1; i++) {
2295                         off = xbar_chans[i][1];
2296                 }
2297         }
2298
2299         irq = platform_get_irq_byname(pdev, "edma3_ccint");
2300         if (irq < 0 && node)
2301                 irq = irq_of_parse_and_map(node, 0);
2302
2303         if (irq >= 0) {
2304                 irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccint",
2305                                           dev_name(dev));
2306                 ret = devm_request_irq(dev, irq, dma_irq_handler, 0, irq_name,
2307                                        ecc);
2308                 if (ret) {
2309                         dev_err(dev, "CCINT (%d) failed --> %d\n", irq, ret);
2310                         return ret;
2311                 }
2312                 ecc->ccint = irq;
2313         }
2314
2315         irq = platform_get_irq_byname(pdev, "edma3_ccerrint");
2316         if (irq < 0 && node)
2317                 irq = irq_of_parse_and_map(node, 2);
2318
2319         if (irq >= 0) {
2320                 irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccerrint",
2321                                           dev_name(dev));
2322                 ret = devm_request_irq(dev, irq, dma_ccerr_handler, 0, irq_name,
2323                                        ecc);
2324                 if (ret) {
2325                         dev_err(dev, "CCERRINT (%d) failed --> %d\n", irq, ret);
2326                         return ret;
2327                 }
2328                 ecc->ccerrint = irq;
2329         }
2330
2331         ecc->dummy_slot = edma_alloc_slot(ecc, EDMA_SLOT_ANY);
2332         if (ecc->dummy_slot < 0) {
2333                 dev_err(dev, "Can't allocate PaRAM dummy slot\n");
2334                 return ecc->dummy_slot;
2335         }
2336
2337         queue_priority_mapping = info->queue_priority_mapping;
2338
2339         if (!ecc->legacy_mode) {
2340                 int lowest_priority = 0;
2341                 struct of_phandle_args tc_args;
2342
2343                 ecc->tc_list = devm_kcalloc(dev, ecc->num_tc,
2344                                             sizeof(*ecc->tc_list), GFP_KERNEL);
2345                 if (!ecc->tc_list)
2346                         return -ENOMEM;
2347
2348                 for (i = 0;; i++) {
2349                         ret = of_parse_phandle_with_fixed_args(node, "ti,tptcs",
2350                                                                1, i, &tc_args);
2351                         if (ret || i == ecc->num_tc)
2352                                 break;
2353
2354                         ecc->tc_list[i].node = tc_args.np;
2355                         ecc->tc_list[i].id = i;
2356                         queue_priority_mapping[i][1] = tc_args.args[0];
2357                         if (queue_priority_mapping[i][1] > lowest_priority) {
2358                                 lowest_priority = queue_priority_mapping[i][1];
2359                                 info->default_queue = i;
2360                         }
2361                 }
2362         }
2363
2364         /* Event queue priority mapping */
2365         for (i = 0; queue_priority_mapping[i][0] != -1; i++)
2366                 edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0],
2367                                               queue_priority_mapping[i][1]);
2368
2369         for (i = 0; i < ecc->num_region; i++) {
2370                 edma_write_array2(ecc, EDMA_DRAE, i, 0, 0x0);
2371                 edma_write_array2(ecc, EDMA_DRAE, i, 1, 0x0);
2372                 edma_write_array(ecc, EDMA_QRAE, i, 0x0);
2373         }
2374         ecc->info = info;
2375
2376         /* Init the dma device and channels */
2377         edma_dma_init(ecc, legacy_mode);
2378
2379         for (i = 0; i < ecc->num_channels; i++) {
2380                 /* Assign all channels to the default queue */
2381                 edma_assign_channel_eventq(&ecc->slave_chans[i],
2382                                            info->default_queue);
2383                 /* Set entry slot to the dummy slot */
2384                 edma_set_chmap(&ecc->slave_chans[i], ecc->dummy_slot);
2385         }
2386
2387         ecc->dma_slave.filter.map = info->slave_map;
2388         ecc->dma_slave.filter.mapcnt = info->slavecnt;
2389         ecc->dma_slave.filter.fn = edma_filter_fn;
2390
2391         ret = dma_async_device_register(&ecc->dma_slave);
2392         if (ret) {
2393                 dev_err(dev, "slave ddev registration failed (%d)\n", ret);
2394                 goto err_reg1;
2395         }
2396
2397         if (ecc->dma_memcpy) {
2398                 ret = dma_async_device_register(ecc->dma_memcpy);
2399                 if (ret) {
2400                         dev_err(dev, "memcpy ddev registration failed (%d)\n",
2401                                 ret);
2402                         dma_async_device_unregister(&ecc->dma_slave);
2403                         goto err_reg1;
2404                 }
2405         }
2406
2407         if (node)
2408                 of_dma_controller_register(node, of_edma_xlate, ecc);
2409
2410         dev_info(dev, "TI EDMA DMA engine driver\n");
2411
2412         return 0;
2413
2414 err_reg1:
2415         edma_free_slot(ecc, ecc->dummy_slot);
2416         return ret;
2417 }
2418
2419 static void edma_cleanupp_vchan(struct dma_device *dmadev)
2420 {
2421         struct edma_chan *echan, *_echan;
2422
2423         list_for_each_entry_safe(echan, _echan,
2424                         &dmadev->channels, vchan.chan.device_node) {
2425                 list_del(&echan->vchan.chan.device_node);
2426                 tasklet_kill(&echan->vchan.task);
2427         }
2428 }
2429
2430 static int edma_remove(struct platform_device *pdev)
2431 {
2432         struct device *dev = &pdev->dev;
2433         struct edma_cc *ecc = dev_get_drvdata(dev);
2434
2435         devm_free_irq(dev, ecc->ccint, ecc);
2436         devm_free_irq(dev, ecc->ccerrint, ecc);
2437
2438         edma_cleanupp_vchan(&ecc->dma_slave);
2439
2440         if (dev->of_node)
2441                 of_dma_controller_free(dev->of_node);
2442         dma_async_device_unregister(&ecc->dma_slave);
2443         if (ecc->dma_memcpy)
2444                 dma_async_device_unregister(ecc->dma_memcpy);
2445         edma_free_slot(ecc, ecc->dummy_slot);
2446
2447         return 0;
2448 }
2449
2450 #ifdef CONFIG_PM_SLEEP
2451 static int edma_pm_suspend(struct device *dev)
2452 {
2453         struct edma_cc *ecc = dev_get_drvdata(dev);
2454         struct edma_chan *echan = ecc->slave_chans;
2455         int i;
2456
2457         for (i = 0; i < ecc->num_channels; i++) {
2458                 if (echan[i].alloced)
2459                         edma_setup_interrupt(&echan[i], false);
2460         }
2461
2462         return 0;
2463 }
2464
2465 static int edma_pm_resume(struct device *dev)
2466 {
2467         struct edma_cc *ecc = dev_get_drvdata(dev);
2468         struct edma_chan *echan = ecc->slave_chans;
2469         int i;
2470         s8 (*queue_priority_mapping)[2];
2471
2472         /* re initialize dummy slot to dummy param set */
2473         edma_write_slot(ecc, ecc->dummy_slot, &dummy_paramset);
2474
2475         queue_priority_mapping = ecc->info->queue_priority_mapping;
2476
2477         /* Event queue priority mapping */
2478         for (i = 0; queue_priority_mapping[i][0] != -1; i++)
2479                 edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0],
2480                                               queue_priority_mapping[i][1]);
2481
2482         for (i = 0; i < ecc->num_channels; i++) {
2483                 if (echan[i].alloced) {
2484                         /* ensure access through shadow region 0 */
2485                         edma_or_array2(ecc, EDMA_DRAE, 0, i >> 5,
2486                                        BIT(i & 0x1f));
2487
2488                         edma_setup_interrupt(&echan[i], true);
2489
2490                         /* Set up channel -> slot mapping for the entry slot */
2491                         edma_set_chmap(&echan[i], echan[i].slot[0]);
2492                 }
2493         }
2494
2495         return 0;
2496 }
2497 #endif
2498
2499 static const struct dev_pm_ops edma_pm_ops = {
2500         SET_LATE_SYSTEM_SLEEP_PM_OPS(edma_pm_suspend, edma_pm_resume)
2501 };
2502
2503 static struct platform_driver edma_driver = {
2504         .probe          = edma_probe,
2505         .remove         = edma_remove,
2506         .driver = {
2507                 .name   = "edma",
2508                 .pm     = &edma_pm_ops,
2509                 .of_match_table = edma_of_ids,
2510         },
2511 };
2512
2513 static int edma_tptc_probe(struct platform_device *pdev)
2514 {
2515         pm_runtime_enable(&pdev->dev);
2516         return pm_runtime_get_sync(&pdev->dev);
2517 }
2518
2519 static struct platform_driver edma_tptc_driver = {
2520         .probe          = edma_tptc_probe,
2521         .driver = {
2522                 .name   = "edma3-tptc",
2523                 .of_match_table = edma_tptc_of_ids,
2524         },
2525 };
2526
2527 bool edma_filter_fn(struct dma_chan *chan, void *param)
2528 {
2529         bool match = false;
2530
2531         if (chan->device->dev->driver == &edma_driver.driver) {
2532                 struct edma_chan *echan = to_edma_chan(chan);
2533                 unsigned ch_req = *(unsigned *)param;
2534                 if (ch_req == echan->ch_num) {
2535                         /* The channel is going to be used as HW synchronized */
2536                         echan->hw_triggered = true;
2537                         match = true;
2538                 }
2539         }
2540         return match;
2541 }
2542 EXPORT_SYMBOL(edma_filter_fn);
2543
2544 static int edma_init(void)
2545 {
2546         int ret;
2547
2548         ret = platform_driver_register(&edma_tptc_driver);
2549         if (ret)
2550                 return ret;
2551
2552         return platform_driver_register(&edma_driver);
2553 }
2554 subsys_initcall(edma_init);
2555
2556 static void __exit edma_exit(void)
2557 {
2558         platform_driver_unregister(&edma_driver);
2559         platform_driver_unregister(&edma_tptc_driver);
2560 }
2561 module_exit(edma_exit);
2562
2563 MODULE_AUTHOR("Matt Porter <matt.porter@linaro.org>");
2564 MODULE_DESCRIPTION("TI EDMA DMA engine driver");
2565 MODULE_LICENSE("GPL v2");