drm/amdgpu/vg20:Restruct uvd.inst to support multiple instances
[muen/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_kms.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <drm/drmP.h>
29 #include "amdgpu.h"
30 #include <drm/amdgpu_drm.h>
31 #include "amdgpu_sched.h"
32 #include "amdgpu_uvd.h"
33 #include "amdgpu_vce.h"
34 #include "atom.h"
35
36 #include <linux/vga_switcheroo.h>
37 #include <linux/slab.h>
38 #include <linux/pm_runtime.h>
39 #include "amdgpu_amdkfd.h"
40
41 /**
42  * amdgpu_driver_unload_kms - Main unload function for KMS.
43  *
44  * @dev: drm dev pointer
45  *
46  * This is the main unload function for KMS (all asics).
47  * Returns 0 on success.
48  */
49 void amdgpu_driver_unload_kms(struct drm_device *dev)
50 {
51         struct amdgpu_device *adev = dev->dev_private;
52
53         if (adev == NULL)
54                 return;
55
56         if (adev->rmmio == NULL)
57                 goto done_free;
58
59         if (amdgpu_sriov_vf(adev))
60                 amdgpu_virt_request_full_gpu(adev, false);
61
62         if (amdgpu_device_is_px(dev)) {
63                 pm_runtime_get_sync(dev->dev);
64                 pm_runtime_forbid(dev->dev);
65         }
66
67         amdgpu_acpi_fini(adev);
68
69         amdgpu_device_fini(adev);
70
71 done_free:
72         kfree(adev);
73         dev->dev_private = NULL;
74 }
75
76 /**
77  * amdgpu_driver_load_kms - Main load function for KMS.
78  *
79  * @dev: drm dev pointer
80  * @flags: device flags
81  *
82  * This is the main load function for KMS (all asics).
83  * Returns 0 on success, error on failure.
84  */
85 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
86 {
87         struct amdgpu_device *adev;
88         int r, acpi_status;
89
90 #ifdef CONFIG_DRM_AMDGPU_SI
91         if (!amdgpu_si_support) {
92                 switch (flags & AMD_ASIC_MASK) {
93                 case CHIP_TAHITI:
94                 case CHIP_PITCAIRN:
95                 case CHIP_VERDE:
96                 case CHIP_OLAND:
97                 case CHIP_HAINAN:
98                         dev_info(dev->dev,
99                                  "SI support provided by radeon.\n");
100                         dev_info(dev->dev,
101                                  "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
102                                 );
103                         return -ENODEV;
104                 }
105         }
106 #endif
107 #ifdef CONFIG_DRM_AMDGPU_CIK
108         if (!amdgpu_cik_support) {
109                 switch (flags & AMD_ASIC_MASK) {
110                 case CHIP_KAVERI:
111                 case CHIP_BONAIRE:
112                 case CHIP_HAWAII:
113                 case CHIP_KABINI:
114                 case CHIP_MULLINS:
115                         dev_info(dev->dev,
116                                  "CIK support provided by radeon.\n");
117                         dev_info(dev->dev,
118                                  "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
119                                 );
120                         return -ENODEV;
121                 }
122         }
123 #endif
124
125         adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
126         if (adev == NULL) {
127                 return -ENOMEM;
128         }
129         dev->dev_private = (void *)adev;
130
131         if ((amdgpu_runtime_pm != 0) &&
132             amdgpu_has_atpx() &&
133             (amdgpu_is_atpx_hybrid() ||
134              amdgpu_has_atpx_dgpu_power_cntl()) &&
135             ((flags & AMD_IS_APU) == 0) &&
136             !pci_is_thunderbolt_attached(dev->pdev))
137                 flags |= AMD_IS_PX;
138
139         /* amdgpu_device_init should report only fatal error
140          * like memory allocation failure or iomapping failure,
141          * or memory manager initialization failure, it must
142          * properly initialize the GPU MC controller and permit
143          * VRAM allocation
144          */
145         r = amdgpu_device_init(adev, dev, dev->pdev, flags);
146         if (r) {
147                 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
148                 goto out;
149         }
150
151         /* Call ACPI methods: require modeset init
152          * but failure is not fatal
153          */
154         if (!r) {
155                 acpi_status = amdgpu_acpi_init(adev);
156                 if (acpi_status)
157                 dev_dbg(&dev->pdev->dev,
158                                 "Error during ACPI methods call\n");
159         }
160
161         if (amdgpu_device_is_px(dev)) {
162                 pm_runtime_use_autosuspend(dev->dev);
163                 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
164                 pm_runtime_set_active(dev->dev);
165                 pm_runtime_allow(dev->dev);
166                 pm_runtime_mark_last_busy(dev->dev);
167                 pm_runtime_put_autosuspend(dev->dev);
168         }
169
170 out:
171         if (r) {
172                 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
173                 if (adev->rmmio && amdgpu_device_is_px(dev))
174                         pm_runtime_put_noidle(dev->dev);
175                 amdgpu_driver_unload_kms(dev);
176         }
177
178         return r;
179 }
180
181 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
182                                 struct drm_amdgpu_query_fw *query_fw,
183                                 struct amdgpu_device *adev)
184 {
185         switch (query_fw->fw_type) {
186         case AMDGPU_INFO_FW_VCE:
187                 fw_info->ver = adev->vce.fw_version;
188                 fw_info->feature = adev->vce.fb_version;
189                 break;
190         case AMDGPU_INFO_FW_UVD:
191                 fw_info->ver = adev->uvd.fw_version;
192                 fw_info->feature = 0;
193                 break;
194         case AMDGPU_INFO_FW_VCN:
195                 fw_info->ver = adev->vcn.fw_version;
196                 fw_info->feature = 0;
197                 break;
198         case AMDGPU_INFO_FW_GMC:
199                 fw_info->ver = adev->gmc.fw_version;
200                 fw_info->feature = 0;
201                 break;
202         case AMDGPU_INFO_FW_GFX_ME:
203                 fw_info->ver = adev->gfx.me_fw_version;
204                 fw_info->feature = adev->gfx.me_feature_version;
205                 break;
206         case AMDGPU_INFO_FW_GFX_PFP:
207                 fw_info->ver = adev->gfx.pfp_fw_version;
208                 fw_info->feature = adev->gfx.pfp_feature_version;
209                 break;
210         case AMDGPU_INFO_FW_GFX_CE:
211                 fw_info->ver = adev->gfx.ce_fw_version;
212                 fw_info->feature = adev->gfx.ce_feature_version;
213                 break;
214         case AMDGPU_INFO_FW_GFX_RLC:
215                 fw_info->ver = adev->gfx.rlc_fw_version;
216                 fw_info->feature = adev->gfx.rlc_feature_version;
217                 break;
218         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
219                 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
220                 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
221                 break;
222         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
223                 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
224                 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
225                 break;
226         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
227                 fw_info->ver = adev->gfx.rlc_srls_fw_version;
228                 fw_info->feature = adev->gfx.rlc_srls_feature_version;
229                 break;
230         case AMDGPU_INFO_FW_GFX_MEC:
231                 if (query_fw->index == 0) {
232                         fw_info->ver = adev->gfx.mec_fw_version;
233                         fw_info->feature = adev->gfx.mec_feature_version;
234                 } else if (query_fw->index == 1) {
235                         fw_info->ver = adev->gfx.mec2_fw_version;
236                         fw_info->feature = adev->gfx.mec2_feature_version;
237                 } else
238                         return -EINVAL;
239                 break;
240         case AMDGPU_INFO_FW_SMC:
241                 fw_info->ver = adev->pm.fw_version;
242                 fw_info->feature = 0;
243                 break;
244         case AMDGPU_INFO_FW_SDMA:
245                 if (query_fw->index >= adev->sdma.num_instances)
246                         return -EINVAL;
247                 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
248                 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
249                 break;
250         case AMDGPU_INFO_FW_SOS:
251                 fw_info->ver = adev->psp.sos_fw_version;
252                 fw_info->feature = adev->psp.sos_feature_version;
253                 break;
254         case AMDGPU_INFO_FW_ASD:
255                 fw_info->ver = adev->psp.asd_fw_version;
256                 fw_info->feature = adev->psp.asd_feature_version;
257                 break;
258         default:
259                 return -EINVAL;
260         }
261         return 0;
262 }
263
264 /*
265  * Userspace get information ioctl
266  */
267 /**
268  * amdgpu_info_ioctl - answer a device specific request.
269  *
270  * @adev: amdgpu device pointer
271  * @data: request object
272  * @filp: drm filp
273  *
274  * This function is used to pass device specific parameters to the userspace
275  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
276  * etc. (all asics).
277  * Returns 0 on success, -EINVAL on failure.
278  */
279 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
280 {
281         struct amdgpu_device *adev = dev->dev_private;
282         struct drm_amdgpu_info *info = data;
283         struct amdgpu_mode_info *minfo = &adev->mode_info;
284         void __user *out = (void __user *)(uintptr_t)info->return_pointer;
285         uint32_t size = info->return_size;
286         struct drm_crtc *crtc;
287         uint32_t ui32 = 0;
288         uint64_t ui64 = 0;
289         int i, j, found;
290         int ui32_size = sizeof(ui32);
291
292         if (!info->return_size || !info->return_pointer)
293                 return -EINVAL;
294
295         /* Ensure IB tests are run on ring */
296         flush_delayed_work(&adev->late_init_work);
297
298         switch (info->query) {
299         case AMDGPU_INFO_ACCEL_WORKING:
300                 ui32 = adev->accel_working;
301                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
302         case AMDGPU_INFO_CRTC_FROM_ID:
303                 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
304                         crtc = (struct drm_crtc *)minfo->crtcs[i];
305                         if (crtc && crtc->base.id == info->mode_crtc.id) {
306                                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
307                                 ui32 = amdgpu_crtc->crtc_id;
308                                 found = 1;
309                                 break;
310                         }
311                 }
312                 if (!found) {
313                         DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
314                         return -EINVAL;
315                 }
316                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
317         case AMDGPU_INFO_HW_IP_INFO: {
318                 struct drm_amdgpu_info_hw_ip ip = {};
319                 enum amd_ip_block_type type;
320                 uint32_t ring_mask = 0;
321                 uint32_t ib_start_alignment = 0;
322                 uint32_t ib_size_alignment = 0;
323
324                 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
325                         return -EINVAL;
326
327                 switch (info->query_hw_ip.type) {
328                 case AMDGPU_HW_IP_GFX:
329                         type = AMD_IP_BLOCK_TYPE_GFX;
330                         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
331                                 ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i);
332                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
333                         ib_size_alignment = 8;
334                         break;
335                 case AMDGPU_HW_IP_COMPUTE:
336                         type = AMD_IP_BLOCK_TYPE_GFX;
337                         for (i = 0; i < adev->gfx.num_compute_rings; i++)
338                                 ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i);
339                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
340                         ib_size_alignment = 8;
341                         break;
342                 case AMDGPU_HW_IP_DMA:
343                         type = AMD_IP_BLOCK_TYPE_SDMA;
344                         for (i = 0; i < adev->sdma.num_instances; i++)
345                                 ring_mask |= ((adev->sdma.instance[i].ring.ready ? 1 : 0) << i);
346                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
347                         ib_size_alignment = 1;
348                         break;
349                 case AMDGPU_HW_IP_UVD:
350                         type = AMD_IP_BLOCK_TYPE_UVD;
351                         for (i = 0; i < adev->uvd.num_uvd_inst; i++)
352                                 ring_mask |= ((adev->uvd.inst[i].ring.ready ? 1 : 0) << i);
353                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
354                         ib_size_alignment = 16;
355                         break;
356                 case AMDGPU_HW_IP_VCE:
357                         type = AMD_IP_BLOCK_TYPE_VCE;
358                         for (i = 0; i < adev->vce.num_rings; i++)
359                                 ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i);
360                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
361                         ib_size_alignment = 1;
362                         break;
363                 case AMDGPU_HW_IP_UVD_ENC:
364                         type = AMD_IP_BLOCK_TYPE_UVD;
365                         for (i = 0; i < adev->uvd.num_uvd_inst; i++)
366                                 for (j = 0; j < adev->uvd.num_enc_rings; j++)
367                                         ring_mask |=
368                                         ((adev->uvd.inst[i].ring_enc[j].ready ? 1 : 0) <<
369                                         (j + i * adev->uvd.num_enc_rings));
370                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
371                         ib_size_alignment = 1;
372                         break;
373                 case AMDGPU_HW_IP_VCN_DEC:
374                         type = AMD_IP_BLOCK_TYPE_VCN;
375                         ring_mask = adev->vcn.ring_dec.ready ? 1 : 0;
376                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
377                         ib_size_alignment = 16;
378                         break;
379                 case AMDGPU_HW_IP_VCN_ENC:
380                         type = AMD_IP_BLOCK_TYPE_VCN;
381                         for (i = 0; i < adev->vcn.num_enc_rings; i++)
382                                 ring_mask |= ((adev->vcn.ring_enc[i].ready ? 1 : 0) << i);
383                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
384                         ib_size_alignment = 1;
385                         break;
386                 default:
387                         return -EINVAL;
388                 }
389
390                 for (i = 0; i < adev->num_ip_blocks; i++) {
391                         if (adev->ip_blocks[i].version->type == type &&
392                             adev->ip_blocks[i].status.valid) {
393                                 ip.hw_ip_version_major = adev->ip_blocks[i].version->major;
394                                 ip.hw_ip_version_minor = adev->ip_blocks[i].version->minor;
395                                 ip.capabilities_flags = 0;
396                                 ip.available_rings = ring_mask;
397                                 ip.ib_start_alignment = ib_start_alignment;
398                                 ip.ib_size_alignment = ib_size_alignment;
399                                 break;
400                         }
401                 }
402                 return copy_to_user(out, &ip,
403                                     min((size_t)size, sizeof(ip))) ? -EFAULT : 0;
404         }
405         case AMDGPU_INFO_HW_IP_COUNT: {
406                 enum amd_ip_block_type type;
407                 uint32_t count = 0;
408
409                 switch (info->query_hw_ip.type) {
410                 case AMDGPU_HW_IP_GFX:
411                         type = AMD_IP_BLOCK_TYPE_GFX;
412                         break;
413                 case AMDGPU_HW_IP_COMPUTE:
414                         type = AMD_IP_BLOCK_TYPE_GFX;
415                         break;
416                 case AMDGPU_HW_IP_DMA:
417                         type = AMD_IP_BLOCK_TYPE_SDMA;
418                         break;
419                 case AMDGPU_HW_IP_UVD:
420                         type = AMD_IP_BLOCK_TYPE_UVD;
421                         break;
422                 case AMDGPU_HW_IP_VCE:
423                         type = AMD_IP_BLOCK_TYPE_VCE;
424                         break;
425                 case AMDGPU_HW_IP_UVD_ENC:
426                         type = AMD_IP_BLOCK_TYPE_UVD;
427                         break;
428                 case AMDGPU_HW_IP_VCN_DEC:
429                 case AMDGPU_HW_IP_VCN_ENC:
430                         type = AMD_IP_BLOCK_TYPE_VCN;
431                         break;
432                 default:
433                         return -EINVAL;
434                 }
435
436                 for (i = 0; i < adev->num_ip_blocks; i++)
437                         if (adev->ip_blocks[i].version->type == type &&
438                             adev->ip_blocks[i].status.valid &&
439                             count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
440                                 count++;
441
442                 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
443         }
444         case AMDGPU_INFO_TIMESTAMP:
445                 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
446                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
447         case AMDGPU_INFO_FW_VERSION: {
448                 struct drm_amdgpu_info_firmware fw_info;
449                 int ret;
450
451                 /* We only support one instance of each IP block right now. */
452                 if (info->query_fw.ip_instance != 0)
453                         return -EINVAL;
454
455                 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
456                 if (ret)
457                         return ret;
458
459                 return copy_to_user(out, &fw_info,
460                                     min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
461         }
462         case AMDGPU_INFO_NUM_BYTES_MOVED:
463                 ui64 = atomic64_read(&adev->num_bytes_moved);
464                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
465         case AMDGPU_INFO_NUM_EVICTIONS:
466                 ui64 = atomic64_read(&adev->num_evictions);
467                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
468         case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
469                 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
470                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
471         case AMDGPU_INFO_VRAM_USAGE:
472                 ui64 = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
473                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
474         case AMDGPU_INFO_VIS_VRAM_USAGE:
475                 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
476                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
477         case AMDGPU_INFO_GTT_USAGE:
478                 ui64 = amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
479                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
480         case AMDGPU_INFO_GDS_CONFIG: {
481                 struct drm_amdgpu_info_gds gds_info;
482
483                 memset(&gds_info, 0, sizeof(gds_info));
484                 gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT;
485                 gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT;
486                 gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT;
487                 gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT;
488                 gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT;
489                 gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT;
490                 gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT;
491                 return copy_to_user(out, &gds_info,
492                                     min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
493         }
494         case AMDGPU_INFO_VRAM_GTT: {
495                 struct drm_amdgpu_info_vram_gtt vram_gtt;
496
497                 vram_gtt.vram_size = adev->gmc.real_vram_size;
498                 vram_gtt.vram_size -= adev->vram_pin_size;
499                 vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size;
500                 vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size);
501                 vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size;
502                 vram_gtt.gtt_size *= PAGE_SIZE;
503                 vram_gtt.gtt_size -= adev->gart_pin_size;
504                 return copy_to_user(out, &vram_gtt,
505                                     min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
506         }
507         case AMDGPU_INFO_MEMORY: {
508                 struct drm_amdgpu_memory_info mem;
509
510                 memset(&mem, 0, sizeof(mem));
511                 mem.vram.total_heap_size = adev->gmc.real_vram_size;
512                 mem.vram.usable_heap_size =
513                         adev->gmc.real_vram_size - adev->vram_pin_size;
514                 mem.vram.heap_usage =
515                         amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
516                 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
517
518                 mem.cpu_accessible_vram.total_heap_size =
519                         adev->gmc.visible_vram_size;
520                 mem.cpu_accessible_vram.usable_heap_size =
521                         adev->gmc.visible_vram_size -
522                         (adev->vram_pin_size - adev->invisible_pin_size);
523                 mem.cpu_accessible_vram.heap_usage =
524                         amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
525                 mem.cpu_accessible_vram.max_allocation =
526                         mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
527
528                 mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size;
529                 mem.gtt.total_heap_size *= PAGE_SIZE;
530                 mem.gtt.usable_heap_size = mem.gtt.total_heap_size
531                         - adev->gart_pin_size;
532                 mem.gtt.heap_usage =
533                         amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
534                 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
535
536                 return copy_to_user(out, &mem,
537                                     min((size_t)size, sizeof(mem)))
538                                     ? -EFAULT : 0;
539         }
540         case AMDGPU_INFO_READ_MMR_REG: {
541                 unsigned n, alloc_size;
542                 uint32_t *regs;
543                 unsigned se_num = (info->read_mmr_reg.instance >>
544                                    AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
545                                   AMDGPU_INFO_MMR_SE_INDEX_MASK;
546                 unsigned sh_num = (info->read_mmr_reg.instance >>
547                                    AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
548                                   AMDGPU_INFO_MMR_SH_INDEX_MASK;
549
550                 /* set full masks if the userspace set all bits
551                  * in the bitfields */
552                 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
553                         se_num = 0xffffffff;
554                 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
555                         sh_num = 0xffffffff;
556
557                 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
558                 if (!regs)
559                         return -ENOMEM;
560                 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
561
562                 for (i = 0; i < info->read_mmr_reg.count; i++)
563                         if (amdgpu_asic_read_register(adev, se_num, sh_num,
564                                                       info->read_mmr_reg.dword_offset + i,
565                                                       &regs[i])) {
566                                 DRM_DEBUG_KMS("unallowed offset %#x\n",
567                                               info->read_mmr_reg.dword_offset + i);
568                                 kfree(regs);
569                                 return -EFAULT;
570                         }
571                 n = copy_to_user(out, regs, min(size, alloc_size));
572                 kfree(regs);
573                 return n ? -EFAULT : 0;
574         }
575         case AMDGPU_INFO_DEV_INFO: {
576                 struct drm_amdgpu_info_device dev_info = {};
577                 uint64_t vm_size;
578
579                 dev_info.device_id = dev->pdev->device;
580                 dev_info.chip_rev = adev->rev_id;
581                 dev_info.external_rev = adev->external_rev_id;
582                 dev_info.pci_rev = dev->pdev->revision;
583                 dev_info.family = adev->family;
584                 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines;
585                 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
586                 /* return all clocks in KHz */
587                 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
588                 if (adev->pm.dpm_enabled) {
589                         dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
590                         dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
591                 } else {
592                         dev_info.max_engine_clock = adev->clock.default_sclk * 10;
593                         dev_info.max_memory_clock = adev->clock.default_mclk * 10;
594                 }
595                 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
596                 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *
597                         adev->gfx.config.max_shader_engines;
598                 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
599                 dev_info._pad = 0;
600                 dev_info.ids_flags = 0;
601                 if (adev->flags & AMD_IS_APU)
602                         dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
603                 if (amdgpu_sriov_vf(adev))
604                         dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
605
606                 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
607                 vm_size -= AMDGPU_VA_RESERVED_SIZE;
608
609                 /* Older VCE FW versions are buggy and can handle only 40bits */
610                 if (adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
611                         vm_size = min(vm_size, 1ULL << 40);
612
613                 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
614                 dev_info.virtual_address_max =
615                         min(vm_size, AMDGPU_VA_HOLE_START);
616
617                 if (vm_size > AMDGPU_VA_HOLE_START) {
618                         dev_info.high_va_offset = AMDGPU_VA_HOLE_END;
619                         dev_info.high_va_max = AMDGPU_VA_HOLE_END | vm_size;
620                 }
621                 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
622                 dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
623                 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
624                 dev_info.cu_active_number = adev->gfx.cu_info.number;
625                 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
626                 dev_info.ce_ram_size = adev->gfx.ce_ram_size;
627                 memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
628                        sizeof(adev->gfx.cu_info.ao_cu_bitmap));
629                 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
630                        sizeof(adev->gfx.cu_info.bitmap));
631                 dev_info.vram_type = adev->gmc.vram_type;
632                 dev_info.vram_bit_width = adev->gmc.vram_width;
633                 dev_info.vce_harvest_config = adev->vce.harvest_config;
634                 dev_info.gc_double_offchip_lds_buf =
635                         adev->gfx.config.double_offchip_lds_buf;
636
637                 if (amdgpu_ngg) {
638                         dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PRIM].gpu_addr;
639                         dev_info.prim_buf_size = adev->gfx.ngg.buf[NGG_PRIM].size;
640                         dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[NGG_POS].gpu_addr;
641                         dev_info.pos_buf_size = adev->gfx.ngg.buf[NGG_POS].size;
642                         dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[NGG_CNTL].gpu_addr;
643                         dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[NGG_CNTL].size;
644                         dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PARAM].gpu_addr;
645                         dev_info.param_buf_size = adev->gfx.ngg.buf[NGG_PARAM].size;
646                 }
647                 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size;
648                 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs;
649                 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
650                 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
651                 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
652                 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
653                 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
654
655                 return copy_to_user(out, &dev_info,
656                                     min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
657         }
658         case AMDGPU_INFO_VCE_CLOCK_TABLE: {
659                 unsigned i;
660                 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
661                 struct amd_vce_state *vce_state;
662
663                 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
664                         vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
665                         if (vce_state) {
666                                 vce_clk_table.entries[i].sclk = vce_state->sclk;
667                                 vce_clk_table.entries[i].mclk = vce_state->mclk;
668                                 vce_clk_table.entries[i].eclk = vce_state->evclk;
669                                 vce_clk_table.num_valid_entries++;
670                         }
671                 }
672
673                 return copy_to_user(out, &vce_clk_table,
674                                     min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
675         }
676         case AMDGPU_INFO_VBIOS: {
677                 uint32_t bios_size = adev->bios_size;
678
679                 switch (info->vbios_info.type) {
680                 case AMDGPU_INFO_VBIOS_SIZE:
681                         return copy_to_user(out, &bios_size,
682                                         min((size_t)size, sizeof(bios_size)))
683                                         ? -EFAULT : 0;
684                 case AMDGPU_INFO_VBIOS_IMAGE: {
685                         uint8_t *bios;
686                         uint32_t bios_offset = info->vbios_info.offset;
687
688                         if (bios_offset >= bios_size)
689                                 return -EINVAL;
690
691                         bios = adev->bios + bios_offset;
692                         return copy_to_user(out, bios,
693                                             min((size_t)size, (size_t)(bios_size - bios_offset)))
694                                         ? -EFAULT : 0;
695                 }
696                 default:
697                         DRM_DEBUG_KMS("Invalid request %d\n",
698                                         info->vbios_info.type);
699                         return -EINVAL;
700                 }
701         }
702         case AMDGPU_INFO_NUM_HANDLES: {
703                 struct drm_amdgpu_info_num_handles handle;
704
705                 switch (info->query_hw_ip.type) {
706                 case AMDGPU_HW_IP_UVD:
707                         /* Starting Polaris, we support unlimited UVD handles */
708                         if (adev->asic_type < CHIP_POLARIS10) {
709                                 handle.uvd_max_handles = adev->uvd.max_handles;
710                                 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
711
712                                 return copy_to_user(out, &handle,
713                                         min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
714                         } else {
715                                 return -ENODATA;
716                         }
717
718                         break;
719                 default:
720                         return -EINVAL;
721                 }
722         }
723         case AMDGPU_INFO_SENSOR: {
724                 if (!adev->pm.dpm_enabled)
725                         return -ENOENT;
726
727                 switch (info->sensor_info.type) {
728                 case AMDGPU_INFO_SENSOR_GFX_SCLK:
729                         /* get sclk in Mhz */
730                         if (amdgpu_dpm_read_sensor(adev,
731                                                    AMDGPU_PP_SENSOR_GFX_SCLK,
732                                                    (void *)&ui32, &ui32_size)) {
733                                 return -EINVAL;
734                         }
735                         ui32 /= 100;
736                         break;
737                 case AMDGPU_INFO_SENSOR_GFX_MCLK:
738                         /* get mclk in Mhz */
739                         if (amdgpu_dpm_read_sensor(adev,
740                                                    AMDGPU_PP_SENSOR_GFX_MCLK,
741                                                    (void *)&ui32, &ui32_size)) {
742                                 return -EINVAL;
743                         }
744                         ui32 /= 100;
745                         break;
746                 case AMDGPU_INFO_SENSOR_GPU_TEMP:
747                         /* get temperature in millidegrees C */
748                         if (amdgpu_dpm_read_sensor(adev,
749                                                    AMDGPU_PP_SENSOR_GPU_TEMP,
750                                                    (void *)&ui32, &ui32_size)) {
751                                 return -EINVAL;
752                         }
753                         break;
754                 case AMDGPU_INFO_SENSOR_GPU_LOAD:
755                         /* get GPU load */
756                         if (amdgpu_dpm_read_sensor(adev,
757                                                    AMDGPU_PP_SENSOR_GPU_LOAD,
758                                                    (void *)&ui32, &ui32_size)) {
759                                 return -EINVAL;
760                         }
761                         break;
762                 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
763                         /* get average GPU power */
764                         if (amdgpu_dpm_read_sensor(adev,
765                                                    AMDGPU_PP_SENSOR_GPU_POWER,
766                                                    (void *)&ui32, &ui32_size)) {
767                                 return -EINVAL;
768                         }
769                         ui32 >>= 8;
770                         break;
771                 case AMDGPU_INFO_SENSOR_VDDNB:
772                         /* get VDDNB in millivolts */
773                         if (amdgpu_dpm_read_sensor(adev,
774                                                    AMDGPU_PP_SENSOR_VDDNB,
775                                                    (void *)&ui32, &ui32_size)) {
776                                 return -EINVAL;
777                         }
778                         break;
779                 case AMDGPU_INFO_SENSOR_VDDGFX:
780                         /* get VDDGFX in millivolts */
781                         if (amdgpu_dpm_read_sensor(adev,
782                                                    AMDGPU_PP_SENSOR_VDDGFX,
783                                                    (void *)&ui32, &ui32_size)) {
784                                 return -EINVAL;
785                         }
786                         break;
787                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
788                         /* get stable pstate sclk in Mhz */
789                         if (amdgpu_dpm_read_sensor(adev,
790                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
791                                                    (void *)&ui32, &ui32_size)) {
792                                 return -EINVAL;
793                         }
794                         ui32 /= 100;
795                         break;
796                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
797                         /* get stable pstate mclk in Mhz */
798                         if (amdgpu_dpm_read_sensor(adev,
799                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
800                                                    (void *)&ui32, &ui32_size)) {
801                                 return -EINVAL;
802                         }
803                         ui32 /= 100;
804                         break;
805                 default:
806                         DRM_DEBUG_KMS("Invalid request %d\n",
807                                       info->sensor_info.type);
808                         return -EINVAL;
809                 }
810                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
811         }
812         case AMDGPU_INFO_VRAM_LOST_COUNTER:
813                 ui32 = atomic_read(&adev->vram_lost_counter);
814                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
815         default:
816                 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
817                 return -EINVAL;
818         }
819         return 0;
820 }
821
822
823 /*
824  * Outdated mess for old drm with Xorg being in charge (void function now).
825  */
826 /**
827  * amdgpu_driver_lastclose_kms - drm callback for last close
828  *
829  * @dev: drm dev pointer
830  *
831  * Switch vga_switcheroo state after last close (all asics).
832  */
833 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
834 {
835         drm_fb_helper_lastclose(dev);
836         vga_switcheroo_process_delayed_switch();
837 }
838
839 /**
840  * amdgpu_driver_open_kms - drm callback for open
841  *
842  * @dev: drm dev pointer
843  * @file_priv: drm file
844  *
845  * On device open, init vm on cayman+ (all asics).
846  * Returns 0 on success, error on failure.
847  */
848 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
849 {
850         struct amdgpu_device *adev = dev->dev_private;
851         struct amdgpu_fpriv *fpriv;
852         int r, pasid;
853
854         file_priv->driver_priv = NULL;
855
856         r = pm_runtime_get_sync(dev->dev);
857         if (r < 0)
858                 return r;
859
860         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
861         if (unlikely(!fpriv)) {
862                 r = -ENOMEM;
863                 goto out_suspend;
864         }
865
866         pasid = amdgpu_pasid_alloc(16);
867         if (pasid < 0) {
868                 dev_warn(adev->dev, "No more PASIDs available!");
869                 pasid = 0;
870         }
871         r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid);
872         if (r)
873                 goto error_pasid;
874
875         fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
876         if (!fpriv->prt_va) {
877                 r = -ENOMEM;
878                 goto error_vm;
879         }
880
881         if (amdgpu_sriov_vf(adev)) {
882                 r = amdgpu_map_static_csa(adev, &fpriv->vm, &fpriv->csa_va);
883                 if (r)
884                         goto error_vm;
885         }
886
887         mutex_init(&fpriv->bo_list_lock);
888         idr_init(&fpriv->bo_list_handles);
889
890         amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
891
892         file_priv->driver_priv = fpriv;
893         goto out_suspend;
894
895 error_vm:
896         amdgpu_vm_fini(adev, &fpriv->vm);
897
898 error_pasid:
899         if (pasid)
900                 amdgpu_pasid_free(pasid);
901
902         kfree(fpriv);
903
904 out_suspend:
905         pm_runtime_mark_last_busy(dev->dev);
906         pm_runtime_put_autosuspend(dev->dev);
907
908         return r;
909 }
910
911 /**
912  * amdgpu_driver_postclose_kms - drm callback for post close
913  *
914  * @dev: drm dev pointer
915  * @file_priv: drm file
916  *
917  * On device post close, tear down vm on cayman+ (all asics).
918  */
919 void amdgpu_driver_postclose_kms(struct drm_device *dev,
920                                  struct drm_file *file_priv)
921 {
922         struct amdgpu_device *adev = dev->dev_private;
923         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
924         struct amdgpu_bo_list *list;
925         struct amdgpu_bo *pd;
926         unsigned int pasid;
927         int handle;
928
929         if (!fpriv)
930                 return;
931
932         pm_runtime_get_sync(dev->dev);
933         amdgpu_ctx_mgr_entity_fini(&fpriv->ctx_mgr);
934
935         if (adev->asic_type != CHIP_RAVEN) {
936                 amdgpu_uvd_free_handles(adev, file_priv);
937                 amdgpu_vce_free_handles(adev, file_priv);
938         }
939
940         amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
941
942         if (amdgpu_sriov_vf(adev)) {
943                 /* TODO: how to handle reserve failure */
944                 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
945                 amdgpu_vm_bo_rmv(adev, fpriv->csa_va);
946                 fpriv->csa_va = NULL;
947                 amdgpu_bo_unreserve(adev->virt.csa_obj);
948         }
949
950         pasid = fpriv->vm.pasid;
951         pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);
952
953         amdgpu_vm_fini(adev, &fpriv->vm);
954         amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
955
956         if (pasid)
957                 amdgpu_pasid_free_delayed(pd->tbo.resv, pasid);
958         amdgpu_bo_unref(&pd);
959
960         idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
961                 amdgpu_bo_list_free(list);
962
963         idr_destroy(&fpriv->bo_list_handles);
964         mutex_destroy(&fpriv->bo_list_lock);
965
966         kfree(fpriv);
967         file_priv->driver_priv = NULL;
968
969         pm_runtime_mark_last_busy(dev->dev);
970         pm_runtime_put_autosuspend(dev->dev);
971 }
972
973 /*
974  * VBlank related functions.
975  */
976 /**
977  * amdgpu_get_vblank_counter_kms - get frame count
978  *
979  * @dev: drm dev pointer
980  * @pipe: crtc to get the frame count from
981  *
982  * Gets the frame count on the requested crtc (all asics).
983  * Returns frame count on success, -EINVAL on failure.
984  */
985 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
986 {
987         struct amdgpu_device *adev = dev->dev_private;
988         int vpos, hpos, stat;
989         u32 count;
990
991         if (pipe >= adev->mode_info.num_crtc) {
992                 DRM_ERROR("Invalid crtc %u\n", pipe);
993                 return -EINVAL;
994         }
995
996         /* The hw increments its frame counter at start of vsync, not at start
997          * of vblank, as is required by DRM core vblank counter handling.
998          * Cook the hw count here to make it appear to the caller as if it
999          * incremented at start of vblank. We measure distance to start of
1000          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1001          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1002          * result by 1 to give the proper appearance to caller.
1003          */
1004         if (adev->mode_info.crtcs[pipe]) {
1005                 /* Repeat readout if needed to provide stable result if
1006                  * we cross start of vsync during the queries.
1007                  */
1008                 do {
1009                         count = amdgpu_display_vblank_get_counter(adev, pipe);
1010                         /* Ask amdgpu_display_get_crtc_scanoutpos to return
1011                          * vpos as distance to start of vblank, instead of
1012                          * regular vertical scanout pos.
1013                          */
1014                         stat = amdgpu_display_get_crtc_scanoutpos(
1015                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1016                                 &vpos, &hpos, NULL, NULL,
1017                                 &adev->mode_info.crtcs[pipe]->base.hwmode);
1018                 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1019
1020                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1021                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1022                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1023                 } else {
1024                         DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1025                                       pipe, vpos);
1026
1027                         /* Bump counter if we are at >= leading edge of vblank,
1028                          * but before vsync where vpos would turn negative and
1029                          * the hw counter really increments.
1030                          */
1031                         if (vpos >= 0)
1032                                 count++;
1033                 }
1034         } else {
1035                 /* Fallback to use value as is. */
1036                 count = amdgpu_display_vblank_get_counter(adev, pipe);
1037                 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1038         }
1039
1040         return count;
1041 }
1042
1043 /**
1044  * amdgpu_enable_vblank_kms - enable vblank interrupt
1045  *
1046  * @dev: drm dev pointer
1047  * @pipe: crtc to enable vblank interrupt for
1048  *
1049  * Enable the interrupt on the requested crtc (all asics).
1050  * Returns 0 on success, -EINVAL on failure.
1051  */
1052 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe)
1053 {
1054         struct amdgpu_device *adev = dev->dev_private;
1055         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1056
1057         return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1058 }
1059
1060 /**
1061  * amdgpu_disable_vblank_kms - disable vblank interrupt
1062  *
1063  * @dev: drm dev pointer
1064  * @pipe: crtc to disable vblank interrupt for
1065  *
1066  * Disable the interrupt on the requested crtc (all asics).
1067  */
1068 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe)
1069 {
1070         struct amdgpu_device *adev = dev->dev_private;
1071         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1072
1073         amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1074 }
1075
1076 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
1077         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1078         DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1079         DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1080         DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
1081         DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1082         DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1083         /* KMS */
1084         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1085         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1086         DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1087         DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1088         DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1089         DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1090         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1091         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1092         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1093         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW)
1094 };
1095 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
1096
1097 /*
1098  * Debugfs info
1099  */
1100 #if defined(CONFIG_DEBUG_FS)
1101
1102 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
1103 {
1104         struct drm_info_node *node = (struct drm_info_node *) m->private;
1105         struct drm_device *dev = node->minor->dev;
1106         struct amdgpu_device *adev = dev->dev_private;
1107         struct drm_amdgpu_info_firmware fw_info;
1108         struct drm_amdgpu_query_fw query_fw;
1109         struct atom_context *ctx = adev->mode_info.atom_context;
1110         int ret, i;
1111
1112         /* VCE */
1113         query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1114         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1115         if (ret)
1116                 return ret;
1117         seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1118                    fw_info.feature, fw_info.ver);
1119
1120         /* UVD */
1121         query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1122         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1123         if (ret)
1124                 return ret;
1125         seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1126                    fw_info.feature, fw_info.ver);
1127
1128         /* GMC */
1129         query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1130         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1131         if (ret)
1132                 return ret;
1133         seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1134                    fw_info.feature, fw_info.ver);
1135
1136         /* ME */
1137         query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1138         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1139         if (ret)
1140                 return ret;
1141         seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1142                    fw_info.feature, fw_info.ver);
1143
1144         /* PFP */
1145         query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1146         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1147         if (ret)
1148                 return ret;
1149         seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1150                    fw_info.feature, fw_info.ver);
1151
1152         /* CE */
1153         query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1154         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1155         if (ret)
1156                 return ret;
1157         seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1158                    fw_info.feature, fw_info.ver);
1159
1160         /* RLC */
1161         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1162         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1163         if (ret)
1164                 return ret;
1165         seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1166                    fw_info.feature, fw_info.ver);
1167
1168         /* RLC SAVE RESTORE LIST CNTL */
1169         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1170         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1171         if (ret)
1172                 return ret;
1173         seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1174                    fw_info.feature, fw_info.ver);
1175
1176         /* RLC SAVE RESTORE LIST GPM MEM */
1177         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1178         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1179         if (ret)
1180                 return ret;
1181         seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1182                    fw_info.feature, fw_info.ver);
1183
1184         /* RLC SAVE RESTORE LIST SRM MEM */
1185         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1186         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1187         if (ret)
1188                 return ret;
1189         seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1190                    fw_info.feature, fw_info.ver);
1191
1192         /* MEC */
1193         query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1194         query_fw.index = 0;
1195         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1196         if (ret)
1197                 return ret;
1198         seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1199                    fw_info.feature, fw_info.ver);
1200
1201         /* MEC2 */
1202         if (adev->asic_type == CHIP_KAVERI ||
1203             (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) {
1204                 query_fw.index = 1;
1205                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1206                 if (ret)
1207                         return ret;
1208                 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1209                            fw_info.feature, fw_info.ver);
1210         }
1211
1212         /* PSP SOS */
1213         query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1214         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1215         if (ret)
1216                 return ret;
1217         seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1218                    fw_info.feature, fw_info.ver);
1219
1220
1221         /* PSP ASD */
1222         query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1223         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1224         if (ret)
1225                 return ret;
1226         seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1227                    fw_info.feature, fw_info.ver);
1228
1229         /* SMC */
1230         query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1231         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1232         if (ret)
1233                 return ret;
1234         seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
1235                    fw_info.feature, fw_info.ver);
1236
1237         /* SDMA */
1238         query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1239         for (i = 0; i < adev->sdma.num_instances; i++) {
1240                 query_fw.index = i;
1241                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1242                 if (ret)
1243                         return ret;
1244                 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1245                            i, fw_info.feature, fw_info.ver);
1246         }
1247
1248         /* VCN */
1249         query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1250         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1251         if (ret)
1252                 return ret;
1253         seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1254                    fw_info.feature, fw_info.ver);
1255
1256
1257         seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1258
1259         return 0;
1260 }
1261
1262 static const struct drm_info_list amdgpu_firmware_info_list[] = {
1263         {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL},
1264 };
1265 #endif
1266
1267 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1268 {
1269 #if defined(CONFIG_DEBUG_FS)
1270         return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list,
1271                                         ARRAY_SIZE(amdgpu_firmware_info_list));
1272 #else
1273         return 0;
1274 #endif
1275 }