9f1a5bd39ae8a8667d31fe025bdf3f0e2fc5b99b
[muen/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_psp.c
1 /*
2  * Copyright 2016 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Author: Huang Rui
23  *
24  */
25
26 #include <linux/firmware.h>
27 #include <drm/drmP.h>
28 #include "amdgpu.h"
29 #include "amdgpu_psp.h"
30 #include "amdgpu_ucode.h"
31 #include "soc15_common.h"
32 #include "psp_v3_1.h"
33 #include "psp_v10_0.h"
34
35 static void psp_set_funcs(struct amdgpu_device *adev);
36
37 static int psp_early_init(void *handle)
38 {
39         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
40
41         psp_set_funcs(adev);
42
43         return 0;
44 }
45
46 static int psp_sw_init(void *handle)
47 {
48         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
49         struct psp_context *psp = &adev->psp;
50         int ret;
51
52         switch (adev->asic_type) {
53         case CHIP_VEGA10:
54         case CHIP_VEGA12:
55         case CHIP_VEGA20:
56                 psp_v3_1_set_psp_funcs(psp);
57                 break;
58         case CHIP_RAVEN:
59                 psp_v10_0_set_psp_funcs(psp);
60                 break;
61         default:
62                 return -EINVAL;
63         }
64
65         psp->adev = adev;
66
67         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
68                 return 0;
69
70         ret = psp_init_microcode(psp);
71         if (ret) {
72                 DRM_ERROR("Failed to load psp firmware!\n");
73                 return ret;
74         }
75
76         return 0;
77 }
78
79 static int psp_sw_fini(void *handle)
80 {
81         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
82
83         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
84                 return 0;
85
86         release_firmware(adev->psp.sos_fw);
87         adev->psp.sos_fw = NULL;
88         release_firmware(adev->psp.asd_fw);
89         adev->psp.asd_fw = NULL;
90         return 0;
91 }
92
93 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
94                  uint32_t reg_val, uint32_t mask, bool check_changed)
95 {
96         uint32_t val;
97         int i;
98         struct amdgpu_device *adev = psp->adev;
99
100         for (i = 0; i < adev->usec_timeout; i++) {
101                 val = RREG32(reg_index);
102                 if (check_changed) {
103                         if (val != reg_val)
104                                 return 0;
105                 } else {
106                         if ((val & mask) == reg_val)
107                                 return 0;
108                 }
109                 udelay(1);
110         }
111
112         return -ETIME;
113 }
114
115 static int
116 psp_cmd_submit_buf(struct psp_context *psp,
117                    struct amdgpu_firmware_info *ucode,
118                    struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr,
119                    int index)
120 {
121         int ret;
122
123         memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
124
125         memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
126
127         ret = psp_cmd_submit(psp, ucode, psp->cmd_buf_mc_addr,
128                              fence_mc_addr, index);
129
130         while (*((unsigned int *)psp->fence_buf) != index) {
131                 msleep(1);
132         }
133
134         return ret;
135 }
136
137 static void psp_prep_tmr_cmd_buf(struct psp_gfx_cmd_resp *cmd,
138                                  uint64_t tmr_mc, uint32_t size)
139 {
140         cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
141         cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
142         cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
143         cmd->cmd.cmd_setup_tmr.buf_size = size;
144 }
145
146 /* Set up Trusted Memory Region */
147 static int psp_tmr_init(struct psp_context *psp)
148 {
149         int ret;
150
151         /*
152          * Allocate 3M memory aligned to 1M from Frame Buffer (local
153          * physical).
154          *
155          * Note: this memory need be reserved till the driver
156          * uninitializes.
157          */
158         ret = amdgpu_bo_create_kernel(psp->adev, 0x300000, 0x100000,
159                                       AMDGPU_GEM_DOMAIN_VRAM,
160                                       &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
161
162         return ret;
163 }
164
165 static int psp_tmr_load(struct psp_context *psp)
166 {
167         int ret;
168         struct psp_gfx_cmd_resp *cmd;
169
170         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
171         if (!cmd)
172                 return -ENOMEM;
173
174         psp_prep_tmr_cmd_buf(cmd, psp->tmr_mc_addr, 0x300000);
175
176         ret = psp_cmd_submit_buf(psp, NULL, cmd,
177                                  psp->fence_buf_mc_addr, 1);
178         if (ret)
179                 goto failed;
180
181         kfree(cmd);
182
183         return 0;
184
185 failed:
186         kfree(cmd);
187         return ret;
188 }
189
190 static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd,
191                                  uint64_t asd_mc, uint64_t asd_mc_shared,
192                                  uint32_t size, uint32_t shared_size)
193 {
194         cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
195         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
196         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
197         cmd->cmd.cmd_load_ta.app_len = size;
198
199         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared);
200         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared);
201         cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
202 }
203
204 static int psp_asd_init(struct psp_context *psp)
205 {
206         int ret;
207
208         /*
209          * Allocate 16k memory aligned to 4k from Frame Buffer (local
210          * physical) for shared ASD <-> Driver
211          */
212         ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE,
213                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
214                                       &psp->asd_shared_bo,
215                                       &psp->asd_shared_mc_addr,
216                                       &psp->asd_shared_buf);
217
218         return ret;
219 }
220
221 static int psp_asd_load(struct psp_context *psp)
222 {
223         int ret;
224         struct psp_gfx_cmd_resp *cmd;
225
226         /* If PSP version doesn't match ASD version, asd loading will be failed.
227          * add workaround to bypass it for sriov now.
228          * TODO: add version check to make it common
229          */
230         if (amdgpu_sriov_vf(psp->adev))
231                 return 0;
232
233         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
234         if (!cmd)
235                 return -ENOMEM;
236
237         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
238         memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
239
240         psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr,
241                              psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE);
242
243         ret = psp_cmd_submit_buf(psp, NULL, cmd,
244                                  psp->fence_buf_mc_addr, 2);
245
246         kfree(cmd);
247
248         return ret;
249 }
250
251 static int psp_hw_start(struct psp_context *psp)
252 {
253         struct amdgpu_device *adev = psp->adev;
254         int ret;
255
256         if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) {
257                 ret = psp_bootloader_load_sysdrv(psp);
258                 if (ret)
259                         return ret;
260
261                 ret = psp_bootloader_load_sos(psp);
262                 if (ret)
263                         return ret;
264         }
265
266         ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
267         if (ret)
268                 return ret;
269
270         ret = psp_tmr_load(psp);
271         if (ret)
272                 return ret;
273
274         ret = psp_asd_load(psp);
275         if (ret)
276                 return ret;
277
278         return 0;
279 }
280
281 static int psp_np_fw_load(struct psp_context *psp)
282 {
283         int i, ret;
284         struct amdgpu_firmware_info *ucode;
285         struct amdgpu_device* adev = psp->adev;
286
287         for (i = 0; i < adev->firmware.max_ucodes; i++) {
288                 ucode = &adev->firmware.ucode[i];
289                 if (!ucode->fw)
290                         continue;
291
292                 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
293                     psp_smu_reload_quirk(psp))
294                         continue;
295                 if (amdgpu_sriov_vf(adev) &&
296                    (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
297                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
298                     || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G))
299                         /*skip ucode loading in SRIOV VF */
300                         continue;
301
302                 ret = psp_prep_cmd_buf(ucode, psp->cmd);
303                 if (ret)
304                         return ret;
305
306                 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
307                                          psp->fence_buf_mc_addr, i + 3);
308                 if (ret)
309                         return ret;
310
311 #if 0
312                 /* check if firmware loaded sucessfully */
313                 if (!amdgpu_psp_check_fw_loading_status(adev, i))
314                         return -EINVAL;
315 #endif
316         }
317
318         return 0;
319 }
320
321 static int psp_load_fw(struct amdgpu_device *adev)
322 {
323         int ret;
324         struct psp_context *psp = &adev->psp;
325
326         if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset != 0)
327                 goto skip_memalloc;
328
329         psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
330         if (!psp->cmd)
331                 return -ENOMEM;
332
333         ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
334                                         AMDGPU_GEM_DOMAIN_GTT,
335                                         &psp->fw_pri_bo,
336                                         &psp->fw_pri_mc_addr,
337                                         &psp->fw_pri_buf);
338         if (ret)
339                 goto failed;
340
341         ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
342                                         AMDGPU_GEM_DOMAIN_VRAM,
343                                         &psp->fence_buf_bo,
344                                         &psp->fence_buf_mc_addr,
345                                         &psp->fence_buf);
346         if (ret)
347                 goto failed_mem2;
348
349         ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
350                                       AMDGPU_GEM_DOMAIN_VRAM,
351                                       &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
352                                       (void **)&psp->cmd_buf_mem);
353         if (ret)
354                 goto failed_mem1;
355
356         memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
357
358         ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
359         if (ret)
360                 goto failed_mem;
361
362         ret = psp_tmr_init(psp);
363         if (ret)
364                 goto failed_mem;
365
366         ret = psp_asd_init(psp);
367         if (ret)
368                 goto failed_mem;
369
370 skip_memalloc:
371         ret = psp_hw_start(psp);
372         if (ret)
373                 goto failed_mem;
374
375         ret = psp_np_fw_load(psp);
376         if (ret)
377                 goto failed_mem;
378
379         return 0;
380
381 failed_mem:
382         amdgpu_bo_free_kernel(&psp->cmd_buf_bo,
383                               &psp->cmd_buf_mc_addr,
384                               (void **)&psp->cmd_buf_mem);
385 failed_mem1:
386         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
387                               &psp->fence_buf_mc_addr, &psp->fence_buf);
388 failed_mem2:
389         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
390                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
391 failed:
392         kfree(psp->cmd);
393         psp->cmd = NULL;
394         return ret;
395 }
396
397 static int psp_hw_init(void *handle)
398 {
399         int ret;
400         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
401
402
403         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
404                 return 0;
405
406         mutex_lock(&adev->firmware.mutex);
407         /*
408          * This sequence is just used on hw_init only once, no need on
409          * resume.
410          */
411         ret = amdgpu_ucode_init_bo(adev);
412         if (ret)
413                 goto failed;
414
415         ret = psp_load_fw(adev);
416         if (ret) {
417                 DRM_ERROR("PSP firmware loading failed\n");
418                 goto failed;
419         }
420
421         mutex_unlock(&adev->firmware.mutex);
422         return 0;
423
424 failed:
425         adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
426         mutex_unlock(&adev->firmware.mutex);
427         return -EINVAL;
428 }
429
430 static int psp_hw_fini(void *handle)
431 {
432         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
433         struct psp_context *psp = &adev->psp;
434
435         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
436                 return 0;
437
438         amdgpu_ucode_fini_bo(adev);
439
440         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
441
442         amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
443         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
444                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
445         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
446                               &psp->fence_buf_mc_addr, &psp->fence_buf);
447         amdgpu_bo_free_kernel(&psp->asd_shared_bo, &psp->asd_shared_mc_addr,
448                               &psp->asd_shared_buf);
449         amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
450                               (void **)&psp->cmd_buf_mem);
451
452         kfree(psp->cmd);
453         psp->cmd = NULL;
454
455         return 0;
456 }
457
458 static int psp_suspend(void *handle)
459 {
460         int ret;
461         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
462         struct psp_context *psp = &adev->psp;
463
464         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
465                 return 0;
466
467         ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
468         if (ret) {
469                 DRM_ERROR("PSP ring stop failed\n");
470                 return ret;
471         }
472
473         return 0;
474 }
475
476 static int psp_resume(void *handle)
477 {
478         int ret;
479         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
480         struct psp_context *psp = &adev->psp;
481
482         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
483                 return 0;
484
485         DRM_INFO("PSP is resuming...\n");
486
487         mutex_lock(&adev->firmware.mutex);
488
489         ret = psp_hw_start(psp);
490         if (ret)
491                 goto failed;
492
493         ret = psp_np_fw_load(psp);
494         if (ret)
495                 goto failed;
496
497         mutex_unlock(&adev->firmware.mutex);
498
499         return 0;
500
501 failed:
502         DRM_ERROR("PSP resume failed\n");
503         mutex_unlock(&adev->firmware.mutex);
504         return ret;
505 }
506
507 int psp_gpu_reset(struct amdgpu_device *adev)
508 {
509         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
510                 return 0;
511
512         return psp_mode1_reset(&adev->psp);
513 }
514
515 static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
516                                         enum AMDGPU_UCODE_ID ucode_type)
517 {
518         struct amdgpu_firmware_info *ucode = NULL;
519
520         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
521                 DRM_INFO("firmware is not loaded by PSP\n");
522                 return true;
523         }
524
525         if (!adev->firmware.fw_size)
526                 return false;
527
528         ucode = &adev->firmware.ucode[ucode_type];
529         if (!ucode->fw || !ucode->ucode_size)
530                 return false;
531
532         return psp_compare_sram_data(&adev->psp, ucode, ucode_type);
533 }
534
535 static int psp_set_clockgating_state(void *handle,
536                                      enum amd_clockgating_state state)
537 {
538         return 0;
539 }
540
541 static int psp_set_powergating_state(void *handle,
542                                      enum amd_powergating_state state)
543 {
544         return 0;
545 }
546
547 const struct amd_ip_funcs psp_ip_funcs = {
548         .name = "psp",
549         .early_init = psp_early_init,
550         .late_init = NULL,
551         .sw_init = psp_sw_init,
552         .sw_fini = psp_sw_fini,
553         .hw_init = psp_hw_init,
554         .hw_fini = psp_hw_fini,
555         .suspend = psp_suspend,
556         .resume = psp_resume,
557         .is_idle = NULL,
558         .check_soft_reset = NULL,
559         .wait_for_idle = NULL,
560         .soft_reset = NULL,
561         .set_clockgating_state = psp_set_clockgating_state,
562         .set_powergating_state = psp_set_powergating_state,
563 };
564
565 static const struct amdgpu_psp_funcs psp_funcs = {
566         .check_fw_loading_status = psp_check_fw_loading_status,
567 };
568
569 static void psp_set_funcs(struct amdgpu_device *adev)
570 {
571         if (NULL == adev->firmware.funcs)
572                 adev->firmware.funcs = &psp_funcs;
573 }
574
575 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
576 {
577         .type = AMD_IP_BLOCK_TYPE_PSP,
578         .major = 3,
579         .minor = 1,
580         .rev = 0,
581         .funcs = &psp_ip_funcs,
582 };
583
584 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
585 {
586         .type = AMD_IP_BLOCK_TYPE_PSP,
587         .major = 10,
588         .minor = 0,
589         .rev = 0,
590         .funcs = &psp_ip_funcs,
591 };