drm/amdgpu/vg20:Restruct uvd.inst to support multiple instances
[muen/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ring.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  *          Christian K├Ânig
28  */
29 #include <linux/seq_file.h>
30 #include <linux/slab.h>
31 #include <linux/debugfs.h>
32 #include <drm/drmP.h>
33 #include <drm/amdgpu_drm.h>
34 #include "amdgpu.h"
35 #include "atom.h"
36
37 /*
38  * Rings
39  * Most engines on the GPU are fed via ring buffers.  Ring
40  * buffers are areas of GPU accessible memory that the host
41  * writes commands into and the GPU reads commands out of.
42  * There is a rptr (read pointer) that determines where the
43  * GPU is currently reading, and a wptr (write pointer)
44  * which determines where the host has written.  When the
45  * pointers are equal, the ring is idle.  When the host
46  * writes commands to the ring buffer, it increments the
47  * wptr.  The GPU then starts fetching commands and executes
48  * them until the pointers are equal again.
49  */
50 static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
51                                     struct amdgpu_ring *ring);
52 static void amdgpu_debugfs_ring_fini(struct amdgpu_ring *ring);
53
54 /**
55  * amdgpu_ring_alloc - allocate space on the ring buffer
56  *
57  * @adev: amdgpu_device pointer
58  * @ring: amdgpu_ring structure holding ring information
59  * @ndw: number of dwords to allocate in the ring buffer
60  *
61  * Allocate @ndw dwords in the ring buffer (all asics).
62  * Returns 0 on success, error on failure.
63  */
64 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw)
65 {
66         /* Align requested size with padding so unlock_commit can
67          * pad safely */
68         ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask;
69
70         /* Make sure we aren't trying to allocate more space
71          * than the maximum for one submission
72          */
73         if (WARN_ON_ONCE(ndw > ring->max_dw))
74                 return -ENOMEM;
75
76         ring->count_dw = ndw;
77         ring->wptr_old = ring->wptr;
78
79         if (ring->funcs->begin_use)
80                 ring->funcs->begin_use(ring);
81
82         return 0;
83 }
84
85 /** amdgpu_ring_insert_nop - insert NOP packets
86  *
87  * @ring: amdgpu_ring structure holding ring information
88  * @count: the number of NOP packets to insert
89  *
90  * This is the generic insert_nop function for rings except SDMA
91  */
92 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
93 {
94         int i;
95
96         for (i = 0; i < count; i++)
97                 amdgpu_ring_write(ring, ring->funcs->nop);
98 }
99
100 /** amdgpu_ring_generic_pad_ib - pad IB with NOP packets
101  *
102  * @ring: amdgpu_ring structure holding ring information
103  * @ib: IB to add NOP packets to
104  *
105  * This is the generic pad_ib function for rings except SDMA
106  */
107 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
108 {
109         while (ib->length_dw & ring->funcs->align_mask)
110                 ib->ptr[ib->length_dw++] = ring->funcs->nop;
111 }
112
113 /**
114  * amdgpu_ring_commit - tell the GPU to execute the new
115  * commands on the ring buffer
116  *
117  * @adev: amdgpu_device pointer
118  * @ring: amdgpu_ring structure holding ring information
119  *
120  * Update the wptr (write pointer) to tell the GPU to
121  * execute new commands on the ring buffer (all asics).
122  */
123 void amdgpu_ring_commit(struct amdgpu_ring *ring)
124 {
125         uint32_t count;
126
127         /* We pad to match fetch size */
128         count = ring->funcs->align_mask + 1 -
129                 (ring->wptr & ring->funcs->align_mask);
130         count %= ring->funcs->align_mask + 1;
131         ring->funcs->insert_nop(ring, count);
132
133         mb();
134         amdgpu_ring_set_wptr(ring);
135
136         if (ring->funcs->end_use)
137                 ring->funcs->end_use(ring);
138
139         if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ)
140                 amdgpu_ring_lru_touch(ring->adev, ring);
141 }
142
143 /**
144  * amdgpu_ring_undo - reset the wptr
145  *
146  * @ring: amdgpu_ring structure holding ring information
147  *
148  * Reset the driver's copy of the wptr (all asics).
149  */
150 void amdgpu_ring_undo(struct amdgpu_ring *ring)
151 {
152         ring->wptr = ring->wptr_old;
153
154         if (ring->funcs->end_use)
155                 ring->funcs->end_use(ring);
156 }
157
158 /**
159  * amdgpu_ring_priority_put - restore a ring's priority
160  *
161  * @ring: amdgpu_ring structure holding the information
162  * @priority: target priority
163  *
164  * Release a request for executing at @priority
165  */
166 void amdgpu_ring_priority_put(struct amdgpu_ring *ring,
167                               enum drm_sched_priority priority)
168 {
169         int i;
170
171         if (!ring->funcs->set_priority)
172                 return;
173
174         if (atomic_dec_return(&ring->num_jobs[priority]) > 0)
175                 return;
176
177         /* no need to restore if the job is already at the lowest priority */
178         if (priority == DRM_SCHED_PRIORITY_NORMAL)
179                 return;
180
181         mutex_lock(&ring->priority_mutex);
182         /* something higher prio is executing, no need to decay */
183         if (ring->priority > priority)
184                 goto out_unlock;
185
186         /* decay priority to the next level with a job available */
187         for (i = priority; i >= DRM_SCHED_PRIORITY_MIN; i--) {
188                 if (i == DRM_SCHED_PRIORITY_NORMAL
189                                 || atomic_read(&ring->num_jobs[i])) {
190                         ring->priority = i;
191                         ring->funcs->set_priority(ring, i);
192                         break;
193                 }
194         }
195
196 out_unlock:
197         mutex_unlock(&ring->priority_mutex);
198 }
199
200 /**
201  * amdgpu_ring_priority_get - change the ring's priority
202  *
203  * @ring: amdgpu_ring structure holding the information
204  * @priority: target priority
205  *
206  * Request a ring's priority to be raised to @priority (refcounted).
207  */
208 void amdgpu_ring_priority_get(struct amdgpu_ring *ring,
209                               enum drm_sched_priority priority)
210 {
211         if (!ring->funcs->set_priority)
212                 return;
213
214         atomic_inc(&ring->num_jobs[priority]);
215
216         mutex_lock(&ring->priority_mutex);
217         if (priority <= ring->priority)
218                 goto out_unlock;
219
220         ring->priority = priority;
221         ring->funcs->set_priority(ring, priority);
222
223 out_unlock:
224         mutex_unlock(&ring->priority_mutex);
225 }
226
227 /**
228  * amdgpu_ring_init - init driver ring struct.
229  *
230  * @adev: amdgpu_device pointer
231  * @ring: amdgpu_ring structure holding ring information
232  * @max_ndw: maximum number of dw for ring alloc
233  * @nop: nop packet for this ring
234  *
235  * Initialize the driver information for the selected ring (all asics).
236  * Returns 0 on success, error on failure.
237  */
238 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
239                      unsigned max_dw, struct amdgpu_irq_src *irq_src,
240                      unsigned irq_type)
241 {
242         int r, i;
243         int sched_hw_submission = amdgpu_sched_hw_submission;
244
245         /* Set the hw submission limit higher for KIQ because
246          * it's used for a number of gfx/compute tasks by both
247          * KFD and KGD which may have outstanding fences and
248          * it doesn't really use the gpu scheduler anyway;
249          * KIQ tasks get submitted directly to the ring.
250          */
251         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
252                 sched_hw_submission = max(sched_hw_submission, 256);
253
254         if (ring->adev == NULL) {
255                 if (adev->num_rings >= AMDGPU_MAX_RINGS)
256                         return -EINVAL;
257
258                 ring->adev = adev;
259                 ring->idx = adev->num_rings++;
260                 adev->rings[ring->idx] = ring;
261                 r = amdgpu_fence_driver_init_ring(ring, sched_hw_submission);
262                 if (r)
263                         return r;
264         }
265
266         r = amdgpu_device_wb_get(adev, &ring->rptr_offs);
267         if (r) {
268                 dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r);
269                 return r;
270         }
271
272         r = amdgpu_device_wb_get(adev, &ring->wptr_offs);
273         if (r) {
274                 dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r);
275                 return r;
276         }
277
278         r = amdgpu_device_wb_get(adev, &ring->fence_offs);
279         if (r) {
280                 dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r);
281                 return r;
282         }
283
284         r = amdgpu_device_wb_get(adev, &ring->cond_exe_offs);
285         if (r) {
286                 dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r);
287                 return r;
288         }
289         ring->cond_exe_gpu_addr = adev->wb.gpu_addr + (ring->cond_exe_offs * 4);
290         ring->cond_exe_cpu_addr = &adev->wb.wb[ring->cond_exe_offs];
291         /* always set cond_exec_polling to CONTINUE */
292         *ring->cond_exe_cpu_addr = 1;
293
294         r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type);
295         if (r) {
296                 dev_err(adev->dev, "failed initializing fences (%d).\n", r);
297                 return r;
298         }
299
300         ring->ring_size = roundup_pow_of_two(max_dw * 4 * sched_hw_submission);
301
302         ring->buf_mask = (ring->ring_size / 4) - 1;
303         ring->ptr_mask = ring->funcs->support_64bit_ptrs ?
304                 0xffffffffffffffff : ring->buf_mask;
305         /* Allocate ring buffer */
306         if (ring->ring_obj == NULL) {
307                 r = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
308                                             AMDGPU_GEM_DOMAIN_GTT,
309                                             &ring->ring_obj,
310                                             &ring->gpu_addr,
311                                             (void **)&ring->ring);
312                 if (r) {
313                         dev_err(adev->dev, "(%d) ring create failed\n", r);
314                         return r;
315                 }
316                 amdgpu_ring_clear_ring(ring);
317         }
318
319         ring->max_dw = max_dw;
320         ring->priority = DRM_SCHED_PRIORITY_NORMAL;
321         mutex_init(&ring->priority_mutex);
322         INIT_LIST_HEAD(&ring->lru_list);
323         amdgpu_ring_lru_touch(adev, ring);
324
325         for (i = 0; i < DRM_SCHED_PRIORITY_MAX; ++i)
326                 atomic_set(&ring->num_jobs[i], 0);
327
328         if (amdgpu_debugfs_ring_init(adev, ring)) {
329                 DRM_ERROR("Failed to register debugfs file for rings !\n");
330         }
331
332         return 0;
333 }
334
335 /**
336  * amdgpu_ring_fini - tear down the driver ring struct.
337  *
338  * @adev: amdgpu_device pointer
339  * @ring: amdgpu_ring structure holding ring information
340  *
341  * Tear down the driver information for the selected ring (all asics).
342  */
343 void amdgpu_ring_fini(struct amdgpu_ring *ring)
344 {
345         ring->ready = false;
346
347         /* Not to finish a ring which is not initialized */
348         if (!(ring->adev) || !(ring->adev->rings[ring->idx]))
349                 return;
350
351         amdgpu_device_wb_free(ring->adev, ring->rptr_offs);
352         amdgpu_device_wb_free(ring->adev, ring->wptr_offs);
353
354         amdgpu_device_wb_free(ring->adev, ring->cond_exe_offs);
355         amdgpu_device_wb_free(ring->adev, ring->fence_offs);
356
357         amdgpu_bo_free_kernel(&ring->ring_obj,
358                               &ring->gpu_addr,
359                               (void **)&ring->ring);
360
361         amdgpu_debugfs_ring_fini(ring);
362
363         dma_fence_put(ring->vmid_wait);
364         ring->vmid_wait = NULL;
365         ring->me = 0;
366
367         ring->adev->rings[ring->idx] = NULL;
368 }
369
370 static void amdgpu_ring_lru_touch_locked(struct amdgpu_device *adev,
371                                          struct amdgpu_ring *ring)
372 {
373         /* list_move_tail handles the case where ring isn't part of the list */
374         list_move_tail(&ring->lru_list, &adev->ring_lru_list);
375 }
376
377 static bool amdgpu_ring_is_blacklisted(struct amdgpu_ring *ring,
378                                        int *blacklist, int num_blacklist)
379 {
380         int i;
381
382         for (i = 0; i < num_blacklist; i++) {
383                 if (ring->idx == blacklist[i])
384                         return true;
385         }
386
387         return false;
388 }
389
390 /**
391  * amdgpu_ring_lru_get - get the least recently used ring for a HW IP block
392  *
393  * @adev: amdgpu_device pointer
394  * @type: amdgpu_ring_type enum
395  * @blacklist: blacklisted ring ids array
396  * @num_blacklist: number of entries in @blacklist
397  * @lru_pipe_order: find a ring from the least recently used pipe
398  * @ring: output ring
399  *
400  * Retrieve the amdgpu_ring structure for the least recently used ring of
401  * a specific IP block (all asics).
402  * Returns 0 on success, error on failure.
403  */
404 int amdgpu_ring_lru_get(struct amdgpu_device *adev, int type,
405                         int *blacklist, int num_blacklist,
406                         bool lru_pipe_order, struct amdgpu_ring **ring)
407 {
408         struct amdgpu_ring *entry;
409
410         /* List is sorted in LRU order, find first entry corresponding
411          * to the desired HW IP */
412         *ring = NULL;
413         spin_lock(&adev->ring_lru_list_lock);
414         list_for_each_entry(entry, &adev->ring_lru_list, lru_list) {
415                 if (entry->funcs->type != type)
416                         continue;
417
418                 if (amdgpu_ring_is_blacklisted(entry, blacklist, num_blacklist))
419                         continue;
420
421                 if (!*ring) {
422                         *ring = entry;
423
424                         /* We are done for ring LRU */
425                         if (!lru_pipe_order)
426                                 break;
427                 }
428
429                 /* Move all rings on the same pipe to the end of the list */
430                 if (entry->pipe == (*ring)->pipe)
431                         amdgpu_ring_lru_touch_locked(adev, entry);
432         }
433
434         /* Move the ring we found to the end of the list */
435         if (*ring)
436                 amdgpu_ring_lru_touch_locked(adev, *ring);
437
438         spin_unlock(&adev->ring_lru_list_lock);
439
440         if (!*ring) {
441                 DRM_ERROR("Ring LRU contains no entries for ring type:%d\n", type);
442                 return -EINVAL;
443         }
444
445         return 0;
446 }
447
448 /**
449  * amdgpu_ring_lru_touch - mark a ring as recently being used
450  *
451  * @adev: amdgpu_device pointer
452  * @ring: ring to touch
453  *
454  * Move @ring to the tail of the lru list
455  */
456 void amdgpu_ring_lru_touch(struct amdgpu_device *adev, struct amdgpu_ring *ring)
457 {
458         spin_lock(&adev->ring_lru_list_lock);
459         amdgpu_ring_lru_touch_locked(adev, ring);
460         spin_unlock(&adev->ring_lru_list_lock);
461 }
462
463 /**
464  * amdgpu_ring_emit_reg_write_reg_wait_helper - ring helper
465  *
466  * @adev: amdgpu_device pointer
467  * @reg0: register to write
468  * @reg1: register to wait on
469  * @ref: reference value to write/wait on
470  * @mask: mask to wait on
471  *
472  * Helper for rings that don't support write and wait in a
473  * single oneshot packet.
474  */
475 void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
476                                                 uint32_t reg0, uint32_t reg1,
477                                                 uint32_t ref, uint32_t mask)
478 {
479         amdgpu_ring_emit_wreg(ring, reg0, ref);
480         amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
481 }
482
483 /*
484  * Debugfs info
485  */
486 #if defined(CONFIG_DEBUG_FS)
487
488 /* Layout of file is 12 bytes consisting of
489  * - rptr
490  * - wptr
491  * - driver's copy of wptr
492  *
493  * followed by n-words of ring data
494  */
495 static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf,
496                                         size_t size, loff_t *pos)
497 {
498         struct amdgpu_ring *ring = file_inode(f)->i_private;
499         int r, i;
500         uint32_t value, result, early[3];
501
502         if (*pos & 3 || size & 3)
503                 return -EINVAL;
504
505         result = 0;
506
507         if (*pos < 12) {
508                 early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask;
509                 early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask;
510                 early[2] = ring->wptr & ring->buf_mask;
511                 for (i = *pos / 4; i < 3 && size; i++) {
512                         r = put_user(early[i], (uint32_t *)buf);
513                         if (r)
514                                 return r;
515                         buf += 4;
516                         result += 4;
517                         size -= 4;
518                         *pos += 4;
519                 }
520         }
521
522         while (size) {
523                 if (*pos >= (ring->ring_size + 12))
524                         return result;
525
526                 value = ring->ring[(*pos - 12)/4];
527                 r = put_user(value, (uint32_t*)buf);
528                 if (r)
529                         return r;
530                 buf += 4;
531                 result += 4;
532                 size -= 4;
533                 *pos += 4;
534         }
535
536         return result;
537 }
538
539 static const struct file_operations amdgpu_debugfs_ring_fops = {
540         .owner = THIS_MODULE,
541         .read = amdgpu_debugfs_ring_read,
542         .llseek = default_llseek
543 };
544
545 #endif
546
547 static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
548                                     struct amdgpu_ring *ring)
549 {
550 #if defined(CONFIG_DEBUG_FS)
551         struct drm_minor *minor = adev->ddev->primary;
552         struct dentry *ent, *root = minor->debugfs_root;
553         char name[32];
554
555         sprintf(name, "amdgpu_ring_%s", ring->name);
556
557         ent = debugfs_create_file(name,
558                                   S_IFREG | S_IRUGO, root,
559                                   ring, &amdgpu_debugfs_ring_fops);
560         if (!ent)
561                 return -ENOMEM;
562
563         i_size_write(ent->d_inode, ring->ring_size + 12);
564         ring->ent = ent;
565 #endif
566         return 0;
567 }
568
569 static void amdgpu_debugfs_ring_fini(struct amdgpu_ring *ring)
570 {
571 #if defined(CONFIG_DEBUG_FS)
572         debugfs_remove(ring->ent);
573 #endif
574 }