02683a039a984ec82083b627ea4a1dece544d3a0
[muen/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_uvd.c
1 /*
2  * Copyright 2011 Advanced Micro Devices, Inc.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sub license, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
20  *
21  * The above copyright notice and this permission notice (including the
22  * next paragraph) shall be included in all copies or substantial portions
23  * of the Software.
24  *
25  */
26 /*
27  * Authors:
28  *    Christian K├Ânig <deathsimple@vodafone.de>
29  */
30
31 #include <linux/firmware.h>
32 #include <linux/module.h>
33 #include <drm/drmP.h>
34 #include <drm/drm.h>
35
36 #include "amdgpu.h"
37 #include "amdgpu_pm.h"
38 #include "amdgpu_uvd.h"
39 #include "cikd.h"
40 #include "uvd/uvd_4_2_d.h"
41
42 /* 1 second timeout */
43 #define UVD_IDLE_TIMEOUT        msecs_to_jiffies(1000)
44
45 /* Firmware versions for VI */
46 #define FW_1_65_10      ((1 << 24) | (65 << 16) | (10 << 8))
47 #define FW_1_87_11      ((1 << 24) | (87 << 16) | (11 << 8))
48 #define FW_1_87_12      ((1 << 24) | (87 << 16) | (12 << 8))
49 #define FW_1_37_15      ((1 << 24) | (37 << 16) | (15 << 8))
50
51 /* Polaris10/11 firmware version */
52 #define FW_1_66_16      ((1 << 24) | (66 << 16) | (16 << 8))
53
54 /* Firmware Names */
55 #ifdef CONFIG_DRM_AMDGPU_CIK
56 #define FIRMWARE_BONAIRE        "radeon/bonaire_uvd.bin"
57 #define FIRMWARE_KABINI "radeon/kabini_uvd.bin"
58 #define FIRMWARE_KAVERI "radeon/kaveri_uvd.bin"
59 #define FIRMWARE_HAWAII "radeon/hawaii_uvd.bin"
60 #define FIRMWARE_MULLINS        "radeon/mullins_uvd.bin"
61 #endif
62 #define FIRMWARE_TONGA          "amdgpu/tonga_uvd.bin"
63 #define FIRMWARE_CARRIZO        "amdgpu/carrizo_uvd.bin"
64 #define FIRMWARE_FIJI           "amdgpu/fiji_uvd.bin"
65 #define FIRMWARE_STONEY         "amdgpu/stoney_uvd.bin"
66 #define FIRMWARE_POLARIS10      "amdgpu/polaris10_uvd.bin"
67 #define FIRMWARE_POLARIS11      "amdgpu/polaris11_uvd.bin"
68 #define FIRMWARE_POLARIS12      "amdgpu/polaris12_uvd.bin"
69 #define FIRMWARE_VEGAM          "amdgpu/vegam_uvd.bin"
70
71 #define FIRMWARE_VEGA10         "amdgpu/vega10_uvd.bin"
72 #define FIRMWARE_VEGA12         "amdgpu/vega12_uvd.bin"
73 #define FIRMWARE_VEGA20         "amdgpu/vega20_uvd.bin"
74
75 #define mmUVD_GPCOM_VCPU_DATA0_VEGA10 (0x03c4 + 0x7e00)
76 #define mmUVD_GPCOM_VCPU_DATA1_VEGA10 (0x03c5 + 0x7e00)
77 #define mmUVD_GPCOM_VCPU_CMD_VEGA10 (0x03c3 + 0x7e00)
78 #define mmUVD_NO_OP_VEGA10 (0x03ff + 0x7e00)
79 #define mmUVD_ENGINE_CNTL_VEGA10 (0x03c6 + 0x7e00)
80
81 /**
82  * amdgpu_uvd_cs_ctx - Command submission parser context
83  *
84  * Used for emulating virtual memory support on UVD 4.2.
85  */
86 struct amdgpu_uvd_cs_ctx {
87         struct amdgpu_cs_parser *parser;
88         unsigned reg, count;
89         unsigned data0, data1;
90         unsigned idx;
91         unsigned ib_idx;
92
93         /* does the IB has a msg command */
94         bool has_msg_cmd;
95
96         /* minimum buffer sizes */
97         unsigned *buf_sizes;
98 };
99
100 #ifdef CONFIG_DRM_AMDGPU_CIK
101 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
102 MODULE_FIRMWARE(FIRMWARE_KABINI);
103 MODULE_FIRMWARE(FIRMWARE_KAVERI);
104 MODULE_FIRMWARE(FIRMWARE_HAWAII);
105 MODULE_FIRMWARE(FIRMWARE_MULLINS);
106 #endif
107 MODULE_FIRMWARE(FIRMWARE_TONGA);
108 MODULE_FIRMWARE(FIRMWARE_CARRIZO);
109 MODULE_FIRMWARE(FIRMWARE_FIJI);
110 MODULE_FIRMWARE(FIRMWARE_STONEY);
111 MODULE_FIRMWARE(FIRMWARE_POLARIS10);
112 MODULE_FIRMWARE(FIRMWARE_POLARIS11);
113 MODULE_FIRMWARE(FIRMWARE_POLARIS12);
114 MODULE_FIRMWARE(FIRMWARE_VEGAM);
115
116 MODULE_FIRMWARE(FIRMWARE_VEGA10);
117 MODULE_FIRMWARE(FIRMWARE_VEGA12);
118 MODULE_FIRMWARE(FIRMWARE_VEGA20);
119
120 static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
121
122 int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
123 {
124         struct amdgpu_ring *ring;
125         struct drm_sched_rq *rq;
126         unsigned long bo_size;
127         const char *fw_name;
128         const struct common_firmware_header *hdr;
129         unsigned version_major, version_minor, family_id;
130         int i, r;
131
132         INIT_DELAYED_WORK(&adev->uvd.inst->idle_work, amdgpu_uvd_idle_work_handler);
133
134         switch (adev->asic_type) {
135 #ifdef CONFIG_DRM_AMDGPU_CIK
136         case CHIP_BONAIRE:
137                 fw_name = FIRMWARE_BONAIRE;
138                 break;
139         case CHIP_KABINI:
140                 fw_name = FIRMWARE_KABINI;
141                 break;
142         case CHIP_KAVERI:
143                 fw_name = FIRMWARE_KAVERI;
144                 break;
145         case CHIP_HAWAII:
146                 fw_name = FIRMWARE_HAWAII;
147                 break;
148         case CHIP_MULLINS:
149                 fw_name = FIRMWARE_MULLINS;
150                 break;
151 #endif
152         case CHIP_TONGA:
153                 fw_name = FIRMWARE_TONGA;
154                 break;
155         case CHIP_FIJI:
156                 fw_name = FIRMWARE_FIJI;
157                 break;
158         case CHIP_CARRIZO:
159                 fw_name = FIRMWARE_CARRIZO;
160                 break;
161         case CHIP_STONEY:
162                 fw_name = FIRMWARE_STONEY;
163                 break;
164         case CHIP_POLARIS10:
165                 fw_name = FIRMWARE_POLARIS10;
166                 break;
167         case CHIP_POLARIS11:
168                 fw_name = FIRMWARE_POLARIS11;
169                 break;
170         case CHIP_POLARIS12:
171                 fw_name = FIRMWARE_POLARIS12;
172                 break;
173         case CHIP_VEGA10:
174                 fw_name = FIRMWARE_VEGA10;
175                 break;
176         case CHIP_VEGA12:
177                 fw_name = FIRMWARE_VEGA12;
178                 break;
179         case CHIP_VEGAM:
180                 fw_name = FIRMWARE_VEGAM;
181                 break;
182         case CHIP_VEGA20:
183                 fw_name = FIRMWARE_VEGA20;
184                 break;
185         default:
186                 return -EINVAL;
187         }
188
189         r = request_firmware(&adev->uvd.fw, fw_name, adev->dev);
190         if (r) {
191                 dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n",
192                         fw_name);
193                 return r;
194         }
195
196         r = amdgpu_ucode_validate(adev->uvd.fw);
197         if (r) {
198                 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n",
199                         fw_name);
200                 release_firmware(adev->uvd.fw);
201                 adev->uvd.fw = NULL;
202                 return r;
203         }
204
205         /* Set the default UVD handles that the firmware can handle */
206         adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES;
207
208         hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
209         family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
210         version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
211         version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
212         DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
213                 version_major, version_minor, family_id);
214
215         /*
216          * Limit the number of UVD handles depending on microcode major
217          * and minor versions. The firmware version which has 40 UVD
218          * instances support is 1.80. So all subsequent versions should
219          * also have the same support.
220          */
221         if ((version_major > 0x01) ||
222             ((version_major == 0x01) && (version_minor >= 0x50)))
223                 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES;
224
225         adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) |
226                                 (family_id << 8));
227
228         if ((adev->asic_type == CHIP_POLARIS10 ||
229              adev->asic_type == CHIP_POLARIS11) &&
230             (adev->uvd.fw_version < FW_1_66_16))
231                 DRM_ERROR("POLARIS10/11 UVD firmware version %hu.%hu is too old.\n",
232                           version_major, version_minor);
233
234         bo_size = AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE
235                   +  AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles;
236         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
237                 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
238
239         r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
240                                     AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.inst->vcpu_bo,
241                                     &adev->uvd.inst->gpu_addr, &adev->uvd.inst->cpu_addr);
242         if (r) {
243                 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r);
244                 return r;
245         }
246
247         ring = &adev->uvd.inst->ring;
248         rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
249         r = drm_sched_entity_init(&ring->sched, &adev->uvd.inst->entity,
250                                   rq, NULL);
251         if (r != 0) {
252                 DRM_ERROR("Failed setting up UVD run queue.\n");
253                 return r;
254         }
255
256         for (i = 0; i < adev->uvd.max_handles; ++i) {
257                 atomic_set(&adev->uvd.inst->handles[i], 0);
258                 adev->uvd.inst->filp[i] = NULL;
259         }
260
261         /* from uvd v5.0 HW addressing capacity increased to 64 bits */
262         if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
263                 adev->uvd.address_64_bit = true;
264
265         switch (adev->asic_type) {
266         case CHIP_TONGA:
267                 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10;
268                 break;
269         case CHIP_CARRIZO:
270                 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11;
271                 break;
272         case CHIP_FIJI:
273                 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12;
274                 break;
275         case CHIP_STONEY:
276                 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15;
277                 break;
278         default:
279                 adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10;
280         }
281
282         return 0;
283 }
284
285 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
286 {
287         int i;
288         kfree(adev->uvd.inst->saved_bo);
289
290         drm_sched_entity_fini(&adev->uvd.inst->ring.sched, &adev->uvd.inst->entity);
291
292         amdgpu_bo_free_kernel(&adev->uvd.inst->vcpu_bo,
293                               &adev->uvd.inst->gpu_addr,
294                               (void **)&adev->uvd.inst->cpu_addr);
295
296         amdgpu_ring_fini(&adev->uvd.inst->ring);
297
298         for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i)
299                 amdgpu_ring_fini(&adev->uvd.inst->ring_enc[i]);
300
301         release_firmware(adev->uvd.fw);
302
303         return 0;
304 }
305
306 int amdgpu_uvd_suspend(struct amdgpu_device *adev)
307 {
308         unsigned size;
309         void *ptr;
310         int i;
311
312         if (adev->uvd.inst->vcpu_bo == NULL)
313                 return 0;
314
315         cancel_delayed_work_sync(&adev->uvd.inst->idle_work);
316
317         /* only valid for physical mode */
318         if (adev->asic_type < CHIP_POLARIS10) {
319                 for (i = 0; i < adev->uvd.max_handles; ++i)
320                         if (atomic_read(&adev->uvd.inst->handles[i]))
321                                 break;
322
323                 if (i == adev->uvd.max_handles)
324                         return 0;
325         }
326
327         size = amdgpu_bo_size(adev->uvd.inst->vcpu_bo);
328         ptr = adev->uvd.inst->cpu_addr;
329
330         adev->uvd.inst->saved_bo = kmalloc(size, GFP_KERNEL);
331         if (!adev->uvd.inst->saved_bo)
332                 return -ENOMEM;
333
334         memcpy_fromio(adev->uvd.inst->saved_bo, ptr, size);
335
336         return 0;
337 }
338
339 int amdgpu_uvd_resume(struct amdgpu_device *adev)
340 {
341         unsigned size;
342         void *ptr;
343
344         if (adev->uvd.inst->vcpu_bo == NULL)
345                 return -EINVAL;
346
347         size = amdgpu_bo_size(adev->uvd.inst->vcpu_bo);
348         ptr = adev->uvd.inst->cpu_addr;
349
350         if (adev->uvd.inst->saved_bo != NULL) {
351                 memcpy_toio(ptr, adev->uvd.inst->saved_bo, size);
352                 kfree(adev->uvd.inst->saved_bo);
353                 adev->uvd.inst->saved_bo = NULL;
354         } else {
355                 const struct common_firmware_header *hdr;
356                 unsigned offset;
357
358                 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
359                 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
360                         offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
361                         memcpy_toio(adev->uvd.inst->cpu_addr, adev->uvd.fw->data + offset,
362                                     le32_to_cpu(hdr->ucode_size_bytes));
363                         size -= le32_to_cpu(hdr->ucode_size_bytes);
364                         ptr += le32_to_cpu(hdr->ucode_size_bytes);
365                 }
366                 memset_io(ptr, 0, size);
367                 /* to restore uvd fence seq */
368                 amdgpu_fence_driver_force_completion(&adev->uvd.inst->ring);
369         }
370
371         return 0;
372 }
373
374 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
375 {
376         struct amdgpu_ring *ring = &adev->uvd.inst->ring;
377         int i, r;
378
379         for (i = 0; i < adev->uvd.max_handles; ++i) {
380                 uint32_t handle = atomic_read(&adev->uvd.inst->handles[i]);
381                 if (handle != 0 && adev->uvd.inst->filp[i] == filp) {
382                         struct dma_fence *fence;
383
384                         r = amdgpu_uvd_get_destroy_msg(ring, handle,
385                                                        false, &fence);
386                         if (r) {
387                                 DRM_ERROR("Error destroying UVD (%d)!\n", r);
388                                 continue;
389                         }
390
391                         dma_fence_wait(fence, false);
392                         dma_fence_put(fence);
393
394                         adev->uvd.inst->filp[i] = NULL;
395                         atomic_set(&adev->uvd.inst->handles[i], 0);
396                 }
397         }
398 }
399
400 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo)
401 {
402         int i;
403         for (i = 0; i < abo->placement.num_placement; ++i) {
404                 abo->placements[i].fpfn = 0 >> PAGE_SHIFT;
405                 abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
406         }
407 }
408
409 static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx)
410 {
411         uint32_t lo, hi;
412         uint64_t addr;
413
414         lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
415         hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
416         addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
417
418         return addr;
419 }
420
421 /**
422  * amdgpu_uvd_cs_pass1 - first parsing round
423  *
424  * @ctx: UVD parser context
425  *
426  * Make sure UVD message and feedback buffers are in VRAM and
427  * nobody is violating an 256MB boundary.
428  */
429 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx)
430 {
431         struct ttm_operation_ctx tctx = { false, false };
432         struct amdgpu_bo_va_mapping *mapping;
433         struct amdgpu_bo *bo;
434         uint32_t cmd;
435         uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);
436         int r = 0;
437
438         r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping);
439         if (r) {
440                 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
441                 return r;
442         }
443
444         if (!ctx->parser->adev->uvd.address_64_bit) {
445                 /* check if it's a message or feedback command */
446                 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
447                 if (cmd == 0x0 || cmd == 0x3) {
448                         /* yes, force it into VRAM */
449                         uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
450                         amdgpu_ttm_placement_from_domain(bo, domain);
451                 }
452                 amdgpu_uvd_force_into_uvd_segment(bo);
453
454                 r = ttm_bo_validate(&bo->tbo, &bo->placement, &tctx);
455         }
456
457         return r;
458 }
459
460 /**
461  * amdgpu_uvd_cs_msg_decode - handle UVD decode message
462  *
463  * @msg: pointer to message structure
464  * @buf_sizes: returned buffer sizes
465  *
466  * Peek into the decode message and calculate the necessary buffer sizes.
467  */
468 static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg,
469         unsigned buf_sizes[])
470 {
471         unsigned stream_type = msg[4];
472         unsigned width = msg[6];
473         unsigned height = msg[7];
474         unsigned dpb_size = msg[9];
475         unsigned pitch = msg[28];
476         unsigned level = msg[57];
477
478         unsigned width_in_mb = width / 16;
479         unsigned height_in_mb = ALIGN(height / 16, 2);
480         unsigned fs_in_mb = width_in_mb * height_in_mb;
481
482         unsigned image_size, tmp, min_dpb_size, num_dpb_buffer;
483         unsigned min_ctx_size = ~0;
484
485         image_size = width * height;
486         image_size += image_size / 2;
487         image_size = ALIGN(image_size, 1024);
488
489         switch (stream_type) {
490         case 0: /* H264 */
491                 switch(level) {
492                 case 30:
493                         num_dpb_buffer = 8100 / fs_in_mb;
494                         break;
495                 case 31:
496                         num_dpb_buffer = 18000 / fs_in_mb;
497                         break;
498                 case 32:
499                         num_dpb_buffer = 20480 / fs_in_mb;
500                         break;
501                 case 41:
502                         num_dpb_buffer = 32768 / fs_in_mb;
503                         break;
504                 case 42:
505                         num_dpb_buffer = 34816 / fs_in_mb;
506                         break;
507                 case 50:
508                         num_dpb_buffer = 110400 / fs_in_mb;
509                         break;
510                 case 51:
511                         num_dpb_buffer = 184320 / fs_in_mb;
512                         break;
513                 default:
514                         num_dpb_buffer = 184320 / fs_in_mb;
515                         break;
516                 }
517                 num_dpb_buffer++;
518                 if (num_dpb_buffer > 17)
519                         num_dpb_buffer = 17;
520
521                 /* reference picture buffer */
522                 min_dpb_size = image_size * num_dpb_buffer;
523
524                 /* macroblock context buffer */
525                 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192;
526
527                 /* IT surface buffer */
528                 min_dpb_size += width_in_mb * height_in_mb * 32;
529                 break;
530
531         case 1: /* VC1 */
532
533                 /* reference picture buffer */
534                 min_dpb_size = image_size * 3;
535
536                 /* CONTEXT_BUFFER */
537                 min_dpb_size += width_in_mb * height_in_mb * 128;
538
539                 /* IT surface buffer */
540                 min_dpb_size += width_in_mb * 64;
541
542                 /* DB surface buffer */
543                 min_dpb_size += width_in_mb * 128;
544
545                 /* BP */
546                 tmp = max(width_in_mb, height_in_mb);
547                 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
548                 break;
549
550         case 3: /* MPEG2 */
551
552                 /* reference picture buffer */
553                 min_dpb_size = image_size * 3;
554                 break;
555
556         case 4: /* MPEG4 */
557
558                 /* reference picture buffer */
559                 min_dpb_size = image_size * 3;
560
561                 /* CM */
562                 min_dpb_size += width_in_mb * height_in_mb * 64;
563
564                 /* IT surface buffer */
565                 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
566                 break;
567
568         case 7: /* H264 Perf */
569                 switch(level) {
570                 case 30:
571                         num_dpb_buffer = 8100 / fs_in_mb;
572                         break;
573                 case 31:
574                         num_dpb_buffer = 18000 / fs_in_mb;
575                         break;
576                 case 32:
577                         num_dpb_buffer = 20480 / fs_in_mb;
578                         break;
579                 case 41:
580                         num_dpb_buffer = 32768 / fs_in_mb;
581                         break;
582                 case 42:
583                         num_dpb_buffer = 34816 / fs_in_mb;
584                         break;
585                 case 50:
586                         num_dpb_buffer = 110400 / fs_in_mb;
587                         break;
588                 case 51:
589                         num_dpb_buffer = 184320 / fs_in_mb;
590                         break;
591                 default:
592                         num_dpb_buffer = 184320 / fs_in_mb;
593                         break;
594                 }
595                 num_dpb_buffer++;
596                 if (num_dpb_buffer > 17)
597                         num_dpb_buffer = 17;
598
599                 /* reference picture buffer */
600                 min_dpb_size = image_size * num_dpb_buffer;
601
602                 if (!adev->uvd.use_ctx_buf){
603                         /* macroblock context buffer */
604                         min_dpb_size +=
605                                 width_in_mb * height_in_mb * num_dpb_buffer * 192;
606
607                         /* IT surface buffer */
608                         min_dpb_size += width_in_mb * height_in_mb * 32;
609                 } else {
610                         /* macroblock context buffer */
611                         min_ctx_size =
612                                 width_in_mb * height_in_mb * num_dpb_buffer * 192;
613                 }
614                 break;
615
616         case 8: /* MJPEG */
617                 min_dpb_size = 0;
618                 break;
619
620         case 16: /* H265 */
621                 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2;
622                 image_size = ALIGN(image_size, 256);
623
624                 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2;
625                 min_dpb_size = image_size * num_dpb_buffer;
626                 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16)
627                                            * 16 * num_dpb_buffer + 52 * 1024;
628                 break;
629
630         default:
631                 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
632                 return -EINVAL;
633         }
634
635         if (width > pitch) {
636                 DRM_ERROR("Invalid UVD decoding target pitch!\n");
637                 return -EINVAL;
638         }
639
640         if (dpb_size < min_dpb_size) {
641                 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
642                           dpb_size, min_dpb_size);
643                 return -EINVAL;
644         }
645
646         buf_sizes[0x1] = dpb_size;
647         buf_sizes[0x2] = image_size;
648         buf_sizes[0x4] = min_ctx_size;
649         return 0;
650 }
651
652 /**
653  * amdgpu_uvd_cs_msg - handle UVD message
654  *
655  * @ctx: UVD parser context
656  * @bo: buffer object containing the message
657  * @offset: offset into the buffer object
658  *
659  * Peek into the UVD message and extract the session id.
660  * Make sure that we don't open up to many sessions.
661  */
662 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
663                              struct amdgpu_bo *bo, unsigned offset)
664 {
665         struct amdgpu_device *adev = ctx->parser->adev;
666         int32_t *msg, msg_type, handle;
667         void *ptr;
668         long r;
669         int i;
670
671         if (offset & 0x3F) {
672                 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
673                 return -EINVAL;
674         }
675
676         r = amdgpu_bo_kmap(bo, &ptr);
677         if (r) {
678                 DRM_ERROR("Failed mapping the UVD message (%ld)!\n", r);
679                 return r;
680         }
681
682         msg = ptr + offset;
683
684         msg_type = msg[1];
685         handle = msg[2];
686
687         if (handle == 0) {
688                 DRM_ERROR("Invalid UVD handle!\n");
689                 return -EINVAL;
690         }
691
692         switch (msg_type) {
693         case 0:
694                 /* it's a create msg, calc image size (width * height) */
695                 amdgpu_bo_kunmap(bo);
696
697                 /* try to alloc a new handle */
698                 for (i = 0; i < adev->uvd.max_handles; ++i) {
699                         if (atomic_read(&adev->uvd.inst->handles[i]) == handle) {
700                                 DRM_ERROR("Handle 0x%x already in use!\n", handle);
701                                 return -EINVAL;
702                         }
703
704                         if (!atomic_cmpxchg(&adev->uvd.inst->handles[i], 0, handle)) {
705                                 adev->uvd.inst->filp[i] = ctx->parser->filp;
706                                 return 0;
707                         }
708                 }
709
710                 DRM_ERROR("No more free UVD handles!\n");
711                 return -ENOSPC;
712
713         case 1:
714                 /* it's a decode msg, calc buffer sizes */
715                 r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes);
716                 amdgpu_bo_kunmap(bo);
717                 if (r)
718                         return r;
719
720                 /* validate the handle */
721                 for (i = 0; i < adev->uvd.max_handles; ++i) {
722                         if (atomic_read(&adev->uvd.inst->handles[i]) == handle) {
723                                 if (adev->uvd.inst->filp[i] != ctx->parser->filp) {
724                                         DRM_ERROR("UVD handle collision detected!\n");
725                                         return -EINVAL;
726                                 }
727                                 return 0;
728                         }
729                 }
730
731                 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle);
732                 return -ENOENT;
733
734         case 2:
735                 /* it's a destroy msg, free the handle */
736                 for (i = 0; i < adev->uvd.max_handles; ++i)
737                         atomic_cmpxchg(&adev->uvd.inst->handles[i], handle, 0);
738                 amdgpu_bo_kunmap(bo);
739                 return 0;
740
741         default:
742                 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
743                 return -EINVAL;
744         }
745         BUG();
746         return -EINVAL;
747 }
748
749 /**
750  * amdgpu_uvd_cs_pass2 - second parsing round
751  *
752  * @ctx: UVD parser context
753  *
754  * Patch buffer addresses, make sure buffer sizes are correct.
755  */
756 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
757 {
758         struct amdgpu_bo_va_mapping *mapping;
759         struct amdgpu_bo *bo;
760         uint32_t cmd;
761         uint64_t start, end;
762         uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);
763         int r;
764
765         r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping);
766         if (r) {
767                 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
768                 return r;
769         }
770
771         start = amdgpu_bo_gpu_offset(bo);
772
773         end = (mapping->last + 1 - mapping->start);
774         end = end * AMDGPU_GPU_PAGE_SIZE + start;
775
776         addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE;
777         start += addr;
778
779         amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0,
780                             lower_32_bits(start));
781         amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1,
782                             upper_32_bits(start));
783
784         cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
785         if (cmd < 0x4) {
786                 if ((end - start) < ctx->buf_sizes[cmd]) {
787                         DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
788                                   (unsigned)(end - start),
789                                   ctx->buf_sizes[cmd]);
790                         return -EINVAL;
791                 }
792
793         } else if (cmd == 0x206) {
794                 if ((end - start) < ctx->buf_sizes[4]) {
795                         DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
796                                           (unsigned)(end - start),
797                                           ctx->buf_sizes[4]);
798                         return -EINVAL;
799                 }
800         } else if ((cmd != 0x100) && (cmd != 0x204)) {
801                 DRM_ERROR("invalid UVD command %X!\n", cmd);
802                 return -EINVAL;
803         }
804
805         if (!ctx->parser->adev->uvd.address_64_bit) {
806                 if ((start >> 28) != ((end - 1) >> 28)) {
807                         DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
808                                   start, end);
809                         return -EINVAL;
810                 }
811
812                 if ((cmd == 0 || cmd == 0x3) &&
813                     (start >> 28) != (ctx->parser->adev->uvd.inst->gpu_addr >> 28)) {
814                         DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
815                                   start, end);
816                         return -EINVAL;
817                 }
818         }
819
820         if (cmd == 0) {
821                 ctx->has_msg_cmd = true;
822                 r = amdgpu_uvd_cs_msg(ctx, bo, addr);
823                 if (r)
824                         return r;
825         } else if (!ctx->has_msg_cmd) {
826                 DRM_ERROR("Message needed before other commands are send!\n");
827                 return -EINVAL;
828         }
829
830         return 0;
831 }
832
833 /**
834  * amdgpu_uvd_cs_reg - parse register writes
835  *
836  * @ctx: UVD parser context
837  * @cb: callback function
838  *
839  * Parse the register writes, call cb on each complete command.
840  */
841 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx,
842                              int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
843 {
844         struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
845         int i, r;
846
847         ctx->idx++;
848         for (i = 0; i <= ctx->count; ++i) {
849                 unsigned reg = ctx->reg + i;
850
851                 if (ctx->idx >= ib->length_dw) {
852                         DRM_ERROR("Register command after end of CS!\n");
853                         return -EINVAL;
854                 }
855
856                 switch (reg) {
857                 case mmUVD_GPCOM_VCPU_DATA0:
858                         ctx->data0 = ctx->idx;
859                         break;
860                 case mmUVD_GPCOM_VCPU_DATA1:
861                         ctx->data1 = ctx->idx;
862                         break;
863                 case mmUVD_GPCOM_VCPU_CMD:
864                         r = cb(ctx);
865                         if (r)
866                                 return r;
867                         break;
868                 case mmUVD_ENGINE_CNTL:
869                 case mmUVD_NO_OP:
870                         break;
871                 default:
872                         DRM_ERROR("Invalid reg 0x%X!\n", reg);
873                         return -EINVAL;
874                 }
875                 ctx->idx++;
876         }
877         return 0;
878 }
879
880 /**
881  * amdgpu_uvd_cs_packets - parse UVD packets
882  *
883  * @ctx: UVD parser context
884  * @cb: callback function
885  *
886  * Parse the command stream packets.
887  */
888 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx,
889                                  int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
890 {
891         struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
892         int r;
893
894         for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) {
895                 uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx);
896                 unsigned type = CP_PACKET_GET_TYPE(cmd);
897                 switch (type) {
898                 case PACKET_TYPE0:
899                         ctx->reg = CP_PACKET0_GET_REG(cmd);
900                         ctx->count = CP_PACKET_GET_COUNT(cmd);
901                         r = amdgpu_uvd_cs_reg(ctx, cb);
902                         if (r)
903                                 return r;
904                         break;
905                 case PACKET_TYPE2:
906                         ++ctx->idx;
907                         break;
908                 default:
909                         DRM_ERROR("Unknown packet type %d !\n", type);
910                         return -EINVAL;
911                 }
912         }
913         return 0;
914 }
915
916 /**
917  * amdgpu_uvd_ring_parse_cs - UVD command submission parser
918  *
919  * @parser: Command submission parser context
920  *
921  * Parse the command stream, patch in addresses as necessary.
922  */
923 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
924 {
925         struct amdgpu_uvd_cs_ctx ctx = {};
926         unsigned buf_sizes[] = {
927                 [0x00000000]    =       2048,
928                 [0x00000001]    =       0xFFFFFFFF,
929                 [0x00000002]    =       0xFFFFFFFF,
930                 [0x00000003]    =       2048,
931                 [0x00000004]    =       0xFFFFFFFF,
932         };
933         struct amdgpu_ib *ib = &parser->job->ibs[ib_idx];
934         int r;
935
936         parser->job->vm = NULL;
937         ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
938
939         if (ib->length_dw % 16) {
940                 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
941                           ib->length_dw);
942                 return -EINVAL;
943         }
944
945         ctx.parser = parser;
946         ctx.buf_sizes = buf_sizes;
947         ctx.ib_idx = ib_idx;
948
949         /* first round only required on chips without UVD 64 bit address support */
950         if (!parser->adev->uvd.address_64_bit) {
951                 /* first round, make sure the buffers are actually in the UVD segment */
952                 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1);
953                 if (r)
954                         return r;
955         }
956
957         /* second round, patch buffer addresses into the command stream */
958         r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2);
959         if (r)
960                 return r;
961
962         if (!ctx.has_msg_cmd) {
963                 DRM_ERROR("UVD-IBs need a msg command!\n");
964                 return -EINVAL;
965         }
966
967         return 0;
968 }
969
970 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
971                                bool direct, struct dma_fence **fence)
972 {
973         struct amdgpu_device *adev = ring->adev;
974         struct dma_fence *f = NULL;
975         struct amdgpu_job *job;
976         struct amdgpu_ib *ib;
977         uint32_t data[4];
978         uint64_t addr;
979         long r;
980         int i;
981
982         amdgpu_bo_kunmap(bo);
983         amdgpu_bo_unpin(bo);
984
985         if (!ring->adev->uvd.address_64_bit) {
986                 struct ttm_operation_ctx ctx = { true, false };
987
988                 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
989                 amdgpu_uvd_force_into_uvd_segment(bo);
990                 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
991                 if (r)
992                         goto err;
993         }
994
995         r = amdgpu_job_alloc_with_ib(adev, 64, &job);
996         if (r)
997                 goto err;
998
999         if (adev->asic_type >= CHIP_VEGA10) {
1000                 data[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0_VEGA10, 0);
1001                 data[1] = PACKET0(mmUVD_GPCOM_VCPU_DATA1_VEGA10, 0);
1002                 data[2] = PACKET0(mmUVD_GPCOM_VCPU_CMD_VEGA10, 0);
1003                 data[3] = PACKET0(mmUVD_NO_OP_VEGA10, 0);
1004         } else {
1005                 data[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0);
1006                 data[1] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0);
1007                 data[2] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0);
1008                 data[3] = PACKET0(mmUVD_NO_OP, 0);
1009         }
1010
1011         ib = &job->ibs[0];
1012         addr = amdgpu_bo_gpu_offset(bo);
1013         ib->ptr[0] = data[0];
1014         ib->ptr[1] = addr;
1015         ib->ptr[2] = data[1];
1016         ib->ptr[3] = addr >> 32;
1017         ib->ptr[4] = data[2];
1018         ib->ptr[5] = 0;
1019         for (i = 6; i < 16; i += 2) {
1020                 ib->ptr[i] = data[3];
1021                 ib->ptr[i+1] = 0;
1022         }
1023         ib->length_dw = 16;
1024
1025         if (direct) {
1026                 r = reservation_object_wait_timeout_rcu(bo->tbo.resv,
1027                                                         true, false,
1028                                                         msecs_to_jiffies(10));
1029                 if (r == 0)
1030                         r = -ETIMEDOUT;
1031                 if (r < 0)
1032                         goto err_free;
1033
1034                 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
1035                 job->fence = dma_fence_get(f);
1036                 if (r)
1037                         goto err_free;
1038
1039                 amdgpu_job_free(job);
1040         } else {
1041                 r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.resv,
1042                                      AMDGPU_FENCE_OWNER_UNDEFINED, false);
1043                 if (r)
1044                         goto err_free;
1045
1046                 r = amdgpu_job_submit(job, ring, &adev->uvd.inst->entity,
1047                                       AMDGPU_FENCE_OWNER_UNDEFINED, &f);
1048                 if (r)
1049                         goto err_free;
1050         }
1051
1052         amdgpu_bo_fence(bo, f, false);
1053         amdgpu_bo_unreserve(bo);
1054         amdgpu_bo_unref(&bo);
1055
1056         if (fence)
1057                 *fence = dma_fence_get(f);
1058         dma_fence_put(f);
1059
1060         return 0;
1061
1062 err_free:
1063         amdgpu_job_free(job);
1064
1065 err:
1066         amdgpu_bo_unreserve(bo);
1067         amdgpu_bo_unref(&bo);
1068         return r;
1069 }
1070
1071 /* multiple fence commands without any stream commands in between can
1072    crash the vcpu so just try to emmit a dummy create/destroy msg to
1073    avoid this */
1074 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
1075                               struct dma_fence **fence)
1076 {
1077         struct amdgpu_device *adev = ring->adev;
1078         struct amdgpu_bo *bo = NULL;
1079         uint32_t *msg;
1080         int r, i;
1081
1082         r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
1083                                       AMDGPU_GEM_DOMAIN_VRAM,
1084                                       &bo, NULL, (void **)&msg);
1085         if (r)
1086                 return r;
1087
1088         /* stitch together an UVD create msg */
1089         msg[0] = cpu_to_le32(0x00000de4);
1090         msg[1] = cpu_to_le32(0x00000000);
1091         msg[2] = cpu_to_le32(handle);
1092         msg[3] = cpu_to_le32(0x00000000);
1093         msg[4] = cpu_to_le32(0x00000000);
1094         msg[5] = cpu_to_le32(0x00000000);
1095         msg[6] = cpu_to_le32(0x00000000);
1096         msg[7] = cpu_to_le32(0x00000780);
1097         msg[8] = cpu_to_le32(0x00000440);
1098         msg[9] = cpu_to_le32(0x00000000);
1099         msg[10] = cpu_to_le32(0x01b37000);
1100         for (i = 11; i < 1024; ++i)
1101                 msg[i] = cpu_to_le32(0x0);
1102
1103         return amdgpu_uvd_send_msg(ring, bo, true, fence);
1104 }
1105
1106 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
1107                                bool direct, struct dma_fence **fence)
1108 {
1109         struct amdgpu_device *adev = ring->adev;
1110         struct amdgpu_bo *bo = NULL;
1111         uint32_t *msg;
1112         int r, i;
1113
1114         r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
1115                                       AMDGPU_GEM_DOMAIN_VRAM,
1116                                       &bo, NULL, (void **)&msg);
1117         if (r)
1118                 return r;
1119
1120         /* stitch together an UVD destroy msg */
1121         msg[0] = cpu_to_le32(0x00000de4);
1122         msg[1] = cpu_to_le32(0x00000002);
1123         msg[2] = cpu_to_le32(handle);
1124         msg[3] = cpu_to_le32(0x00000000);
1125         for (i = 4; i < 1024; ++i)
1126                 msg[i] = cpu_to_le32(0x0);
1127
1128         return amdgpu_uvd_send_msg(ring, bo, direct, fence);
1129 }
1130
1131 static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
1132 {
1133         struct amdgpu_device *adev =
1134                 container_of(work, struct amdgpu_device, uvd.inst->idle_work.work);
1135         unsigned fences = amdgpu_fence_count_emitted(&adev->uvd.inst->ring);
1136
1137         if (fences == 0) {
1138                 if (adev->pm.dpm_enabled) {
1139                         amdgpu_dpm_enable_uvd(adev, false);
1140                 } else {
1141                         amdgpu_asic_set_uvd_clocks(adev, 0, 0);
1142                         /* shutdown the UVD block */
1143                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1144                                                                AMD_PG_STATE_GATE);
1145                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1146                                                                AMD_CG_STATE_GATE);
1147                 }
1148         } else {
1149                 schedule_delayed_work(&adev->uvd.inst->idle_work, UVD_IDLE_TIMEOUT);
1150         }
1151 }
1152
1153 void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring)
1154 {
1155         struct amdgpu_device *adev = ring->adev;
1156         bool set_clocks;
1157
1158         if (amdgpu_sriov_vf(adev))
1159                 return;
1160
1161         set_clocks = !cancel_delayed_work_sync(&adev->uvd.inst->idle_work);
1162         if (set_clocks) {
1163                 if (adev->pm.dpm_enabled) {
1164                         amdgpu_dpm_enable_uvd(adev, true);
1165                 } else {
1166                         amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
1167                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1168                                                                AMD_CG_STATE_UNGATE);
1169                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1170                                                                AMD_PG_STATE_UNGATE);
1171                 }
1172         }
1173 }
1174
1175 void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring)
1176 {
1177         if (!amdgpu_sriov_vf(ring->adev))
1178                 schedule_delayed_work(&ring->adev->uvd.inst->idle_work, UVD_IDLE_TIMEOUT);
1179 }
1180
1181 /**
1182  * amdgpu_uvd_ring_test_ib - test ib execution
1183  *
1184  * @ring: amdgpu_ring pointer
1185  *
1186  * Test if we can successfully execute an IB
1187  */
1188 int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1189 {
1190         struct dma_fence *fence;
1191         long r;
1192
1193         r = amdgpu_uvd_get_create_msg(ring, 1, NULL);
1194         if (r) {
1195                 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
1196                 goto error;
1197         }
1198
1199         r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence);
1200         if (r) {
1201                 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
1202                 goto error;
1203         }
1204
1205         r = dma_fence_wait_timeout(fence, false, timeout);
1206         if (r == 0) {
1207                 DRM_ERROR("amdgpu: IB test timed out.\n");
1208                 r = -ETIMEDOUT;
1209         } else if (r < 0) {
1210                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1211         } else {
1212                 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
1213                 r = 0;
1214         }
1215
1216         dma_fence_put(fence);
1217
1218 error:
1219         return r;
1220 }
1221
1222 /**
1223  * amdgpu_uvd_used_handles - returns used UVD handles
1224  *
1225  * @adev: amdgpu_device pointer
1226  *
1227  * Returns the number of UVD handles in use
1228  */
1229 uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev)
1230 {
1231         unsigned i;
1232         uint32_t used_handles = 0;
1233
1234         for (i = 0; i < adev->uvd.max_handles; ++i) {
1235                 /*
1236                  * Handles can be freed in any order, and not
1237                  * necessarily linear. So we need to count
1238                  * all non-zero handles.
1239                  */
1240                 if (atomic_read(&adev->uvd.inst->handles[i]))
1241                         used_handles++;
1242         }
1243
1244         return used_handles;
1245 }