amdgfx/gfx: don't use static objects for ce/de meta. (v2)
[muen/linux.git] / drivers / gpu / drm / amd / amdgpu / gfx_v8_0.c
1 /*
2  * Copyright 2014 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #include <linux/firmware.h>
24 #include <drm/drmP.h>
25 #include "amdgpu.h"
26 #include "amdgpu_gfx.h"
27 #include "vi.h"
28 #include "vi_structs.h"
29 #include "vid.h"
30 #include "amdgpu_ucode.h"
31 #include "amdgpu_atombios.h"
32 #include "atombios_i2c.h"
33 #include "clearstate_vi.h"
34
35 #include "gmc/gmc_8_2_d.h"
36 #include "gmc/gmc_8_2_sh_mask.h"
37
38 #include "oss/oss_3_0_d.h"
39 #include "oss/oss_3_0_sh_mask.h"
40
41 #include "bif/bif_5_0_d.h"
42 #include "bif/bif_5_0_sh_mask.h"
43 #include "gca/gfx_8_0_d.h"
44 #include "gca/gfx_8_0_enum.h"
45 #include "gca/gfx_8_0_sh_mask.h"
46 #include "gca/gfx_8_0_enum.h"
47
48 #include "dce/dce_10_0_d.h"
49 #include "dce/dce_10_0_sh_mask.h"
50
51 #include "smu/smu_7_1_3_d.h"
52
53 #define GFX8_NUM_GFX_RINGS     1
54 #define GFX8_MEC_HPD_SIZE 2048
55
56 #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
57 #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
58 #define POLARIS11_GB_ADDR_CONFIG_GOLDEN 0x22011002
59 #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
60
61 #define ARRAY_MODE(x)                                   ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
62 #define PIPE_CONFIG(x)                                  ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
63 #define TILE_SPLIT(x)                                   ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
64 #define MICRO_TILE_MODE_NEW(x)                          ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT)
65 #define SAMPLE_SPLIT(x)                                 ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
66 #define BANK_WIDTH(x)                                   ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT)
67 #define BANK_HEIGHT(x)                                  ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT)
68 #define MACRO_TILE_ASPECT(x)                            ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT)
69 #define NUM_BANKS(x)                                    ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT)
70
71 #define RLC_CGTT_MGCG_OVERRIDE__CPF_MASK            0x00000001L
72 #define RLC_CGTT_MGCG_OVERRIDE__RLC_MASK            0x00000002L
73 #define RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK           0x00000004L
74 #define RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK           0x00000008L
75 #define RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK           0x00000010L
76 #define RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK           0x00000020L
77
78 /* BPM SERDES CMD */
79 #define SET_BPM_SERDES_CMD    1
80 #define CLE_BPM_SERDES_CMD    0
81
82 /* BPM Register Address*/
83 enum {
84         BPM_REG_CGLS_EN = 0,        /* Enable/Disable CGLS */
85         BPM_REG_CGLS_ON,            /* ON/OFF CGLS: shall be controlled by RLC FW */
86         BPM_REG_CGCG_OVERRIDE,      /* Set/Clear CGCG Override */
87         BPM_REG_MGCG_OVERRIDE,      /* Set/Clear MGCG Override */
88         BPM_REG_FGCG_OVERRIDE,      /* Set/Clear FGCG Override */
89         BPM_REG_FGCG_MAX
90 };
91
92 #define RLC_FormatDirectRegListLength        14
93
94 MODULE_FIRMWARE("amdgpu/carrizo_ce.bin");
95 MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin");
96 MODULE_FIRMWARE("amdgpu/carrizo_me.bin");
97 MODULE_FIRMWARE("amdgpu/carrizo_mec.bin");
98 MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin");
99 MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin");
100
101 MODULE_FIRMWARE("amdgpu/stoney_ce.bin");
102 MODULE_FIRMWARE("amdgpu/stoney_pfp.bin");
103 MODULE_FIRMWARE("amdgpu/stoney_me.bin");
104 MODULE_FIRMWARE("amdgpu/stoney_mec.bin");
105 MODULE_FIRMWARE("amdgpu/stoney_rlc.bin");
106
107 MODULE_FIRMWARE("amdgpu/tonga_ce.bin");
108 MODULE_FIRMWARE("amdgpu/tonga_pfp.bin");
109 MODULE_FIRMWARE("amdgpu/tonga_me.bin");
110 MODULE_FIRMWARE("amdgpu/tonga_mec.bin");
111 MODULE_FIRMWARE("amdgpu/tonga_mec2.bin");
112 MODULE_FIRMWARE("amdgpu/tonga_rlc.bin");
113
114 MODULE_FIRMWARE("amdgpu/topaz_ce.bin");
115 MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
116 MODULE_FIRMWARE("amdgpu/topaz_me.bin");
117 MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
118 MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");
119
120 MODULE_FIRMWARE("amdgpu/fiji_ce.bin");
121 MODULE_FIRMWARE("amdgpu/fiji_pfp.bin");
122 MODULE_FIRMWARE("amdgpu/fiji_me.bin");
123 MODULE_FIRMWARE("amdgpu/fiji_mec.bin");
124 MODULE_FIRMWARE("amdgpu/fiji_mec2.bin");
125 MODULE_FIRMWARE("amdgpu/fiji_rlc.bin");
126
127 MODULE_FIRMWARE("amdgpu/polaris11_ce.bin");
128 MODULE_FIRMWARE("amdgpu/polaris11_ce_2.bin");
129 MODULE_FIRMWARE("amdgpu/polaris11_pfp.bin");
130 MODULE_FIRMWARE("amdgpu/polaris11_pfp_2.bin");
131 MODULE_FIRMWARE("amdgpu/polaris11_me.bin");
132 MODULE_FIRMWARE("amdgpu/polaris11_me_2.bin");
133 MODULE_FIRMWARE("amdgpu/polaris11_mec.bin");
134 MODULE_FIRMWARE("amdgpu/polaris11_mec_2.bin");
135 MODULE_FIRMWARE("amdgpu/polaris11_mec2.bin");
136 MODULE_FIRMWARE("amdgpu/polaris11_mec2_2.bin");
137 MODULE_FIRMWARE("amdgpu/polaris11_rlc.bin");
138
139 MODULE_FIRMWARE("amdgpu/polaris10_ce.bin");
140 MODULE_FIRMWARE("amdgpu/polaris10_ce_2.bin");
141 MODULE_FIRMWARE("amdgpu/polaris10_pfp.bin");
142 MODULE_FIRMWARE("amdgpu/polaris10_pfp_2.bin");
143 MODULE_FIRMWARE("amdgpu/polaris10_me.bin");
144 MODULE_FIRMWARE("amdgpu/polaris10_me_2.bin");
145 MODULE_FIRMWARE("amdgpu/polaris10_mec.bin");
146 MODULE_FIRMWARE("amdgpu/polaris10_mec_2.bin");
147 MODULE_FIRMWARE("amdgpu/polaris10_mec2.bin");
148 MODULE_FIRMWARE("amdgpu/polaris10_mec2_2.bin");
149 MODULE_FIRMWARE("amdgpu/polaris10_rlc.bin");
150
151 MODULE_FIRMWARE("amdgpu/polaris12_ce.bin");
152 MODULE_FIRMWARE("amdgpu/polaris12_ce_2.bin");
153 MODULE_FIRMWARE("amdgpu/polaris12_pfp.bin");
154 MODULE_FIRMWARE("amdgpu/polaris12_pfp_2.bin");
155 MODULE_FIRMWARE("amdgpu/polaris12_me.bin");
156 MODULE_FIRMWARE("amdgpu/polaris12_me_2.bin");
157 MODULE_FIRMWARE("amdgpu/polaris12_mec.bin");
158 MODULE_FIRMWARE("amdgpu/polaris12_mec_2.bin");
159 MODULE_FIRMWARE("amdgpu/polaris12_mec2.bin");
160 MODULE_FIRMWARE("amdgpu/polaris12_mec2_2.bin");
161 MODULE_FIRMWARE("amdgpu/polaris12_rlc.bin");
162
163 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
164 {
165         {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
166         {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
167         {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
168         {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
169         {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
170         {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
171         {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
172         {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
173         {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
174         {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
175         {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
176         {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
177         {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
178         {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
179         {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
180         {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
181 };
182
183 static const u32 golden_settings_tonga_a11[] =
184 {
185         mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
186         mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
187         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
188         mmGB_GPU_ID, 0x0000000f, 0x00000000,
189         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
190         mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
191         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
192         mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
193         mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
194         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
195         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
196         mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
197         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
198         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
199         mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
200         mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
201 };
202
203 static const u32 tonga_golden_common_all[] =
204 {
205         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
206         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
207         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
208         mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
209         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
210         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
211         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
212         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
213 };
214
215 static const u32 tonga_mgcg_cgcg_init[] =
216 {
217         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
218         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
219         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
220         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
221         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
222         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
223         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
224         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
225         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
226         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
227         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
228         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
229         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
230         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
231         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
232         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
233         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
234         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
235         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
236         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
237         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
238         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
239         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
240         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
241         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
242         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
243         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
244         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
245         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
246         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
247         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
248         mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
249         mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
250         mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
251         mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
252         mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
253         mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
254         mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
255         mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
256         mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
257         mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
258         mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
259         mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
260         mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
261         mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
262         mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
263         mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
264         mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
265         mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
266         mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
267         mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
268         mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
269         mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
270         mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
271         mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
272         mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
273         mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
274         mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
275         mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
276         mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
277         mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
278         mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
279         mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
280         mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
281         mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
282         mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
283         mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
284         mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
285         mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
286         mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
287         mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
288         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
289         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
290         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
291         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
292 };
293
294 static const u32 golden_settings_polaris11_a11[] =
295 {
296         mmCB_HW_CONTROL, 0x0000f3cf, 0x00007208,
297         mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
298         mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
299         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
300         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
301         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
302         mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
303         mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
304         mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
305         mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
306         mmSQ_CONFIG, 0x07f80000, 0x01180000,
307         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
308         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
309         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3,
310         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
311         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210,
312         mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
313 };
314
315 static const u32 polaris11_golden_common_all[] =
316 {
317         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
318         mmGB_ADDR_CONFIG, 0xffffffff, 0x22011002,
319         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
320         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
321         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
322         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
323 };
324
325 static const u32 golden_settings_polaris10_a11[] =
326 {
327         mmATC_MISC_CG, 0x000c0fc0, 0x000c0200,
328         mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208,
329         mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
330         mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
331         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
332         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
333         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
334         mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
335         mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002a,
336         mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
337         mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
338         mmSQ_CONFIG, 0x07f80000, 0x07180000,
339         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
340         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
341         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
342         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
343         mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
344 };
345
346 static const u32 polaris10_golden_common_all[] =
347 {
348         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
349         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
350         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
351         mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
352         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
353         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
354         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
355         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
356 };
357
358 static const u32 fiji_golden_common_all[] =
359 {
360         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
361         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a,
362         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,
363         mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
364         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
365         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
366         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
367         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
368         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
369         mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009,
370 };
371
372 static const u32 golden_settings_fiji_a10[] =
373 {
374         mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
375         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
376         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
377         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
378         mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
379         mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
380         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
381         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
382         mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
383         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff,
384         mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
385 };
386
387 static const u32 fiji_mgcg_cgcg_init[] =
388 {
389         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
390         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
391         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
392         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
393         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
394         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
395         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
396         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
397         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
398         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
399         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
400         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
401         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
402         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
403         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
404         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
405         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
406         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
407         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
408         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
409         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
410         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
411         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
412         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
413         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
414         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
415         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
416         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
417         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
418         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
419         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
420         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
421         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
422         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
423         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
424 };
425
426 static const u32 golden_settings_iceland_a11[] =
427 {
428         mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
429         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
430         mmDB_DEBUG3, 0xc0000000, 0xc0000000,
431         mmGB_GPU_ID, 0x0000000f, 0x00000000,
432         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
433         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
434         mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
435         mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
436         mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
437         mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
438         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
439         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
440         mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
441         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
442         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
443         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
444 };
445
446 static const u32 iceland_golden_common_all[] =
447 {
448         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
449         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
450         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
451         mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
452         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
453         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
454         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
455         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
456 };
457
458 static const u32 iceland_mgcg_cgcg_init[] =
459 {
460         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
461         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
462         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
463         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
464         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
465         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
466         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
467         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
468         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
469         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
470         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
471         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
472         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
473         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
474         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
475         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
476         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
477         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
478         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
479         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
480         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
481         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
482         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
483         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
484         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
485         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
486         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
487         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
488         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
489         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
490         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
491         mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
492         mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
493         mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
494         mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
495         mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
496         mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
497         mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
498         mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
499         mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
500         mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
501         mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
502         mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
503         mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
504         mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
505         mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
506         mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
507         mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
508         mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
509         mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
510         mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
511         mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
512         mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
513         mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
514         mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
515         mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
516         mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
517         mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
518         mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
519         mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
520         mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
521         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
522         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
523         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
524 };
525
526 static const u32 cz_golden_settings_a11[] =
527 {
528         mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
529         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
530         mmGB_GPU_ID, 0x0000000f, 0x00000000,
531         mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
532         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
533         mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
534         mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
535         mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
536         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
537         mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
538         mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
539         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
540 };
541
542 static const u32 cz_golden_common_all[] =
543 {
544         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
545         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
546         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
547         mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
548         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
549         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
550         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
551         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
552 };
553
554 static const u32 cz_mgcg_cgcg_init[] =
555 {
556         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
557         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
558         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
559         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
560         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
561         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
562         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
563         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
564         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
565         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
566         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
567         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
568         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
569         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
570         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
571         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
572         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
573         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
574         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
575         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
576         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
577         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
578         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
579         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
580         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
581         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
582         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
583         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
584         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
585         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
586         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
587         mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
588         mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
589         mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
590         mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
591         mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
592         mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
593         mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
594         mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
595         mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
596         mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
597         mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
598         mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
599         mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
600         mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
601         mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
602         mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
603         mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
604         mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
605         mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
606         mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
607         mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
608         mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
609         mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
610         mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
611         mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
612         mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
613         mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
614         mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
615         mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
616         mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
617         mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
618         mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
619         mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
620         mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
621         mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
622         mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
623         mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
624         mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
625         mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
626         mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
627         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
628         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
629         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
630         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
631 };
632
633 static const u32 stoney_golden_settings_a11[] =
634 {
635         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
636         mmGB_GPU_ID, 0x0000000f, 0x00000000,
637         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
638         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
639         mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
640         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
641         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
642         mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
643         mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f1,
644         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x10101010,
645 };
646
647 static const u32 stoney_golden_common_all[] =
648 {
649         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
650         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000000,
651         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
652         mmGB_ADDR_CONFIG, 0xffffffff, 0x12010001,
653         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
654         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
655         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
656         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
657 };
658
659 static const u32 stoney_mgcg_cgcg_init[] =
660 {
661         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
662         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
663         mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
664         mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
665         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
666 };
667
668 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
669 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
670 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
671 static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev);
672 static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev);
673 static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev);
674 static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring);
675 static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring);
676
677 static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
678 {
679         switch (adev->asic_type) {
680         case CHIP_TOPAZ:
681                 amdgpu_program_register_sequence(adev,
682                                                  iceland_mgcg_cgcg_init,
683                                                  (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
684                 amdgpu_program_register_sequence(adev,
685                                                  golden_settings_iceland_a11,
686                                                  (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
687                 amdgpu_program_register_sequence(adev,
688                                                  iceland_golden_common_all,
689                                                  (const u32)ARRAY_SIZE(iceland_golden_common_all));
690                 break;
691         case CHIP_FIJI:
692                 amdgpu_program_register_sequence(adev,
693                                                  fiji_mgcg_cgcg_init,
694                                                  (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
695                 amdgpu_program_register_sequence(adev,
696                                                  golden_settings_fiji_a10,
697                                                  (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
698                 amdgpu_program_register_sequence(adev,
699                                                  fiji_golden_common_all,
700                                                  (const u32)ARRAY_SIZE(fiji_golden_common_all));
701                 break;
702
703         case CHIP_TONGA:
704                 amdgpu_program_register_sequence(adev,
705                                                  tonga_mgcg_cgcg_init,
706                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
707                 amdgpu_program_register_sequence(adev,
708                                                  golden_settings_tonga_a11,
709                                                  (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
710                 amdgpu_program_register_sequence(adev,
711                                                  tonga_golden_common_all,
712                                                  (const u32)ARRAY_SIZE(tonga_golden_common_all));
713                 break;
714         case CHIP_POLARIS11:
715         case CHIP_POLARIS12:
716                 amdgpu_program_register_sequence(adev,
717                                                  golden_settings_polaris11_a11,
718                                                  (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
719                 amdgpu_program_register_sequence(adev,
720                                                  polaris11_golden_common_all,
721                                                  (const u32)ARRAY_SIZE(polaris11_golden_common_all));
722                 break;
723         case CHIP_POLARIS10:
724                 amdgpu_program_register_sequence(adev,
725                                                  golden_settings_polaris10_a11,
726                                                  (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
727                 amdgpu_program_register_sequence(adev,
728                                                  polaris10_golden_common_all,
729                                                  (const u32)ARRAY_SIZE(polaris10_golden_common_all));
730                 WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C);
731                 if (adev->pdev->revision == 0xc7 &&
732                     ((adev->pdev->subsystem_device == 0xb37 && adev->pdev->subsystem_vendor == 0x1002) ||
733                      (adev->pdev->subsystem_device == 0x4a8 && adev->pdev->subsystem_vendor == 0x1043) ||
734                      (adev->pdev->subsystem_device == 0x9480 && adev->pdev->subsystem_vendor == 0x1682))) {
735                         amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1E, 0xDD);
736                         amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1F, 0xD0);
737                 }
738                 break;
739         case CHIP_CARRIZO:
740                 amdgpu_program_register_sequence(adev,
741                                                  cz_mgcg_cgcg_init,
742                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
743                 amdgpu_program_register_sequence(adev,
744                                                  cz_golden_settings_a11,
745                                                  (const u32)ARRAY_SIZE(cz_golden_settings_a11));
746                 amdgpu_program_register_sequence(adev,
747                                                  cz_golden_common_all,
748                                                  (const u32)ARRAY_SIZE(cz_golden_common_all));
749                 break;
750         case CHIP_STONEY:
751                 amdgpu_program_register_sequence(adev,
752                                                  stoney_mgcg_cgcg_init,
753                                                  (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
754                 amdgpu_program_register_sequence(adev,
755                                                  stoney_golden_settings_a11,
756                                                  (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
757                 amdgpu_program_register_sequence(adev,
758                                                  stoney_golden_common_all,
759                                                  (const u32)ARRAY_SIZE(stoney_golden_common_all));
760                 break;
761         default:
762                 break;
763         }
764 }
765
766 static void gfx_v8_0_scratch_init(struct amdgpu_device *adev)
767 {
768         adev->gfx.scratch.num_reg = 8;
769         adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
770         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
771 }
772
773 static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
774 {
775         struct amdgpu_device *adev = ring->adev;
776         uint32_t scratch;
777         uint32_t tmp = 0;
778         unsigned i;
779         int r;
780
781         r = amdgpu_gfx_scratch_get(adev, &scratch);
782         if (r) {
783                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
784                 return r;
785         }
786         WREG32(scratch, 0xCAFEDEAD);
787         r = amdgpu_ring_alloc(ring, 3);
788         if (r) {
789                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
790                           ring->idx, r);
791                 amdgpu_gfx_scratch_free(adev, scratch);
792                 return r;
793         }
794         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
795         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
796         amdgpu_ring_write(ring, 0xDEADBEEF);
797         amdgpu_ring_commit(ring);
798
799         for (i = 0; i < adev->usec_timeout; i++) {
800                 tmp = RREG32(scratch);
801                 if (tmp == 0xDEADBEEF)
802                         break;
803                 DRM_UDELAY(1);
804         }
805         if (i < adev->usec_timeout) {
806                 DRM_INFO("ring test on %d succeeded in %d usecs\n",
807                          ring->idx, i);
808         } else {
809                 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
810                           ring->idx, scratch, tmp);
811                 r = -EINVAL;
812         }
813         amdgpu_gfx_scratch_free(adev, scratch);
814         return r;
815 }
816
817 static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
818 {
819         struct amdgpu_device *adev = ring->adev;
820         struct amdgpu_ib ib;
821         struct dma_fence *f = NULL;
822         uint32_t scratch;
823         uint32_t tmp = 0;
824         long r;
825
826         r = amdgpu_gfx_scratch_get(adev, &scratch);
827         if (r) {
828                 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
829                 return r;
830         }
831         WREG32(scratch, 0xCAFEDEAD);
832         memset(&ib, 0, sizeof(ib));
833         r = amdgpu_ib_get(adev, NULL, 256, &ib);
834         if (r) {
835                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
836                 goto err1;
837         }
838         ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
839         ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
840         ib.ptr[2] = 0xDEADBEEF;
841         ib.length_dw = 3;
842
843         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
844         if (r)
845                 goto err2;
846
847         r = dma_fence_wait_timeout(f, false, timeout);
848         if (r == 0) {
849                 DRM_ERROR("amdgpu: IB test timed out.\n");
850                 r = -ETIMEDOUT;
851                 goto err2;
852         } else if (r < 0) {
853                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
854                 goto err2;
855         }
856         tmp = RREG32(scratch);
857         if (tmp == 0xDEADBEEF) {
858                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
859                 r = 0;
860         } else {
861                 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
862                           scratch, tmp);
863                 r = -EINVAL;
864         }
865 err2:
866         amdgpu_ib_free(adev, &ib, NULL);
867         dma_fence_put(f);
868 err1:
869         amdgpu_gfx_scratch_free(adev, scratch);
870         return r;
871 }
872
873
874 static void gfx_v8_0_free_microcode(struct amdgpu_device *adev)
875 {
876         release_firmware(adev->gfx.pfp_fw);
877         adev->gfx.pfp_fw = NULL;
878         release_firmware(adev->gfx.me_fw);
879         adev->gfx.me_fw = NULL;
880         release_firmware(adev->gfx.ce_fw);
881         adev->gfx.ce_fw = NULL;
882         release_firmware(adev->gfx.rlc_fw);
883         adev->gfx.rlc_fw = NULL;
884         release_firmware(adev->gfx.mec_fw);
885         adev->gfx.mec_fw = NULL;
886         if ((adev->asic_type != CHIP_STONEY) &&
887             (adev->asic_type != CHIP_TOPAZ))
888                 release_firmware(adev->gfx.mec2_fw);
889         adev->gfx.mec2_fw = NULL;
890
891         kfree(adev->gfx.rlc.register_list_format);
892 }
893
894 static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
895 {
896         const char *chip_name;
897         char fw_name[30];
898         int err;
899         struct amdgpu_firmware_info *info = NULL;
900         const struct common_firmware_header *header = NULL;
901         const struct gfx_firmware_header_v1_0 *cp_hdr;
902         const struct rlc_firmware_header_v2_0 *rlc_hdr;
903         unsigned int *tmp = NULL, i;
904
905         DRM_DEBUG("\n");
906
907         switch (adev->asic_type) {
908         case CHIP_TOPAZ:
909                 chip_name = "topaz";
910                 break;
911         case CHIP_TONGA:
912                 chip_name = "tonga";
913                 break;
914         case CHIP_CARRIZO:
915                 chip_name = "carrizo";
916                 break;
917         case CHIP_FIJI:
918                 chip_name = "fiji";
919                 break;
920         case CHIP_POLARIS11:
921                 chip_name = "polaris11";
922                 break;
923         case CHIP_POLARIS10:
924                 chip_name = "polaris10";
925                 break;
926         case CHIP_POLARIS12:
927                 chip_name = "polaris12";
928                 break;
929         case CHIP_STONEY:
930                 chip_name = "stoney";
931                 break;
932         default:
933                 BUG();
934         }
935
936         if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
937                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp_2.bin", chip_name);
938                 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
939                 if (err == -ENOENT) {
940                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
941                         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
942                 }
943         } else {
944                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
945                 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
946         }
947         if (err)
948                 goto out;
949         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
950         if (err)
951                 goto out;
952         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
953         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
954         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
955
956         if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
957                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me_2.bin", chip_name);
958                 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
959                 if (err == -ENOENT) {
960                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
961                         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
962                 }
963         } else {
964                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
965                 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
966         }
967         if (err)
968                 goto out;
969         err = amdgpu_ucode_validate(adev->gfx.me_fw);
970         if (err)
971                 goto out;
972         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
973         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
974
975         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
976
977         if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
978                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce_2.bin", chip_name);
979                 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
980                 if (err == -ENOENT) {
981                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
982                         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
983                 }
984         } else {
985                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
986                 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
987         }
988         if (err)
989                 goto out;
990         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
991         if (err)
992                 goto out;
993         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
994         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
995         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
996
997         /*
998          * Support for MCBP/Virtualization in combination with chained IBs is
999          * formal released on feature version #46
1000          */
1001         if (adev->gfx.ce_feature_version >= 46 &&
1002             adev->gfx.pfp_feature_version >= 46) {
1003                 adev->virt.chained_ib_support = true;
1004                 DRM_INFO("Chained IB support enabled!\n");
1005         } else
1006                 adev->virt.chained_ib_support = false;
1007
1008         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
1009         err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
1010         if (err)
1011                 goto out;
1012         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
1013         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1014         adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
1015         adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
1016
1017         adev->gfx.rlc.save_and_restore_offset =
1018                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
1019         adev->gfx.rlc.clear_state_descriptor_offset =
1020                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
1021         adev->gfx.rlc.avail_scratch_ram_locations =
1022                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
1023         adev->gfx.rlc.reg_restore_list_size =
1024                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
1025         adev->gfx.rlc.reg_list_format_start =
1026                         le32_to_cpu(rlc_hdr->reg_list_format_start);
1027         adev->gfx.rlc.reg_list_format_separate_start =
1028                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
1029         adev->gfx.rlc.starting_offsets_start =
1030                         le32_to_cpu(rlc_hdr->starting_offsets_start);
1031         adev->gfx.rlc.reg_list_format_size_bytes =
1032                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
1033         adev->gfx.rlc.reg_list_size_bytes =
1034                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
1035
1036         adev->gfx.rlc.register_list_format =
1037                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
1038                                         adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
1039
1040         if (!adev->gfx.rlc.register_list_format) {
1041                 err = -ENOMEM;
1042                 goto out;
1043         }
1044
1045         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
1046                         le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
1047         for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
1048                 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
1049
1050         adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
1051
1052         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
1053                         le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
1054         for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
1055                 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
1056
1057         if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1058                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec_2.bin", chip_name);
1059                 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
1060                 if (err == -ENOENT) {
1061                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
1062                         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
1063                 }
1064         } else {
1065                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
1066                 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
1067         }
1068         if (err)
1069                 goto out;
1070         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
1071         if (err)
1072                 goto out;
1073         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1074         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1075         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1076
1077         if ((adev->asic_type != CHIP_STONEY) &&
1078             (adev->asic_type != CHIP_TOPAZ)) {
1079                 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1080                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2_2.bin", chip_name);
1081                         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
1082                         if (err == -ENOENT) {
1083                                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
1084                                 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
1085                         }
1086                 } else {
1087                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
1088                         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
1089                 }
1090                 if (!err) {
1091                         err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
1092                         if (err)
1093                                 goto out;
1094                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1095                                 adev->gfx.mec2_fw->data;
1096                         adev->gfx.mec2_fw_version =
1097                                 le32_to_cpu(cp_hdr->header.ucode_version);
1098                         adev->gfx.mec2_feature_version =
1099                                 le32_to_cpu(cp_hdr->ucode_feature_version);
1100                 } else {
1101                         err = 0;
1102                         adev->gfx.mec2_fw = NULL;
1103                 }
1104         }
1105
1106         if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) {
1107                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
1108                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
1109                 info->fw = adev->gfx.pfp_fw;
1110                 header = (const struct common_firmware_header *)info->fw->data;
1111                 adev->firmware.fw_size +=
1112                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1113
1114                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
1115                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
1116                 info->fw = adev->gfx.me_fw;
1117                 header = (const struct common_firmware_header *)info->fw->data;
1118                 adev->firmware.fw_size +=
1119                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1120
1121                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
1122                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
1123                 info->fw = adev->gfx.ce_fw;
1124                 header = (const struct common_firmware_header *)info->fw->data;
1125                 adev->firmware.fw_size +=
1126                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1127
1128                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
1129                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
1130                 info->fw = adev->gfx.rlc_fw;
1131                 header = (const struct common_firmware_header *)info->fw->data;
1132                 adev->firmware.fw_size +=
1133                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1134
1135                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
1136                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
1137                 info->fw = adev->gfx.mec_fw;
1138                 header = (const struct common_firmware_header *)info->fw->data;
1139                 adev->firmware.fw_size +=
1140                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1141
1142                 /* we need account JT in */
1143                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1144                 adev->firmware.fw_size +=
1145                         ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
1146
1147                 if (amdgpu_sriov_vf(adev)) {
1148                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_STORAGE];
1149                         info->ucode_id = AMDGPU_UCODE_ID_STORAGE;
1150                         info->fw = adev->gfx.mec_fw;
1151                         adev->firmware.fw_size +=
1152                                 ALIGN(le32_to_cpu(64 * PAGE_SIZE), PAGE_SIZE);
1153                 }
1154
1155                 if (adev->gfx.mec2_fw) {
1156                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
1157                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
1158                         info->fw = adev->gfx.mec2_fw;
1159                         header = (const struct common_firmware_header *)info->fw->data;
1160                         adev->firmware.fw_size +=
1161                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1162                 }
1163
1164         }
1165
1166 out:
1167         if (err) {
1168                 dev_err(adev->dev,
1169                         "gfx8: Failed to load firmware \"%s\"\n",
1170                         fw_name);
1171                 release_firmware(adev->gfx.pfp_fw);
1172                 adev->gfx.pfp_fw = NULL;
1173                 release_firmware(adev->gfx.me_fw);
1174                 adev->gfx.me_fw = NULL;
1175                 release_firmware(adev->gfx.ce_fw);
1176                 adev->gfx.ce_fw = NULL;
1177                 release_firmware(adev->gfx.rlc_fw);
1178                 adev->gfx.rlc_fw = NULL;
1179                 release_firmware(adev->gfx.mec_fw);
1180                 adev->gfx.mec_fw = NULL;
1181                 release_firmware(adev->gfx.mec2_fw);
1182                 adev->gfx.mec2_fw = NULL;
1183         }
1184         return err;
1185 }
1186
1187 static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev,
1188                                     volatile u32 *buffer)
1189 {
1190         u32 count = 0, i;
1191         const struct cs_section_def *sect = NULL;
1192         const struct cs_extent_def *ext = NULL;
1193
1194         if (adev->gfx.rlc.cs_data == NULL)
1195                 return;
1196         if (buffer == NULL)
1197                 return;
1198
1199         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1200         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1201
1202         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
1203         buffer[count++] = cpu_to_le32(0x80000000);
1204         buffer[count++] = cpu_to_le32(0x80000000);
1205
1206         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
1207                 for (ext = sect->section; ext->extent != NULL; ++ext) {
1208                         if (sect->id == SECT_CONTEXT) {
1209                                 buffer[count++] =
1210                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
1211                                 buffer[count++] = cpu_to_le32(ext->reg_index -
1212                                                 PACKET3_SET_CONTEXT_REG_START);
1213                                 for (i = 0; i < ext->reg_count; i++)
1214                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
1215                         } else {
1216                                 return;
1217                         }
1218                 }
1219         }
1220
1221         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
1222         buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG -
1223                         PACKET3_SET_CONTEXT_REG_START);
1224         buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config);
1225         buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1);
1226
1227         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1228         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
1229
1230         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
1231         buffer[count++] = cpu_to_le32(0);
1232 }
1233
1234 static void cz_init_cp_jump_table(struct amdgpu_device *adev)
1235 {
1236         const __le32 *fw_data;
1237         volatile u32 *dst_ptr;
1238         int me, i, max_me = 4;
1239         u32 bo_offset = 0;
1240         u32 table_offset, table_size;
1241
1242         if (adev->asic_type == CHIP_CARRIZO)
1243                 max_me = 5;
1244
1245         /* write the cp table buffer */
1246         dst_ptr = adev->gfx.rlc.cp_table_ptr;
1247         for (me = 0; me < max_me; me++) {
1248                 if (me == 0) {
1249                         const struct gfx_firmware_header_v1_0 *hdr =
1250                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1251                         fw_data = (const __le32 *)
1252                                 (adev->gfx.ce_fw->data +
1253                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1254                         table_offset = le32_to_cpu(hdr->jt_offset);
1255                         table_size = le32_to_cpu(hdr->jt_size);
1256                 } else if (me == 1) {
1257                         const struct gfx_firmware_header_v1_0 *hdr =
1258                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
1259                         fw_data = (const __le32 *)
1260                                 (adev->gfx.pfp_fw->data +
1261                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1262                         table_offset = le32_to_cpu(hdr->jt_offset);
1263                         table_size = le32_to_cpu(hdr->jt_size);
1264                 } else if (me == 2) {
1265                         const struct gfx_firmware_header_v1_0 *hdr =
1266                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1267                         fw_data = (const __le32 *)
1268                                 (adev->gfx.me_fw->data +
1269                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1270                         table_offset = le32_to_cpu(hdr->jt_offset);
1271                         table_size = le32_to_cpu(hdr->jt_size);
1272                 } else if (me == 3) {
1273                         const struct gfx_firmware_header_v1_0 *hdr =
1274                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1275                         fw_data = (const __le32 *)
1276                                 (adev->gfx.mec_fw->data +
1277                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1278                         table_offset = le32_to_cpu(hdr->jt_offset);
1279                         table_size = le32_to_cpu(hdr->jt_size);
1280                 } else  if (me == 4) {
1281                         const struct gfx_firmware_header_v1_0 *hdr =
1282                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
1283                         fw_data = (const __le32 *)
1284                                 (adev->gfx.mec2_fw->data +
1285                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1286                         table_offset = le32_to_cpu(hdr->jt_offset);
1287                         table_size = le32_to_cpu(hdr->jt_size);
1288                 }
1289
1290                 for (i = 0; i < table_size; i ++) {
1291                         dst_ptr[bo_offset + i] =
1292                                 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
1293                 }
1294
1295                 bo_offset += table_size;
1296         }
1297 }
1298
1299 static void gfx_v8_0_rlc_fini(struct amdgpu_device *adev)
1300 {
1301         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, NULL, NULL);
1302         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, NULL, NULL);
1303 }
1304
1305 static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
1306 {
1307         volatile u32 *dst_ptr;
1308         u32 dws;
1309         const struct cs_section_def *cs_data;
1310         int r;
1311
1312         adev->gfx.rlc.cs_data = vi_cs_data;
1313
1314         cs_data = adev->gfx.rlc.cs_data;
1315
1316         if (cs_data) {
1317                 /* clear state block */
1318                 adev->gfx.rlc.clear_state_size = dws = gfx_v8_0_get_csb_size(adev);
1319
1320                 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
1321                                               AMDGPU_GEM_DOMAIN_VRAM,
1322                                               &adev->gfx.rlc.clear_state_obj,
1323                                               &adev->gfx.rlc.clear_state_gpu_addr,
1324                                               (void **)&adev->gfx.rlc.cs_ptr);
1325                 if (r) {
1326                         dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
1327                         gfx_v8_0_rlc_fini(adev);
1328                         return r;
1329                 }
1330
1331                 /* set up the cs buffer */
1332                 dst_ptr = adev->gfx.rlc.cs_ptr;
1333                 gfx_v8_0_get_csb_buffer(adev, dst_ptr);
1334                 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
1335                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1336         }
1337
1338         if ((adev->asic_type == CHIP_CARRIZO) ||
1339             (adev->asic_type == CHIP_STONEY)) {
1340                 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
1341                 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size,
1342                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1343                                               &adev->gfx.rlc.cp_table_obj,
1344                                               &adev->gfx.rlc.cp_table_gpu_addr,
1345                                               (void **)&adev->gfx.rlc.cp_table_ptr);
1346                 if (r) {
1347                         dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r);
1348                         return r;
1349                 }
1350
1351                 cz_init_cp_jump_table(adev);
1352
1353                 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
1354                 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
1355         }
1356
1357         return 0;
1358 }
1359
1360 static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
1361 {
1362         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
1363 }
1364
1365 static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
1366 {
1367         int r;
1368         u32 *hpd;
1369         size_t mec_hpd_size;
1370
1371         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1372
1373         /* take ownership of the relevant compute queues */
1374         amdgpu_gfx_compute_queue_acquire(adev);
1375
1376         mec_hpd_size = adev->gfx.num_compute_rings * GFX8_MEC_HPD_SIZE;
1377
1378         r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
1379                                       AMDGPU_GEM_DOMAIN_GTT,
1380                                       &adev->gfx.mec.hpd_eop_obj,
1381                                       &adev->gfx.mec.hpd_eop_gpu_addr,
1382                                       (void **)&hpd);
1383         if (r) {
1384                 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1385                 return r;
1386         }
1387
1388         memset(hpd, 0, mec_hpd_size);
1389
1390         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1391         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1392
1393         return 0;
1394 }
1395
1396 static const u32 vgpr_init_compute_shader[] =
1397 {
1398         0x7e000209, 0x7e020208,
1399         0x7e040207, 0x7e060206,
1400         0x7e080205, 0x7e0a0204,
1401         0x7e0c0203, 0x7e0e0202,
1402         0x7e100201, 0x7e120200,
1403         0x7e140209, 0x7e160208,
1404         0x7e180207, 0x7e1a0206,
1405         0x7e1c0205, 0x7e1e0204,
1406         0x7e200203, 0x7e220202,
1407         0x7e240201, 0x7e260200,
1408         0x7e280209, 0x7e2a0208,
1409         0x7e2c0207, 0x7e2e0206,
1410         0x7e300205, 0x7e320204,
1411         0x7e340203, 0x7e360202,
1412         0x7e380201, 0x7e3a0200,
1413         0x7e3c0209, 0x7e3e0208,
1414         0x7e400207, 0x7e420206,
1415         0x7e440205, 0x7e460204,
1416         0x7e480203, 0x7e4a0202,
1417         0x7e4c0201, 0x7e4e0200,
1418         0x7e500209, 0x7e520208,
1419         0x7e540207, 0x7e560206,
1420         0x7e580205, 0x7e5a0204,
1421         0x7e5c0203, 0x7e5e0202,
1422         0x7e600201, 0x7e620200,
1423         0x7e640209, 0x7e660208,
1424         0x7e680207, 0x7e6a0206,
1425         0x7e6c0205, 0x7e6e0204,
1426         0x7e700203, 0x7e720202,
1427         0x7e740201, 0x7e760200,
1428         0x7e780209, 0x7e7a0208,
1429         0x7e7c0207, 0x7e7e0206,
1430         0xbf8a0000, 0xbf810000,
1431 };
1432
1433 static const u32 sgpr_init_compute_shader[] =
1434 {
1435         0xbe8a0100, 0xbe8c0102,
1436         0xbe8e0104, 0xbe900106,
1437         0xbe920108, 0xbe940100,
1438         0xbe960102, 0xbe980104,
1439         0xbe9a0106, 0xbe9c0108,
1440         0xbe9e0100, 0xbea00102,
1441         0xbea20104, 0xbea40106,
1442         0xbea60108, 0xbea80100,
1443         0xbeaa0102, 0xbeac0104,
1444         0xbeae0106, 0xbeb00108,
1445         0xbeb20100, 0xbeb40102,
1446         0xbeb60104, 0xbeb80106,
1447         0xbeba0108, 0xbebc0100,
1448         0xbebe0102, 0xbec00104,
1449         0xbec20106, 0xbec40108,
1450         0xbec60100, 0xbec80102,
1451         0xbee60004, 0xbee70005,
1452         0xbeea0006, 0xbeeb0007,
1453         0xbee80008, 0xbee90009,
1454         0xbefc0000, 0xbf8a0000,
1455         0xbf810000, 0x00000000,
1456 };
1457
1458 static const u32 vgpr_init_regs[] =
1459 {
1460         mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xffffffff,
1461         mmCOMPUTE_RESOURCE_LIMITS, 0,
1462         mmCOMPUTE_NUM_THREAD_X, 256*4,
1463         mmCOMPUTE_NUM_THREAD_Y, 1,
1464         mmCOMPUTE_NUM_THREAD_Z, 1,
1465         mmCOMPUTE_PGM_RSRC2, 20,
1466         mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1467         mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1468         mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1469         mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1470         mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1471         mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1472         mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1473         mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1474         mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1475         mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1476 };
1477
1478 static const u32 sgpr1_init_regs[] =
1479 {
1480         mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0x0f,
1481         mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,
1482         mmCOMPUTE_NUM_THREAD_X, 256*5,
1483         mmCOMPUTE_NUM_THREAD_Y, 1,
1484         mmCOMPUTE_NUM_THREAD_Z, 1,
1485         mmCOMPUTE_PGM_RSRC2, 20,
1486         mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1487         mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1488         mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1489         mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1490         mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1491         mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1492         mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1493         mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1494         mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1495         mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1496 };
1497
1498 static const u32 sgpr2_init_regs[] =
1499 {
1500         mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xf0,
1501         mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,
1502         mmCOMPUTE_NUM_THREAD_X, 256*5,
1503         mmCOMPUTE_NUM_THREAD_Y, 1,
1504         mmCOMPUTE_NUM_THREAD_Z, 1,
1505         mmCOMPUTE_PGM_RSRC2, 20,
1506         mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1507         mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1508         mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1509         mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1510         mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1511         mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1512         mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1513         mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1514         mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1515         mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1516 };
1517
1518 static const u32 sec_ded_counter_registers[] =
1519 {
1520         mmCPC_EDC_ATC_CNT,
1521         mmCPC_EDC_SCRATCH_CNT,
1522         mmCPC_EDC_UCODE_CNT,
1523         mmCPF_EDC_ATC_CNT,
1524         mmCPF_EDC_ROQ_CNT,
1525         mmCPF_EDC_TAG_CNT,
1526         mmCPG_EDC_ATC_CNT,
1527         mmCPG_EDC_DMA_CNT,
1528         mmCPG_EDC_TAG_CNT,
1529         mmDC_EDC_CSINVOC_CNT,
1530         mmDC_EDC_RESTORE_CNT,
1531         mmDC_EDC_STATE_CNT,
1532         mmGDS_EDC_CNT,
1533         mmGDS_EDC_GRBM_CNT,
1534         mmGDS_EDC_OA_DED,
1535         mmSPI_EDC_CNT,
1536         mmSQC_ATC_EDC_GATCL1_CNT,
1537         mmSQC_EDC_CNT,
1538         mmSQ_EDC_DED_CNT,
1539         mmSQ_EDC_INFO,
1540         mmSQ_EDC_SEC_CNT,
1541         mmTCC_EDC_CNT,
1542         mmTCP_ATC_EDC_GATCL1_CNT,
1543         mmTCP_EDC_CNT,
1544         mmTD_EDC_CNT
1545 };
1546
1547 static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
1548 {
1549         struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
1550         struct amdgpu_ib ib;
1551         struct dma_fence *f = NULL;
1552         int r, i;
1553         u32 tmp;
1554         unsigned total_size, vgpr_offset, sgpr_offset;
1555         u64 gpu_addr;
1556
1557         /* only supported on CZ */
1558         if (adev->asic_type != CHIP_CARRIZO)
1559                 return 0;
1560
1561         /* bail if the compute ring is not ready */
1562         if (!ring->ready)
1563                 return 0;
1564
1565         tmp = RREG32(mmGB_EDC_MODE);
1566         WREG32(mmGB_EDC_MODE, 0);
1567
1568         total_size =
1569                 (((ARRAY_SIZE(vgpr_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1570         total_size +=
1571                 (((ARRAY_SIZE(sgpr1_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1572         total_size +=
1573                 (((ARRAY_SIZE(sgpr2_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1574         total_size = ALIGN(total_size, 256);
1575         vgpr_offset = total_size;
1576         total_size += ALIGN(sizeof(vgpr_init_compute_shader), 256);
1577         sgpr_offset = total_size;
1578         total_size += sizeof(sgpr_init_compute_shader);
1579
1580         /* allocate an indirect buffer to put the commands in */
1581         memset(&ib, 0, sizeof(ib));
1582         r = amdgpu_ib_get(adev, NULL, total_size, &ib);
1583         if (r) {
1584                 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
1585                 return r;
1586         }
1587
1588         /* load the compute shaders */
1589         for (i = 0; i < ARRAY_SIZE(vgpr_init_compute_shader); i++)
1590                 ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_compute_shader[i];
1591
1592         for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++)
1593                 ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i];
1594
1595         /* init the ib length to 0 */
1596         ib.length_dw = 0;
1597
1598         /* VGPR */
1599         /* write the register state for the compute dispatch */
1600         for (i = 0; i < ARRAY_SIZE(vgpr_init_regs); i += 2) {
1601                 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1602                 ib.ptr[ib.length_dw++] = vgpr_init_regs[i] - PACKET3_SET_SH_REG_START;
1603                 ib.ptr[ib.length_dw++] = vgpr_init_regs[i + 1];
1604         }
1605         /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1606         gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8;
1607         ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1608         ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1609         ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1610         ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1611
1612         /* write dispatch packet */
1613         ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1614         ib.ptr[ib.length_dw++] = 8; /* x */
1615         ib.ptr[ib.length_dw++] = 1; /* y */
1616         ib.ptr[ib.length_dw++] = 1; /* z */
1617         ib.ptr[ib.length_dw++] =
1618                 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1619
1620         /* write CS partial flush packet */
1621         ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1622         ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1623
1624         /* SGPR1 */
1625         /* write the register state for the compute dispatch */
1626         for (i = 0; i < ARRAY_SIZE(sgpr1_init_regs); i += 2) {
1627                 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1628                 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i] - PACKET3_SET_SH_REG_START;
1629                 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i + 1];
1630         }
1631         /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1632         gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
1633         ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1634         ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1635         ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1636         ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1637
1638         /* write dispatch packet */
1639         ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1640         ib.ptr[ib.length_dw++] = 8; /* x */
1641         ib.ptr[ib.length_dw++] = 1; /* y */
1642         ib.ptr[ib.length_dw++] = 1; /* z */
1643         ib.ptr[ib.length_dw++] =
1644                 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1645
1646         /* write CS partial flush packet */
1647         ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1648         ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1649
1650         /* SGPR2 */
1651         /* write the register state for the compute dispatch */
1652         for (i = 0; i < ARRAY_SIZE(sgpr2_init_regs); i += 2) {
1653                 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1654                 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i] - PACKET3_SET_SH_REG_START;
1655                 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i + 1];
1656         }
1657         /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1658         gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
1659         ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1660         ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1661         ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1662         ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1663
1664         /* write dispatch packet */
1665         ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1666         ib.ptr[ib.length_dw++] = 8; /* x */
1667         ib.ptr[ib.length_dw++] = 1; /* y */
1668         ib.ptr[ib.length_dw++] = 1; /* z */
1669         ib.ptr[ib.length_dw++] =
1670                 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1671
1672         /* write CS partial flush packet */
1673         ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1674         ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1675
1676         /* shedule the ib on the ring */
1677         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1678         if (r) {
1679                 DRM_ERROR("amdgpu: ib submit failed (%d).\n", r);
1680                 goto fail;
1681         }
1682
1683         /* wait for the GPU to finish processing the IB */
1684         r = dma_fence_wait(f, false);
1685         if (r) {
1686                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
1687                 goto fail;
1688         }
1689
1690         tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2);
1691         tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1);
1692         WREG32(mmGB_EDC_MODE, tmp);
1693
1694         tmp = RREG32(mmCC_GC_EDC_CONFIG);
1695         tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1;
1696         WREG32(mmCC_GC_EDC_CONFIG, tmp);
1697
1698
1699         /* read back registers to clear the counters */
1700         for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++)
1701                 RREG32(sec_ded_counter_registers[i]);
1702
1703 fail:
1704         amdgpu_ib_free(adev, &ib, NULL);
1705         dma_fence_put(f);
1706
1707         return r;
1708 }
1709
1710 static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
1711 {
1712         u32 gb_addr_config;
1713         u32 mc_shared_chmap, mc_arb_ramcfg;
1714         u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
1715         u32 tmp;
1716         int ret;
1717
1718         switch (adev->asic_type) {
1719         case CHIP_TOPAZ:
1720                 adev->gfx.config.max_shader_engines = 1;
1721                 adev->gfx.config.max_tile_pipes = 2;
1722                 adev->gfx.config.max_cu_per_sh = 6;
1723                 adev->gfx.config.max_sh_per_se = 1;
1724                 adev->gfx.config.max_backends_per_se = 2;
1725                 adev->gfx.config.max_texture_channel_caches = 2;
1726                 adev->gfx.config.max_gprs = 256;
1727                 adev->gfx.config.max_gs_threads = 32;
1728                 adev->gfx.config.max_hw_contexts = 8;
1729
1730                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1731                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1732                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1733                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1734                 gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
1735                 break;
1736         case CHIP_FIJI:
1737                 adev->gfx.config.max_shader_engines = 4;
1738                 adev->gfx.config.max_tile_pipes = 16;
1739                 adev->gfx.config.max_cu_per_sh = 16;
1740                 adev->gfx.config.max_sh_per_se = 1;
1741                 adev->gfx.config.max_backends_per_se = 4;
1742                 adev->gfx.config.max_texture_channel_caches = 16;
1743                 adev->gfx.config.max_gprs = 256;
1744                 adev->gfx.config.max_gs_threads = 32;
1745                 adev->gfx.config.max_hw_contexts = 8;
1746
1747                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1748                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1749                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1750                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1751                 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1752                 break;
1753         case CHIP_POLARIS11:
1754         case CHIP_POLARIS12:
1755                 ret = amdgpu_atombios_get_gfx_info(adev);
1756                 if (ret)
1757                         return ret;
1758                 adev->gfx.config.max_gprs = 256;
1759                 adev->gfx.config.max_gs_threads = 32;
1760                 adev->gfx.config.max_hw_contexts = 8;
1761
1762                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1763                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1764                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1765                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1766                 gb_addr_config = POLARIS11_GB_ADDR_CONFIG_GOLDEN;
1767                 break;
1768         case CHIP_POLARIS10:
1769                 ret = amdgpu_atombios_get_gfx_info(adev);
1770                 if (ret)
1771                         return ret;
1772                 adev->gfx.config.max_gprs = 256;
1773                 adev->gfx.config.max_gs_threads = 32;
1774                 adev->gfx.config.max_hw_contexts = 8;
1775
1776                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1777                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1778                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1779                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1780                 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1781                 break;
1782         case CHIP_TONGA:
1783                 adev->gfx.config.max_shader_engines = 4;
1784                 adev->gfx.config.max_tile_pipes = 8;
1785                 adev->gfx.config.max_cu_per_sh = 8;
1786                 adev->gfx.config.max_sh_per_se = 1;
1787                 adev->gfx.config.max_backends_per_se = 2;
1788                 adev->gfx.config.max_texture_channel_caches = 8;
1789                 adev->gfx.config.max_gprs = 256;
1790                 adev->gfx.config.max_gs_threads = 32;
1791                 adev->gfx.config.max_hw_contexts = 8;
1792
1793                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1794                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1795                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1796                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1797                 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1798                 break;
1799         case CHIP_CARRIZO:
1800                 adev->gfx.config.max_shader_engines = 1;
1801                 adev->gfx.config.max_tile_pipes = 2;
1802                 adev->gfx.config.max_sh_per_se = 1;
1803                 adev->gfx.config.max_backends_per_se = 2;
1804                 adev->gfx.config.max_cu_per_sh = 8;
1805                 adev->gfx.config.max_texture_channel_caches = 2;
1806                 adev->gfx.config.max_gprs = 256;
1807                 adev->gfx.config.max_gs_threads = 32;
1808                 adev->gfx.config.max_hw_contexts = 8;
1809
1810                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1811                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1812                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1813                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1814                 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1815                 break;
1816         case CHIP_STONEY:
1817                 adev->gfx.config.max_shader_engines = 1;
1818                 adev->gfx.config.max_tile_pipes = 2;
1819                 adev->gfx.config.max_sh_per_se = 1;
1820                 adev->gfx.config.max_backends_per_se = 1;
1821                 adev->gfx.config.max_cu_per_sh = 3;
1822                 adev->gfx.config.max_texture_channel_caches = 2;
1823                 adev->gfx.config.max_gprs = 256;
1824                 adev->gfx.config.max_gs_threads = 16;
1825                 adev->gfx.config.max_hw_contexts = 8;
1826
1827                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1828                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1829                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1830                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1831                 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1832                 break;
1833         default:
1834                 adev->gfx.config.max_shader_engines = 2;
1835                 adev->gfx.config.max_tile_pipes = 4;
1836                 adev->gfx.config.max_cu_per_sh = 2;
1837                 adev->gfx.config.max_sh_per_se = 1;
1838                 adev->gfx.config.max_backends_per_se = 2;
1839                 adev->gfx.config.max_texture_channel_caches = 4;
1840                 adev->gfx.config.max_gprs = 256;
1841                 adev->gfx.config.max_gs_threads = 32;
1842                 adev->gfx.config.max_hw_contexts = 8;
1843
1844                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1845                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1846                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1847                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1848                 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1849                 break;
1850         }
1851
1852         mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
1853         adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1854         mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
1855
1856         adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1857         adev->gfx.config.mem_max_burst_length_bytes = 256;
1858         if (adev->flags & AMD_IS_APU) {
1859                 /* Get memory bank mapping mode. */
1860                 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
1861                 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1862                 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1863
1864                 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
1865                 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1866                 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1867
1868                 /* Validate settings in case only one DIMM installed. */
1869                 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
1870                         dimm00_addr_map = 0;
1871                 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
1872                         dimm01_addr_map = 0;
1873                 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
1874                         dimm10_addr_map = 0;
1875                 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
1876                         dimm11_addr_map = 0;
1877
1878                 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
1879                 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
1880                 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
1881                         adev->gfx.config.mem_row_size_in_kb = 2;
1882                 else
1883                         adev->gfx.config.mem_row_size_in_kb = 1;
1884         } else {
1885                 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
1886                 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1887                 if (adev->gfx.config.mem_row_size_in_kb > 4)
1888                         adev->gfx.config.mem_row_size_in_kb = 4;
1889         }
1890
1891         adev->gfx.config.shader_engine_tile_size = 32;
1892         adev->gfx.config.num_gpus = 1;
1893         adev->gfx.config.multi_gpu_tile_size = 64;
1894
1895         /* fix up row size */
1896         switch (adev->gfx.config.mem_row_size_in_kb) {
1897         case 1:
1898         default:
1899                 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
1900                 break;
1901         case 2:
1902                 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
1903                 break;
1904         case 4:
1905                 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
1906                 break;
1907         }
1908         adev->gfx.config.gb_addr_config = gb_addr_config;
1909
1910         return 0;
1911 }
1912
1913 static int gfx_v8_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1914                                         int mec, int pipe, int queue)
1915 {
1916         int r;
1917         unsigned irq_type;
1918         struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1919
1920         ring = &adev->gfx.compute_ring[ring_id];
1921
1922         /* mec0 is me1 */
1923         ring->me = mec + 1;
1924         ring->pipe = pipe;
1925         ring->queue = queue;
1926
1927         ring->ring_obj = NULL;
1928         ring->use_doorbell = true;
1929         ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + ring_id;
1930         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1931                                 + (ring_id * GFX8_MEC_HPD_SIZE);
1932         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1933
1934         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1935                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1936                 + ring->pipe;
1937
1938         /* type-2 packets are deprecated on MEC, use type-3 instead */
1939         r = amdgpu_ring_init(adev, ring, 1024,
1940                         &adev->gfx.eop_irq, irq_type);
1941         if (r)
1942                 return r;
1943
1944
1945         return 0;
1946 }
1947
1948 static int gfx_v8_0_sw_init(void *handle)
1949 {
1950         int i, j, k, r, ring_id;
1951         struct amdgpu_ring *ring;
1952         struct amdgpu_kiq *kiq;
1953         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1954
1955         switch (adev->asic_type) {
1956         case CHIP_FIJI:
1957         case CHIP_TONGA:
1958         case CHIP_POLARIS11:
1959         case CHIP_POLARIS12:
1960         case CHIP_POLARIS10:
1961         case CHIP_CARRIZO:
1962                 adev->gfx.mec.num_mec = 2;
1963                 break;
1964         case CHIP_TOPAZ:
1965         case CHIP_STONEY:
1966         default:
1967                 adev->gfx.mec.num_mec = 1;
1968                 break;
1969         }
1970
1971         adev->gfx.mec.num_pipe_per_mec = 4;
1972         adev->gfx.mec.num_queue_per_pipe = 8;
1973
1974         /* KIQ event */
1975         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 178, &adev->gfx.kiq.irq);
1976         if (r)
1977                 return r;
1978
1979         /* EOP Event */
1980         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
1981         if (r)
1982                 return r;
1983
1984         /* Privileged reg */
1985         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 184,
1986                               &adev->gfx.priv_reg_irq);
1987         if (r)
1988                 return r;
1989
1990         /* Privileged inst */
1991         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 185,
1992                               &adev->gfx.priv_inst_irq);
1993         if (r)
1994                 return r;
1995
1996         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1997
1998         gfx_v8_0_scratch_init(adev);
1999
2000         r = gfx_v8_0_init_microcode(adev);
2001         if (r) {
2002                 DRM_ERROR("Failed to load gfx firmware!\n");
2003                 return r;
2004         }
2005
2006         r = gfx_v8_0_rlc_init(adev);
2007         if (r) {
2008                 DRM_ERROR("Failed to init rlc BOs!\n");
2009                 return r;
2010         }
2011
2012         r = gfx_v8_0_mec_init(adev);
2013         if (r) {
2014                 DRM_ERROR("Failed to init MEC BOs!\n");
2015                 return r;
2016         }
2017
2018         /* set up the gfx ring */
2019         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
2020                 ring = &adev->gfx.gfx_ring[i];
2021                 ring->ring_obj = NULL;
2022                 sprintf(ring->name, "gfx");
2023                 /* no gfx doorbells on iceland */
2024                 if (adev->asic_type != CHIP_TOPAZ) {
2025                         ring->use_doorbell = true;
2026                         ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0;
2027                 }
2028
2029                 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq,
2030                                      AMDGPU_CP_IRQ_GFX_EOP);
2031                 if (r)
2032                         return r;
2033         }
2034
2035
2036         /* set up the compute queues - allocate horizontally across pipes */
2037         ring_id = 0;
2038         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
2039                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
2040                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
2041                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
2042                                         continue;
2043
2044                                 r = gfx_v8_0_compute_ring_init(adev,
2045                                                                 ring_id,
2046                                                                 i, k, j);
2047                                 if (r)
2048                                         return r;
2049
2050                                 ring_id++;
2051                         }
2052                 }
2053         }
2054
2055         r = amdgpu_gfx_kiq_init(adev, GFX8_MEC_HPD_SIZE);
2056         if (r) {
2057                 DRM_ERROR("Failed to init KIQ BOs!\n");
2058                 return r;
2059         }
2060
2061         kiq = &adev->gfx.kiq;
2062         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
2063         if (r)
2064                 return r;
2065
2066         /* create MQD for all compute queues as well as KIQ for SRIOV case */
2067         r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct vi_mqd_allocation));
2068         if (r)
2069                 return r;
2070
2071         /* reserve GDS, GWS and OA resource for gfx */
2072         r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
2073                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
2074                                     &adev->gds.gds_gfx_bo, NULL, NULL);
2075         if (r)
2076                 return r;
2077
2078         r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
2079                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
2080                                     &adev->gds.gws_gfx_bo, NULL, NULL);
2081         if (r)
2082                 return r;
2083
2084         r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
2085                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
2086                                     &adev->gds.oa_gfx_bo, NULL, NULL);
2087         if (r)
2088                 return r;
2089
2090         adev->gfx.ce_ram_size = 0x8000;
2091
2092         r = gfx_v8_0_gpu_early_init(adev);
2093         if (r)
2094                 return r;
2095
2096         return 0;
2097 }
2098
2099 static int gfx_v8_0_sw_fini(void *handle)
2100 {
2101         int i;
2102         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2103
2104         amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
2105         amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
2106         amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
2107
2108         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2109                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
2110         for (i = 0; i < adev->gfx.num_compute_rings; i++)
2111                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
2112
2113         amdgpu_gfx_compute_mqd_sw_fini(adev);
2114         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
2115         amdgpu_gfx_kiq_fini(adev);
2116         amdgpu_bo_free_kernel(&adev->virt.csa_obj, &adev->virt.csa_vmid0_addr, NULL);
2117
2118         gfx_v8_0_mec_fini(adev);
2119         gfx_v8_0_rlc_fini(adev);
2120         gfx_v8_0_free_microcode(adev);
2121
2122         return 0;
2123 }
2124
2125 static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
2126 {
2127         uint32_t *modearray, *mod2array;
2128         const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);
2129         const u32 num_secondary_tile_mode_states = ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
2130         u32 reg_offset;
2131
2132         modearray = adev->gfx.config.tile_mode_array;
2133         mod2array = adev->gfx.config.macrotile_mode_array;
2134
2135         for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2136                 modearray[reg_offset] = 0;
2137
2138         for (reg_offset = 0; reg_offset <  num_secondary_tile_mode_states; reg_offset++)
2139                 mod2array[reg_offset] = 0;
2140
2141         switch (adev->asic_type) {
2142         case CHIP_TOPAZ:
2143                 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2144                                 PIPE_CONFIG(ADDR_SURF_P2) |
2145                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2146                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2147                 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2148                                 PIPE_CONFIG(ADDR_SURF_P2) |
2149                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2150                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2151                 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2152                                 PIPE_CONFIG(ADDR_SURF_P2) |
2153                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2154                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2155                 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2156                                 PIPE_CONFIG(ADDR_SURF_P2) |
2157                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2158                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2159                 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2160                                 PIPE_CONFIG(ADDR_SURF_P2) |
2161                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2162                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2163                 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2164                                 PIPE_CONFIG(ADDR_SURF_P2) |
2165                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2166                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2167                 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2168                                 PIPE_CONFIG(ADDR_SURF_P2) |
2169                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2170                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2171                 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2172                                 PIPE_CONFIG(ADDR_SURF_P2));
2173                 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2174                                 PIPE_CONFIG(ADDR_SURF_P2) |
2175                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2176                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2177                 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2178                                  PIPE_CONFIG(ADDR_SURF_P2) |
2179                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2180                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2181                 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2182                                  PIPE_CONFIG(ADDR_SURF_P2) |
2183                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2184                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2185                 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2186                                  PIPE_CONFIG(ADDR_SURF_P2) |
2187                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2188                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2189                 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2190                                  PIPE_CONFIG(ADDR_SURF_P2) |
2191                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2192                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2193                 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2194                                  PIPE_CONFIG(ADDR_SURF_P2) |
2195                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2196                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2197                 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2198                                  PIPE_CONFIG(ADDR_SURF_P2) |
2199                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2200                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2201                 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2202                                  PIPE_CONFIG(ADDR_SURF_P2) |
2203                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2204                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2205                 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2206                                  PIPE_CONFIG(ADDR_SURF_P2) |
2207                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2208                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2209                 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2210                                  PIPE_CONFIG(ADDR_SURF_P2) |
2211                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2212                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2213                 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2214                                  PIPE_CONFIG(ADDR_SURF_P2) |
2215                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2216                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2217                 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2218                                  PIPE_CONFIG(ADDR_SURF_P2) |
2219                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2220                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2221                 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2222                                  PIPE_CONFIG(ADDR_SURF_P2) |
2223                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2224                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2225                 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2226                                  PIPE_CONFIG(ADDR_SURF_P2) |
2227                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2228                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2229                 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2230                                  PIPE_CONFIG(ADDR_SURF_P2) |
2231                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2232                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2233                 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2234                                  PIPE_CONFIG(ADDR_SURF_P2) |
2235                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2236                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2237                 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2238                                  PIPE_CONFIG(ADDR_SURF_P2) |
2239                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2240                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2241                 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2242                                  PIPE_CONFIG(ADDR_SURF_P2) |
2243                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2244                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2245
2246                 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2247                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2248                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2249                                 NUM_BANKS(ADDR_SURF_8_BANK));
2250                 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2251                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2252                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2253                                 NUM_BANKS(ADDR_SURF_8_BANK));
2254                 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2255                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2256                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2257                                 NUM_BANKS(ADDR_SURF_8_BANK));
2258                 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2259                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2260                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2261                                 NUM_BANKS(ADDR_SURF_8_BANK));
2262                 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2263                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2264                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2265                                 NUM_BANKS(ADDR_SURF_8_BANK));
2266                 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2267                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2268                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2269                                 NUM_BANKS(ADDR_SURF_8_BANK));
2270                 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2271                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2272                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2273                                 NUM_BANKS(ADDR_SURF_8_BANK));
2274                 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2275                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2276                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2277                                 NUM_BANKS(ADDR_SURF_16_BANK));
2278                 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2279                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2280                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2281                                 NUM_BANKS(ADDR_SURF_16_BANK));
2282                 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2283                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2284                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2285                                  NUM_BANKS(ADDR_SURF_16_BANK));
2286                 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2287                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2288                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2289                                  NUM_BANKS(ADDR_SURF_16_BANK));
2290                 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2291                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2292                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2293                                  NUM_BANKS(ADDR_SURF_16_BANK));
2294                 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2295                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2296                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2297                                  NUM_BANKS(ADDR_SURF_16_BANK));
2298                 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2299                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2300                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2301                                  NUM_BANKS(ADDR_SURF_8_BANK));
2302
2303                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2304                         if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
2305                             reg_offset != 23)
2306                                 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2307
2308                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2309                         if (reg_offset != 7)
2310                                 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2311
2312                 break;
2313         case CHIP_FIJI:
2314                 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2315                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2316                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2317                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2318                 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2319                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2320                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2321                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2322                 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2323                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2324                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2325                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2326                 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2327                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2328                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2329                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2330                 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2331                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2332                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2333                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2334                 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2335                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2336                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2337                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2338                 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2339                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2340                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2341                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2342                 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2343                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2344                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2345                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2346                 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2347                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
2348                 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2349                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2350                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2351                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2352                 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2353                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2354                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2355                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2356                 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2357                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2358                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2359                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2360                 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2361                                  PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2362                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2363                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2364                 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2365                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2366                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2367                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2368                 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2369                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2370                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2371                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2372                 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2373                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2374                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2375                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2376                 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2377                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2378                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2379                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2380                 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2381                                  PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2382                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2383                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2384                 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2385                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2386                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2387                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2388                 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2389                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2390                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2391                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2392                 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2393                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2394                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2395                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2396                 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2397                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2398                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2399                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2400                 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2401                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2402                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2403                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2404                 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2405                                  PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2406                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2407                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2408                 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2409                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2410                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2411                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2412                 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2413                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2414                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2415                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2416                 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2417                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2418                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2419                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2420                 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2421                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2422                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2423                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2424                 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2425                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2426                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2427                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2428                 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2429                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2430                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2431                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2432                 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2433                                  PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2434                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2435                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2436
2437                 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2438                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2439                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2440                                 NUM_BANKS(ADDR_SURF_8_BANK));
2441                 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2442                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2443                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2444                                 NUM_BANKS(ADDR_SURF_8_BANK));
2445                 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2446                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2447                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2448                                 NUM_BANKS(ADDR_SURF_8_BANK));
2449                 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2450                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2451                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2452                                 NUM_BANKS(ADDR_SURF_8_BANK));
2453                 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2454                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2455                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2456                                 NUM_BANKS(ADDR_SURF_8_BANK));
2457                 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2458                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2459                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2460                                 NUM_BANKS(ADDR_SURF_8_BANK));
2461                 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2462                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2463                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2464                                 NUM_BANKS(ADDR_SURF_8_BANK));
2465                 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2466                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2467                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2468                                 NUM_BANKS(ADDR_SURF_8_BANK));
2469                 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2470                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2471                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2472                                 NUM_BANKS(ADDR_SURF_8_BANK));
2473                 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2474                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2475                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2476                                  NUM_BANKS(ADDR_SURF_8_BANK));
2477                 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2478                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2479                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2480                                  NUM_BANKS(ADDR_SURF_8_BANK));
2481                 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2482                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2483                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2484                                  NUM_BANKS(ADDR_SURF_8_BANK));
2485                 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2486                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2487                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2488                                  NUM_BANKS(ADDR_SURF_8_BANK));
2489                 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2490                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2491                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2492                                  NUM_BANKS(ADDR_SURF_4_BANK));
2493
2494                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2495                         WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2496
2497                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2498                         if (reg_offset != 7)
2499                                 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2500
2501                 break;
2502         case CHIP_TONGA:
2503                 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2504                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2505                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2506                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2507                 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2508                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2509                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2510                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2511                 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2512                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2513                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2514                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2515                 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2516                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2517                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2518                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2519                 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2520                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2521                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2522                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2523                 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2524                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2525                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2526                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2527                 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2528                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2529                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2530                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2531                 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2532                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2533                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2534                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2535                 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2536                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2537                 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2538                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2539                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2540                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2541                 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2542                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2543                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2544                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2545                 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2546                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2547                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2548                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2549                 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2550                                  PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2551                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2552                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2553                 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2554                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2555                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2556                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2557                 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2558                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2559                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2560                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2561                 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2562                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2563                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2564                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2565                 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2566                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2567                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2568                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2569                 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2570                                  PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2571                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2572                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2573                 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2574                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2575                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2576                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2577                 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2578                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2579                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2580                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2581                 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2582                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2583                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2584                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2585                 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2586                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2587                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2588                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2589                 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2590                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2591                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2592                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2593                 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2594                                  PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2595                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2596                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2597                 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2598                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2599                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2600                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2601                 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2602                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2603                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2604                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2605                 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2606                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2607                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2608                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2609                 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2610                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2611                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2612                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2613                 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2614                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2615                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2616                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2617                 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2618                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2619                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2620                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2621                 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2622                                  PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2623                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2624                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2625
2626                 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2627                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2628                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2629                                 NUM_BANKS(ADDR_SURF_16_BANK));
2630                 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2631                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2632                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2633                                 NUM_BANKS(ADDR_SURF_16_BANK));
2634                 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2635                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2636                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2637                                 NUM_BANKS(ADDR_SURF_16_BANK));
2638                 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2639                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2640                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2641                                 NUM_BANKS(ADDR_SURF_16_BANK));
2642                 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2643                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2644                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2645                                 NUM_BANKS(ADDR_SURF_16_BANK));
2646                 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2647                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2648                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2649                                 NUM_BANKS(ADDR_SURF_16_BANK));
2650                 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2651                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2652                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2653                                 NUM_BANKS(ADDR_SURF_16_BANK));
2654                 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2655                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2656                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2657                                 NUM_BANKS(ADDR_SURF_16_BANK));
2658                 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2659                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2660                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2661                                 NUM_BANKS(ADDR_SURF_16_BANK));
2662                 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2663                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2664                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2665                                  NUM_BANKS(ADDR_SURF_16_BANK));
2666                 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2667                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2668                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2669                                  NUM_BANKS(ADDR_SURF_16_BANK));
2670                 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2671                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2672                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2673                                  NUM_BANKS(ADDR_SURF_8_BANK));
2674                 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2675                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2676                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2677                                  NUM_BANKS(ADDR_SURF_4_BANK));
2678                 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2679                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2680                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2681                                  NUM_BANKS(ADDR_SURF_4_BANK));
2682
2683                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2684                         WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2685
2686                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2687                         if (reg_offset != 7)
2688                                 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2689
2690                 break;
2691         case CHIP_POLARIS11:
2692         case CHIP_POLARIS12:
2693                 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2694                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2695                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2696                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2697                 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2698                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2699                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2700                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2701                 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2702                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2703                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2704                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2705                 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2706                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2707                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2708                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2709                 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2710                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2711                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2712                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2713                 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2714                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2715                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2716                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2717                 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2718                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2719                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2720                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2721                 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2722                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2723                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2724                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2725                 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2726                                 PIPE_CONFIG(ADDR_SURF_P4_16x16));
2727                 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2728                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2729                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2730                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2731                 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2732                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2733                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2734                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2735                 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2736                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2737                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2738                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2739                 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2740                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2741                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2742                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2743                 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2744                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2745                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2746                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2747                 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2748                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2749                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2750                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2751                 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2752                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2753                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2754                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2755                 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2756                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2757                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2758                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2759                 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2760                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2761                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2762                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2763                 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2764                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2765                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2766                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2767                 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2768                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2769                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2770                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2771                 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2772                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2773                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2774                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2775                 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2776                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2777                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2778                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2779                 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2780                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2781                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2782                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2783                 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2784                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2785                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2786                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2787                 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2788                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2789                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2790                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2791                 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2792                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2793                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2794                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2795                 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2796                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2797                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2798                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2799                 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2800                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2801                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2802                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2803                 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2804                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2805                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2806                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2807                 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2808                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2809                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2810                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2811                 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2812                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2813                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2814                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2815
2816                 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2817                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2818                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2819                                 NUM_BANKS(ADDR_SURF_16_BANK));
2820
2821                 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2822                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2823                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2824                                 NUM_BANKS(ADDR_SURF_16_BANK));
2825
2826                 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2827                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2828                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2829                                 NUM_BANKS(ADDR_SURF_16_BANK));
2830
2831                 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2832                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2833                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2834                                 NUM_BANKS(ADDR_SURF_16_BANK));
2835
2836                 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2837                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2838                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2839                                 NUM_BANKS(ADDR_SURF_16_BANK));
2840
2841                 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2842                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2843                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2844                                 NUM_BANKS(ADDR_SURF_16_BANK));
2845
2846                 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2847                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2848                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2849                                 NUM_BANKS(ADDR_SURF_16_BANK));
2850
2851                 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2852                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2853                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2854                                 NUM_BANKS(ADDR_SURF_16_BANK));
2855
2856                 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2857                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2858                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2859                                 NUM_BANKS(ADDR_SURF_16_BANK));
2860
2861                 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2862                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2863                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2864                                 NUM_BANKS(ADDR_SURF_16_BANK));
2865
2866                 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2867                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2868                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2869                                 NUM_BANKS(ADDR_SURF_16_BANK));
2870
2871                 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2872                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2873                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2874                                 NUM_BANKS(ADDR_SURF_16_BANK));
2875
2876                 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2877                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2878                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2879                                 NUM_BANKS(ADDR_SURF_8_BANK));
2880
2881                 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2882                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2883                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2884                                 NUM_BANKS(ADDR_SURF_4_BANK));
2885
2886                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2887                         WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2888
2889                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2890                         if (reg_offset != 7)
2891                                 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2892
2893                 break;
2894         case CHIP_POLARIS10:
2895                 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2896                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2897                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2898                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2899                 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2900                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2901                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2902                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2903               &n