2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
28 #include "amdgpu_atombios.h"
29 #include "amdgpu_ih.h"
30 #include "amdgpu_uvd.h"
31 #include "amdgpu_vce.h"
32 #include "amdgpu_ucode.h"
33 #include "amdgpu_psp.h"
37 #include "uvd/uvd_7_0_offset.h"
38 #include "gc/gc_9_0_offset.h"
39 #include "gc/gc_9_0_sh_mask.h"
40 #include "sdma0/sdma0_4_0_offset.h"
41 #include "sdma1/sdma1_4_0_offset.h"
42 #include "hdp/hdp_4_0_offset.h"
43 #include "hdp/hdp_4_0_sh_mask.h"
44 #include "smuio/smuio_9_0_offset.h"
45 #include "smuio/smuio_9_0_sh_mask.h"
48 #include "soc15_common.h"
51 #include "gfxhub_v1_0.h"
52 #include "mmhub_v1_0.h"
54 #include "vega10_ih.h"
55 #include "sdma_v4_0.h"
59 #include "dce_virtual.h"
62 #define mmMP0_MISC_CGTT_CTRL0 0x01b9
63 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
64 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
65 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
68 * Indirect registers accessor
70 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
72 unsigned long flags, address, data;
74 address = adev->nbio_funcs->get_pcie_index_offset(adev);
75 data = adev->nbio_funcs->get_pcie_data_offset(adev);
77 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
79 (void)RREG32(address);
81 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
85 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
87 unsigned long flags, address, data;
89 address = adev->nbio_funcs->get_pcie_index_offset(adev);
90 data = adev->nbio_funcs->get_pcie_data_offset(adev);
92 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
94 (void)RREG32(address);
97 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
100 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
102 unsigned long flags, address, data;
105 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
106 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
108 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
109 WREG32(address, ((reg) & 0x1ff));
111 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
115 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
117 unsigned long flags, address, data;
119 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
120 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
122 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
123 WREG32(address, ((reg) & 0x1ff));
125 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
128 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
130 unsigned long flags, address, data;
133 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
134 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
136 spin_lock_irqsave(&adev->didt_idx_lock, flags);
137 WREG32(address, (reg));
139 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
143 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
145 unsigned long flags, address, data;
147 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
148 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
150 spin_lock_irqsave(&adev->didt_idx_lock, flags);
151 WREG32(address, (reg));
153 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
156 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
161 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
162 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
163 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
164 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
168 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
172 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
173 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
174 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
175 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
178 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
183 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
184 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
185 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
186 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
190 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
194 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
195 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
196 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
197 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
200 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
202 return adev->nbio_funcs->get_memsize(adev);
205 static u32 soc15_get_xclk(struct amdgpu_device *adev)
207 return adev->clock.spll.reference_freq;
211 void soc15_grbm_select(struct amdgpu_device *adev,
212 u32 me, u32 pipe, u32 queue, u32 vmid)
214 u32 grbm_gfx_cntl = 0;
215 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
216 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
217 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
218 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
220 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
223 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
228 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
234 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
235 u8 *bios, u32 length_bytes)
242 if (length_bytes == 0)
244 /* APU vbios image is part of sbios image */
245 if (adev->flags & AMD_IS_APU)
248 dw_ptr = (u32 *)bios;
249 length_dw = ALIGN(length_bytes, 4) / 4;
251 /* set rom index to 0 */
252 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
253 /* read out the rom data */
254 for (i = 0; i < length_dw; i++)
255 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
260 struct soc15_allowed_register_entry {
269 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
270 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
271 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
272 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
273 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
274 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
275 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
276 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
277 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
278 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
279 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
280 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
281 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
282 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
283 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
284 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
285 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
286 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
287 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
288 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
291 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
292 u32 sh_num, u32 reg_offset)
296 mutex_lock(&adev->grbm_idx_mutex);
297 if (se_num != 0xffffffff || sh_num != 0xffffffff)
298 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
300 val = RREG32(reg_offset);
302 if (se_num != 0xffffffff || sh_num != 0xffffffff)
303 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
304 mutex_unlock(&adev->grbm_idx_mutex);
308 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
309 bool indexed, u32 se_num,
310 u32 sh_num, u32 reg_offset)
313 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
315 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
316 return adev->gfx.config.gb_addr_config;
317 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
318 return adev->gfx.config.db_debug2;
319 return RREG32(reg_offset);
323 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
324 u32 sh_num, u32 reg_offset, u32 *value)
327 struct soc15_allowed_register_entry *en;
330 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
331 en = &soc15_allowed_read_registers[i];
332 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
336 *value = soc15_get_register_value(adev,
337 soc15_allowed_read_registers[i].grbm_indexed,
338 se_num, sh_num, reg_offset);
346 * soc15_program_register_sequence - program an array of registers.
348 * @adev: amdgpu_device pointer
349 * @regs: pointer to the register array
350 * @array_size: size of the register array
352 * Programs an array or registers with and and or masks.
353 * This is a helper for setting golden registers.
356 void soc15_program_register_sequence(struct amdgpu_device *adev,
357 const struct soc15_reg_golden *regs,
358 const u32 array_size)
360 const struct soc15_reg_golden *entry;
364 for (i = 0; i < array_size; ++i) {
366 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
368 if (entry->and_mask == 0xffffffff) {
369 tmp = entry->or_mask;
372 tmp &= ~(entry->and_mask);
373 tmp |= entry->or_mask;
381 static int soc15_asic_reset(struct amdgpu_device *adev)
385 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
387 dev_info(adev->dev, "GPU reset\n");
390 pci_clear_master(adev->pdev);
392 pci_save_state(adev->pdev);
396 pci_restore_state(adev->pdev);
398 /* wait for asic to come out of reset */
399 for (i = 0; i < adev->usec_timeout; i++) {
400 u32 memsize = adev->nbio_funcs->get_memsize(adev);
402 if (memsize != 0xffffffff)
407 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
412 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
413 u32 cntl_reg, u32 status_reg)
418 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
422 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
426 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
431 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
438 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
440 if (pci_is_root_bus(adev->pdev->bus))
443 if (amdgpu_pcie_gen2 == 0)
446 if (adev->flags & AMD_IS_APU)
449 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
450 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
456 static void soc15_program_aspm(struct amdgpu_device *adev)
459 if (amdgpu_aspm == 0)
465 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
468 adev->nbio_funcs->enable_doorbell_aperture(adev, enable);
469 adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable);
472 static const struct amdgpu_ip_block_version vega10_common_ip_block =
474 .type = AMD_IP_BLOCK_TYPE_COMMON,
478 .funcs = &soc15_common_ip_funcs,
481 int soc15_set_ip_blocks(struct amdgpu_device *adev)
483 /* Set IP register base before any HW register access */
484 switch (adev->asic_type) {
488 vega10_reg_base_init(adev);
491 vega20_reg_base_init(adev);
497 if (adev->flags & AMD_IS_APU)
498 adev->nbio_funcs = &nbio_v7_0_funcs;
499 else if (adev->asic_type == CHIP_VEGA20)
500 adev->nbio_funcs = &nbio_v7_0_funcs;
502 adev->nbio_funcs = &nbio_v6_1_funcs;
504 adev->df_funcs = &df_v1_7_funcs;
505 adev->nbio_funcs->detect_hw_virt(adev);
507 if (amdgpu_sriov_vf(adev))
508 adev->virt.ops = &xgpu_ai_virt_ops;
510 switch (adev->asic_type) {
514 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
515 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
516 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
517 if (adev->asic_type != CHIP_VEGA20) {
518 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
519 if (!amdgpu_sriov_vf(adev))
520 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
522 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
523 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
524 #if defined(CONFIG_DRM_AMD_DC)
525 else if (amdgpu_device_has_dc_support(adev))
526 amdgpu_device_ip_block_add(adev, &dm_ip_block);
528 # warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
530 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
531 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
532 if (adev->asic_type != CHIP_VEGA20) {
533 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
534 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
538 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
539 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
540 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
541 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
542 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
543 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
544 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
545 #if defined(CONFIG_DRM_AMD_DC)
546 else if (amdgpu_device_has_dc_support(adev))
547 amdgpu_device_ip_block_add(adev, &dm_ip_block);
549 # warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
551 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
552 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
553 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
562 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
564 return adev->nbio_funcs->get_rev_id(adev);
567 static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
569 adev->nbio_funcs->hdp_flush(adev, ring);
572 static void soc15_invalidate_hdp(struct amdgpu_device *adev,
573 struct amdgpu_ring *ring)
575 if (!ring || !ring->funcs->emit_wreg)
576 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
578 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
579 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
582 static bool soc15_need_full_reset(struct amdgpu_device *adev)
584 /* change this when we implement soft reset */
588 static const struct amdgpu_asic_funcs soc15_asic_funcs =
590 .read_disabled_bios = &soc15_read_disabled_bios,
591 .read_bios_from_rom = &soc15_read_bios_from_rom,
592 .read_register = &soc15_read_register,
593 .reset = &soc15_asic_reset,
594 .set_vga_state = &soc15_vga_set_state,
595 .get_xclk = &soc15_get_xclk,
596 .set_uvd_clocks = &soc15_set_uvd_clocks,
597 .set_vce_clocks = &soc15_set_vce_clocks,
598 .get_config_memsize = &soc15_get_config_memsize,
599 .flush_hdp = &soc15_flush_hdp,
600 .invalidate_hdp = &soc15_invalidate_hdp,
601 .need_full_reset = &soc15_need_full_reset,
604 static int soc15_common_early_init(void *handle)
606 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
608 adev->smc_rreg = NULL;
609 adev->smc_wreg = NULL;
610 adev->pcie_rreg = &soc15_pcie_rreg;
611 adev->pcie_wreg = &soc15_pcie_wreg;
612 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
613 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
614 adev->didt_rreg = &soc15_didt_rreg;
615 adev->didt_wreg = &soc15_didt_wreg;
616 adev->gc_cac_rreg = &soc15_gc_cac_rreg;
617 adev->gc_cac_wreg = &soc15_gc_cac_wreg;
618 adev->se_cac_rreg = &soc15_se_cac_rreg;
619 adev->se_cac_wreg = &soc15_se_cac_wreg;
621 adev->asic_funcs = &soc15_asic_funcs;
623 adev->rev_id = soc15_get_rev_id(adev);
624 adev->external_rev_id = 0xFF;
625 switch (adev->asic_type) {
627 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
628 AMD_CG_SUPPORT_GFX_MGLS |
629 AMD_CG_SUPPORT_GFX_RLC_LS |
630 AMD_CG_SUPPORT_GFX_CP_LS |
631 AMD_CG_SUPPORT_GFX_3D_CGCG |
632 AMD_CG_SUPPORT_GFX_3D_CGLS |
633 AMD_CG_SUPPORT_GFX_CGCG |
634 AMD_CG_SUPPORT_GFX_CGLS |
635 AMD_CG_SUPPORT_BIF_MGCG |
636 AMD_CG_SUPPORT_BIF_LS |
637 AMD_CG_SUPPORT_HDP_LS |
638 AMD_CG_SUPPORT_DRM_MGCG |
639 AMD_CG_SUPPORT_DRM_LS |
640 AMD_CG_SUPPORT_ROM_MGCG |
641 AMD_CG_SUPPORT_DF_MGCG |
642 AMD_CG_SUPPORT_SDMA_MGCG |
643 AMD_CG_SUPPORT_SDMA_LS |
644 AMD_CG_SUPPORT_MC_MGCG |
645 AMD_CG_SUPPORT_MC_LS;
647 adev->external_rev_id = 0x1;
650 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
651 AMD_CG_SUPPORT_GFX_MGLS |
652 AMD_CG_SUPPORT_GFX_CGCG |
653 AMD_CG_SUPPORT_GFX_CGLS |
654 AMD_CG_SUPPORT_GFX_3D_CGCG |
655 AMD_CG_SUPPORT_GFX_3D_CGLS |
656 AMD_CG_SUPPORT_GFX_CP_LS |
657 AMD_CG_SUPPORT_MC_LS |
658 AMD_CG_SUPPORT_MC_MGCG |
659 AMD_CG_SUPPORT_SDMA_MGCG |
660 AMD_CG_SUPPORT_SDMA_LS |
661 AMD_CG_SUPPORT_BIF_MGCG |
662 AMD_CG_SUPPORT_BIF_LS |
663 AMD_CG_SUPPORT_HDP_MGCG |
664 AMD_CG_SUPPORT_HDP_LS |
665 AMD_CG_SUPPORT_ROM_MGCG |
666 AMD_CG_SUPPORT_VCE_MGCG |
667 AMD_CG_SUPPORT_UVD_MGCG;
669 adev->external_rev_id = adev->rev_id + 0x14;
672 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
673 AMD_CG_SUPPORT_GFX_MGLS |
674 AMD_CG_SUPPORT_GFX_CGCG |
675 AMD_CG_SUPPORT_GFX_CGLS |
676 AMD_CG_SUPPORT_GFX_3D_CGCG |
677 AMD_CG_SUPPORT_GFX_3D_CGLS |
678 AMD_CG_SUPPORT_GFX_CP_LS |
679 AMD_CG_SUPPORT_MC_LS |
680 AMD_CG_SUPPORT_MC_MGCG |
681 AMD_CG_SUPPORT_SDMA_MGCG |
682 AMD_CG_SUPPORT_SDMA_LS |
683 AMD_CG_SUPPORT_BIF_MGCG |
684 AMD_CG_SUPPORT_BIF_LS |
685 AMD_CG_SUPPORT_HDP_MGCG |
686 AMD_CG_SUPPORT_ROM_MGCG |
687 AMD_CG_SUPPORT_VCE_MGCG |
688 AMD_CG_SUPPORT_UVD_MGCG;
690 adev->external_rev_id = adev->rev_id + 0x28;
693 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
694 AMD_CG_SUPPORT_GFX_MGLS |
695 AMD_CG_SUPPORT_GFX_RLC_LS |
696 AMD_CG_SUPPORT_GFX_CP_LS |
697 AMD_CG_SUPPORT_GFX_3D_CGCG |
698 AMD_CG_SUPPORT_GFX_3D_CGLS |
699 AMD_CG_SUPPORT_GFX_CGCG |
700 AMD_CG_SUPPORT_GFX_CGLS |
701 AMD_CG_SUPPORT_BIF_MGCG |
702 AMD_CG_SUPPORT_BIF_LS |
703 AMD_CG_SUPPORT_HDP_MGCG |
704 AMD_CG_SUPPORT_HDP_LS |
705 AMD_CG_SUPPORT_DRM_MGCG |
706 AMD_CG_SUPPORT_DRM_LS |
707 AMD_CG_SUPPORT_ROM_MGCG |
708 AMD_CG_SUPPORT_MC_MGCG |
709 AMD_CG_SUPPORT_MC_LS |
710 AMD_CG_SUPPORT_SDMA_MGCG |
711 AMD_CG_SUPPORT_SDMA_LS;
712 adev->pg_flags = AMD_PG_SUPPORT_SDMA;
714 if (adev->powerplay.pp_feature & PP_GFXOFF_MASK)
715 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
717 AMD_PG_SUPPORT_RLC_SMU_HS;
719 adev->external_rev_id = 0x1;
722 /* FIXME: not supported yet */
726 if (amdgpu_sriov_vf(adev)) {
727 amdgpu_virt_init_setting(adev);
728 xgpu_ai_mailbox_set_irq_funcs(adev);
734 static int soc15_common_late_init(void *handle)
736 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
738 if (amdgpu_sriov_vf(adev))
739 xgpu_ai_mailbox_get_irq(adev);
744 static int soc15_common_sw_init(void *handle)
746 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
748 if (amdgpu_sriov_vf(adev))
749 xgpu_ai_mailbox_add_irq_id(adev);
754 static int soc15_common_sw_fini(void *handle)
759 static int soc15_common_hw_init(void *handle)
761 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
763 /* enable pcie gen2/3 link */
764 soc15_pcie_gen3_enable(adev);
766 soc15_program_aspm(adev);
767 /* setup nbio registers */
768 adev->nbio_funcs->init_registers(adev);
769 /* enable the doorbell aperture */
770 soc15_enable_doorbell_aperture(adev, true);
775 static int soc15_common_hw_fini(void *handle)
777 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
779 /* disable the doorbell aperture */
780 soc15_enable_doorbell_aperture(adev, false);
781 if (amdgpu_sriov_vf(adev))
782 xgpu_ai_mailbox_put_irq(adev);
787 static int soc15_common_suspend(void *handle)
789 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
791 return soc15_common_hw_fini(adev);
794 static int soc15_common_resume(void *handle)
796 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
798 return soc15_common_hw_init(adev);
801 static bool soc15_common_is_idle(void *handle)
806 static int soc15_common_wait_for_idle(void *handle)
811 static int soc15_common_soft_reset(void *handle)
816 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
820 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
822 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
823 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
825 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
828 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
831 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
835 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
837 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
838 data &= ~(0x01000000 |
847 data |= (0x01000000 |
857 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
860 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
864 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
866 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
872 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
875 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
880 def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
882 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
883 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
884 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
886 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
887 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
890 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
893 static int soc15_common_set_clockgating_state(void *handle,
894 enum amd_clockgating_state state)
896 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
898 if (amdgpu_sriov_vf(adev))
901 switch (adev->asic_type) {
905 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
906 state == AMD_CG_STATE_GATE ? true : false);
907 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
908 state == AMD_CG_STATE_GATE ? true : false);
909 soc15_update_hdp_light_sleep(adev,
910 state == AMD_CG_STATE_GATE ? true : false);
911 soc15_update_drm_clock_gating(adev,
912 state == AMD_CG_STATE_GATE ? true : false);
913 soc15_update_drm_light_sleep(adev,
914 state == AMD_CG_STATE_GATE ? true : false);
915 soc15_update_rom_medium_grain_clock_gating(adev,
916 state == AMD_CG_STATE_GATE ? true : false);
917 adev->df_funcs->update_medium_grain_clock_gating(adev,
918 state == AMD_CG_STATE_GATE ? true : false);
921 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
922 state == AMD_CG_STATE_GATE ? true : false);
923 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
924 state == AMD_CG_STATE_GATE ? true : false);
925 soc15_update_hdp_light_sleep(adev,
926 state == AMD_CG_STATE_GATE ? true : false);
927 soc15_update_drm_clock_gating(adev,
928 state == AMD_CG_STATE_GATE ? true : false);
929 soc15_update_drm_light_sleep(adev,
930 state == AMD_CG_STATE_GATE ? true : false);
931 soc15_update_rom_medium_grain_clock_gating(adev,
932 state == AMD_CG_STATE_GATE ? true : false);
940 static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
942 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
945 if (amdgpu_sriov_vf(adev))
948 adev->nbio_funcs->get_clockgating_state(adev, flags);
950 /* AMD_CG_SUPPORT_HDP_LS */
951 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
952 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
953 *flags |= AMD_CG_SUPPORT_HDP_LS;
955 /* AMD_CG_SUPPORT_DRM_MGCG */
956 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
957 if (!(data & 0x01000000))
958 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
960 /* AMD_CG_SUPPORT_DRM_LS */
961 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
963 *flags |= AMD_CG_SUPPORT_DRM_LS;
965 /* AMD_CG_SUPPORT_ROM_MGCG */
966 data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
967 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
968 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
970 adev->df_funcs->get_clockgating_state(adev, flags);
973 static int soc15_common_set_powergating_state(void *handle,
974 enum amd_powergating_state state)
980 const struct amd_ip_funcs soc15_common_ip_funcs = {
981 .name = "soc15_common",
982 .early_init = soc15_common_early_init,
983 .late_init = soc15_common_late_init,
984 .sw_init = soc15_common_sw_init,
985 .sw_fini = soc15_common_sw_fini,
986 .hw_init = soc15_common_hw_init,
987 .hw_fini = soc15_common_hw_fini,
988 .suspend = soc15_common_suspend,
989 .resume = soc15_common_resume,
990 .is_idle = soc15_common_is_idle,
991 .wait_for_idle = soc15_common_wait_for_idle,
992 .soft_reset = soc15_common_soft_reset,
993 .set_clockgating_state = soc15_common_set_clockgating_state,
994 .set_powergating_state = soc15_common_set_powergating_state,
995 .get_clockgating_state= soc15_common_get_clockgating_state,