drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Christian König <christian.koenig@amd.com>
  23  */
  24
  25 #include <linux/firmware.h>
  26 #include <drm/drmP.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_uvd.h"
  29 #include "vid.h"
  30 #include "uvd/uvd_6_0_d.h"
  31 #include "uvd/uvd_6_0_sh_mask.h"
  32 #include "oss/oss_2_0_d.h"
  33 #include "oss/oss_2_0_sh_mask.h"
  34 #include "smu/smu_7_1_3_d.h"
  35 #include "smu/smu_7_1_3_sh_mask.h"
  36 #include "bif/bif_5_1_d.h"
  37 #include "gmc/gmc_8_1_d.h"
  38 #include "vi.h"
  39
  40 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev);
  41 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev);
  42 static int uvd_v6_0_start(struct amdgpu_device *adev);
  43 static void uvd_v6_0_stop(struct amdgpu_device *adev);
  44 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev);
  45 static int uvd_v6_0_set_clockgating_state(void *handle,
  46                                           enum amd_clockgating_state state);
  47 static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
  48                                  bool enable);
  49
  50 /**
  51 * uvd_v6_0_enc_support - get encode support status
  52 *
  53 * @adev: amdgpu_device pointer
  54 *
  55 * Returns the current hardware encode support status
  56 */
  57 static inline bool uvd_v6_0_enc_support(struct amdgpu_device *adev)
  58 {
  59         return ((adev->asic_type >= CHIP_POLARIS10) && (adev->asic_type <= CHIP_POLARIS12));
  60 }
  61
  62 /**
  63  * uvd_v6_0_ring_get_rptr - get read pointer
  64  *
  65  * @ring: amdgpu_ring pointer
  66  *
  67  * Returns the current hardware read pointer
  68  */
  69 static uint64_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
  70 {
  71         struct amdgpu_device *adev = ring->adev;
  72
  73         return RREG32(mmUVD_RBC_RB_RPTR);
  74 }
  75
  76 /**
  77  * uvd_v6_0_enc_ring_get_rptr - get enc read pointer
  78  *
  79  * @ring: amdgpu_ring pointer
  80  *
  81  * Returns the current hardware enc read pointer
  82  */
  83 static uint64_t uvd_v6_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
  84 {
  85         struct amdgpu_device *adev = ring->adev;
  86
  87         if (ring == &adev->uvd.ring_enc[0])
  88                 return RREG32(mmUVD_RB_RPTR);
  89         else
  90                 return RREG32(mmUVD_RB_RPTR2);
  91 }
  92 /**
  93  * uvd_v6_0_ring_get_wptr - get write pointer
  94  *
  95  * @ring: amdgpu_ring pointer
  96  *
  97  * Returns the current hardware write pointer
  98  */
  99 static uint64_t uvd_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
 100 {
 101         struct amdgpu_device *adev = ring->adev;
 102
 103         return RREG32(mmUVD_RBC_RB_WPTR);
 104 }
 105
 106 /**
 107  * uvd_v6_0_enc_ring_get_wptr - get enc write pointer
 108  *
 109  * @ring: amdgpu_ring pointer
 110  *
 111  * Returns the current hardware enc write pointer
 112  */
 113 static uint64_t uvd_v6_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
 114 {
 115         struct amdgpu_device *adev = ring->adev;
 116
 117         if (ring == &adev->uvd.ring_enc[0])
 118                 return RREG32(mmUVD_RB_WPTR);
 119         else
 120                 return RREG32(mmUVD_RB_WPTR2);
 121 }
 122
 123 /**
 124  * uvd_v6_0_ring_set_wptr - set write pointer
 125  *
 126  * @ring: amdgpu_ring pointer
 127  *
 128  * Commits the write pointer to the hardware
 129  */
 130 static void uvd_v6_0_ring_set_wptr(struct amdgpu_ring *ring)
 131 {
 132         struct amdgpu_device *adev = ring->adev;
 133
 134         WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
 135 }
 136
 137 /**
 138  * uvd_v6_0_enc_ring_set_wptr - set enc write pointer
 139  *
 140  * @ring: amdgpu_ring pointer
 141  *
 142  * Commits the enc write pointer to the hardware
 143  */
 144 static void uvd_v6_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
 145 {
 146         struct amdgpu_device *adev = ring->adev;
 147
 148         if (ring == &adev->uvd.ring_enc[0])
 149                 WREG32(mmUVD_RB_WPTR,
 150                         lower_32_bits(ring->wptr));
 151         else
 152                 WREG32(mmUVD_RB_WPTR2,
 153                         lower_32_bits(ring->wptr));
 154 }
 155
 156 static int uvd_v6_0_early_init(void *handle)
 157 {
 158         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 159
 160         uvd_v6_0_set_ring_funcs(adev);
 161
 162         if (uvd_v6_0_enc_support(adev)) {
 163                 adev->uvd.num_enc_rings = 2;
 164         }
 165
 166         uvd_v6_0_set_irq_funcs(adev);
 167
 168         return 0;
 169 }
 170
 171 static int uvd_v6_0_sw_init(void *handle)
 172 {
 173         struct amdgpu_ring *ring;
 174         int i, r;
 175         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 176
 177         /* UVD TRAP */
 178         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.irq);
 179         if (r)
 180                 return r;
 181
 182         r = amdgpu_uvd_sw_init(adev);
 183         if (r)
 184                 return r;
 185
 186         r = amdgpu_uvd_resume(adev);
 187         if (r)
 188                 return r;
 189
 190         ring = &adev->uvd.ring;
 191         sprintf(ring->name, "uvd");
 192         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
 193         if (r)
 194                 return r;
 195
 196         if (uvd_v6_0_enc_support(adev)) {
 197                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 198                         ring = &adev->uvd.ring_enc[i];
 199                         sprintf(ring->name, "uvd_enc%d", i);
 200                         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
 201                         if (r)
 202                                 return r;
 203                 }
 204         }
 205
 206         return r;
 207 }
 208
 209 static int uvd_v6_0_sw_fini(void *handle)
 210 {
 211         int i, r;
 212         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 213
 214         r = amdgpu_uvd_suspend(adev);
 215         if (r)
 216                 return r;
 217
 218         if (uvd_v6_0_enc_support(adev)) {
 219                 for (i = 0; i < adev->uvd.num_enc_rings; ++i)
 220                         amdgpu_ring_fini(&adev->uvd.ring_enc[i]);
 221         }
 222
 223         return amdgpu_uvd_sw_fini(adev);
 224 }
 225
 226 /**
 227  * uvd_v6_0_hw_init - start and test UVD block
 228  *
 229  * @adev: amdgpu_device pointer
 230  *
 231  * Initialize the hardware, boot up the VCPU and do some testing
 232  */
 233 static int uvd_v6_0_hw_init(void *handle)
 234 {
 235         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 236         struct amdgpu_ring *ring = &adev->uvd.ring;
 237         uint32_t tmp;
 238         int r;
 239
 240         amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
 241         uvd_v6_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
 242         uvd_v6_0_enable_mgcg(adev, true);
 243
 244         ring->ready = true;
 245         r = amdgpu_ring_test_ring(ring);
 246         if (r) {
 247                 ring->ready = false;
 248                 goto done;
 249         }
 250
 251         r = amdgpu_ring_alloc(ring, 10);
 252         if (r) {
 253                 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
 254                 goto done;
 255         }
 256
 257         tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
 258         amdgpu_ring_write(ring, tmp);
 259         amdgpu_ring_write(ring, 0xFFFFF);
 260
 261         tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
 262         amdgpu_ring_write(ring, tmp);
 263         amdgpu_ring_write(ring, 0xFFFFF);
 264
 265         tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
 266         amdgpu_ring_write(ring, tmp);
 267         amdgpu_ring_write(ring, 0xFFFFF);
 268
 269         /* Clear timeout status bits */
 270         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
 271         amdgpu_ring_write(ring, 0x8);
 272
 273         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
 274         amdgpu_ring_write(ring, 3);
 275
 276         amdgpu_ring_commit(ring);
 277
 278 done:
 279         if (!r)
 280                 DRM_INFO("UVD initialized successfully.\n");
 281
 282         return r;
 283 }
 284
 285 /**
 286  * uvd_v6_0_hw_fini - stop the hardware block
 287  *
 288  * @adev: amdgpu_device pointer
 289  *
 290  * Stop the UVD block, mark ring as not ready any more
 291  */
 292 static int uvd_v6_0_hw_fini(void *handle)
 293 {
 294         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 295         struct amdgpu_ring *ring = &adev->uvd.ring;
 296
 297         if (RREG32(mmUVD_STATUS) != 0)
 298                 uvd_v6_0_stop(adev);
 299
 300         ring->ready = false;
 301
 302         return 0;
 303 }
 304
 305 static int uvd_v6_0_suspend(void *handle)
 306 {
 307         int r;
 308         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 309
 310         r = uvd_v6_0_hw_fini(adev);
 311         if (r)
 312                 return r;
 313
 314         /* Skip this for APU for now */
 315         if (!(adev->flags & AMD_IS_APU))
 316                 r = amdgpu_uvd_suspend(adev);
 317
 318         return r;
 319 }
 320
 321 static int uvd_v6_0_resume(void *handle)
 322 {
 323         int r;
 324         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 325
 326         /* Skip this for APU for now */
 327         if (!(adev->flags & AMD_IS_APU)) {
 328                 r = amdgpu_uvd_resume(adev);
 329                 if (r)
 330                         return r;
 331         }
 332         return uvd_v6_0_hw_init(adev);
 333 }
 334
 335 /**
 336  * uvd_v6_0_mc_resume - memory controller programming
 337  *
 338  * @adev: amdgpu_device pointer
 339  *
 340  * Let the UVD memory controller know it's offsets
 341  */
 342 static void uvd_v6_0_mc_resume(struct amdgpu_device *adev)
 343 {
 344         uint64_t offset;
 345         uint32_t size;
 346
 347         /* programm memory controller bits 0-27 */
 348         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 349                         lower_32_bits(adev->uvd.gpu_addr));
 350         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 351                         upper_32_bits(adev->uvd.gpu_addr));
 352
 353         offset = AMDGPU_UVD_FIRMWARE_OFFSET;
 354         size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
 355         WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
 356         WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
 357
 358         offset += size;
 359         size = AMDGPU_UVD_HEAP_SIZE;
 360         WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
 361         WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
 362
 363         offset += size;
 364         size = AMDGPU_UVD_STACK_SIZE +
 365                (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles);
 366         WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
 367         WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
 368
 369         WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 370         WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 371         WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 372
 373         WREG32(mmUVD_GP_SCRATCH4, adev->uvd.max_handles);
 374 }
 375
 376 #if 0
 377 static void cz_set_uvd_clock_gating_branches(struct amdgpu_device *adev,
 378                 bool enable)
 379 {
 380         u32 data, data1;
 381
 382         data = RREG32(mmUVD_CGC_GATE);
 383         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
 384         if (enable) {
 385                 data |= UVD_CGC_GATE__SYS_MASK |
 386                                 UVD_CGC_GATE__UDEC_MASK |
 387                                 UVD_CGC_GATE__MPEG2_MASK |
 388                                 UVD_CGC_GATE__RBC_MASK |
 389                                 UVD_CGC_GATE__LMI_MC_MASK |
 390                                 UVD_CGC_GATE__IDCT_MASK |
 391                                 UVD_CGC_GATE__MPRD_MASK |
 392                                 UVD_CGC_GATE__MPC_MASK |
 393                                 UVD_CGC_GATE__LBSI_MASK |
 394                                 UVD_CGC_GATE__LRBBM_MASK |
 395                                 UVD_CGC_GATE__UDEC_RE_MASK |
 396                                 UVD_CGC_GATE__UDEC_CM_MASK |
 397                                 UVD_CGC_GATE__UDEC_IT_MASK |
 398                                 UVD_CGC_GATE__UDEC_DB_MASK |
 399                                 UVD_CGC_GATE__UDEC_MP_MASK |
 400                                 UVD_CGC_GATE__WCB_MASK |
 401                                 UVD_CGC_GATE__VCPU_MASK |
 402                                 UVD_CGC_GATE__SCPU_MASK;
 403                 data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
 404                                 UVD_SUVD_CGC_GATE__SIT_MASK |
 405                                 UVD_SUVD_CGC_GATE__SMP_MASK |
 406                                 UVD_SUVD_CGC_GATE__SCM_MASK |
 407                                 UVD_SUVD_CGC_GATE__SDB_MASK |
 408                                 UVD_SUVD_CGC_GATE__SRE_H264_MASK |
 409                                 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
 410                                 UVD_SUVD_CGC_GATE__SIT_H264_MASK |
 411                                 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
 412                                 UVD_SUVD_CGC_GATE__SCM_H264_MASK |
 413                                 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
 414                                 UVD_SUVD_CGC_GATE__SDB_H264_MASK |
 415                                 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK;
 416         } else {
 417                 data &= ~(UVD_CGC_GATE__SYS_MASK |
 418                                 UVD_CGC_GATE__UDEC_MASK |
 419                                 UVD_CGC_GATE__MPEG2_MASK |
 420                                 UVD_CGC_GATE__RBC_MASK |
 421                                 UVD_CGC_GATE__LMI_MC_MASK |
 422                                 UVD_CGC_GATE__LMI_UMC_MASK |
 423                                 UVD_CGC_GATE__IDCT_MASK |
 424                                 UVD_CGC_GATE__MPRD_MASK |
 425                                 UVD_CGC_GATE__MPC_MASK |
 426                                 UVD_CGC_GATE__LBSI_MASK |
 427                                 UVD_CGC_GATE__LRBBM_MASK |
 428                                 UVD_CGC_GATE__UDEC_RE_MASK |
 429                                 UVD_CGC_GATE__UDEC_CM_MASK |
 430                                 UVD_CGC_GATE__UDEC_IT_MASK |
 431                                 UVD_CGC_GATE__UDEC_DB_MASK |
 432                                 UVD_CGC_GATE__UDEC_MP_MASK |
 433                                 UVD_CGC_GATE__WCB_MASK |
 434                                 UVD_CGC_GATE__VCPU_MASK |
 435                                 UVD_CGC_GATE__SCPU_MASK);
 436                 data1 &= ~(UVD_SUVD_CGC_GATE__SRE_MASK |
 437                                 UVD_SUVD_CGC_GATE__SIT_MASK |
 438                                 UVD_SUVD_CGC_GATE__SMP_MASK |
 439                                 UVD_SUVD_CGC_GATE__SCM_MASK |
 440                                 UVD_SUVD_CGC_GATE__SDB_MASK |
 441                                 UVD_SUVD_CGC_GATE__SRE_H264_MASK |
 442                                 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
 443                                 UVD_SUVD_CGC_GATE__SIT_H264_MASK |
 444                                 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
 445                                 UVD_SUVD_CGC_GATE__SCM_H264_MASK |
 446                                 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
 447                                 UVD_SUVD_CGC_GATE__SDB_H264_MASK |
 448                                 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK);
 449         }
 450         WREG32(mmUVD_CGC_GATE, data);
 451         WREG32(mmUVD_SUVD_CGC_GATE, data1);
 452 }
 453 #endif
 454
 455 /**
 456  * uvd_v6_0_start - start UVD block
 457  *
 458  * @adev: amdgpu_device pointer
 459  *
 460  * Setup and start the UVD block
 461  */
 462 static int uvd_v6_0_start(struct amdgpu_device *adev)
 463 {
 464         struct amdgpu_ring *ring = &adev->uvd.ring;
 465         uint32_t rb_bufsz, tmp;
 466         uint32_t lmi_swap_cntl;
 467         uint32_t mp_swap_cntl;
 468         int i, j, r;
 469
 470         /* disable DPG */
 471         WREG32_P(mmUVD_POWER_STATUS, 0, ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
 472
 473         /* disable byte swapping */
 474         lmi_swap_cntl = 0;
 475         mp_swap_cntl = 0;
 476
 477         uvd_v6_0_mc_resume(adev);
 478
 479         /* disable interupt */
 480         WREG32_FIELD(UVD_MASTINT_EN, VCPU_EN, 0);
 481
 482         /* stall UMC and register bus before resetting VCPU */
 483         WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 1);
 484         mdelay(1);
 485
 486         /* put LMI, VCPU, RBC etc... into reset */
 487         WREG32(mmUVD_SOFT_RESET,
 488                 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 489                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
 490                 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 491                 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
 492                 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 493                 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
 494                 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 495                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
 496         mdelay(5);
 497
 498         /* take UVD block out of reset */
 499         WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_UVD, 0);
 500         mdelay(5);
 501
 502         /* initialize UVD memory controller */
 503         WREG32(mmUVD_LMI_CTRL,
 504                 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 505                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 506                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 507                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 508                 UVD_LMI_CTRL__REQ_MODE_MASK |
 509                 UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK);
 510
 511 #ifdef __BIG_ENDIAN
 512         /* swap (8 in 32) RB and IB */
 513         lmi_swap_cntl = 0xa;
 514         mp_swap_cntl = 0;
 515 #endif
 516         WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
 517         WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
 518
 519         WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
 520         WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
 521         WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
 522         WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
 523         WREG32(mmUVD_MPC_SET_ALU, 0);
 524         WREG32(mmUVD_MPC_SET_MUX, 0x88);
 525
 526         /* take all subblocks out of reset, except VCPU */
 527         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 528         mdelay(5);
 529
 530         /* enable VCPU clock */
 531         WREG32(mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
 532
 533         /* enable UMC */
 534         WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 0);
 535
 536         /* boot up the VCPU */
 537         WREG32(mmUVD_SOFT_RESET, 0);
 538         mdelay(10);
 539
 540         for (i = 0; i < 10; ++i) {
 541                 uint32_t status;
 542
 543                 for (j = 0; j < 100; ++j) {
 544                         status = RREG32(mmUVD_STATUS);
 545                         if (status & 2)
 546                                 break;
 547                         mdelay(10);
 548                 }
 549                 r = 0;
 550                 if (status & 2)
 551                         break;
 552
 553                 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
 554                 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 1);
 555                 mdelay(10);
 556                 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 0);
 557                 mdelay(10);
 558                 r = -1;
 559         }
 560
 561         if (r) {
 562                 DRM_ERROR("UVD not responding, giving up!!!\n");
 563                 return r;
 564         }
 565         /* enable master interrupt */
 566         WREG32_P(mmUVD_MASTINT_EN,
 567                 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
 568                 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
 569
 570         /* clear the bit 4 of UVD_STATUS */
 571         WREG32_P(mmUVD_STATUS, 0, ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
 572
 573         /* force RBC into idle state */
 574         rb_bufsz = order_base_2(ring->ring_size);
 575         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
 576         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
 577         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 578         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
 579         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
 580         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
 581         WREG32(mmUVD_RBC_RB_CNTL, tmp);
 582
 583         /* set the write pointer delay */
 584         WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
 585
 586         /* set the wb address */
 587         WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));
 588
 589         /* programm the RB_BASE for ring buffer */
 590         WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
 591                         lower_32_bits(ring->gpu_addr));
 592         WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
 593                         upper_32_bits(ring->gpu_addr));
 594
 595         /* Initialize the ring buffer's read and write pointers */
 596         WREG32(mmUVD_RBC_RB_RPTR, 0);
 597
 598         ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
 599         WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
 600
 601         WREG32_FIELD(UVD_RBC_RB_CNTL, RB_NO_FETCH, 0);
 602
 603         if (uvd_v6_0_enc_support(adev)) {
 604                 ring = &adev->uvd.ring_enc[0];
 605                 WREG32(mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
 606                 WREG32(mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
 607                 WREG32(mmUVD_RB_BASE_LO, ring->gpu_addr);
 608                 WREG32(mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
 609                 WREG32(mmUVD_RB_SIZE, ring->ring_size / 4);
 610
 611                 ring = &adev->uvd.ring_enc[1];
 612                 WREG32(mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
 613                 WREG32(mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
 614                 WREG32(mmUVD_RB_BASE_LO2, ring->gpu_addr);
 615                 WREG32(mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
 616                 WREG32(mmUVD_RB_SIZE2, ring->ring_size / 4);
 617         }
 618
 619         return 0;
 620 }
 621
 622 /**
 623  * uvd_v6_0_stop - stop UVD block
 624  *
 625  * @adev: amdgpu_device pointer
 626  *
 627  * stop the UVD block
 628  */
 629 static void uvd_v6_0_stop(struct amdgpu_device *adev)
 630 {
 631         /* force RBC into idle state */
 632         WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
 633
 634         /* Stall UMC and register bus before resetting VCPU */
 635         WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
 636         mdelay(1);
 637
 638         /* put VCPU into reset */
 639         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 640         mdelay(5);
 641
 642         /* disable VCPU clock */
 643         WREG32(mmUVD_VCPU_CNTL, 0x0);
 644
 645         /* Unstall UMC and register bus */
 646         WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
 647
 648         WREG32(mmUVD_STATUS, 0);
 649 }
 650
 651 /**
 652  * uvd_v6_0_ring_emit_fence - emit an fence & trap command
 653  *
 654  * @ring: amdgpu_ring pointer
 655  * @fence: fence to emit
 656  *
 657  * Write a fence and a trap command to the ring.
 658  */
 659 static void uvd_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 660                                      unsigned flags)
 661 {
 662         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 663
 664         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
 665         amdgpu_ring_write(ring, seq);
 666         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 667         amdgpu_ring_write(ring, addr & 0xffffffff);
 668         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 669         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
 670         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 671         amdgpu_ring_write(ring, 0);
 672
 673         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 674         amdgpu_ring_write(ring, 0);
 675         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 676         amdgpu_ring_write(ring, 0);
 677         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 678         amdgpu_ring_write(ring, 2);
 679 }
 680
 681 /**
 682  * uvd_v6_0_enc_ring_emit_fence - emit an enc fence & trap command
 683  *
 684  * @ring: amdgpu_ring pointer
 685  * @fence: fence to emit
 686  *
 687  * Write enc a fence and a trap command to the ring.
 688  */
 689 static void uvd_v6_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
 690                         u64 seq, unsigned flags)
 691 {
 692         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 693
 694         amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE);
 695         amdgpu_ring_write(ring, addr);
 696         amdgpu_ring_write(ring, upper_32_bits(addr));
 697         amdgpu_ring_write(ring, seq);
 698         amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
 699 }
 700
 701 /**
 702  * uvd_v6_0_ring_emit_hdp_flush - emit an hdp flush
 703  *
 704  * @ring: amdgpu_ring pointer
 705  *
 706  * Emits an hdp flush.
 707  */
 708 static void uvd_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 709 {
 710         amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0));
 711         amdgpu_ring_write(ring, 0);
 712 }
 713
 714 /**
 715  * uvd_v6_0_ring_hdp_invalidate - emit an hdp invalidate
 716  *
 717  * @ring: amdgpu_ring pointer
 718  *
 719  * Emits an hdp invalidate.
 720  */
 721 static void uvd_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
 722 {
 723         amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0));
 724         amdgpu_ring_write(ring, 1);
 725 }
 726
 727 /**
 728  * uvd_v6_0_ring_test_ring - register write test
 729  *
 730  * @ring: amdgpu_ring pointer
 731  *
 732  * Test if we can successfully write to the context register
 733  */
 734 static int uvd_v6_0_ring_test_ring(struct amdgpu_ring *ring)
 735 {
 736         struct amdgpu_device *adev = ring->adev;
 737         uint32_t tmp = 0;
 738         unsigned i;
 739         int r;
 740
 741         WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
 742         r = amdgpu_ring_alloc(ring, 3);
 743         if (r) {
 744                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 745                           ring->idx, r);
 746                 return r;
 747         }
 748         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
 749         amdgpu_ring_write(ring, 0xDEADBEEF);
 750         amdgpu_ring_commit(ring);
 751         for (i = 0; i < adev->usec_timeout; i++) {
 752                 tmp = RREG32(mmUVD_CONTEXT_ID);
 753                 if (tmp == 0xDEADBEEF)
 754                         break;
 755                 DRM_UDELAY(1);
 756         }
 757
 758         if (i < adev->usec_timeout) {
 759                 DRM_INFO("ring test on %d succeeded in %d usecs\n",
 760                          ring->idx, i);
 761         } else {
 762                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 763                           ring->idx, tmp);
 764                 r = -EINVAL;
 765         }
 766         return r;
 767 }
 768
 769 /**
 770  * uvd_v6_0_ring_emit_ib - execute indirect buffer
 771  *
 772  * @ring: amdgpu_ring pointer
 773  * @ib: indirect buffer to execute
 774  *
 775  * Write ring commands to execute the indirect buffer
 776  */
 777 static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
 778                                   struct amdgpu_ib *ib,
 779                                   unsigned vm_id, bool ctx_switch)
 780 {
 781         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_VMID, 0));
 782         amdgpu_ring_write(ring, vm_id);
 783
 784         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
 785         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
 786         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0));
 787         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 788         amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
 789         amdgpu_ring_write(ring, ib->length_dw);
 790 }
 791
 792 /**
 793  * uvd_v6_0_enc_ring_emit_ib - enc execute indirect buffer
 794  *
 795  * @ring: amdgpu_ring pointer
 796  * @ib: indirect buffer to execute
 797  *
 798  * Write enc ring commands to execute the indirect buffer
 799  */
 800 static void uvd_v6_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
 801                 struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch)
 802 {
 803         amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM);
 804         amdgpu_ring_write(ring, vm_id);
 805         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
 806         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 807         amdgpu_ring_write(ring, ib->length_dw);
 808 }
 809
 810 static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
 811                                          unsigned vm_id, uint64_t pd_addr)
 812 {
 813         uint32_t reg;
 814
 815         if (vm_id < 8)
 816                 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id;
 817         else
 818                 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8;
 819
 820         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 821         amdgpu_ring_write(ring, reg << 2);
 822         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 823         amdgpu_ring_write(ring, pd_addr >> 12);
 824         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 825         amdgpu_ring_write(ring, 0x8);
 826
 827         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 828         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
 829         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 830         amdgpu_ring_write(ring, 1 << vm_id);
 831         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 832         amdgpu_ring_write(ring, 0x8);
 833
 834         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 835         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
 836         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 837         amdgpu_ring_write(ring, 0);
 838         amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0));
 839         amdgpu_ring_write(ring, 1 << vm_id); /* mask */
 840         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 841         amdgpu_ring_write(ring, 0xC);
 842 }
 843
 844 static void uvd_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
 845 {
 846         uint32_t seq = ring->fence_drv.sync_seq;
 847         uint64_t addr = ring->fence_drv.gpu_addr;
 848
 849         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 850         amdgpu_ring_write(ring, lower_32_bits(addr));
 851         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 852         amdgpu_ring_write(ring, upper_32_bits(addr));
 853         amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0));
 854         amdgpu_ring_write(ring, 0xffffffff); /* mask */
 855         amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH9, 0));
 856         amdgpu_ring_write(ring, seq);
 857         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 858         amdgpu_ring_write(ring, 0xE);
 859 }
 860
 861 static void uvd_v6_0_enc_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
 862 {
 863         uint32_t seq = ring->fence_drv.sync_seq;
 864         uint64_t addr = ring->fence_drv.gpu_addr;
 865
 866         amdgpu_ring_write(ring, HEVC_ENC_CMD_WAIT_GE);
 867         amdgpu_ring_write(ring, lower_32_bits(addr));
 868         amdgpu_ring_write(ring, upper_32_bits(addr));
 869         amdgpu_ring_write(ring, seq);
 870 }
 871
 872 static void uvd_v6_0_enc_ring_insert_end(struct amdgpu_ring *ring)
 873 {
 874         amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
 875 }
 876
 877 static void uvd_v6_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
 878         unsigned int vm_id, uint64_t pd_addr)
 879 {
 880         amdgpu_ring_write(ring, HEVC_ENC_CMD_UPDATE_PTB);
 881         amdgpu_ring_write(ring, vm_id);
 882         amdgpu_ring_write(ring, pd_addr >> 12);
 883
 884         amdgpu_ring_write(ring, HEVC_ENC_CMD_FLUSH_TLB);
 885         amdgpu_ring_write(ring, vm_id);
 886 }
 887
 888 static bool uvd_v6_0_is_idle(void *handle)
 889 {
 890         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 891
 892         return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
 893 }
 894
 895 static int uvd_v6_0_wait_for_idle(void *handle)
 896 {
 897         unsigned i;
 898         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 899
 900         for (i = 0; i < adev->usec_timeout; i++) {
 901                 if (uvd_v6_0_is_idle(handle))
 902                         return 0;
 903         }
 904         return -ETIMEDOUT;
 905 }
 906
 907 #define AMDGPU_UVD_STATUS_BUSY_MASK    0xfd
 908 static bool uvd_v6_0_check_soft_reset(void *handle)
 909 {
 910         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 911         u32 srbm_soft_reset = 0;
 912         u32 tmp = RREG32(mmSRBM_STATUS);
 913
 914         if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) ||
 915             REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) ||
 916             (RREG32(mmUVD_STATUS) & AMDGPU_UVD_STATUS_BUSY_MASK))
 917                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
 918
 919         if (srbm_soft_reset) {
 920                 adev->uvd.srbm_soft_reset = srbm_soft_reset;
 921                 return true;
 922         } else {
 923                 adev->uvd.srbm_soft_reset = 0;
 924                 return false;
 925         }
 926 }
 927
 928 static int uvd_v6_0_pre_soft_reset(void *handle)
 929 {
 930         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 931
 932         if (!adev->uvd.srbm_soft_reset)
 933                 return 0;
 934
 935         uvd_v6_0_stop(adev);
 936         return 0;
 937 }
 938
 939 static int uvd_v6_0_soft_reset(void *handle)
 940 {
 941         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 942         u32 srbm_soft_reset;
 943
 944         if (!adev->uvd.srbm_soft_reset)
 945                 return 0;
 946         srbm_soft_reset = adev->uvd.srbm_soft_reset;
 947
 948         if (srbm_soft_reset) {
 949                 u32 tmp;
 950
 951                 tmp = RREG32(mmSRBM_SOFT_RESET);
 952                 tmp |= srbm_soft_reset;
 953                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
 954                 WREG32(mmSRBM_SOFT_RESET, tmp);
 955                 tmp = RREG32(mmSRBM_SOFT_RESET);
 956
 957                 udelay(50);
 958
 959                 tmp &= ~srbm_soft_reset;
 960                 WREG32(mmSRBM_SOFT_RESET, tmp);
 961                 tmp = RREG32(mmSRBM_SOFT_RESET);
 962
 963                 /* Wait a little for things to settle down */
 964                 udelay(50);
 965         }
 966
 967         return 0;
 968 }
 969
 970 static int uvd_v6_0_post_soft_reset(void *handle)
 971 {
 972         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 973
 974         if (!adev->uvd.srbm_soft_reset)
 975                 return 0;
 976
 977         mdelay(5);
 978
 979         return uvd_v6_0_start(adev);
 980 }
 981
 982 static int uvd_v6_0_set_interrupt_state(struct amdgpu_device *adev,
 983                                         struct amdgpu_irq_src *source,
 984                                         unsigned type,
 985                                         enum amdgpu_interrupt_state state)
 986 {
 987         // TODO
 988         return 0;
 989 }
 990
 991 static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev,
 992                                       struct amdgpu_irq_src *source,
 993                                       struct amdgpu_iv_entry *entry)
 994 {
 995         DRM_DEBUG("IH: UVD TRAP\n");
 996         amdgpu_fence_process(&adev->uvd.ring);
 997         return 0;
 998 }
 999
1000 static void uvd_v6_0_enable_clock_gating(struct amdgpu_device *adev, bool enable)
1001 {
1002         uint32_t data1, data3;
1003
1004         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
1005         data3 = RREG32(mmUVD_CGC_GATE);
1006
1007         data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
1008                      UVD_SUVD_CGC_GATE__SIT_MASK |
1009                      UVD_SUVD_CGC_GATE__SMP_MASK |
1010                      UVD_SUVD_CGC_GATE__SCM_MASK |
1011                      UVD_SUVD_CGC_GATE__SDB_MASK |
1012                      UVD_SUVD_CGC_GATE__SRE_H264_MASK |
1013                      UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
1014                      UVD_SUVD_CGC_GATE__SIT_H264_MASK |
1015                      UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
1016                      UVD_SUVD_CGC_GATE__SCM_H264_MASK |
1017                      UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
1018                      UVD_SUVD_CGC_GATE__SDB_H264_MASK |
1019                      UVD_SUVD_CGC_GATE__SDB_HEVC_MASK;
1020
1021         if (enable) {
1022                 data3 |= (UVD_CGC_GATE__SYS_MASK       |
1023                         UVD_CGC_GATE__UDEC_MASK      |
1024                         UVD_CGC_GATE__MPEG2_MASK     |
1025                         UVD_CGC_GATE__RBC_MASK       |
1026                         UVD_CGC_GATE__LMI_MC_MASK    |
1027                         UVD_CGC_GATE__LMI_UMC_MASK   |
1028                         UVD_CGC_GATE__IDCT_MASK      |
1029                         UVD_CGC_GATE__MPRD_MASK      |
1030                         UVD_CGC_GATE__MPC_MASK       |
1031                         UVD_CGC_GATE__LBSI_MASK      |
1032                         UVD_CGC_GATE__LRBBM_MASK     |
1033                         UVD_CGC_GATE__UDEC_RE_MASK   |
1034                         UVD_CGC_GATE__UDEC_CM_MASK   |
1035                         UVD_CGC_GATE__UDEC_IT_MASK   |
1036                         UVD_CGC_GATE__UDEC_DB_MASK   |
1037                         UVD_CGC_GATE__UDEC_MP_MASK   |
1038                         UVD_CGC_GATE__WCB_MASK       |
1039                         UVD_CGC_GATE__JPEG_MASK      |
1040                         UVD_CGC_GATE__SCPU_MASK      |
1041                         UVD_CGC_GATE__JPEG2_MASK);
1042                 /* only in pg enabled, we can gate clock to vcpu*/
1043                 if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
1044                         data3 |= UVD_CGC_GATE__VCPU_MASK;
1045
1046                 data3 &= ~UVD_CGC_GATE__REGS_MASK;
1047         } else {
1048                 data3 = 0;
1049         }
1050
1051         WREG32(mmUVD_SUVD_CGC_GATE, data1);
1052         WREG32(mmUVD_CGC_GATE, data3);
1053 }
1054
1055 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev)
1056 {
1057         uint32_t data, data2;
1058
1059         data = RREG32(mmUVD_CGC_CTRL);
1060         data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
1061
1062
1063         data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
1064                   UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
1065
1066
1067         data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
1068                 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
1069                 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
1070
1071         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
1072                         UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
1073                         UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
1074                         UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
1075                         UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
1076                         UVD_CGC_CTRL__SYS_MODE_MASK |
1077                         UVD_CGC_CTRL__UDEC_MODE_MASK |
1078                         UVD_CGC_CTRL__MPEG2_MODE_MASK |
1079                         UVD_CGC_CTRL__REGS_MODE_MASK |
1080                         UVD_CGC_CTRL__RBC_MODE_MASK |
1081                         UVD_CGC_CTRL__LMI_MC_MODE_MASK |
1082                         UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
1083                         UVD_CGC_CTRL__IDCT_MODE_MASK |
1084                         UVD_CGC_CTRL__MPRD_MODE_MASK |
1085                         UVD_CGC_CTRL__MPC_MODE_MASK |
1086                         UVD_CGC_CTRL__LBSI_MODE_MASK |
1087                         UVD_CGC_CTRL__LRBBM_MODE_MASK |
1088                         UVD_CGC_CTRL__WCB_MODE_MASK |
1089                         UVD_CGC_CTRL__VCPU_MODE_MASK |
1090                         UVD_CGC_CTRL__JPEG_MODE_MASK |
1091                         UVD_CGC_CTRL__SCPU_MODE_MASK |
1092                         UVD_CGC_CTRL__JPEG2_MODE_MASK);
1093         data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
1094                         UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
1095                         UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
1096                         UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
1097                         UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
1098
1099         WREG32(mmUVD_CGC_CTRL, data);
1100         WREG32(mmUVD_SUVD_CGC_CTRL, data2);
1101 }
1102
1103 #if 0
1104 static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev)
1105 {
1106         uint32_t data, data1, cgc_flags, suvd_flags;
1107
1108         data = RREG32(mmUVD_CGC_GATE);
1109         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
1110
1111         cgc_flags = UVD_CGC_GATE__SYS_MASK |
1112                 UVD_CGC_GATE__UDEC_MASK |
1113                 UVD_CGC_GATE__MPEG2_MASK |
1114                 UVD_CGC_GATE__RBC_MASK |
1115                 UVD_CGC_GATE__LMI_MC_MASK |
1116                 UVD_CGC_GATE__IDCT_MASK |
1117                 UVD_CGC_GATE__MPRD_MASK |
1118                 UVD_CGC_GATE__MPC_MASK |
1119                 UVD_CGC_GATE__LBSI_MASK |
1120                 UVD_CGC_GATE__LRBBM_MASK |
1121                 UVD_CGC_GATE__UDEC_RE_MASK |
1122                 UVD_CGC_GATE__UDEC_CM_MASK |
1123                 UVD_CGC_GATE__UDEC_IT_MASK |
1124                 UVD_CGC_GATE__UDEC_DB_MASK |
1125                 UVD_CGC_GATE__UDEC_MP_MASK |
1126                 UVD_CGC_GATE__WCB_MASK |
1127                 UVD_CGC_GATE__VCPU_MASK |
1128                 UVD_CGC_GATE__SCPU_MASK |
1129                 UVD_CGC_GATE__JPEG_MASK |
1130                 UVD_CGC_GATE__JPEG2_MASK;
1131
1132         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1133                                 UVD_SUVD_CGC_GATE__SIT_MASK |
1134                                 UVD_SUVD_CGC_GATE__SMP_MASK |
1135                                 UVD_SUVD_CGC_GATE__SCM_MASK |
1136                                 UVD_SUVD_CGC_GATE__SDB_MASK;
1137
1138         data |= cgc_flags;
1139         data1 |= suvd_flags;
1140
1141         WREG32(mmUVD_CGC_GATE, data);
1142         WREG32(mmUVD_SUVD_CGC_GATE, data1);
1143 }
1144 #endif
1145
1146 static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
1147                                  bool enable)
1148 {
1149         u32 orig, data;
1150
1151         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
1152                 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
1153                 data |= 0xfff;
1154                 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
1155
1156                 orig = data = RREG32(mmUVD_CGC_CTRL);
1157                 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
1158                 if (orig != data)
1159                         WREG32(mmUVD_CGC_CTRL, data);
1160         } else {
1161                 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
1162                 data &= ~0xfff;
1163                 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
1164
1165                 orig = data = RREG32(mmUVD_CGC_CTRL);
1166                 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
1167                 if (orig != data)
1168                         WREG32(mmUVD_CGC_CTRL, data);
1169         }
1170 }
1171
1172 static int uvd_v6_0_set_clockgating_state(void *handle,
1173                                           enum amd_clockgating_state state)
1174 {
1175         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1176         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1177
1178         if (enable) {
1179                 /* wait for STATUS to clear */
1180                 if (uvd_v6_0_wait_for_idle(handle))
1181                         return -EBUSY;
1182                 uvd_v6_0_enable_clock_gating(adev, true);
1183                 /* enable HW gates because UVD is idle */
1184 /*              uvd_v6_0_set_hw_clock_gating(adev); */
1185         } else {
1186                 /* disable HW gating and enable Sw gating */
1187                 uvd_v6_0_enable_clock_gating(adev, false);
1188         }
1189         uvd_v6_0_set_sw_clock_gating(adev);
1190         return 0;
1191 }
1192
1193 static int uvd_v6_0_set_powergating_state(void *handle,
1194                                           enum amd_powergating_state state)
1195 {
1196         /* This doesn't actually powergate the UVD block.
1197          * That's done in the dpm code via the SMC.  This
1198          * just re-inits the block as necessary.  The actual
1199          * gating still happens in the dpm code.  We should
1200          * revisit this when there is a cleaner line between
1201          * the smc and the hw blocks
1202          */
1203         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1204         int ret = 0;
1205
1206         WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
1207
1208         if (state == AMD_PG_STATE_GATE) {
1209                 uvd_v6_0_stop(adev);
1210         } else {
1211                 ret = uvd_v6_0_start(adev);
1212                 if (ret)
1213                         goto out;
1214         }
1215
1216 out:
1217         return ret;
1218 }
1219
1220 static void uvd_v6_0_get_clockgating_state(void *handle, u32 *flags)
1221 {
1222         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1223         int data;
1224
1225         mutex_lock(&adev->pm.mutex);
1226
1227         if (adev->flags & AMD_IS_APU)
1228                 data = RREG32_SMC(ixCURRENT_PG_STATUS_APU);
1229         else
1230                 data = RREG32_SMC(ixCURRENT_PG_STATUS);
1231
1232         if (data & CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) {
1233                 DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
1234                 goto out;
1235         }
1236
1237         /* AMD_CG_SUPPORT_UVD_MGCG */
1238         data = RREG32(mmUVD_CGC_CTRL);
1239         if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)
1240                 *flags |= AMD_CG_SUPPORT_UVD_MGCG;
1241
1242 out:
1243         mutex_unlock(&adev->pm.mutex);
1244 }
1245
1246 static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
1247         .name = "uvd_v6_0",
1248         .early_init = uvd_v6_0_early_init,
1249         .late_init = NULL,
1250         .sw_init = uvd_v6_0_sw_init,
1251         .sw_fini = uvd_v6_0_sw_fini,
1252         .hw_init = uvd_v6_0_hw_init,
1253         .hw_fini = uvd_v6_0_hw_fini,
1254         .suspend = uvd_v6_0_suspend,
1255         .resume = uvd_v6_0_resume,
1256         .is_idle = uvd_v6_0_is_idle,
1257         .wait_for_idle = uvd_v6_0_wait_for_idle,
1258         .check_soft_reset = uvd_v6_0_check_soft_reset,
1259         .pre_soft_reset = uvd_v6_0_pre_soft_reset,
1260         .soft_reset = uvd_v6_0_soft_reset,
1261         .post_soft_reset = uvd_v6_0_post_soft_reset,
1262         .set_clockgating_state = uvd_v6_0_set_clockgating_state,
1263         .set_powergating_state = uvd_v6_0_set_powergating_state,
1264         .get_clockgating_state = uvd_v6_0_get_clockgating_state,
1265 };
1266
1267 static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
1268         .type = AMDGPU_RING_TYPE_UVD,
1269         .align_mask = 0xf,
1270         .nop = PACKET0(mmUVD_NO_OP, 0),
1271         .support_64bit_ptrs = false,
1272         .get_rptr = uvd_v6_0_ring_get_rptr,
1273         .get_wptr = uvd_v6_0_ring_get_wptr,
1274         .set_wptr = uvd_v6_0_ring_set_wptr,
1275         .parse_cs = amdgpu_uvd_ring_parse_cs,
1276         .emit_frame_size =
1277                 2 + /* uvd_v6_0_ring_emit_hdp_flush */
1278                 2 + /* uvd_v6_0_ring_emit_hdp_invalidate */
1279                 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
1280                 14, /* uvd_v6_0_ring_emit_fence x1 no user fence */
1281         .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
1282         .emit_ib = uvd_v6_0_ring_emit_ib,
1283         .emit_fence = uvd_v6_0_ring_emit_fence,
1284         .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
1285         .emit_hdp_invalidate = uvd_v6_0_ring_emit_hdp_invalidate,
1286         .test_ring = uvd_v6_0_ring_test_ring,
1287         .test_ib = amdgpu_uvd_ring_test_ib,
1288         .insert_nop = amdgpu_ring_insert_nop,
1289         .pad_ib = amdgpu_ring_generic_pad_ib,
1290         .begin_use = amdgpu_uvd_ring_begin_use,
1291         .end_use = amdgpu_uvd_ring_end_use,
1292 };
1293
1294 static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
1295         .type = AMDGPU_RING_TYPE_UVD,
1296         .align_mask = 0xf,
1297         .nop = PACKET0(mmUVD_NO_OP, 0),
1298         .support_64bit_ptrs = false,
1299         .get_rptr = uvd_v6_0_ring_get_rptr,
1300         .get_wptr = uvd_v6_0_ring_get_wptr,
1301         .set_wptr = uvd_v6_0_ring_set_wptr,
1302         .emit_frame_size =
1303                 2 + /* uvd_v6_0_ring_emit_hdp_flush */
1304                 2 + /* uvd_v6_0_ring_emit_hdp_invalidate */
1305                 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
1306                 20 + /* uvd_v6_0_ring_emit_vm_flush */
1307                 14 + 14, /* uvd_v6_0_ring_emit_fence x2 vm fence */
1308         .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
1309         .emit_ib = uvd_v6_0_ring_emit_ib,
1310         .emit_fence = uvd_v6_0_ring_emit_fence,
1311         .emit_vm_flush = uvd_v6_0_ring_emit_vm_flush,
1312         .emit_pipeline_sync = uvd_v6_0_ring_emit_pipeline_sync,
1313         .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
1314         .emit_hdp_invalidate = uvd_v6_0_ring_emit_hdp_invalidate,
1315         .test_ring = uvd_v6_0_ring_test_ring,
1316         .test_ib = amdgpu_uvd_ring_test_ib,
1317         .insert_nop = amdgpu_ring_insert_nop,
1318         .pad_ib = amdgpu_ring_generic_pad_ib,
1319         .begin_use = amdgpu_uvd_ring_begin_use,
1320         .end_use = amdgpu_uvd_ring_end_use,
1321 };
1322
1323 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev)
1324 {
1325         if (adev->asic_type >= CHIP_POLARIS10) {
1326                 adev->uvd.ring.funcs = &uvd_v6_0_ring_vm_funcs;
1327                 DRM_INFO("UVD is enabled in VM mode\n");
1328         } else {
1329                 adev->uvd.ring.funcs = &uvd_v6_0_ring_phys_funcs;
1330                 DRM_INFO("UVD is enabled in physical mode\n");
1331         }
1332 }
1333
1334 static const struct amdgpu_irq_src_funcs uvd_v6_0_irq_funcs = {
1335         .set = uvd_v6_0_set_interrupt_state,
1336         .process = uvd_v6_0_process_interrupt,
1337 };
1338
1339 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1340 {
1341         adev->uvd.irq.num_types = 1;
1342         adev->uvd.irq.funcs = &uvd_v6_0_irq_funcs;
1343 }
1344
1345 const struct amdgpu_ip_block_version uvd_v6_0_ip_block =
1346 {
1347                 .type = AMD_IP_BLOCK_TYPE_UVD,
1348                 .major = 6,
1349                 .minor = 0,
1350                 .rev = 0,
1351                 .funcs = &uvd_v6_0_ip_funcs,
1352 };
1353
1354 const struct amdgpu_ip_block_version uvd_v6_2_ip_block =
1355 {
1356                 .type = AMD_IP_BLOCK_TYPE_UVD,
1357                 .major = 6,
1358                 .minor = 2,
1359                 .rev = 0,
1360                 .funcs = &uvd_v6_0_ip_funcs,
1361 };
1362
1363 const struct amdgpu_ip_block_version uvd_v6_3_ip_block =
1364 {
1365                 .type = AMD_IP_BLOCK_TYPE_UVD,
1366                 .major = 6,
1367                 .minor = 3,
1368                 .rev = 0,
1369                 .funcs = &uvd_v6_0_ip_funcs,
1370 };