5fd14c972fe781aaa30d7717faa02ca7cc95dae5
[muen/linux.git] / drivers / gpu / drm / amd / amdgpu / uvd_v6_0.c
1 /*
2  * Copyright 2014 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Christian K├Ânig <christian.koenig@amd.com>
23  */
24
25 #include <linux/firmware.h>
26 #include <drm/drmP.h>
27 #include "amdgpu.h"
28 #include "amdgpu_uvd.h"
29 #include "vid.h"
30 #include "uvd/uvd_6_0_d.h"
31 #include "uvd/uvd_6_0_sh_mask.h"
32 #include "oss/oss_2_0_d.h"
33 #include "oss/oss_2_0_sh_mask.h"
34 #include "smu/smu_7_1_3_d.h"
35 #include "smu/smu_7_1_3_sh_mask.h"
36 #include "bif/bif_5_1_d.h"
37 #include "gmc/gmc_8_1_d.h"
38 #include "vi.h"
39
40 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev);
41 static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev);
42
43 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev);
44 static int uvd_v6_0_start(struct amdgpu_device *adev);
45 static void uvd_v6_0_stop(struct amdgpu_device *adev);
46 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev);
47 static int uvd_v6_0_set_clockgating_state(void *handle,
48                                           enum amd_clockgating_state state);
49 static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
50                                  bool enable);
51
52 /**
53 * uvd_v6_0_enc_support - get encode support status
54 *
55 * @adev: amdgpu_device pointer
56 *
57 * Returns the current hardware encode support status
58 */
59 static inline bool uvd_v6_0_enc_support(struct amdgpu_device *adev)
60 {
61         return ((adev->asic_type >= CHIP_POLARIS10) && (adev->asic_type <= CHIP_POLARIS12));
62 }
63
64 /**
65  * uvd_v6_0_ring_get_rptr - get read pointer
66  *
67  * @ring: amdgpu_ring pointer
68  *
69  * Returns the current hardware read pointer
70  */
71 static uint64_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
72 {
73         struct amdgpu_device *adev = ring->adev;
74
75         return RREG32(mmUVD_RBC_RB_RPTR);
76 }
77
78 /**
79  * uvd_v6_0_enc_ring_get_rptr - get enc read pointer
80  *
81  * @ring: amdgpu_ring pointer
82  *
83  * Returns the current hardware enc read pointer
84  */
85 static uint64_t uvd_v6_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
86 {
87         struct amdgpu_device *adev = ring->adev;
88
89         if (ring == &adev->uvd.ring_enc[0])
90                 return RREG32(mmUVD_RB_RPTR);
91         else
92                 return RREG32(mmUVD_RB_RPTR2);
93 }
94 /**
95  * uvd_v6_0_ring_get_wptr - get write pointer
96  *
97  * @ring: amdgpu_ring pointer
98  *
99  * Returns the current hardware write pointer
100  */
101 static uint64_t uvd_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
102 {
103         struct amdgpu_device *adev = ring->adev;
104
105         return RREG32(mmUVD_RBC_RB_WPTR);
106 }
107
108 /**
109  * uvd_v6_0_enc_ring_get_wptr - get enc write pointer
110  *
111  * @ring: amdgpu_ring pointer
112  *
113  * Returns the current hardware enc write pointer
114  */
115 static uint64_t uvd_v6_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
116 {
117         struct amdgpu_device *adev = ring->adev;
118
119         if (ring == &adev->uvd.ring_enc[0])
120                 return RREG32(mmUVD_RB_WPTR);
121         else
122                 return RREG32(mmUVD_RB_WPTR2);
123 }
124
125 /**
126  * uvd_v6_0_ring_set_wptr - set write pointer
127  *
128  * @ring: amdgpu_ring pointer
129  *
130  * Commits the write pointer to the hardware
131  */
132 static void uvd_v6_0_ring_set_wptr(struct amdgpu_ring *ring)
133 {
134         struct amdgpu_device *adev = ring->adev;
135
136         WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
137 }
138
139 /**
140  * uvd_v6_0_enc_ring_set_wptr - set enc write pointer
141  *
142  * @ring: amdgpu_ring pointer
143  *
144  * Commits the enc write pointer to the hardware
145  */
146 static void uvd_v6_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
147 {
148         struct amdgpu_device *adev = ring->adev;
149
150         if (ring == &adev->uvd.ring_enc[0])
151                 WREG32(mmUVD_RB_WPTR,
152                         lower_32_bits(ring->wptr));
153         else
154                 WREG32(mmUVD_RB_WPTR2,
155                         lower_32_bits(ring->wptr));
156 }
157
158 /**
159  * uvd_v6_0_enc_ring_test_ring - test if UVD ENC ring is working
160  *
161  * @ring: the engine to test on
162  *
163  */
164 static int uvd_v6_0_enc_ring_test_ring(struct amdgpu_ring *ring)
165 {
166         struct amdgpu_device *adev = ring->adev;
167         uint32_t rptr = amdgpu_ring_get_rptr(ring);
168         unsigned i;
169         int r;
170
171         r = amdgpu_ring_alloc(ring, 16);
172         if (r) {
173                 DRM_ERROR("amdgpu: uvd enc failed to lock ring %d (%d).\n",
174                           ring->idx, r);
175                 return r;
176         }
177         amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
178         amdgpu_ring_commit(ring);
179
180         for (i = 0; i < adev->usec_timeout; i++) {
181                 if (amdgpu_ring_get_rptr(ring) != rptr)
182                         break;
183                 DRM_UDELAY(1);
184         }
185
186         if (i < adev->usec_timeout) {
187                 DRM_INFO("ring test on %d succeeded in %d usecs\n",
188                          ring->idx, i);
189         } else {
190                 DRM_ERROR("amdgpu: ring %d test failed\n",
191                           ring->idx);
192                 r = -ETIMEDOUT;
193         }
194
195         return r;
196 }
197
198 /**
199  * uvd_v6_0_enc_get_create_msg - generate a UVD ENC create msg
200  *
201  * @adev: amdgpu_device pointer
202  * @ring: ring we should submit the msg to
203  * @handle: session handle to use
204  * @fence: optional fence to return
205  *
206  * Open up a stream for HW test
207  */
208 static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
209                                        struct dma_fence **fence)
210 {
211         const unsigned ib_size_dw = 16;
212         struct amdgpu_job *job;
213         struct amdgpu_ib *ib;
214         struct dma_fence *f = NULL;
215         uint64_t dummy;
216         int i, r;
217
218         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
219         if (r)
220                 return r;
221
222         ib = &job->ibs[0];
223         dummy = ib->gpu_addr + 1024;
224
225         ib->length_dw = 0;
226         ib->ptr[ib->length_dw++] = 0x00000018;
227         ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
228         ib->ptr[ib->length_dw++] = handle;
229         ib->ptr[ib->length_dw++] = 0x00010000;
230         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
231         ib->ptr[ib->length_dw++] = dummy;
232
233         ib->ptr[ib->length_dw++] = 0x00000014;
234         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
235         ib->ptr[ib->length_dw++] = 0x0000001c;
236         ib->ptr[ib->length_dw++] = 0x00000001;
237         ib->ptr[ib->length_dw++] = 0x00000000;
238
239         ib->ptr[ib->length_dw++] = 0x00000008;
240         ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
241
242         for (i = ib->length_dw; i < ib_size_dw; ++i)
243                 ib->ptr[i] = 0x0;
244
245         r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
246         job->fence = dma_fence_get(f);
247         if (r)
248                 goto err;
249
250         amdgpu_job_free(job);
251         if (fence)
252                 *fence = dma_fence_get(f);
253         dma_fence_put(f);
254         return 0;
255
256 err:
257         amdgpu_job_free(job);
258         return r;
259 }
260
261 /**
262  * uvd_v6_0_enc_get_destroy_msg - generate a UVD ENC destroy msg
263  *
264  * @adev: amdgpu_device pointer
265  * @ring: ring we should submit the msg to
266  * @handle: session handle to use
267  * @fence: optional fence to return
268  *
269  * Close up a stream for HW test or if userspace failed to do so
270  */
271 int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
272                                  bool direct, struct dma_fence **fence)
273 {
274         const unsigned ib_size_dw = 16;
275         struct amdgpu_job *job;
276         struct amdgpu_ib *ib;
277         struct dma_fence *f = NULL;
278         uint64_t dummy;
279         int i, r;
280
281         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
282         if (r)
283                 return r;
284
285         ib = &job->ibs[0];
286         dummy = ib->gpu_addr + 1024;
287
288         ib->length_dw = 0;
289         ib->ptr[ib->length_dw++] = 0x00000018;
290         ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
291         ib->ptr[ib->length_dw++] = handle;
292         ib->ptr[ib->length_dw++] = 0x00010000;
293         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
294         ib->ptr[ib->length_dw++] = dummy;
295
296         ib->ptr[ib->length_dw++] = 0x00000014;
297         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
298         ib->ptr[ib->length_dw++] = 0x0000001c;
299         ib->ptr[ib->length_dw++] = 0x00000001;
300         ib->ptr[ib->length_dw++] = 0x00000000;
301
302         ib->ptr[ib->length_dw++] = 0x00000008;
303         ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
304
305         for (i = ib->length_dw; i < ib_size_dw; ++i)
306                 ib->ptr[i] = 0x0;
307
308         if (direct) {
309                 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
310                 job->fence = dma_fence_get(f);
311                 if (r)
312                         goto err;
313
314                 amdgpu_job_free(job);
315         } else {
316                 r = amdgpu_job_submit(job, ring, &ring->adev->vce.entity,
317                                       AMDGPU_FENCE_OWNER_UNDEFINED, &f);
318                 if (r)
319                         goto err;
320         }
321
322         if (fence)
323                 *fence = dma_fence_get(f);
324         dma_fence_put(f);
325         return 0;
326
327 err:
328         amdgpu_job_free(job);
329         return r;
330 }
331
332 /**
333  * uvd_v6_0_enc_ring_test_ib - test if UVD ENC IBs are working
334  *
335  * @ring: the engine to test on
336  *
337  */
338 static int uvd_v6_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
339 {
340         struct dma_fence *fence = NULL;
341         long r;
342
343         r = uvd_v6_0_enc_get_create_msg(ring, 1, NULL);
344         if (r) {
345                 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
346                 goto error;
347         }
348
349         r = uvd_v6_0_enc_get_destroy_msg(ring, 1, true, &fence);
350         if (r) {
351                 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
352                 goto error;
353         }
354
355         r = dma_fence_wait_timeout(fence, false, timeout);
356         if (r == 0) {
357                 DRM_ERROR("amdgpu: IB test timed out.\n");
358                 r = -ETIMEDOUT;
359         } else if (r < 0) {
360                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
361         } else {
362                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
363                 r = 0;
364         }
365 error:
366         dma_fence_put(fence);
367         return r;
368 }
369 static int uvd_v6_0_early_init(void *handle)
370 {
371         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
372
373         uvd_v6_0_set_ring_funcs(adev);
374
375         if (uvd_v6_0_enc_support(adev)) {
376                 adev->uvd.num_enc_rings = 2;
377                 uvd_v6_0_set_enc_ring_funcs(adev);
378         }
379
380         uvd_v6_0_set_irq_funcs(adev);
381
382         return 0;
383 }
384
385 static int uvd_v6_0_sw_init(void *handle)
386 {
387         struct amdgpu_ring *ring;
388         int i, r;
389         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
390
391         /* UVD TRAP */
392         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.irq);
393         if (r)
394                 return r;
395
396         r = amdgpu_uvd_sw_init(adev);
397         if (r)
398                 return r;
399
400         if (uvd_v6_0_enc_support(adev)) {
401                 struct amd_sched_rq *rq;
402                 ring = &adev->uvd.ring_enc[0];
403                 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
404                 r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity_enc,
405                                           rq, amdgpu_sched_jobs);
406                 if (r) {
407                         DRM_ERROR("Failed setting up UVD ENC run queue.\n");
408                         return r;
409                 }
410         }
411
412         r = amdgpu_uvd_resume(adev);
413         if (r)
414                 return r;
415
416         ring = &adev->uvd.ring;
417         sprintf(ring->name, "uvd");
418         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
419         if (r)
420                 return r;
421
422         if (uvd_v6_0_enc_support(adev)) {
423                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
424                         ring = &adev->uvd.ring_enc[i];
425                         sprintf(ring->name, "uvd_enc%d", i);
426                         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
427                         if (r)
428                                 return r;
429                 }
430         }
431
432         return r;
433 }
434
435 static int uvd_v6_0_sw_fini(void *handle)
436 {
437         int i, r;
438         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
439
440         r = amdgpu_uvd_suspend(adev);
441         if (r)
442                 return r;
443
444         if (uvd_v6_0_enc_support(adev)) {
445                 amd_sched_entity_fini(&adev->uvd.ring_enc[0].sched, &adev->uvd.entity_enc);
446
447                 for (i = 0; i < adev->uvd.num_enc_rings; ++i)
448                         amdgpu_ring_fini(&adev->uvd.ring_enc[i]);
449         }
450
451         return amdgpu_uvd_sw_fini(adev);
452 }
453
454 /**
455  * uvd_v6_0_hw_init - start and test UVD block
456  *
457  * @adev: amdgpu_device pointer
458  *
459  * Initialize the hardware, boot up the VCPU and do some testing
460  */
461 static int uvd_v6_0_hw_init(void *handle)
462 {
463         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
464         struct amdgpu_ring *ring = &adev->uvd.ring;
465         uint32_t tmp;
466         int i, r;
467
468         amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
469         uvd_v6_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
470         uvd_v6_0_enable_mgcg(adev, true);
471
472         ring->ready = true;
473         r = amdgpu_ring_test_ring(ring);
474         if (r) {
475                 ring->ready = false;
476                 goto done;
477         }
478
479         r = amdgpu_ring_alloc(ring, 10);
480         if (r) {
481                 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
482                 goto done;
483         }
484
485         tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
486         amdgpu_ring_write(ring, tmp);
487         amdgpu_ring_write(ring, 0xFFFFF);
488
489         tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
490         amdgpu_ring_write(ring, tmp);
491         amdgpu_ring_write(ring, 0xFFFFF);
492
493         tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
494         amdgpu_ring_write(ring, tmp);
495         amdgpu_ring_write(ring, 0xFFFFF);
496
497         /* Clear timeout status bits */
498         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
499         amdgpu_ring_write(ring, 0x8);
500
501         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
502         amdgpu_ring_write(ring, 3);
503
504         amdgpu_ring_commit(ring);
505
506         if (uvd_v6_0_enc_support(adev)) {
507                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
508                         ring = &adev->uvd.ring_enc[i];
509                         ring->ready = true;
510                         r = amdgpu_ring_test_ring(ring);
511                         if (r) {
512                                 ring->ready = false;
513                                 goto done;
514                         }
515                 }
516         }
517
518 done:
519         if (!r) {
520                 if (uvd_v6_0_enc_support(adev))
521                         DRM_INFO("UVD and UVD ENC initialized successfully.\n");
522                 else
523                         DRM_INFO("UVD initialized successfully.\n");
524         }
525
526         return r;
527 }
528
529 /**
530  * uvd_v6_0_hw_fini - stop the hardware block
531  *
532  * @adev: amdgpu_device pointer
533  *
534  * Stop the UVD block, mark ring as not ready any more
535  */
536 static int uvd_v6_0_hw_fini(void *handle)
537 {
538         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
539         struct amdgpu_ring *ring = &adev->uvd.ring;
540
541         if (RREG32(mmUVD_STATUS) != 0)
542                 uvd_v6_0_stop(adev);
543
544         ring->ready = false;
545
546         return 0;
547 }
548
549 static int uvd_v6_0_suspend(void *handle)
550 {
551         int r;
552         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
553
554         r = uvd_v6_0_hw_fini(adev);
555         if (r)
556                 return r;
557
558         /* Skip this for APU for now */
559         if (!(adev->flags & AMD_IS_APU))
560                 r = amdgpu_uvd_suspend(adev);
561
562         return r;
563 }
564
565 static int uvd_v6_0_resume(void *handle)
566 {
567         int r;
568         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
569
570         /* Skip this for APU for now */
571         if (!(adev->flags & AMD_IS_APU)) {
572                 r = amdgpu_uvd_resume(adev);
573                 if (r)
574                         return r;
575         }
576         return uvd_v6_0_hw_init(adev);
577 }
578
579 /**
580  * uvd_v6_0_mc_resume - memory controller programming
581  *
582  * @adev: amdgpu_device pointer
583  *
584  * Let the UVD memory controller know it's offsets
585  */
586 static void uvd_v6_0_mc_resume(struct amdgpu_device *adev)
587 {
588         uint64_t offset;
589         uint32_t size;
590
591         /* programm memory controller bits 0-27 */
592         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
593                         lower_32_bits(adev->uvd.gpu_addr));
594         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
595                         upper_32_bits(adev->uvd.gpu_addr));
596
597         offset = AMDGPU_UVD_FIRMWARE_OFFSET;
598         size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
599         WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
600         WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
601
602         offset += size;
603         size = AMDGPU_UVD_HEAP_SIZE;
604         WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
605         WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
606
607         offset += size;
608         size = AMDGPU_UVD_STACK_SIZE +
609                (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles);
610         WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
611         WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
612
613         WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
614         WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
615         WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
616
617         WREG32(mmUVD_GP_SCRATCH4, adev->uvd.max_handles);
618 }
619
620 #if 0
621 static void cz_set_uvd_clock_gating_branches(struct amdgpu_device *adev,
622                 bool enable)
623 {
624         u32 data, data1;
625
626         data = RREG32(mmUVD_CGC_GATE);
627         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
628         if (enable) {
629                 data |= UVD_CGC_GATE__SYS_MASK |
630                                 UVD_CGC_GATE__UDEC_MASK |
631                                 UVD_CGC_GATE__MPEG2_MASK |
632                                 UVD_CGC_GATE__RBC_MASK |
633                                 UVD_CGC_GATE__LMI_MC_MASK |
634                                 UVD_CGC_GATE__IDCT_MASK |
635                                 UVD_CGC_GATE__MPRD_MASK |
636                                 UVD_CGC_GATE__MPC_MASK |
637                                 UVD_CGC_GATE__LBSI_MASK |
638                                 UVD_CGC_GATE__LRBBM_MASK |
639                                 UVD_CGC_GATE__UDEC_RE_MASK |
640                                 UVD_CGC_GATE__UDEC_CM_MASK |
641                                 UVD_CGC_GATE__UDEC_IT_MASK |
642                                 UVD_CGC_GATE__UDEC_DB_MASK |
643                                 UVD_CGC_GATE__UDEC_MP_MASK |
644                                 UVD_CGC_GATE__WCB_MASK |
645                                 UVD_CGC_GATE__VCPU_MASK |
646                                 UVD_CGC_GATE__SCPU_MASK;
647                 data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
648                                 UVD_SUVD_CGC_GATE__SIT_MASK |
649                                 UVD_SUVD_CGC_GATE__SMP_MASK |
650                                 UVD_SUVD_CGC_GATE__SCM_MASK |
651                                 UVD_SUVD_CGC_GATE__SDB_MASK |
652                                 UVD_SUVD_CGC_GATE__SRE_H264_MASK |
653                                 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
654                                 UVD_SUVD_CGC_GATE__SIT_H264_MASK |
655                                 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
656                                 UVD_SUVD_CGC_GATE__SCM_H264_MASK |
657                                 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
658                                 UVD_SUVD_CGC_GATE__SDB_H264_MASK |
659                                 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK;
660         } else {
661                 data &= ~(UVD_CGC_GATE__SYS_MASK |
662                                 UVD_CGC_GATE__UDEC_MASK |
663                                 UVD_CGC_GATE__MPEG2_MASK |
664                                 UVD_CGC_GATE__RBC_MASK |
665                                 UVD_CGC_GATE__LMI_MC_MASK |
666                                 UVD_CGC_GATE__LMI_UMC_MASK |
667                                 UVD_CGC_GATE__IDCT_MASK |
668                                 UVD_CGC_GATE__MPRD_MASK |
669                                 UVD_CGC_GATE__MPC_MASK |
670                                 UVD_CGC_GATE__LBSI_MASK |
671                                 UVD_CGC_GATE__LRBBM_MASK |
672                                 UVD_CGC_GATE__UDEC_RE_MASK |
673                                 UVD_CGC_GATE__UDEC_CM_MASK |
674                                 UVD_CGC_GATE__UDEC_IT_MASK |
675                                 UVD_CGC_GATE__UDEC_DB_MASK |
676                                 UVD_CGC_GATE__UDEC_MP_MASK |
677                                 UVD_CGC_GATE__WCB_MASK |
678                                 UVD_CGC_GATE__VCPU_MASK |
679                                 UVD_CGC_GATE__SCPU_MASK);
680                 data1 &= ~(UVD_SUVD_CGC_GATE__SRE_MASK |
681                                 UVD_SUVD_CGC_GATE__SIT_MASK |
682                                 UVD_SUVD_CGC_GATE__SMP_MASK |
683                                 UVD_SUVD_CGC_GATE__SCM_MASK |
684                                 UVD_SUVD_CGC_GATE__SDB_MASK |
685                                 UVD_SUVD_CGC_GATE__SRE_H264_MASK |
686                                 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
687                                 UVD_SUVD_CGC_GATE__SIT_H264_MASK |
688                                 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
689                                 UVD_SUVD_CGC_GATE__SCM_H264_MASK |
690                                 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
691                                 UVD_SUVD_CGC_GATE__SDB_H264_MASK |
692                                 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK);
693         }
694         WREG32(mmUVD_CGC_GATE, data);
695         WREG32(mmUVD_SUVD_CGC_GATE, data1);
696 }
697 #endif
698
699 /**
700  * uvd_v6_0_start - start UVD block
701  *
702  * @adev: amdgpu_device pointer
703  *
704  * Setup and start the UVD block
705  */
706 static int uvd_v6_0_start(struct amdgpu_device *adev)
707 {
708         struct amdgpu_ring *ring = &adev->uvd.ring;
709         uint32_t rb_bufsz, tmp;
710         uint32_t lmi_swap_cntl;
711         uint32_t mp_swap_cntl;
712         int i, j, r;
713
714         /* disable DPG */
715         WREG32_P(mmUVD_POWER_STATUS, 0, ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
716
717         /* disable byte swapping */
718         lmi_swap_cntl = 0;
719         mp_swap_cntl = 0;
720
721         uvd_v6_0_mc_resume(adev);
722
723         /* disable interupt */
724         WREG32_FIELD(UVD_MASTINT_EN, VCPU_EN, 0);
725
726         /* stall UMC and register bus before resetting VCPU */
727         WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 1);
728         mdelay(1);
729
730         /* put LMI, VCPU, RBC etc... into reset */
731         WREG32(mmUVD_SOFT_RESET,
732                 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
733                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
734                 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
735                 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
736                 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
737                 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
738                 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
739                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
740         mdelay(5);
741
742         /* take UVD block out of reset */
743         WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_UVD, 0);
744         mdelay(5);
745
746         /* initialize UVD memory controller */
747         WREG32(mmUVD_LMI_CTRL,
748                 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
749                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
750                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
751                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
752                 UVD_LMI_CTRL__REQ_MODE_MASK |
753                 UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK);
754
755 #ifdef __BIG_ENDIAN
756         /* swap (8 in 32) RB and IB */
757         lmi_swap_cntl = 0xa;
758         mp_swap_cntl = 0;
759 #endif
760         WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
761         WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
762
763         WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
764         WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
765         WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
766         WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
767         WREG32(mmUVD_MPC_SET_ALU, 0);
768         WREG32(mmUVD_MPC_SET_MUX, 0x88);
769
770         /* take all subblocks out of reset, except VCPU */
771         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
772         mdelay(5);
773
774         /* enable VCPU clock */
775         WREG32(mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
776
777         /* enable UMC */
778         WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 0);
779
780         /* boot up the VCPU */
781         WREG32(mmUVD_SOFT_RESET, 0);
782         mdelay(10);
783
784         for (i = 0; i < 10; ++i) {
785                 uint32_t status;
786
787                 for (j = 0; j < 100; ++j) {
788                         status = RREG32(mmUVD_STATUS);
789                         if (status & 2)
790                                 break;
791                         mdelay(10);
792                 }
793                 r = 0;
794                 if (status & 2)
795                         break;
796
797                 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
798                 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 1);
799                 mdelay(10);
800                 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 0);
801                 mdelay(10);
802                 r = -1;
803         }
804
805         if (r) {
806                 DRM_ERROR("UVD not responding, giving up!!!\n");
807                 return r;
808         }
809         /* enable master interrupt */
810         WREG32_P(mmUVD_MASTINT_EN,
811                 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
812                 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
813
814         /* clear the bit 4 of UVD_STATUS */
815         WREG32_P(mmUVD_STATUS, 0, ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
816
817         /* force RBC into idle state */
818         rb_bufsz = order_base_2(ring->ring_size);
819         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
820         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
821         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
822         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
823         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
824         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
825         WREG32(mmUVD_RBC_RB_CNTL, tmp);
826
827         /* set the write pointer delay */
828         WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
829
830         /* set the wb address */
831         WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));
832
833         /* programm the RB_BASE for ring buffer */
834         WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
835                         lower_32_bits(ring->gpu_addr));
836         WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
837                         upper_32_bits(ring->gpu_addr));
838
839         /* Initialize the ring buffer's read and write pointers */
840         WREG32(mmUVD_RBC_RB_RPTR, 0);
841
842         ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
843         WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
844
845         WREG32_FIELD(UVD_RBC_RB_CNTL, RB_NO_FETCH, 0);
846
847         if (uvd_v6_0_enc_support(adev)) {
848                 ring = &adev->uvd.ring_enc[0];
849                 WREG32(mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
850                 WREG32(mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
851                 WREG32(mmUVD_RB_BASE_LO, ring->gpu_addr);
852                 WREG32(mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
853                 WREG32(mmUVD_RB_SIZE, ring->ring_size / 4);
854
855                 ring = &adev->uvd.ring_enc[1];
856                 WREG32(mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
857                 WREG32(mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
858                 WREG32(mmUVD_RB_BASE_LO2, ring->gpu_addr);
859                 WREG32(mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
860                 WREG32(mmUVD_RB_SIZE2, ring->ring_size / 4);
861         }
862
863         return 0;
864 }
865
866 /**
867  * uvd_v6_0_stop - stop UVD block
868  *
869  * @adev: amdgpu_device pointer
870  *
871  * stop the UVD block
872  */
873 static void uvd_v6_0_stop(struct amdgpu_device *adev)
874 {
875         /* force RBC into idle state */
876         WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
877
878         /* Stall UMC and register bus before resetting VCPU */
879         WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
880         mdelay(1);
881
882         /* put VCPU into reset */
883         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
884         mdelay(5);
885
886         /* disable VCPU clock */
887         WREG32(mmUVD_VCPU_CNTL, 0x0);
888
889         /* Unstall UMC and register bus */
890         WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
891
892         WREG32(mmUVD_STATUS, 0);
893 }
894
895 /**
896  * uvd_v6_0_ring_emit_fence - emit an fence & trap command
897  *
898  * @ring: amdgpu_ring pointer
899  * @fence: fence to emit
900  *
901  * Write a fence and a trap command to the ring.
902  */
903 static void uvd_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
904                                      unsigned flags)
905 {
906         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
907
908         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
909         amdgpu_ring_write(ring, seq);
910         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
911         amdgpu_ring_write(ring, addr & 0xffffffff);
912         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
913         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
914         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
915         amdgpu_ring_write(ring, 0);
916
917         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
918         amdgpu_ring_write(ring, 0);
919         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
920         amdgpu_ring_write(ring, 0);
921         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
922         amdgpu_ring_write(ring, 2);
923 }
924
925 /**
926  * uvd_v6_0_enc_ring_emit_fence - emit an enc fence & trap command
927  *
928  * @ring: amdgpu_ring pointer
929  * @fence: fence to emit
930  *
931  * Write enc a fence and a trap command to the ring.
932  */
933 static void uvd_v6_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
934                         u64 seq, unsigned flags)
935 {
936         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
937
938         amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE);
939         amdgpu_ring_write(ring, addr);
940         amdgpu_ring_write(ring, upper_32_bits(addr));
941         amdgpu_ring_write(ring, seq);
942         amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
943 }
944
945 /**
946  * uvd_v6_0_ring_emit_hdp_flush - emit an hdp flush
947  *
948  * @ring: amdgpu_ring pointer
949  *
950  * Emits an hdp flush.
951  */
952 static void uvd_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
953 {
954         amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0));
955         amdgpu_ring_write(ring, 0);
956 }
957
958 /**
959  * uvd_v6_0_ring_hdp_invalidate - emit an hdp invalidate
960  *
961  * @ring: amdgpu_ring pointer
962  *
963  * Emits an hdp invalidate.
964  */
965 static void uvd_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
966 {
967         amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0));
968         amdgpu_ring_write(ring, 1);
969 }
970
971 /**
972  * uvd_v6_0_ring_test_ring - register write test
973  *
974  * @ring: amdgpu_ring pointer
975  *
976  * Test if we can successfully write to the context register
977  */
978 static int uvd_v6_0_ring_test_ring(struct amdgpu_ring *ring)
979 {
980         struct amdgpu_device *adev = ring->adev;
981         uint32_t tmp = 0;
982         unsigned i;
983         int r;
984
985         WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
986         r = amdgpu_ring_alloc(ring, 3);
987         if (r) {
988                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
989                           ring->idx, r);
990                 return r;
991         }
992         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
993         amdgpu_ring_write(ring, 0xDEADBEEF);
994         amdgpu_ring_commit(ring);
995         for (i = 0; i < adev->usec_timeout; i++) {
996                 tmp = RREG32(mmUVD_CONTEXT_ID);
997                 if (tmp == 0xDEADBEEF)
998                         break;
999                 DRM_UDELAY(1);
1000         }
1001
1002         if (i < adev->usec_timeout) {
1003                 DRM_INFO("ring test on %d succeeded in %d usecs\n",
1004                          ring->idx, i);
1005         } else {
1006                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
1007                           ring->idx, tmp);
1008                 r = -EINVAL;
1009         }
1010         return r;
1011 }
1012
1013 /**
1014  * uvd_v6_0_ring_emit_ib - execute indirect buffer
1015  *
1016  * @ring: amdgpu_ring pointer
1017  * @ib: indirect buffer to execute
1018  *
1019  * Write ring commands to execute the indirect buffer
1020  */
1021 static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
1022                                   struct amdgpu_ib *ib,
1023                                   unsigned vm_id, bool ctx_switch)
1024 {
1025         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_VMID, 0));
1026         amdgpu_ring_write(ring, vm_id);
1027
1028         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
1029         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1030         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0));
1031         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1032         amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
1033         amdgpu_ring_write(ring, ib->length_dw);
1034 }
1035
1036 /**
1037  * uvd_v6_0_enc_ring_emit_ib - enc execute indirect buffer
1038  *
1039  * @ring: amdgpu_ring pointer
1040  * @ib: indirect buffer to execute
1041  *
1042  * Write enc ring commands to execute the indirect buffer
1043  */
1044 static void uvd_v6_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1045                 struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch)
1046 {
1047         amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM);
1048         amdgpu_ring_write(ring, vm_id);
1049         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1050         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1051         amdgpu_ring_write(ring, ib->length_dw);
1052 }
1053
1054 static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1055                                          unsigned vm_id, uint64_t pd_addr)
1056 {
1057         uint32_t reg;
1058
1059         if (vm_id < 8)
1060                 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id;
1061         else
1062                 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8;
1063
1064         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
1065         amdgpu_ring_write(ring, reg << 2);
1066         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
1067         amdgpu_ring_write(ring, pd_addr >> 12);
1068         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
1069         amdgpu_ring_write(ring, 0x8);
1070
1071         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
1072         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1073         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
1074         amdgpu_ring_write(ring, 1 << vm_id);
1075         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
1076         amdgpu_ring_write(ring, 0x8);
1077
1078         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
1079         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1080         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
1081         amdgpu_ring_write(ring, 0);
1082         amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0));
1083         amdgpu_ring_write(ring, 1 << vm_id); /* mask */
1084         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
1085         amdgpu_ring_write(ring, 0xC);
1086 }
1087
1088 static void uvd_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1089 {
1090         uint32_t seq = ring->fence_drv.sync_seq;
1091         uint64_t addr = ring->fence_drv.gpu_addr;
1092
1093         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
1094         amdgpu_ring_write(ring, lower_32_bits(addr));
1095         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
1096         amdgpu_ring_write(ring, upper_32_bits(addr));
1097         amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0));
1098         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1099         amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH9, 0));
1100         amdgpu_ring_write(ring, seq);
1101         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
1102         amdgpu_ring_write(ring, 0xE);
1103 }
1104
1105 static void uvd_v6_0_enc_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1106 {
1107         uint32_t seq = ring->fence_drv.sync_seq;
1108         uint64_t addr = ring->fence_drv.gpu_addr;
1109
1110         amdgpu_ring_write(ring, HEVC_ENC_CMD_WAIT_GE);
1111         amdgpu_ring_write(ring, lower_32_bits(addr));
1112         amdgpu_ring_write(ring, upper_32_bits(addr));
1113         amdgpu_ring_write(ring, seq);
1114 }
1115
1116 static void uvd_v6_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1117 {
1118         amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
1119 }
1120
1121 static void uvd_v6_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1122         unsigned int vm_id, uint64_t pd_addr)
1123 {
1124         amdgpu_ring_write(ring, HEVC_ENC_CMD_UPDATE_PTB);
1125         amdgpu_ring_write(ring, vm_id);
1126         amdgpu_ring_write(ring, pd_addr >> 12);
1127
1128         amdgpu_ring_write(ring, HEVC_ENC_CMD_FLUSH_TLB);
1129         amdgpu_ring_write(ring, vm_id);
1130 }
1131
1132 static bool uvd_v6_0_is_idle(void *handle)
1133 {
1134         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1135
1136         return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
1137 }
1138
1139 static int uvd_v6_0_wait_for_idle(void *handle)
1140 {
1141         unsigned i;
1142         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1143
1144         for (i = 0; i < adev->usec_timeout; i++) {
1145                 if (uvd_v6_0_is_idle(handle))
1146                         return 0;
1147         }
1148         return -ETIMEDOUT;
1149 }
1150
1151 #define AMDGPU_UVD_STATUS_BUSY_MASK    0xfd
1152 static bool uvd_v6_0_check_soft_reset(void *handle)
1153 {
1154         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1155         u32 srbm_soft_reset = 0;
1156         u32 tmp = RREG32(mmSRBM_STATUS);
1157
1158         if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) ||
1159             REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) ||
1160             (RREG32(mmUVD_STATUS) & AMDGPU_UVD_STATUS_BUSY_MASK))
1161                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
1162
1163         if (srbm_soft_reset) {
1164                 adev->uvd.srbm_soft_reset = srbm_soft_reset;
1165                 return true;
1166         } else {
1167                 adev->uvd.srbm_soft_reset = 0;
1168                 return false;
1169         }
1170 }
1171
1172 static int uvd_v6_0_pre_soft_reset(void *handle)
1173 {
1174         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1175
1176         if (!adev->uvd.srbm_soft_reset)
1177                 return 0;
1178
1179         uvd_v6_0_stop(adev);
1180         return 0;
1181 }
1182
1183 static int uvd_v6_0_soft_reset(void *handle)
1184 {
1185         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1186         u32 srbm_soft_reset;
1187
1188         if (!adev->uvd.srbm_soft_reset)
1189                 return 0;
1190         srbm_soft_reset = adev->uvd.srbm_soft_reset;
1191
1192         if (srbm_soft_reset) {
1193                 u32 tmp;
1194
1195                 tmp = RREG32(mmSRBM_SOFT_RESET);
1196                 tmp |= srbm_soft_reset;
1197                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1198                 WREG32(mmSRBM_SOFT_RESET, tmp);
1199                 tmp = RREG32(mmSRBM_SOFT_RESET);
1200
1201                 udelay(50);
1202
1203                 tmp &= ~srbm_soft_reset;
1204                 WREG32(mmSRBM_SOFT_RESET, tmp);
1205                 tmp = RREG32(mmSRBM_SOFT_RESET);
1206
1207                 /* Wait a little for things to settle down */
1208                 udelay(50);
1209         }
1210
1211         return 0;
1212 }
1213
1214 static int uvd_v6_0_post_soft_reset(void *handle)
1215 {
1216         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1217
1218         if (!adev->uvd.srbm_soft_reset)
1219                 return 0;
1220
1221         mdelay(5);
1222
1223         return uvd_v6_0_start(adev);
1224 }
1225
1226 static int uvd_v6_0_set_interrupt_state(struct amdgpu_device *adev,
1227                                         struct amdgpu_irq_src *source,
1228                                         unsigned type,
1229                                         enum amdgpu_interrupt_state state)
1230 {
1231         // TODO
1232         return 0;
1233 }
1234
1235 static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev,
1236                                       struct amdgpu_irq_src *source,
1237                                       struct amdgpu_iv_entry *entry)
1238 {
1239         DRM_DEBUG("IH: UVD TRAP\n");
1240         amdgpu_fence_process(&adev->uvd.ring);
1241         return 0;
1242 }
1243
1244 static void uvd_v6_0_enable_clock_gating(struct amdgpu_device *adev, bool enable)
1245 {
1246         uint32_t data1, data3;
1247
1248         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
1249         data3 = RREG32(mmUVD_CGC_GATE);
1250
1251         data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
1252                      UVD_SUVD_CGC_GATE__SIT_MASK |
1253                      UVD_SUVD_CGC_GATE__SMP_MASK |
1254                      UVD_SUVD_CGC_GATE__SCM_MASK |
1255                      UVD_SUVD_CGC_GATE__SDB_MASK |
1256                      UVD_SUVD_CGC_GATE__SRE_H264_MASK |
1257                      UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
1258                      UVD_SUVD_CGC_GATE__SIT_H264_MASK |
1259                      UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
1260                      UVD_SUVD_CGC_GATE__SCM_H264_MASK |
1261                      UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
1262                      UVD_SUVD_CGC_GATE__SDB_H264_MASK |
1263                      UVD_SUVD_CGC_GATE__SDB_HEVC_MASK;
1264
1265         if (enable) {
1266                 data3 |= (UVD_CGC_GATE__SYS_MASK       |
1267                         UVD_CGC_GATE__UDEC_MASK      |
1268                         UVD_CGC_GATE__MPEG2_MASK     |
1269                         UVD_CGC_GATE__RBC_MASK       |
1270                         UVD_CGC_GATE__LMI_MC_MASK    |
1271                         UVD_CGC_GATE__LMI_UMC_MASK   |
1272                         UVD_CGC_GATE__IDCT_MASK      |
1273                         UVD_CGC_GATE__MPRD_MASK      |
1274                         UVD_CGC_GATE__MPC_MASK       |
1275                         UVD_CGC_GATE__LBSI_MASK      |
1276                         UVD_CGC_GATE__LRBBM_MASK     |
1277                         UVD_CGC_GATE__UDEC_RE_MASK   |
1278                         UVD_CGC_GATE__UDEC_CM_MASK   |
1279                         UVD_CGC_GATE__UDEC_IT_MASK   |
1280                         UVD_CGC_GATE__UDEC_DB_MASK   |
1281                         UVD_CGC_GATE__UDEC_MP_MASK   |
1282                         UVD_CGC_GATE__WCB_MASK       |
1283                         UVD_CGC_GATE__JPEG_MASK      |
1284                         UVD_CGC_GATE__SCPU_MASK      |
1285                         UVD_CGC_GATE__JPEG2_MASK);
1286                 /* only in pg enabled, we can gate clock to vcpu*/
1287                 if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
1288                         data3 |= UVD_CGC_GATE__VCPU_MASK;
1289
1290                 data3 &= ~UVD_CGC_GATE__REGS_MASK;
1291         } else {
1292                 data3 = 0;
1293         }
1294
1295         WREG32(mmUVD_SUVD_CGC_GATE, data1);
1296         WREG32(mmUVD_CGC_GATE, data3);
1297 }
1298
1299 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev)
1300 {
1301         uint32_t data, data2;
1302
1303         data = RREG32(mmUVD_CGC_CTRL);
1304         data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
1305
1306
1307         data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
1308                   UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
1309
1310
1311         data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
1312                 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
1313                 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
1314
1315         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
1316                         UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
1317                         UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
1318                         UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
1319                         UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
1320                         UVD_CGC_CTRL__SYS_MODE_MASK |
1321                         UVD_CGC_CTRL__UDEC_MODE_MASK |
1322                         UVD_CGC_CTRL__MPEG2_MODE_MASK |
1323                         UVD_CGC_CTRL__REGS_MODE_MASK |
1324                         UVD_CGC_CTRL__RBC_MODE_MASK |
1325                         UVD_CGC_CTRL__LMI_MC_MODE_MASK |
1326                         UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
1327                         UVD_CGC_CTRL__IDCT_MODE_MASK |
1328                         UVD_CGC_CTRL__MPRD_MODE_MASK |
1329                         UVD_CGC_CTRL__MPC_MODE_MASK |
1330                         UVD_CGC_CTRL__LBSI_MODE_MASK |
1331                         UVD_CGC_CTRL__LRBBM_MODE_MASK |
1332                         UVD_CGC_CTRL__WCB_MODE_MASK |
1333                         UVD_CGC_CTRL__VCPU_MODE_MASK |
1334                         UVD_CGC_CTRL__JPEG_MODE_MASK |
1335                         UVD_CGC_CTRL__SCPU_MODE_MASK |
1336                         UVD_CGC_CTRL__JPEG2_MODE_MASK);
1337         data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
1338                         UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
1339                         UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
1340                         UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
1341                         UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
1342
1343         WREG32(mmUVD_CGC_CTRL, data);
1344         WREG32(mmUVD_SUVD_CGC_CTRL, data2);
1345 }
1346
1347 #if 0
1348 static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev)
1349 {
1350         uint32_t data, data1, cgc_flags, suvd_flags;
1351
1352         data = RREG32(mmUVD_CGC_GATE);
1353         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
1354
1355         cgc_flags = UVD_CGC_GATE__SYS_MASK |
1356                 UVD_CGC_GATE__UDEC_MASK |
1357                 UVD_CGC_GATE__MPEG2_MASK |
1358                 UVD_CGC_GATE__RBC_MASK |
1359                 UVD_CGC_GATE__LMI_MC_MASK |
1360                 UVD_CGC_GATE__IDCT_MASK |
1361                 UVD_CGC_GATE__MPRD_MASK |
1362                 UVD_CGC_GATE__MPC_MASK |
1363                 UVD_CGC_GATE__LBSI_MASK |
1364                 UVD_CGC_GATE__LRBBM_MASK |
1365                 UVD_CGC_GATE__UDEC_RE_MASK |
1366                 UVD_CGC_GATE__UDEC_CM_MASK |
1367                 UVD_CGC_GATE__UDEC_IT_MASK |
1368                 UVD_CGC_GATE__UDEC_DB_MASK |
1369                 UVD_CGC_GATE__UDEC_MP_MASK |
1370                 UVD_CGC_GATE__WCB_MASK |
1371                 UVD_CGC_GATE__VCPU_MASK |
1372                 UVD_CGC_GATE__SCPU_MASK |
1373                 UVD_CGC_GATE__JPEG_MASK |
1374                 UVD_CGC_GATE__JPEG2_MASK;
1375
1376         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1377                                 UVD_SUVD_CGC_GATE__SIT_MASK |
1378                                 UVD_SUVD_CGC_GATE__SMP_MASK |
1379                                 UVD_SUVD_CGC_GATE__SCM_MASK |
1380                                 UVD_SUVD_CGC_GATE__SDB_MASK;
1381
1382         data |= cgc_flags;
1383         data1 |= suvd_flags;
1384
1385         WREG32(mmUVD_CGC_GATE, data);
1386         WREG32(mmUVD_SUVD_CGC_GATE, data1);
1387 }
1388 #endif
1389
1390 static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
1391                                  bool enable)
1392 {
1393         u32 orig, data;
1394
1395         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
1396                 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
1397                 data |= 0xfff;
1398                 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
1399
1400                 orig = data = RREG32(mmUVD_CGC_CTRL);
1401                 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
1402                 if (orig != data)
1403                         WREG32(mmUVD_CGC_CTRL, data);
1404         } else {
1405                 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
1406                 data &= ~0xfff;
1407                 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
1408
1409                 orig = data = RREG32(mmUVD_CGC_CTRL);
1410                 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
1411                 if (orig != data)
1412                         WREG32(mmUVD_CGC_CTRL, data);
1413         }
1414 }
1415
1416 static int uvd_v6_0_set_clockgating_state(void *handle,
1417                                           enum amd_clockgating_state state)
1418 {
1419         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1420         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1421
1422         if (enable) {
1423                 /* wait for STATUS to clear */
1424                 if (uvd_v6_0_wait_for_idle(handle))
1425                         return -EBUSY;
1426                 uvd_v6_0_enable_clock_gating(adev, true);
1427                 /* enable HW gates because UVD is idle */
1428 /*              uvd_v6_0_set_hw_clock_gating(adev); */
1429         } else {
1430                 /* disable HW gating and enable Sw gating */
1431                 uvd_v6_0_enable_clock_gating(adev, false);
1432         }
1433         uvd_v6_0_set_sw_clock_gating(adev);
1434         return 0;
1435 }
1436
1437 static int uvd_v6_0_set_powergating_state(void *handle,
1438                                           enum amd_powergating_state state)
1439 {
1440         /* This doesn't actually powergate the UVD block.
1441          * That's done in the dpm code via the SMC.  This
1442          * just re-inits the block as necessary.  The actual
1443          * gating still happens in the dpm code.  We should
1444          * revisit this when there is a cleaner line between
1445          * the smc and the hw blocks
1446          */
1447         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1448         int ret = 0;
1449
1450         WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
1451
1452         if (state == AMD_PG_STATE_GATE) {
1453                 uvd_v6_0_stop(adev);
1454         } else {
1455                 ret = uvd_v6_0_start(adev);
1456                 if (ret)
1457                         goto out;
1458         }
1459
1460 out:
1461         return ret;
1462 }
1463
1464 static void uvd_v6_0_get_clockgating_state(void *handle, u32 *flags)
1465 {
1466         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1467         int data;
1468
1469         mutex_lock(&adev->pm.mutex);
1470
1471         if (adev->flags & AMD_IS_APU)
1472                 data = RREG32_SMC(ixCURRENT_PG_STATUS_APU);
1473         else
1474                 data = RREG32_SMC(ixCURRENT_PG_STATUS);
1475
1476         if (data & CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) {
1477                 DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
1478                 goto out;
1479         }
1480
1481         /* AMD_CG_SUPPORT_UVD_MGCG */
1482         data = RREG32(mmUVD_CGC_CTRL);
1483         if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)
1484                 *flags |= AMD_CG_SUPPORT_UVD_MGCG;
1485
1486 out:
1487         mutex_unlock(&adev->pm.mutex);
1488 }
1489
1490 static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
1491         .name = "uvd_v6_0",
1492         .early_init = uvd_v6_0_early_init,
1493         .late_init = NULL,
1494         .sw_init = uvd_v6_0_sw_init,
1495         .sw_fini = uvd_v6_0_sw_fini,
1496         .hw_init = uvd_v6_0_hw_init,
1497         .hw_fini = uvd_v6_0_hw_fini,
1498         .suspend = uvd_v6_0_suspend,
1499         .resume = uvd_v6_0_resume,
1500         .is_idle = uvd_v6_0_is_idle,
1501         .wait_for_idle = uvd_v6_0_wait_for_idle,
1502         .check_soft_reset = uvd_v6_0_check_soft_reset,
1503         .pre_soft_reset = uvd_v6_0_pre_soft_reset,
1504         .soft_reset = uvd_v6_0_soft_reset,
1505         .post_soft_reset = uvd_v6_0_post_soft_reset,
1506         .set_clockgating_state = uvd_v6_0_set_clockgating_state,
1507         .set_powergating_state = uvd_v6_0_set_powergating_state,
1508         .get_clockgating_state = uvd_v6_0_get_clockgating_state,
1509 };
1510
1511 static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
1512         .type = AMDGPU_RING_TYPE_UVD,
1513         .align_mask = 0xf,
1514         .nop = PACKET0(mmUVD_NO_OP, 0),
1515         .support_64bit_ptrs = false,
1516         .get_rptr = uvd_v6_0_ring_get_rptr,
1517         .get_wptr = uvd_v6_0_ring_get_wptr,
1518         .set_wptr = uvd_v6_0_ring_set_wptr,
1519         .parse_cs = amdgpu_uvd_ring_parse_cs,
1520         .emit_frame_size =
1521                 2 + /* uvd_v6_0_ring_emit_hdp_flush */
1522                 2 + /* uvd_v6_0_ring_emit_hdp_invalidate */
1523                 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
1524                 14, /* uvd_v6_0_ring_emit_fence x1 no user fence */
1525         .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
1526         .emit_ib = uvd_v6_0_ring_emit_ib,
1527         .emit_fence = uvd_v6_0_ring_emit_fence,
1528         .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
1529         .emit_hdp_invalidate = uvd_v6_0_ring_emit_hdp_invalidate,
1530         .test_ring = uvd_v6_0_ring_test_ring,
1531         .test_ib = amdgpu_uvd_ring_test_ib,
1532         .insert_nop = amdgpu_ring_insert_nop,
1533         .pad_ib = amdgpu_ring_generic_pad_ib,
1534         .begin_use = amdgpu_uvd_ring_begin_use,
1535         .end_use = amdgpu_uvd_ring_end_use,
1536 };
1537
1538 static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
1539         .type = AMDGPU_RING_TYPE_UVD,
1540         .align_mask = 0xf,
1541         .nop = PACKET0(mmUVD_NO_OP, 0),
1542         .support_64bit_ptrs = false,
1543         .get_rptr = uvd_v6_0_ring_get_rptr,
1544         .get_wptr = uvd_v6_0_ring_get_wptr,
1545         .set_wptr = uvd_v6_0_ring_set_wptr,
1546         .emit_frame_size =
1547                 2 + /* uvd_v6_0_ring_emit_hdp_flush */
1548                 2 + /* uvd_v6_0_ring_emit_hdp_invalidate */
1549                 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
1550                 20 + /* uvd_v6_0_ring_emit_vm_flush */
1551                 14 + 14, /* uvd_v6_0_ring_emit_fence x2 vm fence */
1552         .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
1553         .emit_ib = uvd_v6_0_ring_emit_ib,
1554         .emit_fence = uvd_v6_0_ring_emit_fence,
1555         .emit_vm_flush = uvd_v6_0_ring_emit_vm_flush,
1556         .emit_pipeline_sync = uvd_v6_0_ring_emit_pipeline_sync,
1557         .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
1558         .emit_hdp_invalidate = uvd_v6_0_ring_emit_hdp_invalidate,
1559         .test_ring = uvd_v6_0_ring_test_ring,
1560         .test_ib = amdgpu_uvd_ring_test_ib,
1561         .insert_nop = amdgpu_ring_insert_nop,
1562         .pad_ib = amdgpu_ring_generic_pad_ib,
1563         .begin_use = amdgpu_uvd_ring_begin_use,
1564         .end_use = amdgpu_uvd_ring_end_use,
1565 };
1566
1567 static const struct amdgpu_ring_funcs uvd_v6_0_enc_ring_vm_funcs = {
1568         .type = AMDGPU_RING_TYPE_UVD_ENC,
1569         .align_mask = 0x3f,
1570         .nop = HEVC_ENC_CMD_NO_OP,
1571         .support_64bit_ptrs = false,
1572         .get_rptr = uvd_v6_0_enc_ring_get_rptr,
1573         .get_wptr = uvd_v6_0_enc_ring_get_wptr,
1574         .set_wptr = uvd_v6_0_enc_ring_set_wptr,
1575         .emit_frame_size =
1576                 4 + /* uvd_v6_0_enc_ring_emit_pipeline_sync */
1577                 6 + /* uvd_v6_0_enc_ring_emit_vm_flush */
1578                 5 + 5 + /* uvd_v6_0_enc_ring_emit_fence x2 vm fence */
1579                 1, /* uvd_v6_0_enc_ring_insert_end */
1580         .emit_ib_size = 5, /* uvd_v6_0_enc_ring_emit_ib */
1581         .emit_ib = uvd_v6_0_enc_ring_emit_ib,
1582         .emit_fence = uvd_v6_0_enc_ring_emit_fence,
1583         .emit_vm_flush = uvd_v6_0_enc_ring_emit_vm_flush,
1584         .emit_pipeline_sync = uvd_v6_0_enc_ring_emit_pipeline_sync,
1585         .test_ring = uvd_v6_0_enc_ring_test_ring,
1586         .test_ib = uvd_v6_0_enc_ring_test_ib,
1587         .insert_nop = amdgpu_ring_insert_nop,
1588         .insert_end = uvd_v6_0_enc_ring_insert_end,
1589         .pad_ib = amdgpu_ring_generic_pad_ib,
1590         .begin_use = amdgpu_uvd_ring_begin_use,
1591         .end_use = amdgpu_uvd_ring_end_use,
1592 };
1593
1594 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev)
1595 {
1596         if (adev->asic_type >= CHIP_POLARIS10) {
1597                 adev->uvd.ring.funcs = &uvd_v6_0_ring_vm_funcs;
1598                 DRM_INFO("UVD is enabled in VM mode\n");
1599         } else {
1600                 adev->uvd.ring.funcs = &uvd_v6_0_ring_phys_funcs;
1601                 DRM_INFO("UVD is enabled in physical mode\n");
1602         }
1603 }
1604
1605 static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev)
1606 {
1607         int i;
1608
1609         for (i = 0; i < adev->uvd.num_enc_rings; ++i)
1610                 adev->uvd.ring_enc[i].funcs = &uvd_v6_0_enc_ring_vm_funcs;
1611
1612         DRM_INFO("UVD ENC is enabled in VM mode\n");
1613 }
1614
1615 static const struct amdgpu_irq_src_funcs uvd_v6_0_irq_funcs = {
1616         .set = uvd_v6_0_set_interrupt_state,
1617         .process = uvd_v6_0_process_interrupt,
1618 };
1619
1620 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1621 {
1622         adev->uvd.irq.num_types = 1;
1623         adev->uvd.irq.funcs = &uvd_v6_0_irq_funcs;
1624 }
1625
1626 const struct amdgpu_ip_block_version uvd_v6_0_ip_block =
1627 {
1628                 .type = AMD_IP_BLOCK_TYPE_UVD,
1629                 .major = 6,
1630                 .minor = 0,
1631                 .rev = 0,
1632                 .funcs = &uvd_v6_0_ip_funcs,
1633 };
1634
1635 const struct amdgpu_ip_block_version uvd_v6_2_ip_block =
1636 {
1637                 .type = AMD_IP_BLOCK_TYPE_UVD,
1638                 .major = 6,
1639                 .minor = 2,
1640                 .rev = 0,
1641                 .funcs = &uvd_v6_0_ip_funcs,
1642 };
1643
1644 const struct amdgpu_ip_block_version uvd_v6_3_ip_block =
1645 {
1646                 .type = AMD_IP_BLOCK_TYPE_UVD,
1647                 .major = 6,
1648                 .minor = 3,
1649                 .rev = 0,
1650                 .funcs = &uvd_v6_0_ip_funcs,
1651 };