drm/amdgpu: add uvd enc into run queue
[muen/linux.git] / drivers / gpu / drm / amd / amdgpu / uvd_v6_0.c
1 /*
2  * Copyright 2014 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Christian K├Ânig <christian.koenig@amd.com>
23  */
24
25 #include <linux/firmware.h>
26 #include <drm/drmP.h>
27 #include "amdgpu.h"
28 #include "amdgpu_uvd.h"
29 #include "vid.h"
30 #include "uvd/uvd_6_0_d.h"
31 #include "uvd/uvd_6_0_sh_mask.h"
32 #include "oss/oss_2_0_d.h"
33 #include "oss/oss_2_0_sh_mask.h"
34 #include "smu/smu_7_1_3_d.h"
35 #include "smu/smu_7_1_3_sh_mask.h"
36 #include "bif/bif_5_1_d.h"
37 #include "gmc/gmc_8_1_d.h"
38 #include "vi.h"
39
40 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev);
41 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev);
42 static int uvd_v6_0_start(struct amdgpu_device *adev);
43 static void uvd_v6_0_stop(struct amdgpu_device *adev);
44 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev);
45 static int uvd_v6_0_set_clockgating_state(void *handle,
46                                           enum amd_clockgating_state state);
47 static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
48                                  bool enable);
49
50 /**
51 * uvd_v6_0_enc_support - get encode support status
52 *
53 * @adev: amdgpu_device pointer
54 *
55 * Returns the current hardware encode support status
56 */
57 static inline bool uvd_v6_0_enc_support(struct amdgpu_device *adev)
58 {
59         return ((adev->asic_type >= CHIP_POLARIS10) && (adev->asic_type <= CHIP_POLARIS12));
60 }
61
62 /**
63  * uvd_v6_0_ring_get_rptr - get read pointer
64  *
65  * @ring: amdgpu_ring pointer
66  *
67  * Returns the current hardware read pointer
68  */
69 static uint64_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
70 {
71         struct amdgpu_device *adev = ring->adev;
72
73         return RREG32(mmUVD_RBC_RB_RPTR);
74 }
75
76 /**
77  * uvd_v6_0_enc_ring_get_rptr - get enc read pointer
78  *
79  * @ring: amdgpu_ring pointer
80  *
81  * Returns the current hardware enc read pointer
82  */
83 static uint64_t uvd_v6_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
84 {
85         struct amdgpu_device *adev = ring->adev;
86
87         if (ring == &adev->uvd.ring_enc[0])
88                 return RREG32(mmUVD_RB_RPTR);
89         else
90                 return RREG32(mmUVD_RB_RPTR2);
91 }
92 /**
93  * uvd_v6_0_ring_get_wptr - get write pointer
94  *
95  * @ring: amdgpu_ring pointer
96  *
97  * Returns the current hardware write pointer
98  */
99 static uint64_t uvd_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
100 {
101         struct amdgpu_device *adev = ring->adev;
102
103         return RREG32(mmUVD_RBC_RB_WPTR);
104 }
105
106 /**
107  * uvd_v6_0_enc_ring_get_wptr - get enc write pointer
108  *
109  * @ring: amdgpu_ring pointer
110  *
111  * Returns the current hardware enc write pointer
112  */
113 static uint64_t uvd_v6_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
114 {
115         struct amdgpu_device *adev = ring->adev;
116
117         if (ring == &adev->uvd.ring_enc[0])
118                 return RREG32(mmUVD_RB_WPTR);
119         else
120                 return RREG32(mmUVD_RB_WPTR2);
121 }
122
123 /**
124  * uvd_v6_0_ring_set_wptr - set write pointer
125  *
126  * @ring: amdgpu_ring pointer
127  *
128  * Commits the write pointer to the hardware
129  */
130 static void uvd_v6_0_ring_set_wptr(struct amdgpu_ring *ring)
131 {
132         struct amdgpu_device *adev = ring->adev;
133
134         WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
135 }
136
137 /**
138  * uvd_v6_0_enc_ring_set_wptr - set enc write pointer
139  *
140  * @ring: amdgpu_ring pointer
141  *
142  * Commits the enc write pointer to the hardware
143  */
144 static void uvd_v6_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
145 {
146         struct amdgpu_device *adev = ring->adev;
147
148         if (ring == &adev->uvd.ring_enc[0])
149                 WREG32(mmUVD_RB_WPTR,
150                         lower_32_bits(ring->wptr));
151         else
152                 WREG32(mmUVD_RB_WPTR2,
153                         lower_32_bits(ring->wptr));
154 }
155
156 static int uvd_v6_0_early_init(void *handle)
157 {
158         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
159
160         uvd_v6_0_set_ring_funcs(adev);
161
162         if (uvd_v6_0_enc_support(adev)) {
163                 adev->uvd.num_enc_rings = 2;
164         }
165
166         uvd_v6_0_set_irq_funcs(adev);
167
168         return 0;
169 }
170
171 static int uvd_v6_0_sw_init(void *handle)
172 {
173         struct amdgpu_ring *ring;
174         int i, r;
175         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
176
177         /* UVD TRAP */
178         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.irq);
179         if (r)
180                 return r;
181
182         r = amdgpu_uvd_sw_init(adev);
183         if (r)
184                 return r;
185
186         if (uvd_v6_0_enc_support(adev)) {
187                 struct amd_sched_rq *rq;
188                 ring = &adev->uvd.ring_enc[0];
189                 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
190                 r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity_enc,
191                                           rq, amdgpu_sched_jobs);
192                 if (r) {
193                         DRM_ERROR("Failed setting up UVD ENC run queue.\n");
194                         return r;
195                 }
196         }
197
198         r = amdgpu_uvd_resume(adev);
199         if (r)
200                 return r;
201
202         ring = &adev->uvd.ring;
203         sprintf(ring->name, "uvd");
204         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
205         if (r)
206                 return r;
207
208         if (uvd_v6_0_enc_support(adev)) {
209                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
210                         ring = &adev->uvd.ring_enc[i];
211                         sprintf(ring->name, "uvd_enc%d", i);
212                         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
213                         if (r)
214                                 return r;
215                 }
216         }
217
218         return r;
219 }
220
221 static int uvd_v6_0_sw_fini(void *handle)
222 {
223         int i, r;
224         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
225
226         r = amdgpu_uvd_suspend(adev);
227         if (r)
228                 return r;
229
230         if (uvd_v6_0_enc_support(adev)) {
231                 amd_sched_entity_fini(&adev->uvd.ring_enc[0].sched, &adev->uvd.entity_enc);
232
233                 for (i = 0; i < adev->uvd.num_enc_rings; ++i)
234                         amdgpu_ring_fini(&adev->uvd.ring_enc[i]);
235         }
236
237         return amdgpu_uvd_sw_fini(adev);
238 }
239
240 /**
241  * uvd_v6_0_hw_init - start and test UVD block
242  *
243  * @adev: amdgpu_device pointer
244  *
245  * Initialize the hardware, boot up the VCPU and do some testing
246  */
247 static int uvd_v6_0_hw_init(void *handle)
248 {
249         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
250         struct amdgpu_ring *ring = &adev->uvd.ring;
251         uint32_t tmp;
252         int r;
253
254         amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
255         uvd_v6_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
256         uvd_v6_0_enable_mgcg(adev, true);
257
258         ring->ready = true;
259         r = amdgpu_ring_test_ring(ring);
260         if (r) {
261                 ring->ready = false;
262                 goto done;
263         }
264
265         r = amdgpu_ring_alloc(ring, 10);
266         if (r) {
267                 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
268                 goto done;
269         }
270
271         tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
272         amdgpu_ring_write(ring, tmp);
273         amdgpu_ring_write(ring, 0xFFFFF);
274
275         tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
276         amdgpu_ring_write(ring, tmp);
277         amdgpu_ring_write(ring, 0xFFFFF);
278
279         tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
280         amdgpu_ring_write(ring, tmp);
281         amdgpu_ring_write(ring, 0xFFFFF);
282
283         /* Clear timeout status bits */
284         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
285         amdgpu_ring_write(ring, 0x8);
286
287         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
288         amdgpu_ring_write(ring, 3);
289
290         amdgpu_ring_commit(ring);
291
292 done:
293         if (!r)
294                 DRM_INFO("UVD initialized successfully.\n");
295
296         return r;
297 }
298
299 /**
300  * uvd_v6_0_hw_fini - stop the hardware block
301  *
302  * @adev: amdgpu_device pointer
303  *
304  * Stop the UVD block, mark ring as not ready any more
305  */
306 static int uvd_v6_0_hw_fini(void *handle)
307 {
308         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
309         struct amdgpu_ring *ring = &adev->uvd.ring;
310
311         if (RREG32(mmUVD_STATUS) != 0)
312                 uvd_v6_0_stop(adev);
313
314         ring->ready = false;
315
316         return 0;
317 }
318
319 static int uvd_v6_0_suspend(void *handle)
320 {
321         int r;
322         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
323
324         r = uvd_v6_0_hw_fini(adev);
325         if (r)
326                 return r;
327
328         /* Skip this for APU for now */
329         if (!(adev->flags & AMD_IS_APU))
330                 r = amdgpu_uvd_suspend(adev);
331
332         return r;
333 }
334
335 static int uvd_v6_0_resume(void *handle)
336 {
337         int r;
338         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
339
340         /* Skip this for APU for now */
341         if (!(adev->flags & AMD_IS_APU)) {
342                 r = amdgpu_uvd_resume(adev);
343                 if (r)
344                         return r;
345         }
346         return uvd_v6_0_hw_init(adev);
347 }
348
349 /**
350  * uvd_v6_0_mc_resume - memory controller programming
351  *
352  * @adev: amdgpu_device pointer
353  *
354  * Let the UVD memory controller know it's offsets
355  */
356 static void uvd_v6_0_mc_resume(struct amdgpu_device *adev)
357 {
358         uint64_t offset;
359         uint32_t size;
360
361         /* programm memory controller bits 0-27 */
362         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
363                         lower_32_bits(adev->uvd.gpu_addr));
364         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
365                         upper_32_bits(adev->uvd.gpu_addr));
366
367         offset = AMDGPU_UVD_FIRMWARE_OFFSET;
368         size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
369         WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
370         WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
371
372         offset += size;
373         size = AMDGPU_UVD_HEAP_SIZE;
374         WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
375         WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
376
377         offset += size;
378         size = AMDGPU_UVD_STACK_SIZE +
379                (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles);
380         WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
381         WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
382
383         WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
384         WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
385         WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
386
387         WREG32(mmUVD_GP_SCRATCH4, adev->uvd.max_handles);
388 }
389
390 #if 0
391 static void cz_set_uvd_clock_gating_branches(struct amdgpu_device *adev,
392                 bool enable)
393 {
394         u32 data, data1;
395
396         data = RREG32(mmUVD_CGC_GATE);
397         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
398         if (enable) {
399                 data |= UVD_CGC_GATE__SYS_MASK |
400                                 UVD_CGC_GATE__UDEC_MASK |
401                                 UVD_CGC_GATE__MPEG2_MASK |
402                                 UVD_CGC_GATE__RBC_MASK |
403                                 UVD_CGC_GATE__LMI_MC_MASK |
404                                 UVD_CGC_GATE__IDCT_MASK |
405                                 UVD_CGC_GATE__MPRD_MASK |
406                                 UVD_CGC_GATE__MPC_MASK |
407                                 UVD_CGC_GATE__LBSI_MASK |
408                                 UVD_CGC_GATE__LRBBM_MASK |
409                                 UVD_CGC_GATE__UDEC_RE_MASK |
410                                 UVD_CGC_GATE__UDEC_CM_MASK |
411                                 UVD_CGC_GATE__UDEC_IT_MASK |
412                                 UVD_CGC_GATE__UDEC_DB_MASK |
413                                 UVD_CGC_GATE__UDEC_MP_MASK |
414                                 UVD_CGC_GATE__WCB_MASK |
415                                 UVD_CGC_GATE__VCPU_MASK |
416                                 UVD_CGC_GATE__SCPU_MASK;
417                 data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
418                                 UVD_SUVD_CGC_GATE__SIT_MASK |
419                                 UVD_SUVD_CGC_GATE__SMP_MASK |
420                                 UVD_SUVD_CGC_GATE__SCM_MASK |
421                                 UVD_SUVD_CGC_GATE__SDB_MASK |
422                                 UVD_SUVD_CGC_GATE__SRE_H264_MASK |
423                                 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
424                                 UVD_SUVD_CGC_GATE__SIT_H264_MASK |
425                                 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
426                                 UVD_SUVD_CGC_GATE__SCM_H264_MASK |
427                                 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
428                                 UVD_SUVD_CGC_GATE__SDB_H264_MASK |
429                                 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK;
430         } else {
431                 data &= ~(UVD_CGC_GATE__SYS_MASK |
432                                 UVD_CGC_GATE__UDEC_MASK |
433                                 UVD_CGC_GATE__MPEG2_MASK |
434                                 UVD_CGC_GATE__RBC_MASK |
435                                 UVD_CGC_GATE__LMI_MC_MASK |
436                                 UVD_CGC_GATE__LMI_UMC_MASK |
437                                 UVD_CGC_GATE__IDCT_MASK |
438                                 UVD_CGC_GATE__MPRD_MASK |
439                                 UVD_CGC_GATE__MPC_MASK |
440                                 UVD_CGC_GATE__LBSI_MASK |
441                                 UVD_CGC_GATE__LRBBM_MASK |
442                                 UVD_CGC_GATE__UDEC_RE_MASK |
443                                 UVD_CGC_GATE__UDEC_CM_MASK |
444                                 UVD_CGC_GATE__UDEC_IT_MASK |
445                                 UVD_CGC_GATE__UDEC_DB_MASK |
446                                 UVD_CGC_GATE__UDEC_MP_MASK |
447                                 UVD_CGC_GATE__WCB_MASK |
448                                 UVD_CGC_GATE__VCPU_MASK |
449                                 UVD_CGC_GATE__SCPU_MASK);
450                 data1 &= ~(UVD_SUVD_CGC_GATE__SRE_MASK |
451                                 UVD_SUVD_CGC_GATE__SIT_MASK |
452                                 UVD_SUVD_CGC_GATE__SMP_MASK |
453                                 UVD_SUVD_CGC_GATE__SCM_MASK |
454                                 UVD_SUVD_CGC_GATE__SDB_MASK |
455                                 UVD_SUVD_CGC_GATE__SRE_H264_MASK |
456                                 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
457                                 UVD_SUVD_CGC_GATE__SIT_H264_MASK |
458                                 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
459                                 UVD_SUVD_CGC_GATE__SCM_H264_MASK |
460                                 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
461                                 UVD_SUVD_CGC_GATE__SDB_H264_MASK |
462                                 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK);
463         }
464         WREG32(mmUVD_CGC_GATE, data);
465         WREG32(mmUVD_SUVD_CGC_GATE, data1);
466 }
467 #endif
468
469 /**
470  * uvd_v6_0_start - start UVD block
471  *
472  * @adev: amdgpu_device pointer
473  *
474  * Setup and start the UVD block
475  */
476 static int uvd_v6_0_start(struct amdgpu_device *adev)
477 {
478         struct amdgpu_ring *ring = &adev->uvd.ring;
479         uint32_t rb_bufsz, tmp;
480         uint32_t lmi_swap_cntl;
481         uint32_t mp_swap_cntl;
482         int i, j, r;
483
484         /* disable DPG */
485         WREG32_P(mmUVD_POWER_STATUS, 0, ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
486
487         /* disable byte swapping */
488         lmi_swap_cntl = 0;
489         mp_swap_cntl = 0;
490
491         uvd_v6_0_mc_resume(adev);
492
493         /* disable interupt */
494         WREG32_FIELD(UVD_MASTINT_EN, VCPU_EN, 0);
495
496         /* stall UMC and register bus before resetting VCPU */
497         WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 1);
498         mdelay(1);
499
500         /* put LMI, VCPU, RBC etc... into reset */
501         WREG32(mmUVD_SOFT_RESET,
502                 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
503                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
504                 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
505                 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
506                 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
507                 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
508                 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
509                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
510         mdelay(5);
511
512         /* take UVD block out of reset */
513         WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_UVD, 0);
514         mdelay(5);
515
516         /* initialize UVD memory controller */
517         WREG32(mmUVD_LMI_CTRL,
518                 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
519                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
520                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
521                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
522                 UVD_LMI_CTRL__REQ_MODE_MASK |
523                 UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK);
524
525 #ifdef __BIG_ENDIAN
526         /* swap (8 in 32) RB and IB */
527         lmi_swap_cntl = 0xa;
528         mp_swap_cntl = 0;
529 #endif
530         WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
531         WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
532
533         WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
534         WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
535         WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
536         WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
537         WREG32(mmUVD_MPC_SET_ALU, 0);
538         WREG32(mmUVD_MPC_SET_MUX, 0x88);
539
540         /* take all subblocks out of reset, except VCPU */
541         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
542         mdelay(5);
543
544         /* enable VCPU clock */
545         WREG32(mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
546
547         /* enable UMC */
548         WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 0);
549
550         /* boot up the VCPU */
551         WREG32(mmUVD_SOFT_RESET, 0);
552         mdelay(10);
553
554         for (i = 0; i < 10; ++i) {
555                 uint32_t status;
556
557                 for (j = 0; j < 100; ++j) {
558                         status = RREG32(mmUVD_STATUS);
559                         if (status & 2)
560                                 break;
561                         mdelay(10);
562                 }
563                 r = 0;
564                 if (status & 2)
565                         break;
566
567                 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
568                 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 1);
569                 mdelay(10);
570                 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 0);
571                 mdelay(10);
572                 r = -1;
573         }
574
575         if (r) {
576                 DRM_ERROR("UVD not responding, giving up!!!\n");
577                 return r;
578         }
579         /* enable master interrupt */
580         WREG32_P(mmUVD_MASTINT_EN,
581                 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
582                 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
583
584         /* clear the bit 4 of UVD_STATUS */
585         WREG32_P(mmUVD_STATUS, 0, ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
586
587         /* force RBC into idle state */
588         rb_bufsz = order_base_2(ring->ring_size);
589         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
590         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
591         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
592         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
593         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
594         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
595         WREG32(mmUVD_RBC_RB_CNTL, tmp);
596
597         /* set the write pointer delay */
598         WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
599
600         /* set the wb address */
601         WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));
602
603         /* programm the RB_BASE for ring buffer */
604         WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
605                         lower_32_bits(ring->gpu_addr));
606         WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
607                         upper_32_bits(ring->gpu_addr));
608
609         /* Initialize the ring buffer's read and write pointers */
610         WREG32(mmUVD_RBC_RB_RPTR, 0);
611
612         ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
613         WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
614
615         WREG32_FIELD(UVD_RBC_RB_CNTL, RB_NO_FETCH, 0);
616
617         if (uvd_v6_0_enc_support(adev)) {
618                 ring = &adev->uvd.ring_enc[0];
619                 WREG32(mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
620                 WREG32(mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
621                 WREG32(mmUVD_RB_BASE_LO, ring->gpu_addr);
622                 WREG32(mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
623                 WREG32(mmUVD_RB_SIZE, ring->ring_size / 4);
624
625                 ring = &adev->uvd.ring_enc[1];
626                 WREG32(mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
627                 WREG32(mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
628                 WREG32(mmUVD_RB_BASE_LO2, ring->gpu_addr);
629                 WREG32(mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
630                 WREG32(mmUVD_RB_SIZE2, ring->ring_size / 4);
631         }
632
633         return 0;
634 }
635
636 /**
637  * uvd_v6_0_stop - stop UVD block
638  *
639  * @adev: amdgpu_device pointer
640  *
641  * stop the UVD block
642  */
643 static void uvd_v6_0_stop(struct amdgpu_device *adev)
644 {
645         /* force RBC into idle state */
646         WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
647
648         /* Stall UMC and register bus before resetting VCPU */
649         WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
650         mdelay(1);
651
652         /* put VCPU into reset */
653         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
654         mdelay(5);
655
656         /* disable VCPU clock */
657         WREG32(mmUVD_VCPU_CNTL, 0x0);
658
659         /* Unstall UMC and register bus */
660         WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
661
662         WREG32(mmUVD_STATUS, 0);
663 }
664
665 /**
666  * uvd_v6_0_ring_emit_fence - emit an fence & trap command
667  *
668  * @ring: amdgpu_ring pointer
669  * @fence: fence to emit
670  *
671  * Write a fence and a trap command to the ring.
672  */
673 static void uvd_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
674                                      unsigned flags)
675 {
676         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
677
678         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
679         amdgpu_ring_write(ring, seq);
680         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
681         amdgpu_ring_write(ring, addr & 0xffffffff);
682         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
683         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
684         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
685         amdgpu_ring_write(ring, 0);
686
687         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
688         amdgpu_ring_write(ring, 0);
689         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
690         amdgpu_ring_write(ring, 0);
691         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
692         amdgpu_ring_write(ring, 2);
693 }
694
695 /**
696  * uvd_v6_0_enc_ring_emit_fence - emit an enc fence & trap command
697  *
698  * @ring: amdgpu_ring pointer
699  * @fence: fence to emit
700  *
701  * Write enc a fence and a trap command to the ring.
702  */
703 static void uvd_v6_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
704                         u64 seq, unsigned flags)
705 {
706         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
707
708         amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE);
709         amdgpu_ring_write(ring, addr);
710         amdgpu_ring_write(ring, upper_32_bits(addr));
711         amdgpu_ring_write(ring, seq);
712         amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
713 }
714
715 /**
716  * uvd_v6_0_ring_emit_hdp_flush - emit an hdp flush
717  *
718  * @ring: amdgpu_ring pointer
719  *
720  * Emits an hdp flush.
721  */
722 static void uvd_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
723 {
724         amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0));
725         amdgpu_ring_write(ring, 0);
726 }
727
728 /**
729  * uvd_v6_0_ring_hdp_invalidate - emit an hdp invalidate
730  *
731  * @ring: amdgpu_ring pointer
732  *
733  * Emits an hdp invalidate.
734  */
735 static void uvd_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
736 {
737         amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0));
738         amdgpu_ring_write(ring, 1);
739 }
740
741 /**
742  * uvd_v6_0_ring_test_ring - register write test
743  *
744  * @ring: amdgpu_ring pointer
745  *
746  * Test if we can successfully write to the context register
747  */
748 static int uvd_v6_0_ring_test_ring(struct amdgpu_ring *ring)
749 {
750         struct amdgpu_device *adev = ring->adev;
751         uint32_t tmp = 0;
752         unsigned i;
753         int r;
754
755         WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
756         r = amdgpu_ring_alloc(ring, 3);
757         if (r) {
758                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
759                           ring->idx, r);
760                 return r;
761         }
762         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
763         amdgpu_ring_write(ring, 0xDEADBEEF);
764         amdgpu_ring_commit(ring);
765         for (i = 0; i < adev->usec_timeout; i++) {
766                 tmp = RREG32(mmUVD_CONTEXT_ID);
767                 if (tmp == 0xDEADBEEF)
768                         break;
769                 DRM_UDELAY(1);
770         }
771
772         if (i < adev->usec_timeout) {
773                 DRM_INFO("ring test on %d succeeded in %d usecs\n",
774                          ring->idx, i);
775         } else {
776                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
777                           ring->idx, tmp);
778                 r = -EINVAL;
779         }
780         return r;
781 }
782
783 /**
784  * uvd_v6_0_ring_emit_ib - execute indirect buffer
785  *
786  * @ring: amdgpu_ring pointer
787  * @ib: indirect buffer to execute
788  *
789  * Write ring commands to execute the indirect buffer
790  */
791 static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
792                                   struct amdgpu_ib *ib,
793                                   unsigned vm_id, bool ctx_switch)
794 {
795         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_VMID, 0));
796         amdgpu_ring_write(ring, vm_id);
797
798         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
799         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
800         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0));
801         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
802         amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
803         amdgpu_ring_write(ring, ib->length_dw);
804 }
805
806 /**
807  * uvd_v6_0_enc_ring_emit_ib - enc execute indirect buffer
808  *
809  * @ring: amdgpu_ring pointer
810  * @ib: indirect buffer to execute
811  *
812  * Write enc ring commands to execute the indirect buffer
813  */
814 static void uvd_v6_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
815                 struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch)
816 {
817         amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM);
818         amdgpu_ring_write(ring, vm_id);
819         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
820         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
821         amdgpu_ring_write(ring, ib->length_dw);
822 }
823
824 static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
825                                          unsigned vm_id, uint64_t pd_addr)
826 {
827         uint32_t reg;
828
829         if (vm_id < 8)
830                 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id;
831         else
832                 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8;
833
834         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
835         amdgpu_ring_write(ring, reg << 2);
836         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
837         amdgpu_ring_write(ring, pd_addr >> 12);
838         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
839         amdgpu_ring_write(ring, 0x8);
840
841         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
842         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
843         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
844         amdgpu_ring_write(ring, 1 << vm_id);
845         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
846         amdgpu_ring_write(ring, 0x8);
847
848         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
849         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
850         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
851         amdgpu_ring_write(ring, 0);
852         amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0));
853         amdgpu_ring_write(ring, 1 << vm_id); /* mask */
854         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
855         amdgpu_ring_write(ring, 0xC);
856 }
857
858 static void uvd_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
859 {
860         uint32_t seq = ring->fence_drv.sync_seq;
861         uint64_t addr = ring->fence_drv.gpu_addr;
862
863         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
864         amdgpu_ring_write(ring, lower_32_bits(addr));
865         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
866         amdgpu_ring_write(ring, upper_32_bits(addr));
867         amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0));
868         amdgpu_ring_write(ring, 0xffffffff); /* mask */
869         amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH9, 0));
870         amdgpu_ring_write(ring, seq);
871         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
872         amdgpu_ring_write(ring, 0xE);
873 }
874
875 static void uvd_v6_0_enc_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
876 {
877         uint32_t seq = ring->fence_drv.sync_seq;
878         uint64_t addr = ring->fence_drv.gpu_addr;
879
880         amdgpu_ring_write(ring, HEVC_ENC_CMD_WAIT_GE);
881         amdgpu_ring_write(ring, lower_32_bits(addr));
882         amdgpu_ring_write(ring, upper_32_bits(addr));
883         amdgpu_ring_write(ring, seq);
884 }
885
886 static void uvd_v6_0_enc_ring_insert_end(struct amdgpu_ring *ring)
887 {
888         amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
889 }
890
891 static void uvd_v6_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
892         unsigned int vm_id, uint64_t pd_addr)
893 {
894         amdgpu_ring_write(ring, HEVC_ENC_CMD_UPDATE_PTB);
895         amdgpu_ring_write(ring, vm_id);
896         amdgpu_ring_write(ring, pd_addr >> 12);
897
898         amdgpu_ring_write(ring, HEVC_ENC_CMD_FLUSH_TLB);
899         amdgpu_ring_write(ring, vm_id);
900 }
901
902 static bool uvd_v6_0_is_idle(void *handle)
903 {
904         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
905
906         return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
907 }
908
909 static int uvd_v6_0_wait_for_idle(void *handle)
910 {
911         unsigned i;
912         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
913
914         for (i = 0; i < adev->usec_timeout; i++) {
915                 if (uvd_v6_0_is_idle(handle))
916                         return 0;
917         }
918         return -ETIMEDOUT;
919 }
920
921 #define AMDGPU_UVD_STATUS_BUSY_MASK    0xfd
922 static bool uvd_v6_0_check_soft_reset(void *handle)
923 {
924         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
925         u32 srbm_soft_reset = 0;
926         u32 tmp = RREG32(mmSRBM_STATUS);
927
928         if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) ||
929             REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) ||
930             (RREG32(mmUVD_STATUS) & AMDGPU_UVD_STATUS_BUSY_MASK))
931                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
932
933         if (srbm_soft_reset) {
934                 adev->uvd.srbm_soft_reset = srbm_soft_reset;
935                 return true;
936         } else {
937                 adev->uvd.srbm_soft_reset = 0;
938                 return false;
939         }
940 }
941
942 static int uvd_v6_0_pre_soft_reset(void *handle)
943 {
944         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
945
946         if (!adev->uvd.srbm_soft_reset)
947                 return 0;
948
949         uvd_v6_0_stop(adev);
950         return 0;
951 }
952
953 static int uvd_v6_0_soft_reset(void *handle)
954 {
955         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
956         u32 srbm_soft_reset;
957
958         if (!adev->uvd.srbm_soft_reset)
959                 return 0;
960         srbm_soft_reset = adev->uvd.srbm_soft_reset;
961
962         if (srbm_soft_reset) {
963                 u32 tmp;
964
965                 tmp = RREG32(mmSRBM_SOFT_RESET);
966                 tmp |= srbm_soft_reset;
967                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
968                 WREG32(mmSRBM_SOFT_RESET, tmp);
969                 tmp = RREG32(mmSRBM_SOFT_RESET);
970
971                 udelay(50);
972
973                 tmp &= ~srbm_soft_reset;
974                 WREG32(mmSRBM_SOFT_RESET, tmp);
975                 tmp = RREG32(mmSRBM_SOFT_RESET);
976
977                 /* Wait a little for things to settle down */
978                 udelay(50);
979         }
980
981         return 0;
982 }
983
984 static int uvd_v6_0_post_soft_reset(void *handle)
985 {
986         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
987
988         if (!adev->uvd.srbm_soft_reset)
989                 return 0;
990
991         mdelay(5);
992
993         return uvd_v6_0_start(adev);
994 }
995
996 static int uvd_v6_0_set_interrupt_state(struct amdgpu_device *adev,
997                                         struct amdgpu_irq_src *source,
998                                         unsigned type,
999                                         enum amdgpu_interrupt_state state)
1000 {
1001         // TODO
1002         return 0;
1003 }
1004
1005 static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev,
1006                                       struct amdgpu_irq_src *source,
1007                                       struct amdgpu_iv_entry *entry)
1008 {
1009         DRM_DEBUG("IH: UVD TRAP\n");
1010         amdgpu_fence_process(&adev->uvd.ring);
1011         return 0;
1012 }
1013
1014 static void uvd_v6_0_enable_clock_gating(struct amdgpu_device *adev, bool enable)
1015 {
1016         uint32_t data1, data3;
1017
1018         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
1019         data3 = RREG32(mmUVD_CGC_GATE);
1020
1021         data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
1022                      UVD_SUVD_CGC_GATE__SIT_MASK |
1023                      UVD_SUVD_CGC_GATE__SMP_MASK |
1024                      UVD_SUVD_CGC_GATE__SCM_MASK |
1025                      UVD_SUVD_CGC_GATE__SDB_MASK |
1026                      UVD_SUVD_CGC_GATE__SRE_H264_MASK |
1027                      UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
1028                      UVD_SUVD_CGC_GATE__SIT_H264_MASK |
1029                      UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
1030                      UVD_SUVD_CGC_GATE__SCM_H264_MASK |
1031                      UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
1032                      UVD_SUVD_CGC_GATE__SDB_H264_MASK |
1033                      UVD_SUVD_CGC_GATE__SDB_HEVC_MASK;
1034
1035         if (enable) {
1036                 data3 |= (UVD_CGC_GATE__SYS_MASK       |
1037                         UVD_CGC_GATE__UDEC_MASK      |
1038                         UVD_CGC_GATE__MPEG2_MASK     |
1039                         UVD_CGC_GATE__RBC_MASK       |
1040                         UVD_CGC_GATE__LMI_MC_MASK    |
1041                         UVD_CGC_GATE__LMI_UMC_MASK   |
1042                         UVD_CGC_GATE__IDCT_MASK      |
1043                         UVD_CGC_GATE__MPRD_MASK      |
1044                         UVD_CGC_GATE__MPC_MASK       |
1045                         UVD_CGC_GATE__LBSI_MASK      |
1046                         UVD_CGC_GATE__LRBBM_MASK     |
1047                         UVD_CGC_GATE__UDEC_RE_MASK   |
1048                         UVD_CGC_GATE__UDEC_CM_MASK   |
1049                         UVD_CGC_GATE__UDEC_IT_MASK   |
1050                         UVD_CGC_GATE__UDEC_DB_MASK   |
1051                         UVD_CGC_GATE__UDEC_MP_MASK   |
1052                         UVD_CGC_GATE__WCB_MASK       |
1053                         UVD_CGC_GATE__JPEG_MASK      |
1054                         UVD_CGC_GATE__SCPU_MASK      |
1055                         UVD_CGC_GATE__JPEG2_MASK);
1056                 /* only in pg enabled, we can gate clock to vcpu*/
1057                 if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
1058                         data3 |= UVD_CGC_GATE__VCPU_MASK;
1059
1060                 data3 &= ~UVD_CGC_GATE__REGS_MASK;
1061         } else {
1062                 data3 = 0;
1063         }
1064
1065         WREG32(mmUVD_SUVD_CGC_GATE, data1);
1066         WREG32(mmUVD_CGC_GATE, data3);
1067 }
1068
1069 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev)
1070 {
1071         uint32_t data, data2;
1072
1073         data = RREG32(mmUVD_CGC_CTRL);
1074         data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
1075
1076
1077         data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
1078                   UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
1079
1080
1081         data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
1082                 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
1083                 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
1084
1085         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
1086                         UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
1087                         UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
1088                         UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
1089                         UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
1090                         UVD_CGC_CTRL__SYS_MODE_MASK |
1091                         UVD_CGC_CTRL__UDEC_MODE_MASK |
1092                         UVD_CGC_CTRL__MPEG2_MODE_MASK |
1093                         UVD_CGC_CTRL__REGS_MODE_MASK |
1094                         UVD_CGC_CTRL__RBC_MODE_MASK |
1095                         UVD_CGC_CTRL__LMI_MC_MODE_MASK |
1096                         UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
1097                         UVD_CGC_CTRL__IDCT_MODE_MASK |
1098                         UVD_CGC_CTRL__MPRD_MODE_MASK |
1099                         UVD_CGC_CTRL__MPC_MODE_MASK |
1100                         UVD_CGC_CTRL__LBSI_MODE_MASK |
1101                         UVD_CGC_CTRL__LRBBM_MODE_MASK |
1102                         UVD_CGC_CTRL__WCB_MODE_MASK |
1103                         UVD_CGC_CTRL__VCPU_MODE_MASK |
1104                         UVD_CGC_CTRL__JPEG_MODE_MASK |
1105                         UVD_CGC_CTRL__SCPU_MODE_MASK |
1106                         UVD_CGC_CTRL__JPEG2_MODE_MASK);
1107         data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
1108                         UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
1109                         UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
1110                         UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
1111                         UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
1112
1113         WREG32(mmUVD_CGC_CTRL, data);
1114         WREG32(mmUVD_SUVD_CGC_CTRL, data2);
1115 }
1116
1117 #if 0
1118 static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev)
1119 {
1120         uint32_t data, data1, cgc_flags, suvd_flags;
1121
1122         data = RREG32(mmUVD_CGC_GATE);
1123         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
1124
1125         cgc_flags = UVD_CGC_GATE__SYS_MASK |
1126                 UVD_CGC_GATE__UDEC_MASK |
1127                 UVD_CGC_GATE__MPEG2_MASK |
1128                 UVD_CGC_GATE__RBC_MASK |
1129                 UVD_CGC_GATE__LMI_MC_MASK |
1130                 UVD_CGC_GATE__IDCT_MASK |
1131                 UVD_CGC_GATE__MPRD_MASK |
1132                 UVD_CGC_GATE__MPC_MASK |
1133                 UVD_CGC_GATE__LBSI_MASK |
1134                 UVD_CGC_GATE__LRBBM_MASK |
1135                 UVD_CGC_GATE__UDEC_RE_MASK |
1136                 UVD_CGC_GATE__UDEC_CM_MASK |
1137                 UVD_CGC_GATE__UDEC_IT_MASK |
1138                 UVD_CGC_GATE__UDEC_DB_MASK |
1139                 UVD_CGC_GATE__UDEC_MP_MASK |
1140                 UVD_CGC_GATE__WCB_MASK |
1141                 UVD_CGC_GATE__VCPU_MASK |
1142                 UVD_CGC_GATE__SCPU_MASK |
1143                 UVD_CGC_GATE__JPEG_MASK |
1144                 UVD_CGC_GATE__JPEG2_MASK;
1145
1146         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1147                                 UVD_SUVD_CGC_GATE__SIT_MASK |
1148                                 UVD_SUVD_CGC_GATE__SMP_MASK |
1149                                 UVD_SUVD_CGC_GATE__SCM_MASK |
1150                                 UVD_SUVD_CGC_GATE__SDB_MASK;
1151
1152         data |= cgc_flags;
1153         data1 |= suvd_flags;
1154
1155         WREG32(mmUVD_CGC_GATE, data);
1156         WREG32(mmUVD_SUVD_CGC_GATE, data1);
1157 }
1158 #endif
1159
1160 static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
1161                                  bool enable)
1162 {
1163         u32 orig, data;
1164
1165         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
1166                 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
1167                 data |= 0xfff;
1168                 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
1169
1170                 orig = data = RREG32(mmUVD_CGC_CTRL);
1171                 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
1172                 if (orig != data)
1173                         WREG32(mmUVD_CGC_CTRL, data);
1174         } else {
1175                 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
1176                 data &= ~0xfff;
1177                 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
1178
1179                 orig = data = RREG32(mmUVD_CGC_CTRL);
1180                 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
1181                 if (orig != data)
1182                         WREG32(mmUVD_CGC_CTRL, data);
1183         }
1184 }
1185
1186 static int uvd_v6_0_set_clockgating_state(void *handle,
1187                                           enum amd_clockgating_state state)
1188 {
1189         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1190         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1191
1192         if (enable) {
1193                 /* wait for STATUS to clear */
1194                 if (uvd_v6_0_wait_for_idle(handle))
1195                         return -EBUSY;
1196                 uvd_v6_0_enable_clock_gating(adev, true);
1197                 /* enable HW gates because UVD is idle */
1198 /*              uvd_v6_0_set_hw_clock_gating(adev); */
1199         } else {
1200                 /* disable HW gating and enable Sw gating */
1201                 uvd_v6_0_enable_clock_gating(adev, false);
1202         }
1203         uvd_v6_0_set_sw_clock_gating(adev);
1204         return 0;
1205 }
1206
1207 static int uvd_v6_0_set_powergating_state(void *handle,
1208                                           enum amd_powergating_state state)
1209 {
1210         /* This doesn't actually powergate the UVD block.
1211          * That's done in the dpm code via the SMC.  This
1212          * just re-inits the block as necessary.  The actual
1213          * gating still happens in the dpm code.  We should
1214          * revisit this when there is a cleaner line between
1215          * the smc and the hw blocks
1216          */
1217         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1218         int ret = 0;
1219
1220         WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
1221
1222         if (state == AMD_PG_STATE_GATE) {
1223                 uvd_v6_0_stop(adev);
1224         } else {
1225                 ret = uvd_v6_0_start(adev);
1226                 if (ret)
1227                         goto out;
1228         }
1229
1230 out:
1231         return ret;
1232 }
1233
1234 static void uvd_v6_0_get_clockgating_state(void *handle, u32 *flags)
1235 {
1236         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1237         int data;
1238
1239         mutex_lock(&adev->pm.mutex);
1240
1241         if (adev->flags & AMD_IS_APU)
1242                 data = RREG32_SMC(ixCURRENT_PG_STATUS_APU);
1243         else
1244                 data = RREG32_SMC(ixCURRENT_PG_STATUS);
1245
1246         if (data & CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) {
1247                 DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
1248                 goto out;
1249         }
1250
1251         /* AMD_CG_SUPPORT_UVD_MGCG */
1252         data = RREG32(mmUVD_CGC_CTRL);
1253         if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)
1254                 *flags |= AMD_CG_SUPPORT_UVD_MGCG;
1255
1256 out:
1257         mutex_unlock(&adev->pm.mutex);
1258 }
1259
1260 static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
1261         .name = "uvd_v6_0",
1262         .early_init = uvd_v6_0_early_init,
1263         .late_init = NULL,
1264         .sw_init = uvd_v6_0_sw_init,
1265         .sw_fini = uvd_v6_0_sw_fini,
1266         .hw_init = uvd_v6_0_hw_init,
1267         .hw_fini = uvd_v6_0_hw_fini,
1268         .suspend = uvd_v6_0_suspend,
1269         .resume = uvd_v6_0_resume,
1270         .is_idle = uvd_v6_0_is_idle,
1271         .wait_for_idle = uvd_v6_0_wait_for_idle,
1272         .check_soft_reset = uvd_v6_0_check_soft_reset,
1273         .pre_soft_reset = uvd_v6_0_pre_soft_reset,
1274         .soft_reset = uvd_v6_0_soft_reset,
1275         .post_soft_reset = uvd_v6_0_post_soft_reset,
1276         .set_clockgating_state = uvd_v6_0_set_clockgating_state,
1277         .set_powergating_state = uvd_v6_0_set_powergating_state,
1278         .get_clockgating_state = uvd_v6_0_get_clockgating_state,
1279 };
1280
1281 static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
1282         .type = AMDGPU_RING_TYPE_UVD,
1283         .align_mask = 0xf,
1284         .nop = PACKET0(mmUVD_NO_OP, 0),
1285         .support_64bit_ptrs = false,
1286         .get_rptr = uvd_v6_0_ring_get_rptr,
1287         .get_wptr = uvd_v6_0_ring_get_wptr,
1288         .set_wptr = uvd_v6_0_ring_set_wptr,
1289         .parse_cs = amdgpu_uvd_ring_parse_cs,
1290         .emit_frame_size =
1291                 2 + /* uvd_v6_0_ring_emit_hdp_flush */
1292                 2 + /* uvd_v6_0_ring_emit_hdp_invalidate */
1293                 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
1294                 14, /* uvd_v6_0_ring_emit_fence x1 no user fence */
1295         .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
1296         .emit_ib = uvd_v6_0_ring_emit_ib,
1297         .emit_fence = uvd_v6_0_ring_emit_fence,
1298         .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
1299         .emit_hdp_invalidate = uvd_v6_0_ring_emit_hdp_invalidate,
1300         .test_ring = uvd_v6_0_ring_test_ring,
1301         .test_ib = amdgpu_uvd_ring_test_ib,
1302         .insert_nop = amdgpu_ring_insert_nop,
1303         .pad_ib = amdgpu_ring_generic_pad_ib,
1304         .begin_use = amdgpu_uvd_ring_begin_use,
1305         .end_use = amdgpu_uvd_ring_end_use,
1306 };
1307
1308 static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
1309         .type = AMDGPU_RING_TYPE_UVD,
1310         .align_mask = 0xf,
1311         .nop = PACKET0(mmUVD_NO_OP, 0),
1312         .support_64bit_ptrs = false,
1313         .get_rptr = uvd_v6_0_ring_get_rptr,
1314         .get_wptr = uvd_v6_0_ring_get_wptr,
1315         .set_wptr = uvd_v6_0_ring_set_wptr,
1316         .emit_frame_size =
1317                 2 + /* uvd_v6_0_ring_emit_hdp_flush */
1318                 2 + /* uvd_v6_0_ring_emit_hdp_invalidate */
1319                 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
1320                 20 + /* uvd_v6_0_ring_emit_vm_flush */
1321                 14 + 14, /* uvd_v6_0_ring_emit_fence x2 vm fence */
1322         .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
1323         .emit_ib = uvd_v6_0_ring_emit_ib,
1324         .emit_fence = uvd_v6_0_ring_emit_fence,
1325         .emit_vm_flush = uvd_v6_0_ring_emit_vm_flush,
1326         .emit_pipeline_sync = uvd_v6_0_ring_emit_pipeline_sync,
1327         .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
1328         .emit_hdp_invalidate = uvd_v6_0_ring_emit_hdp_invalidate,
1329         .test_ring = uvd_v6_0_ring_test_ring,
1330         .test_ib = amdgpu_uvd_ring_test_ib,
1331         .insert_nop = amdgpu_ring_insert_nop,
1332         .pad_ib = amdgpu_ring_generic_pad_ib,
1333         .begin_use = amdgpu_uvd_ring_begin_use,
1334         .end_use = amdgpu_uvd_ring_end_use,
1335 };
1336
1337 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev)
1338 {
1339         if (adev->asic_type >= CHIP_POLARIS10) {
1340                 adev->uvd.ring.funcs = &uvd_v6_0_ring_vm_funcs;
1341                 DRM_INFO("UVD is enabled in VM mode\n");
1342         } else {
1343                 adev->uvd.ring.funcs = &uvd_v6_0_ring_phys_funcs;
1344                 DRM_INFO("UVD is enabled in physical mode\n");
1345         }
1346 }
1347
1348 static const struct amdgpu_irq_src_funcs uvd_v6_0_irq_funcs = {
1349         .set = uvd_v6_0_set_interrupt_state,
1350         .process = uvd_v6_0_process_interrupt,
1351 };
1352
1353 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1354 {
1355         adev->uvd.irq.num_types = 1;
1356         adev->uvd.irq.funcs = &uvd_v6_0_irq_funcs;
1357 }
1358
1359 const struct amdgpu_ip_block_version uvd_v6_0_ip_block =
1360 {
1361                 .type = AMD_IP_BLOCK_TYPE_UVD,
1362                 .major = 6,
1363                 .minor = 0,
1364                 .rev = 0,
1365                 .funcs = &uvd_v6_0_ip_funcs,
1366 };
1367
1368 const struct amdgpu_ip_block_version uvd_v6_2_ip_block =
1369 {
1370                 .type = AMD_IP_BLOCK_TYPE_UVD,
1371                 .major = 6,
1372                 .minor = 2,
1373                 .rev = 0,
1374                 .funcs = &uvd_v6_0_ip_funcs,
1375 };
1376
1377 const struct amdgpu_ip_block_version uvd_v6_3_ip_block =
1378 {
1379                 .type = AMD_IP_BLOCK_TYPE_UVD,
1380                 .major = 6,
1381                 .minor = 3,
1382                 .rev = 0,
1383                 .funcs = &uvd_v6_0_ip_funcs,
1384 };