drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_uvd.h"
  28 #include "soc15.h"
  29 #include "soc15d.h"
  30 #include "soc15_common.h"
  31 #include "mmsch_v1_0.h"
  32
  33 #include "uvd/uvd_7_0_offset.h"
  34 #include "uvd/uvd_7_0_sh_mask.h"
  35 #include "vce/vce_4_0_offset.h"
  36 #include "vce/vce_4_0_default.h"
  37 #include "vce/vce_4_0_sh_mask.h"
  38 #include "nbif/nbif_6_1_offset.h"
  39 #include "hdp/hdp_4_0_offset.h"
  40 #include "mmhub/mmhub_1_0_offset.h"
  41 #include "mmhub/mmhub_1_0_sh_mask.h"
  42
  43 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev);
  44 static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev);
  45 static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev);
  46 static int uvd_v7_0_start(struct amdgpu_device *adev);
  47 static void uvd_v7_0_stop(struct amdgpu_device *adev);
  48 static int uvd_v7_0_sriov_start(struct amdgpu_device *adev);
  49
  50 /**
  51  * uvd_v7_0_ring_get_rptr - get read pointer
  52  *
  53  * @ring: amdgpu_ring pointer
  54  *
  55  * Returns the current hardware read pointer
  56  */
  57 static uint64_t uvd_v7_0_ring_get_rptr(struct amdgpu_ring *ring)
  58 {
  59         struct amdgpu_device *adev = ring->adev;
  60
  61         return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR);
  62 }
  63
  64 /**
  65  * uvd_v7_0_enc_ring_get_rptr - get enc read pointer
  66  *
  67  * @ring: amdgpu_ring pointer
  68  *
  69  * Returns the current hardware enc read pointer
  70  */
  71 static uint64_t uvd_v7_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
  72 {
  73         struct amdgpu_device *adev = ring->adev;
  74
  75         if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
  76                 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR);
  77         else
  78                 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2);
  79 }
  80
  81 /**
  82  * uvd_v7_0_ring_get_wptr - get write pointer
  83  *
  84  * @ring: amdgpu_ring pointer
  85  *
  86  * Returns the current hardware write pointer
  87  */
  88 static uint64_t uvd_v7_0_ring_get_wptr(struct amdgpu_ring *ring)
  89 {
  90         struct amdgpu_device *adev = ring->adev;
  91
  92         return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR);
  93 }
  94
  95 /**
  96  * uvd_v7_0_enc_ring_get_wptr - get enc write pointer
  97  *
  98  * @ring: amdgpu_ring pointer
  99  *
 100  * Returns the current hardware enc write pointer
 101  */
 102 static uint64_t uvd_v7_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
 103 {
 104         struct amdgpu_device *adev = ring->adev;
 105
 106         if (ring->use_doorbell)
 107                 return adev->wb.wb[ring->wptr_offs];
 108
 109         if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
 110                 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR);
 111         else
 112                 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2);
 113 }
 114
 115 /**
 116  * uvd_v7_0_ring_set_wptr - set write pointer
 117  *
 118  * @ring: amdgpu_ring pointer
 119  *
 120  * Commits the write pointer to the hardware
 121  */
 122 static void uvd_v7_0_ring_set_wptr(struct amdgpu_ring *ring)
 123 {
 124         struct amdgpu_device *adev = ring->adev;
 125
 126         WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
 127 }
 128
 129 /**
 130  * uvd_v7_0_enc_ring_set_wptr - set enc write pointer
 131  *
 132  * @ring: amdgpu_ring pointer
 133  *
 134  * Commits the enc write pointer to the hardware
 135  */
 136 static void uvd_v7_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
 137 {
 138         struct amdgpu_device *adev = ring->adev;
 139
 140         if (ring->use_doorbell) {
 141                 /* XXX check if swapping is necessary on BE */
 142                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
 143                 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
 144                 return;
 145         }
 146
 147         if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
 148                 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR,
 149                         lower_32_bits(ring->wptr));
 150         else
 151                 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2,
 152                         lower_32_bits(ring->wptr));
 153 }
 154
 155 /**
 156  * uvd_v7_0_enc_ring_test_ring - test if UVD ENC ring is working
 157  *
 158  * @ring: the engine to test on
 159  *
 160  */
 161 static int uvd_v7_0_enc_ring_test_ring(struct amdgpu_ring *ring)
 162 {
 163         struct amdgpu_device *adev = ring->adev;
 164         uint32_t rptr = amdgpu_ring_get_rptr(ring);
 165         unsigned i;
 166         int r;
 167
 168         if (amdgpu_sriov_vf(adev))
 169                 return 0;
 170
 171         r = amdgpu_ring_alloc(ring, 16);
 172         if (r) {
 173                 DRM_ERROR("amdgpu: uvd enc failed to lock (%d)ring %d (%d).\n",
 174                           ring->me, ring->idx, r);
 175                 return r;
 176         }
 177         amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
 178         amdgpu_ring_commit(ring);
 179
 180         for (i = 0; i < adev->usec_timeout; i++) {
 181                 if (amdgpu_ring_get_rptr(ring) != rptr)
 182                         break;
 183                 DRM_UDELAY(1);
 184         }
 185
 186         if (i < adev->usec_timeout) {
 187                 DRM_DEBUG("(%d)ring test on %d succeeded in %d usecs\n",
 188                          ring->me, ring->idx, i);
 189         } else {
 190                 DRM_ERROR("amdgpu: (%d)ring %d test failed\n",
 191                           ring->me, ring->idx);
 192                 r = -ETIMEDOUT;
 193         }
 194
 195         return r;
 196 }
 197
 198 /**
 199  * uvd_v7_0_enc_get_create_msg - generate a UVD ENC create msg
 200  *
 201  * @adev: amdgpu_device pointer
 202  * @ring: ring we should submit the msg to
 203  * @handle: session handle to use
 204  * @fence: optional fence to return
 205  *
 206  * Open up a stream for HW test
 207  */
 208 static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 209                                        struct dma_fence **fence)
 210 {
 211         const unsigned ib_size_dw = 16;
 212         struct amdgpu_job *job;
 213         struct amdgpu_ib *ib;
 214         struct dma_fence *f = NULL;
 215         uint64_t dummy;
 216         int i, r;
 217
 218         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 219         if (r)
 220                 return r;
 221
 222         ib = &job->ibs[0];
 223         dummy = ib->gpu_addr + 1024;
 224
 225         ib->length_dw = 0;
 226         ib->ptr[ib->length_dw++] = 0x00000018;
 227         ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
 228         ib->ptr[ib->length_dw++] = handle;
 229         ib->ptr[ib->length_dw++] = 0x00000000;
 230         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 231         ib->ptr[ib->length_dw++] = dummy;
 232
 233         ib->ptr[ib->length_dw++] = 0x00000014;
 234         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 235         ib->ptr[ib->length_dw++] = 0x0000001c;
 236         ib->ptr[ib->length_dw++] = 0x00000000;
 237         ib->ptr[ib->length_dw++] = 0x00000000;
 238
 239         ib->ptr[ib->length_dw++] = 0x00000008;
 240         ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
 241
 242         for (i = ib->length_dw; i < ib_size_dw; ++i)
 243                 ib->ptr[i] = 0x0;
 244
 245         r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
 246         job->fence = dma_fence_get(f);
 247         if (r)
 248                 goto err;
 249
 250         amdgpu_job_free(job);
 251         if (fence)
 252                 *fence = dma_fence_get(f);
 253         dma_fence_put(f);
 254         return 0;
 255
 256 err:
 257         amdgpu_job_free(job);
 258         return r;
 259 }
 260
 261 /**
 262  * uvd_v7_0_enc_get_destroy_msg - generate a UVD ENC destroy msg
 263  *
 264  * @adev: amdgpu_device pointer
 265  * @ring: ring we should submit the msg to
 266  * @handle: session handle to use
 267  * @fence: optional fence to return
 268  *
 269  * Close up a stream for HW test or if userspace failed to do so
 270  */
 271 int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 272                                  bool direct, struct dma_fence **fence)
 273 {
 274         const unsigned ib_size_dw = 16;
 275         struct amdgpu_job *job;
 276         struct amdgpu_ib *ib;
 277         struct dma_fence *f = NULL;
 278         uint64_t dummy;
 279         int i, r;
 280
 281         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 282         if (r)
 283                 return r;
 284
 285         ib = &job->ibs[0];
 286         dummy = ib->gpu_addr + 1024;
 287
 288         ib->length_dw = 0;
 289         ib->ptr[ib->length_dw++] = 0x00000018;
 290         ib->ptr[ib->length_dw++] = 0x00000001;
 291         ib->ptr[ib->length_dw++] = handle;
 292         ib->ptr[ib->length_dw++] = 0x00000000;
 293         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 294         ib->ptr[ib->length_dw++] = dummy;
 295
 296         ib->ptr[ib->length_dw++] = 0x00000014;
 297         ib->ptr[ib->length_dw++] = 0x00000002;
 298         ib->ptr[ib->length_dw++] = 0x0000001c;
 299         ib->ptr[ib->length_dw++] = 0x00000000;
 300         ib->ptr[ib->length_dw++] = 0x00000000;
 301
 302         ib->ptr[ib->length_dw++] = 0x00000008;
 303         ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
 304
 305         for (i = ib->length_dw; i < ib_size_dw; ++i)
 306                 ib->ptr[i] = 0x0;
 307
 308         if (direct) {
 309                 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
 310                 job->fence = dma_fence_get(f);
 311                 if (r)
 312                         goto err;
 313
 314                 amdgpu_job_free(job);
 315         } else {
 316                 r = amdgpu_job_submit(job, ring, &ring->adev->vce.entity,
 317                                       AMDGPU_FENCE_OWNER_UNDEFINED, &f);
 318                 if (r)
 319                         goto err;
 320         }
 321
 322         if (fence)
 323                 *fence = dma_fence_get(f);
 324         dma_fence_put(f);
 325         return 0;
 326
 327 err:
 328         amdgpu_job_free(job);
 329         return r;
 330 }
 331
 332 /**
 333  * uvd_v7_0_enc_ring_test_ib - test if UVD ENC IBs are working
 334  *
 335  * @ring: the engine to test on
 336  *
 337  */
 338 static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 339 {
 340         struct dma_fence *fence = NULL;
 341         long r;
 342
 343         r = uvd_v7_0_enc_get_create_msg(ring, 1, NULL);
 344         if (r) {
 345                 DRM_ERROR("amdgpu: (%d)failed to get create msg (%ld).\n", ring->me, r);
 346                 goto error;
 347         }
 348
 349         r = uvd_v7_0_enc_get_destroy_msg(ring, 1, true, &fence);
 350         if (r) {
 351                 DRM_ERROR("amdgpu: (%d)failed to get destroy ib (%ld).\n", ring->me, r);
 352                 goto error;
 353         }
 354
 355         r = dma_fence_wait_timeout(fence, false, timeout);
 356         if (r == 0) {
 357                 DRM_ERROR("amdgpu: (%d)IB test timed out.\n", ring->me);
 358                 r = -ETIMEDOUT;
 359         } else if (r < 0) {
 360                 DRM_ERROR("amdgpu: (%d)fence wait failed (%ld).\n", ring->me, r);
 361         } else {
 362                 DRM_DEBUG("ib test on (%d)ring %d succeeded\n", ring->me, ring->idx);
 363                 r = 0;
 364         }
 365 error:
 366         dma_fence_put(fence);
 367         return r;
 368 }
 369
 370 static int uvd_v7_0_early_init(void *handle)
 371 {
 372         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 373         adev->uvd.num_uvd_inst = 1;
 374
 375         if (amdgpu_sriov_vf(adev))
 376                 adev->uvd.num_enc_rings = 1;
 377         else
 378                 adev->uvd.num_enc_rings = 2;
 379         uvd_v7_0_set_ring_funcs(adev);
 380         uvd_v7_0_set_enc_ring_funcs(adev);
 381         uvd_v7_0_set_irq_funcs(adev);
 382
 383         return 0;
 384 }
 385
 386 static int uvd_v7_0_sw_init(void *handle)
 387 {
 388         struct amdgpu_ring *ring;
 389         struct drm_sched_rq *rq;
 390         int i, j, r;
 391         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 392
 393         for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
 394                 /* UVD TRAP */
 395                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UVD, 124, &adev->uvd.inst[j].irq);
 396                 if (r)
 397                         return r;
 398
 399                 /* UVD ENC TRAP */
 400                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 401                         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UVD, i + 119, &adev->uvd.inst[j].irq);
 402                         if (r)
 403                                 return r;
 404                 }
 405         }
 406
 407         r = amdgpu_uvd_sw_init(adev);
 408         if (r)
 409                 return r;
 410
 411         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 412                 const struct common_firmware_header *hdr;
 413                 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
 414                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].ucode_id = AMDGPU_UCODE_ID_UVD;
 415                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].fw = adev->uvd.fw;
 416                 adev->firmware.fw_size +=
 417                         ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
 418                 DRM_INFO("PSP loading UVD firmware\n");
 419         }
 420
 421         for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
 422                 ring = &adev->uvd.inst[j].ring_enc[0];
 423                 rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
 424                 r = drm_sched_entity_init(&ring->sched, &adev->uvd.inst[j].entity_enc,
 425                                           rq, NULL);
 426                 if (r) {
 427                         DRM_ERROR("(%d)Failed setting up UVD ENC run queue.\n", j);
 428                         return r;
 429                 }
 430         }
 431
 432         r = amdgpu_uvd_resume(adev);
 433         if (r)
 434                 return r;
 435
 436         for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
 437                 if (!amdgpu_sriov_vf(adev)) {
 438                         ring = &adev->uvd.inst[j].ring;
 439                         sprintf(ring->name, "uvd<%d>", j);
 440                         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst[j].irq, 0);
 441                         if (r)
 442                                 return r;
 443                 }
 444
 445                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 446                         ring = &adev->uvd.inst[j].ring_enc[i];
 447                         sprintf(ring->name, "uvd_enc%d<%d>", i, j);
 448                         if (amdgpu_sriov_vf(adev)) {
 449                                 ring->use_doorbell = true;
 450
 451                                 /* currently only use the first enconding ring for
 452                                  * sriov, so set unused location for other unused rings.
 453                                  */
 454                                 if (i == 0)
 455                                         ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING0_1 * 2;
 456                                 else
 457                                         ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING2_3 * 2 + 1;
 458                         }
 459                         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst[j].irq, 0);
 460                         if (r)
 461                                 return r;
 462                 }
 463         }
 464
 465         r = amdgpu_virt_alloc_mm_table(adev);
 466         if (r)
 467                 return r;
 468
 469         return r;
 470 }
 471
 472 static int uvd_v7_0_sw_fini(void *handle)
 473 {
 474         int i, j, r;
 475         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 476
 477         amdgpu_virt_free_mm_table(adev);
 478
 479         r = amdgpu_uvd_suspend(adev);
 480         if (r)
 481                 return r;
 482
 483         for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
 484                 drm_sched_entity_fini(&adev->uvd.inst[j].ring_enc[0].sched, &adev->uvd.inst[j].entity_enc);
 485
 486                 for (i = 0; i < adev->uvd.num_enc_rings; ++i)
 487                         amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]);
 488         }
 489         return amdgpu_uvd_sw_fini(adev);
 490 }
 491
 492 /**
 493  * uvd_v7_0_hw_init - start and test UVD block
 494  *
 495  * @adev: amdgpu_device pointer
 496  *
 497  * Initialize the hardware, boot up the VCPU and do some testing
 498  */
 499 static int uvd_v7_0_hw_init(void *handle)
 500 {
 501         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 502         struct amdgpu_ring *ring;
 503         uint32_t tmp;
 504         int i, j, r;
 505
 506         if (amdgpu_sriov_vf(adev))
 507                 r = uvd_v7_0_sriov_start(adev);
 508         else
 509                 r = uvd_v7_0_start(adev);
 510         if (r)
 511                 goto done;
 512
 513         for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
 514                 ring = &adev->uvd.inst[j].ring;
 515
 516                 if (!amdgpu_sriov_vf(adev)) {
 517                         ring->ready = true;
 518                         r = amdgpu_ring_test_ring(ring);
 519                         if (r) {
 520                                 ring->ready = false;
 521                                 goto done;
 522                         }
 523
 524                         r = amdgpu_ring_alloc(ring, 10);
 525                         if (r) {
 526                                 DRM_ERROR("amdgpu: (%d)ring failed to lock UVD ring (%d).\n", j, r);
 527                                 goto done;
 528                         }
 529
 530                         tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
 531                                 mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL), 0);
 532                         amdgpu_ring_write(ring, tmp);
 533                         amdgpu_ring_write(ring, 0xFFFFF);
 534
 535                         tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
 536                                 mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL), 0);
 537                         amdgpu_ring_write(ring, tmp);
 538                         amdgpu_ring_write(ring, 0xFFFFF);
 539
 540                         tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
 541                                 mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL), 0);
 542                         amdgpu_ring_write(ring, tmp);
 543                         amdgpu_ring_write(ring, 0xFFFFF);
 544
 545                         /* Clear timeout status bits */
 546                         amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,
 547                                 mmUVD_SEMA_TIMEOUT_STATUS), 0));
 548                         amdgpu_ring_write(ring, 0x8);
 549
 550                         amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,
 551                                 mmUVD_SEMA_CNTL), 0));
 552                         amdgpu_ring_write(ring, 3);
 553
 554                         amdgpu_ring_commit(ring);
 555                 }
 556
 557                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 558                         ring = &adev->uvd.inst[j].ring_enc[i];
 559                         ring->ready = true;
 560                         r = amdgpu_ring_test_ring(ring);
 561                         if (r) {
 562                                 ring->ready = false;
 563                                 goto done;
 564                         }
 565                 }
 566         }
 567 done:
 568         if (!r)
 569                 DRM_INFO("UVD and UVD ENC initialized successfully.\n");
 570
 571         return r;
 572 }
 573
 574 /**
 575  * uvd_v7_0_hw_fini - stop the hardware block
 576  *
 577  * @adev: amdgpu_device pointer
 578  *
 579  * Stop the UVD block, mark ring as not ready any more
 580  */
 581 static int uvd_v7_0_hw_fini(void *handle)
 582 {
 583         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 584         int i;
 585
 586         if (!amdgpu_sriov_vf(adev))
 587                 uvd_v7_0_stop(adev);
 588         else {
 589                 /* full access mode, so don't touch any UVD register */
 590                 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
 591         }
 592
 593         for (i = 0; i < adev->uvd.num_uvd_inst; ++i)
 594                 adev->uvd.inst[i].ring.ready = false;
 595
 596         return 0;
 597 }
 598
 599 static int uvd_v7_0_suspend(void *handle)
 600 {
 601         int r;
 602         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 603
 604         r = uvd_v7_0_hw_fini(adev);
 605         if (r)
 606                 return r;
 607
 608         return amdgpu_uvd_suspend(adev);
 609 }
 610
 611 static int uvd_v7_0_resume(void *handle)
 612 {
 613         int r;
 614         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 615
 616         r = amdgpu_uvd_resume(adev);
 617         if (r)
 618                 return r;
 619
 620         return uvd_v7_0_hw_init(adev);
 621 }
 622
 623 /**
 624  * uvd_v7_0_mc_resume - memory controller programming
 625  *
 626  * @adev: amdgpu_device pointer
 627  *
 628  * Let the UVD memory controller know it's offsets
 629  */
 630 static void uvd_v7_0_mc_resume(struct amdgpu_device *adev)
 631 {
 632         uint32_t size = AMDGPU_UVD_FIRMWARE_SIZE(adev);
 633         uint32_t offset;
 634         int i;
 635
 636         for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
 637                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 638                         WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 639                                 lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
 640                         WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 641                                 upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
 642                         offset = 0;
 643                 } else {
 644                         WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 645                                 lower_32_bits(adev->uvd.inst[i].gpu_addr));
 646                         WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 647                                 upper_32_bits(adev->uvd.inst[i].gpu_addr));
 648                         offset = size;
 649                 }
 650
 651                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0,
 652                                         AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 653                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size);
 654
 655                 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 656                                 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset));
 657                 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 658                                 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset));
 659                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET1, (1 << 21));
 660                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_UVD_HEAP_SIZE);
 661
 662                 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 663                                 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 664                 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 665                                 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 666                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET2, (2 << 21));
 667                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE2,
 668                                 AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40));
 669
 670                 WREG32_SOC15(UVD, i, mmUVD_UDEC_ADDR_CONFIG,
 671                                 adev->gfx.config.gb_addr_config);
 672                 WREG32_SOC15(UVD, i, mmUVD_UDEC_DB_ADDR_CONFIG,
 673                                 adev->gfx.config.gb_addr_config);
 674                 WREG32_SOC15(UVD, i, mmUVD_UDEC_DBW_ADDR_CONFIG,
 675                                 adev->gfx.config.gb_addr_config);
 676
 677                 WREG32_SOC15(UVD, i, mmUVD_GP_SCRATCH4, adev->uvd.max_handles);
 678         }
 679 }
 680
 681 static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev,
 682                                 struct amdgpu_mm_table *table)
 683 {
 684         uint32_t data = 0, loop;
 685         uint64_t addr = table->gpu_addr;
 686         struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)table->cpu_addr;
 687         uint32_t size;
 688         int i;
 689
 690         size = header->header_size + header->vce_table_size + header->uvd_table_size;
 691
 692         /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of memory descriptor location */
 693         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));
 694         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));
 695
 696         /* 2, update vmid of descriptor */
 697         data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID);
 698         data &= ~VCE_MMSCH_VF_VMID__VF_CTX_VMID_MASK;
 699         data |= (0 << VCE_MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); /* use domain0 for MM scheduler */
 700         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID, data);
 701
 702         /* 3, notify mmsch about the size of this descriptor */
 703         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_SIZE, size);
 704
 705         /* 4, set resp to zero */
 706         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP, 0);
 707
 708         for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
 709                 WDOORBELL32(adev->uvd.inst[i].ring_enc[0].doorbell_index, 0);
 710                 adev->wb.wb[adev->uvd.inst[i].ring_enc[0].wptr_offs] = 0;
 711                 adev->uvd.inst[i].ring_enc[0].wptr = 0;
 712                 adev->uvd.inst[i].ring_enc[0].wptr_old = 0;
 713         }
 714         /* 5, kick off the initialization and wait until VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */
 715         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST, 0x10000001);
 716
 717         data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP);
 718         loop = 1000;
 719         while ((data & 0x10000002) != 0x10000002) {
 720                 udelay(10);
 721                 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP);
 722                 loop--;
 723                 if (!loop)
 724                         break;
 725         }
 726
 727         if (!loop) {
 728                 dev_err(adev->dev, "failed to init MMSCH, mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data);
 729                 return -EBUSY;
 730         }
 731
 732         return 0;
 733 }
 734
 735 static int uvd_v7_0_sriov_start(struct amdgpu_device *adev)
 736 {
 737         struct amdgpu_ring *ring;
 738         uint32_t offset, size, tmp;
 739         uint32_t table_size = 0;
 740         struct mmsch_v1_0_cmd_direct_write direct_wt = { {0} };
 741         struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} };
 742         struct mmsch_v1_0_cmd_direct_polling direct_poll = { {0} };
 743         struct mmsch_v1_0_cmd_end end = { {0} };
 744         uint32_t *init_table = adev->virt.mm_table.cpu_addr;
 745         struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)init_table;
 746         uint8_t i = 0;
 747
 748         direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE;
 749         direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
 750         direct_poll.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_POLLING;
 751         end.cmd_header.command_type = MMSCH_COMMAND__END;
 752
 753         if (header->uvd_table_offset == 0 && header->uvd_table_size == 0) {
 754                 header->version = MMSCH_VERSION;
 755                 header->header_size = sizeof(struct mmsch_v1_0_init_header) >> 2;
 756
 757                 if (header->vce_table_offset == 0 && header->vce_table_size == 0)
 758                         header->uvd_table_offset = header->header_size;
 759                 else
 760                         header->uvd_table_offset = header->vce_table_size + header->vce_table_offset;
 761
 762                 init_table += header->uvd_table_offset;
 763
 764                 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
 765                         ring = &adev->uvd.inst[i].ring;
 766                         ring->wptr = 0;
 767                         size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
 768
 769                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
 770                                                            0xFFFFFFFF, 0x00000004);
 771                         /* mc resume*/
 772                         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 773                                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 774                                                             lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
 775                                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 776                                                             upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
 777                                 offset = 0;
 778                         } else {
 779                                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 780                                                             lower_32_bits(adev->uvd.inst[i].gpu_addr));
 781                                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 782                                                             upper_32_bits(adev->uvd.inst[i].gpu_addr));
 783                                 offset = size;
 784                         }
 785
 786                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0),
 787                                                     AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 788                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), size);
 789
 790                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
 791                                                     lower_32_bits(adev->uvd.inst[i].gpu_addr + offset));
 792                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
 793                                                     upper_32_bits(adev->uvd.inst[i].gpu_addr + offset));
 794                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21));
 795                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_UVD_HEAP_SIZE);
 796
 797                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
 798                                                     lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 799                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
 800                                                     upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 801                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21));
 802                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2),
 803                                                     AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40));
 804
 805                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_GP_SCRATCH4), adev->uvd.max_handles);
 806                         /* mc resume end*/
 807
 808                         /* disable clock gating */
 809                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_CGC_CTRL),
 810                                                            ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK, 0);
 811
 812                         /* disable interupt */
 813                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),
 814                                                            ~UVD_MASTINT_EN__VCPU_EN_MASK, 0);
 815
 816                         /* stall UMC and register bus before resetting VCPU */
 817                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),
 818                                                            ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
 819                                                            UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 820
 821                         /* put LMI, VCPU, RBC etc... into reset */
 822                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET),
 823                                                     (uint32_t)(UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 824                                                                UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
 825                                                                UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 826                                                                UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
 827                                                                UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 828                                                                UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
 829                                                                UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 830                                                                UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK));
 831
 832                         /* initialize UVD memory controller */
 833                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL),
 834                                                     (uint32_t)((0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 835                                                                UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 836                                                                UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 837                                                                UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 838                                                                UVD_LMI_CTRL__REQ_MODE_MASK |
 839                                                                0x00100000L));
 840
 841                         /* take all subblocks out of reset, except VCPU */
 842                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET),
 843                                                     UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 844
 845                         /* enable VCPU clock */
 846                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),
 847                                                     UVD_VCPU_CNTL__CLK_EN_MASK);
 848
 849                         /* enable master interrupt */
 850                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),
 851                                                            ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
 852                                                            (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
 853
 854                         /* clear the bit 4 of UVD_STATUS */
 855                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
 856                                                            ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT), 0);
 857
 858                         /* force RBC into idle state */
 859                         size = order_base_2(ring->ring_size);
 860                         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size);
 861                         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 862                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp);
 863
 864                         ring = &adev->uvd.inst[i].ring_enc[0];
 865                         ring->wptr = 0;
 866                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), ring->gpu_addr);
 867                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr));
 868                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), ring->ring_size / 4);
 869
 870                         /* boot up the VCPU */
 871                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 0);
 872
 873                         /* enable UMC */
 874                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),
 875                                                                                            ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0);
 876
 877                         MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0x02, 0x02);
 878                 }
 879                 /* add end packet */
 880                 memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end));
 881                 table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4;
 882                 header->uvd_table_size = table_size;
 883
 884         }
 885         return uvd_v7_0_mmsch_start(adev, &adev->virt.mm_table);
 886 }
 887
 888 /**
 889  * uvd_v7_0_start - start UVD block
 890  *
 891  * @adev: amdgpu_device pointer
 892  *
 893  * Setup and start the UVD block
 894  */
 895 static int uvd_v7_0_start(struct amdgpu_device *adev)
 896 {
 897         struct amdgpu_ring *ring;
 898         uint32_t rb_bufsz, tmp;
 899         uint32_t lmi_swap_cntl;
 900         uint32_t mp_swap_cntl;
 901         int i, j, k, r;
 902
 903         for (k = 0; k < adev->uvd.num_uvd_inst; ++k) {
 904                 /* disable DPG */
 905                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_POWER_STATUS), 0,
 906                                 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
 907         }
 908
 909         /* disable byte swapping */
 910         lmi_swap_cntl = 0;
 911         mp_swap_cntl = 0;
 912
 913         uvd_v7_0_mc_resume(adev);
 914
 915         for (k = 0; k < adev->uvd.num_uvd_inst; ++k) {
 916                 ring = &adev->uvd.inst[k].ring;
 917                 /* disable clock gating */
 918                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0,
 919                                 ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK);
 920
 921                 /* disable interupt */
 922                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 0,
 923                                 ~UVD_MASTINT_EN__VCPU_EN_MASK);
 924
 925                 /* stall UMC and register bus before resetting VCPU */
 926                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2),
 927                                 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
 928                                 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 929                 mdelay(1);
 930
 931                 /* put LMI, VCPU, RBC etc... into reset */
 932                 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET,
 933                         UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 934                         UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
 935                         UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 936                         UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
 937                         UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 938                         UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
 939                         UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 940                         UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
 941                 mdelay(5);
 942
 943                 /* initialize UVD memory controller */
 944                 WREG32_SOC15(UVD, k, mmUVD_LMI_CTRL,
 945                         (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 946                         UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 947                         UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 948                         UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 949                         UVD_LMI_CTRL__REQ_MODE_MASK |
 950                         0x00100000L);
 951
 952 #ifdef __BIG_ENDIAN
 953                 /* swap (8 in 32) RB and IB */
 954                 lmi_swap_cntl = 0xa;
 955                 mp_swap_cntl = 0;
 956 #endif
 957                 WREG32_SOC15(UVD, k, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
 958                 WREG32_SOC15(UVD, k, mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
 959
 960                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA0, 0x40c2040);
 961                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA1, 0x0);
 962                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB0, 0x40c2040);
 963                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB1, 0x0);
 964                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_ALU, 0);
 965                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUX, 0x88);
 966
 967                 /* take all subblocks out of reset, except VCPU */
 968                 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET,
 969                                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 970                 mdelay(5);
 971
 972                 /* enable VCPU clock */
 973                 WREG32_SOC15(UVD, k, mmUVD_VCPU_CNTL,
 974                                 UVD_VCPU_CNTL__CLK_EN_MASK);
 975
 976                 /* enable UMC */
 977                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 0,
 978                                 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 979
 980                 /* boot up the VCPU */
 981                 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 0);
 982                 mdelay(10);
 983
 984                 for (i = 0; i < 10; ++i) {
 985                         uint32_t status;
 986
 987                         for (j = 0; j < 100; ++j) {
 988                                 status = RREG32_SOC15(UVD, k, mmUVD_STATUS);
 989                                 if (status & 2)
 990                                         break;
 991                                 mdelay(10);
 992                         }
 993                         r = 0;
 994                         if (status & 2)
 995                                 break;
 996
 997                         DRM_ERROR("UVD(%d) not responding, trying to reset the VCPU!!!\n", k);
 998                         WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET),
 999                                         UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1000                                         ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1001                         mdelay(10);
1002                         WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 0,
1003                                         ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1004                         mdelay(10);
1005                         r = -1;
1006                 }
1007
1008                 if (r) {
1009                         DRM_ERROR("UVD(%d) not responding, giving up!!!\n", k);
1010                         return r;
1011                 }
1012                 /* enable master interrupt */
1013                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN),
1014                         (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
1015                         ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
1016
1017                 /* clear the bit 4 of UVD_STATUS */
1018                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0,
1019                                 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1020
1021                 /* force RBC into idle state */
1022                 rb_bufsz = order_base_2(ring->ring_size);
1023                 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1024                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1025                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1026                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
1027                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1028                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1029                 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_CNTL, tmp);
1030
1031                 /* set the write pointer delay */
1032                 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR_CNTL, 0);
1033
1034                 /* set the wb address */
1035                 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR_ADDR,
1036                                 (upper_32_bits(ring->gpu_addr) >> 2));
1037
1038                 /* programm the RB_BASE for ring buffer */
1039                 WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1040                                 lower_32_bits(ring->gpu_addr));
1041                 WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1042                                 upper_32_bits(ring->gpu_addr));
1043
1044                 /* Initialize the ring buffer's read and write pointers */
1045                 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR, 0);
1046
1047                 ring->wptr = RREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR);
1048                 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR,
1049                                 lower_32_bits(ring->wptr));
1050
1051                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_RBC_RB_CNTL), 0,
1052                                 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
1053
1054                 ring = &adev->uvd.inst[k].ring_enc[0];
1055                 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1056                 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1057                 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO, ring->gpu_addr);
1058                 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1059                 WREG32_SOC15(UVD, k, mmUVD_RB_SIZE, ring->ring_size / 4);
1060
1061                 ring = &adev->uvd.inst[k].ring_enc[1];
1062                 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1063                 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1064                 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1065                 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1066                 WREG32_SOC15(UVD, k, mmUVD_RB_SIZE2, ring->ring_size / 4);
1067         }
1068         return 0;
1069 }
1070
1071 /**
1072  * uvd_v7_0_stop - stop UVD block
1073  *
1074  * @adev: amdgpu_device pointer
1075  *
1076  * stop the UVD block
1077  */
1078 static void uvd_v7_0_stop(struct amdgpu_device *adev)
1079 {
1080         uint8_t i = 0;
1081
1082         for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
1083                 /* force RBC into idle state */
1084                 WREG32_SOC15(UVD, i, mmUVD_RBC_RB_CNTL, 0x11010101);
1085
1086                 /* Stall UMC and register bus before resetting VCPU */
1087                 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),
1088                                 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
1089                                 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1090                 mdelay(1);
1091
1092                 /* put VCPU into reset */
1093                 WREG32_SOC15(UVD, i, mmUVD_SOFT_RESET,
1094                                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1095                 mdelay(5);
1096
1097                 /* disable VCPU clock */
1098                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CNTL, 0x0);
1099
1100                 /* Unstall UMC and register bus */
1101                 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0,
1102                                 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1103         }
1104 }
1105
1106 /**
1107  * uvd_v7_0_ring_emit_fence - emit an fence & trap command
1108  *
1109  * @ring: amdgpu_ring pointer
1110  * @fence: fence to emit
1111  *
1112  * Write a fence and a trap command to the ring.
1113  */
1114 static void uvd_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1115                                      unsigned flags)
1116 {
1117         struct amdgpu_device *adev = ring->adev;
1118
1119         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1120
1121         amdgpu_ring_write(ring,
1122                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));
1123         amdgpu_ring_write(ring, seq);
1124         amdgpu_ring_write(ring,
1125                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
1126         amdgpu_ring_write(ring, addr & 0xffffffff);
1127         amdgpu_ring_write(ring,
1128                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1129         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1130         amdgpu_ring_write(ring,
1131                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1132         amdgpu_ring_write(ring, 0);
1133
1134         amdgpu_ring_write(ring,
1135                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
1136         amdgpu_ring_write(ring, 0);
1137         amdgpu_ring_write(ring,
1138                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1139         amdgpu_ring_write(ring, 0);
1140         amdgpu_ring_write(ring,
1141                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1142         amdgpu_ring_write(ring, 2);
1143 }
1144
1145 /**
1146  * uvd_v7_0_enc_ring_emit_fence - emit an enc fence & trap command
1147  *
1148  * @ring: amdgpu_ring pointer
1149  * @fence: fence to emit
1150  *
1151  * Write enc a fence and a trap command to the ring.
1152  */
1153 static void uvd_v7_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1154                         u64 seq, unsigned flags)
1155 {
1156
1157         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1158
1159         amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE);
1160         amdgpu_ring_write(ring, addr);
1161         amdgpu_ring_write(ring, upper_32_bits(addr));
1162         amdgpu_ring_write(ring, seq);
1163         amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
1164 }
1165
1166 /**
1167  * uvd_v7_0_ring_emit_hdp_flush - skip HDP flushing
1168  *
1169  * @ring: amdgpu_ring pointer
1170  */
1171 static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
1172 {
1173         /* The firmware doesn't seem to like touching registers at this point. */
1174 }
1175
1176 /**
1177  * uvd_v7_0_ring_test_ring - register write test
1178  *
1179  * @ring: amdgpu_ring pointer
1180  *
1181  * Test if we can successfully write to the context register
1182  */
1183 static int uvd_v7_0_ring_test_ring(struct amdgpu_ring *ring)
1184 {
1185         struct amdgpu_device *adev = ring->adev;
1186         uint32_t tmp = 0;
1187         unsigned i;
1188         int r;
1189
1190         WREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID, 0xCAFEDEAD);
1191         r = amdgpu_ring_alloc(ring, 3);
1192         if (r) {
1193                 DRM_ERROR("amdgpu: (%d)cp failed to lock ring %d (%d).\n",
1194                           ring->me, ring->idx, r);
1195                 return r;
1196         }
1197         amdgpu_ring_write(ring,
1198                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));
1199         amdgpu_ring_write(ring, 0xDEADBEEF);
1200         amdgpu_ring_commit(ring);
1201         for (i = 0; i < adev->usec_timeout; i++) {
1202                 tmp = RREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID);
1203                 if (tmp == 0xDEADBEEF)
1204                         break;
1205                 DRM_UDELAY(1);
1206         }
1207
1208         if (i < adev->usec_timeout) {
1209                 DRM_DEBUG("(%d)ring test on %d succeeded in %d usecs\n",
1210                          ring->me, ring->idx, i);
1211         } else {
1212                 DRM_ERROR("(%d)amdgpu: ring %d test failed (0x%08X)\n",
1213                           ring->me, ring->idx, tmp);
1214                 r = -EINVAL;
1215         }
1216         return r;
1217 }
1218
1219 /**
1220  * uvd_v7_0_ring_emit_ib - execute indirect buffer
1221  *
1222  * @ring: amdgpu_ring pointer
1223  * @ib: indirect buffer to execute
1224  *
1225  * Write ring commands to execute the indirect buffer
1226  */
1227 static void uvd_v7_0_ring_emit_ib(struct amdgpu_ring *ring,
1228                                   struct amdgpu_ib *ib,
1229                                   unsigned vmid, bool ctx_switch)
1230 {
1231         struct amdgpu_device *adev = ring->adev;
1232
1233         amdgpu_ring_write(ring,
1234                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_VMID), 0));
1235         amdgpu_ring_write(ring, vmid);
1236
1237         amdgpu_ring_write(ring,
1238                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
1239         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1240         amdgpu_ring_write(ring,
1241                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
1242         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1243         amdgpu_ring_write(ring,
1244                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_RBC_IB_SIZE), 0));
1245         amdgpu_ring_write(ring, ib->length_dw);
1246 }
1247
1248 /**
1249  * uvd_v7_0_enc_ring_emit_ib - enc execute indirect buffer
1250  *
1251  * @ring: amdgpu_ring pointer
1252  * @ib: indirect buffer to execute
1253  *
1254  * Write enc ring commands to execute the indirect buffer
1255  */
1256 static void uvd_v7_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1257                 struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch)
1258 {
1259         amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM);
1260         amdgpu_ring_write(ring, vmid);
1261         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1262         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1263         amdgpu_ring_write(ring, ib->length_dw);
1264 }
1265
1266 static void uvd_v7_0_ring_emit_wreg(struct amdgpu_ring *ring,
1267                                     uint32_t reg, uint32_t val)
1268 {
1269         struct amdgpu_device *adev = ring->adev;
1270
1271         amdgpu_ring_write(ring,
1272                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
1273         amdgpu_ring_write(ring, reg << 2);
1274         amdgpu_ring_write(ring,
1275                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1276         amdgpu_ring_write(ring, val);
1277         amdgpu_ring_write(ring,
1278                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1279         amdgpu_ring_write(ring, 8);
1280 }
1281
1282 static void uvd_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1283                                         uint32_t val, uint32_t mask)
1284 {
1285         struct amdgpu_device *adev = ring->adev;
1286
1287         amdgpu_ring_write(ring,
1288                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
1289         amdgpu_ring_write(ring, reg << 2);
1290         amdgpu_ring_write(ring,
1291                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1292         amdgpu_ring_write(ring, val);
1293         amdgpu_ring_write(ring,
1294                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GP_SCRATCH8), 0));
1295         amdgpu_ring_write(ring, mask);
1296         amdgpu_ring_write(ring,
1297                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1298         amdgpu_ring_write(ring, 12);
1299 }
1300
1301 static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1302                                         unsigned vmid, uint64_t pd_addr)
1303 {
1304         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1305         uint32_t data0, data1, mask;
1306
1307         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1308
1309         /* wait for reg writes */
1310         data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
1311         data1 = lower_32_bits(pd_addr);
1312         mask = 0xffffffff;
1313         uvd_v7_0_ring_emit_reg_wait(ring, data0, data1, mask);
1314 }
1315
1316 static void uvd_v7_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1317 {
1318         int i;
1319         struct amdgpu_device *adev = ring->adev;
1320
1321         for (i = 0; i < count; i++)
1322                 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_NO_OP), 0));
1323
1324 }
1325
1326 static void uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1327 {
1328         amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
1329 }
1330
1331 static void uvd_v7_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring,
1332                                             uint32_t reg, uint32_t val,
1333                                             uint32_t mask)
1334 {
1335         amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);
1336         amdgpu_ring_write(ring, reg << 2);
1337         amdgpu_ring_write(ring, mask);
1338         amdgpu_ring_write(ring, val);
1339 }
1340
1341 static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1342                                             unsigned int vmid, uint64_t pd_addr)
1343 {
1344         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1345
1346         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1347
1348         /* wait for reg writes */
1349         uvd_v7_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2,
1350                                         lower_32_bits(pd_addr), 0xffffffff);
1351 }
1352
1353 static void uvd_v7_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
1354                                         uint32_t reg, uint32_t val)
1355 {
1356         amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
1357         amdgpu_ring_write(ring, reg << 2);
1358         amdgpu_ring_write(ring, val);
1359 }
1360
1361 #if 0
1362 static bool uvd_v7_0_is_idle(void *handle)
1363 {
1364         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1365
1366         return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
1367 }
1368
1369 static int uvd_v7_0_wait_for_idle(void *handle)
1370 {
1371         unsigned i;
1372         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1373
1374         for (i = 0; i < adev->usec_timeout; i++) {
1375                 if (uvd_v7_0_is_idle(handle))
1376                         return 0;
1377         }
1378         return -ETIMEDOUT;
1379 }
1380
1381 #define AMDGPU_UVD_STATUS_BUSY_MASK    0xfd
1382 static bool uvd_v7_0_check_soft_reset(void *handle)
1383 {
1384         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1385         u32 srbm_soft_reset = 0;
1386         u32 tmp = RREG32(mmSRBM_STATUS);
1387
1388         if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) ||
1389             REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) ||
1390             (RREG32_SOC15(UVD, ring->me, mmUVD_STATUS) &
1391                     AMDGPU_UVD_STATUS_BUSY_MASK))
1392                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1393                                 SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
1394
1395         if (srbm_soft_reset) {
1396                 adev->uvd.inst[ring->me].srbm_soft_reset = srbm_soft_reset;
1397                 return true;
1398         } else {
1399                 adev->uvd.inst[ring->me].srbm_soft_reset = 0;
1400                 return false;
1401         }
1402 }
1403
1404 static int uvd_v7_0_pre_soft_reset(void *handle)
1405 {
1406         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1407
1408         if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1409                 return 0;
1410
1411         uvd_v7_0_stop(adev);
1412         return 0;
1413 }
1414
1415 static int uvd_v7_0_soft_reset(void *handle)
1416 {
1417         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1418         u32 srbm_soft_reset;
1419
1420         if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1421                 return 0;
1422         srbm_soft_reset = adev->uvd.inst[ring->me].srbm_soft_reset;
1423
1424         if (srbm_soft_reset) {
1425                 u32 tmp;
1426
1427                 tmp = RREG32(mmSRBM_SOFT_RESET);
1428                 tmp |= srbm_soft_reset;
1429                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1430                 WREG32(mmSRBM_SOFT_RESET, tmp);
1431                 tmp = RREG32(mmSRBM_SOFT_RESET);
1432
1433                 udelay(50);
1434
1435                 tmp &= ~srbm_soft_reset;
1436                 WREG32(mmSRBM_SOFT_RESET, tmp);
1437                 tmp = RREG32(mmSRBM_SOFT_RESET);
1438
1439                 /* Wait a little for things to settle down */
1440                 udelay(50);
1441         }
1442
1443         return 0;
1444 }
1445
1446 static int uvd_v7_0_post_soft_reset(void *handle)
1447 {
1448         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1449
1450         if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1451                 return 0;
1452
1453         mdelay(5);
1454
1455         return uvd_v7_0_start(adev);
1456 }
1457 #endif
1458
1459 static int uvd_v7_0_set_interrupt_state(struct amdgpu_device *adev,
1460                                         struct amdgpu_irq_src *source,
1461                                         unsigned type,
1462                                         enum amdgpu_interrupt_state state)
1463 {
1464         // TODO
1465         return 0;
1466 }
1467
1468 static int uvd_v7_0_process_interrupt(struct amdgpu_device *adev,
1469                                       struct amdgpu_irq_src *source,
1470                                       struct amdgpu_iv_entry *entry)
1471 {
1472         uint32_t ip_instance;
1473
1474         switch (entry->client_id) {
1475         case SOC15_IH_CLIENTID_UVD:
1476                 ip_instance = 0;
1477                 break;
1478         default:
1479                 DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
1480                 return 0;
1481         }
1482
1483         DRM_DEBUG("IH: UVD TRAP\n");
1484
1485         switch (entry->src_id) {
1486         case 124:
1487                 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring);
1488                 break;
1489         case 119:
1490                 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[0]);
1491                 break;
1492         case 120:
1493                 if (!amdgpu_sriov_vf(adev))
1494                         amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[1]);
1495                 break;
1496         default:
1497                 DRM_ERROR("Unhandled interrupt: %d %d\n",
1498                           entry->src_id, entry->src_data[0]);
1499                 break;
1500         }
1501
1502         return 0;
1503 }
1504
1505 #if 0
1506 static void uvd_v7_0_set_sw_clock_gating(struct amdgpu_device *adev)
1507 {
1508         uint32_t data, data1, data2, suvd_flags;
1509
1510         data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL);
1511         data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1512         data2 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL);
1513
1514         data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
1515                   UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
1516
1517         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1518                      UVD_SUVD_CGC_GATE__SIT_MASK |
1519                      UVD_SUVD_CGC_GATE__SMP_MASK |
1520                      UVD_SUVD_CGC_GATE__SCM_MASK |
1521                      UVD_SUVD_CGC_GATE__SDB_MASK;
1522
1523         data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
1524                 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
1525                 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
1526
1527         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
1528                         UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
1529                         UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
1530                         UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
1531                         UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
1532                         UVD_CGC_CTRL__SYS_MODE_MASK |
1533                         UVD_CGC_CTRL__UDEC_MODE_MASK |
1534                         UVD_CGC_CTRL__MPEG2_MODE_MASK |
1535                         UVD_CGC_CTRL__REGS_MODE_MASK |
1536                         UVD_CGC_CTRL__RBC_MODE_MASK |
1537                         UVD_CGC_CTRL__LMI_MC_MODE_MASK |
1538                         UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
1539                         UVD_CGC_CTRL__IDCT_MODE_MASK |
1540                         UVD_CGC_CTRL__MPRD_MODE_MASK |
1541                         UVD_CGC_CTRL__MPC_MODE_MASK |
1542                         UVD_CGC_CTRL__LBSI_MODE_MASK |
1543                         UVD_CGC_CTRL__LRBBM_MODE_MASK |
1544                         UVD_CGC_CTRL__WCB_MODE_MASK |
1545                         UVD_CGC_CTRL__VCPU_MODE_MASK |
1546                         UVD_CGC_CTRL__JPEG_MODE_MASK |
1547                         UVD_CGC_CTRL__JPEG2_MODE_MASK |
1548                         UVD_CGC_CTRL__SCPU_MODE_MASK);
1549         data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
1550                         UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
1551                         UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
1552                         UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
1553                         UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
1554         data1 |= suvd_flags;
1555
1556         WREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL, data);
1557         WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, 0);
1558         WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
1559         WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL, data2);
1560 }
1561
1562 static void uvd_v7_0_set_hw_clock_gating(struct amdgpu_device *adev)
1563 {
1564         uint32_t data, data1, cgc_flags, suvd_flags;
1565
1566         data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE);
1567         data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1568
1569         cgc_flags = UVD_CGC_GATE__SYS_MASK |
1570                 UVD_CGC_GATE__UDEC_MASK |
1571                 UVD_CGC_GATE__MPEG2_MASK |
1572                 UVD_CGC_GATE__RBC_MASK |
1573                 UVD_CGC_GATE__LMI_MC_MASK |
1574                 UVD_CGC_GATE__IDCT_MASK |
1575                 UVD_CGC_GATE__MPRD_MASK |
1576                 UVD_CGC_GATE__MPC_MASK |
1577                 UVD_CGC_GATE__LBSI_MASK |
1578                 UVD_CGC_GATE__LRBBM_MASK |
1579                 UVD_CGC_GATE__UDEC_RE_MASK |
1580                 UVD_CGC_GATE__UDEC_CM_MASK |
1581                 UVD_CGC_GATE__UDEC_IT_MASK |
1582                 UVD_CGC_GATE__UDEC_DB_MASK |
1583                 UVD_CGC_GATE__UDEC_MP_MASK |
1584                 UVD_CGC_GATE__WCB_MASK |
1585                 UVD_CGC_GATE__VCPU_MASK |
1586                 UVD_CGC_GATE__SCPU_MASK |
1587                 UVD_CGC_GATE__JPEG_MASK |
1588                 UVD_CGC_GATE__JPEG2_MASK;
1589
1590         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1591                                 UVD_SUVD_CGC_GATE__SIT_MASK |
1592                                 UVD_SUVD_CGC_GATE__SMP_MASK |
1593                                 UVD_SUVD_CGC_GATE__SCM_MASK |
1594                                 UVD_SUVD_CGC_GATE__SDB_MASK;
1595
1596         data |= cgc_flags;
1597         data1 |= suvd_flags;
1598
1599         WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, data);
1600         WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
1601 }
1602
1603 static void uvd_v7_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
1604 {
1605         u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
1606
1607         if (enable)
1608                 tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
1609                         GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
1610         else
1611                 tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
1612                          GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
1613
1614         WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
1615 }
1616
1617
1618 static int uvd_v7_0_set_clockgating_state(void *handle,
1619                                           enum amd_clockgating_state state)
1620 {
1621         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1622         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1623
1624         uvd_v7_0_set_bypass_mode(adev, enable);
1625
1626         if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
1627                 return 0;
1628
1629         if (enable) {
1630                 /* disable HW gating and enable Sw gating */
1631                 uvd_v7_0_set_sw_clock_gating(adev);
1632         } else {
1633                 /* wait for STATUS to clear */
1634                 if (uvd_v7_0_wait_for_idle(handle))
1635                         return -EBUSY;
1636
1637                 /* enable HW gates because UVD is idle */
1638                 /* uvd_v7_0_set_hw_clock_gating(adev); */
1639         }
1640
1641         return 0;
1642 }
1643
1644 static int uvd_v7_0_set_powergating_state(void *handle,
1645                                           enum amd_powergating_state state)
1646 {
1647         /* This doesn't actually powergate the UVD block.
1648          * That's done in the dpm code via the SMC.  This
1649          * just re-inits the block as necessary.  The actual
1650          * gating still happens in the dpm code.  We should
1651          * revisit this when there is a cleaner line between
1652          * the smc and the hw blocks
1653          */
1654         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1655
1656         if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
1657                 return 0;
1658
1659         WREG32_SOC15(UVD, ring->me, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
1660
1661         if (state == AMD_PG_STATE_GATE) {
1662                 uvd_v7_0_stop(adev);
1663                 return 0;
1664         } else {
1665                 return uvd_v7_0_start(adev);
1666         }
1667 }
1668 #endif
1669
1670 static int uvd_v7_0_set_clockgating_state(void *handle,
1671                                           enum amd_clockgating_state state)
1672 {
1673         /* needed for driver unload*/
1674         return 0;
1675 }
1676
1677 const struct amd_ip_funcs uvd_v7_0_ip_funcs = {
1678         .name = "uvd_v7_0",
1679         .early_init = uvd_v7_0_early_init,
1680         .late_init = NULL,
1681         .sw_init = uvd_v7_0_sw_init,
1682         .sw_fini = uvd_v7_0_sw_fini,
1683         .hw_init = uvd_v7_0_hw_init,
1684         .hw_fini = uvd_v7_0_hw_fini,
1685         .suspend = uvd_v7_0_suspend,
1686         .resume = uvd_v7_0_resume,
1687         .is_idle = NULL /* uvd_v7_0_is_idle */,
1688         .wait_for_idle = NULL /* uvd_v7_0_wait_for_idle */,
1689         .check_soft_reset = NULL /* uvd_v7_0_check_soft_reset */,
1690         .pre_soft_reset = NULL /* uvd_v7_0_pre_soft_reset */,
1691         .soft_reset = NULL /* uvd_v7_0_soft_reset */,
1692         .post_soft_reset = NULL /* uvd_v7_0_post_soft_reset */,
1693         .set_clockgating_state = uvd_v7_0_set_clockgating_state,
1694         .set_powergating_state = NULL /* uvd_v7_0_set_powergating_state */,
1695 };
1696
1697 static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = {
1698         .type = AMDGPU_RING_TYPE_UVD,
1699         .align_mask = 0xf,
1700         .nop = PACKET0(0x81ff, 0),
1701         .support_64bit_ptrs = false,
1702         .vmhub = AMDGPU_MMHUB,
1703         .get_rptr = uvd_v7_0_ring_get_rptr,
1704         .get_wptr = uvd_v7_0_ring_get_wptr,
1705         .set_wptr = uvd_v7_0_ring_set_wptr,
1706         .emit_frame_size =
1707                 6 + /* hdp invalidate */
1708                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1709                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
1710                 8 + /* uvd_v7_0_ring_emit_vm_flush */
1711                 14 + 14, /* uvd_v7_0_ring_emit_fence x2 vm fence */
1712         .emit_ib_size = 8, /* uvd_v7_0_ring_emit_ib */
1713         .emit_ib = uvd_v7_0_ring_emit_ib,
1714         .emit_fence = uvd_v7_0_ring_emit_fence,
1715         .emit_vm_flush = uvd_v7_0_ring_emit_vm_flush,
1716         .emit_hdp_flush = uvd_v7_0_ring_emit_hdp_flush,
1717         .test_ring = uvd_v7_0_ring_test_ring,
1718         .test_ib = amdgpu_uvd_ring_test_ib,
1719         .insert_nop = uvd_v7_0_ring_insert_nop,
1720         .pad_ib = amdgpu_ring_generic_pad_ib,
1721         .begin_use = amdgpu_uvd_ring_begin_use,
1722         .end_use = amdgpu_uvd_ring_end_use,
1723         .emit_wreg = uvd_v7_0_ring_emit_wreg,
1724         .emit_reg_wait = uvd_v7_0_ring_emit_reg_wait,
1725         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1726 };
1727
1728 static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = {
1729         .type = AMDGPU_RING_TYPE_UVD_ENC,
1730         .align_mask = 0x3f,
1731         .nop = HEVC_ENC_CMD_NO_OP,
1732         .support_64bit_ptrs = false,
1733         .vmhub = AMDGPU_MMHUB,
1734         .get_rptr = uvd_v7_0_enc_ring_get_rptr,
1735         .get_wptr = uvd_v7_0_enc_ring_get_wptr,
1736         .set_wptr = uvd_v7_0_enc_ring_set_wptr,
1737         .emit_frame_size =
1738                 3 + 3 + /* hdp flush / invalidate */
1739                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1740                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1741                 4 + /* uvd_v7_0_enc_ring_emit_vm_flush */
1742                 5 + 5 + /* uvd_v7_0_enc_ring_emit_fence x2 vm fence */
1743                 1, /* uvd_v7_0_enc_ring_insert_end */
1744         .emit_ib_size = 5, /* uvd_v7_0_enc_ring_emit_ib */
1745         .emit_ib = uvd_v7_0_enc_ring_emit_ib,
1746         .emit_fence = uvd_v7_0_enc_ring_emit_fence,
1747         .emit_vm_flush = uvd_v7_0_enc_ring_emit_vm_flush,
1748         .test_ring = uvd_v7_0_enc_ring_test_ring,
1749         .test_ib = uvd_v7_0_enc_ring_test_ib,
1750         .insert_nop = amdgpu_ring_insert_nop,
1751         .insert_end = uvd_v7_0_enc_ring_insert_end,
1752         .pad_ib = amdgpu_ring_generic_pad_ib,
1753         .begin_use = amdgpu_uvd_ring_begin_use,
1754         .end_use = amdgpu_uvd_ring_end_use,
1755         .emit_wreg = uvd_v7_0_enc_ring_emit_wreg,
1756         .emit_reg_wait = uvd_v7_0_enc_ring_emit_reg_wait,
1757         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1758 };
1759
1760 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev)
1761 {
1762         int i;
1763
1764         for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
1765                 adev->uvd.inst[i].ring.funcs = &uvd_v7_0_ring_vm_funcs;
1766                 adev->uvd.inst[i].ring.me = i;
1767                 DRM_INFO("UVD(%d) is enabled in VM mode\n", i);
1768         }
1769 }
1770
1771 static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev)
1772 {
1773         int i, j;
1774
1775         for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
1776                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
1777                         adev->uvd.inst[j].ring_enc[i].funcs = &uvd_v7_0_enc_ring_vm_funcs;
1778                         adev->uvd.inst[j].ring_enc[i].me = j;
1779                 }
1780
1781                 DRM_INFO("UVD(%d) ENC is enabled in VM mode\n", j);
1782         }
1783 }
1784
1785 static const struct amdgpu_irq_src_funcs uvd_v7_0_irq_funcs = {
1786         .set = uvd_v7_0_set_interrupt_state,
1787         .process = uvd_v7_0_process_interrupt,
1788 };
1789
1790 static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1791 {
1792         int i;
1793
1794         for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
1795                 adev->uvd.inst[i].irq.num_types = adev->uvd.num_enc_rings + 1;
1796                 adev->uvd.inst[i].irq.funcs = &uvd_v7_0_irq_funcs;
1797         }
1798 }
1799
1800 const struct amdgpu_ip_block_version uvd_v7_0_ip_block =
1801 {
1802                 .type = AMD_IP_BLOCK_TYPE_UVD,
1803                 .major = 7,
1804                 .minor = 0,
1805                 .rev = 0,
1806                 .funcs = &uvd_v7_0_ip_funcs,
1807 };