drm/amdgpu/vcn:Update latest spg mode stop for VCN
[muen/linux.git] / drivers / gpu / drm / amd / amdgpu / vcn_v1_0.c
1 /*
2  * Copyright 2016 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23
24 #include <linux/firmware.h>
25 #include <drm/drmP.h>
26 #include "amdgpu.h"
27 #include "amdgpu_vcn.h"
28 #include "soc15.h"
29 #include "soc15d.h"
30 #include "soc15_common.h"
31
32 #include "vcn/vcn_1_0_offset.h"
33 #include "vcn/vcn_1_0_sh_mask.h"
34 #include "hdp/hdp_4_0_offset.h"
35 #include "mmhub/mmhub_9_1_offset.h"
36 #include "mmhub/mmhub_9_1_sh_mask.h"
37
38 #include "ivsrcid/vcn/irqsrcs_vcn_1_0.h"
39
40 static int vcn_v1_0_stop(struct amdgpu_device *adev);
41 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
42 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
43 static void vcn_v1_0_set_jpeg_ring_funcs(struct amdgpu_device *adev);
44 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);
45 static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr);
46
47 /**
48  * vcn_v1_0_early_init - set function pointers
49  *
50  * @handle: amdgpu_device pointer
51  *
52  * Set ring and irq function pointers
53  */
54 static int vcn_v1_0_early_init(void *handle)
55 {
56         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
57
58         adev->vcn.num_enc_rings = 2;
59
60         vcn_v1_0_set_dec_ring_funcs(adev);
61         vcn_v1_0_set_enc_ring_funcs(adev);
62         vcn_v1_0_set_jpeg_ring_funcs(adev);
63         vcn_v1_0_set_irq_funcs(adev);
64
65         return 0;
66 }
67
68 /**
69  * vcn_v1_0_sw_init - sw init for VCN block
70  *
71  * @handle: amdgpu_device pointer
72  *
73  * Load firmware and sw initialization
74  */
75 static int vcn_v1_0_sw_init(void *handle)
76 {
77         struct amdgpu_ring *ring;
78         int i, r;
79         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
80
81         /* VCN DEC TRAP */
82         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.irq);
83         if (r)
84                 return r;
85
86         /* VCN ENC TRAP */
87         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
88                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
89                                         &adev->vcn.irq);
90                 if (r)
91                         return r;
92         }
93
94         /* VCN JPEG TRAP */
95         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 126, &adev->vcn.irq);
96         if (r)
97                 return r;
98
99         r = amdgpu_vcn_sw_init(adev);
100         if (r)
101                 return r;
102
103         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
104                 const struct common_firmware_header *hdr;
105                 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
106                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
107                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
108                 adev->firmware.fw_size +=
109                         ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
110                 DRM_INFO("PSP loading VCN firmware\n");
111         }
112
113         r = amdgpu_vcn_resume(adev);
114         if (r)
115                 return r;
116
117         ring = &adev->vcn.ring_dec;
118         sprintf(ring->name, "vcn_dec");
119         r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
120         if (r)
121                 return r;
122
123         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
124                 ring = &adev->vcn.ring_enc[i];
125                 sprintf(ring->name, "vcn_enc%d", i);
126                 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
127                 if (r)
128                         return r;
129         }
130
131         ring = &adev->vcn.ring_jpeg;
132         sprintf(ring->name, "vcn_jpeg");
133         r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
134         if (r)
135                 return r;
136
137         return r;
138 }
139
140 /**
141  * vcn_v1_0_sw_fini - sw fini for VCN block
142  *
143  * @handle: amdgpu_device pointer
144  *
145  * VCN suspend and free up sw allocation
146  */
147 static int vcn_v1_0_sw_fini(void *handle)
148 {
149         int r;
150         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
151
152         r = amdgpu_vcn_suspend(adev);
153         if (r)
154                 return r;
155
156         r = amdgpu_vcn_sw_fini(adev);
157
158         return r;
159 }
160
161 /**
162  * vcn_v1_0_hw_init - start and test VCN block
163  *
164  * @handle: amdgpu_device pointer
165  *
166  * Initialize the hardware, boot up the VCPU and do some testing
167  */
168 static int vcn_v1_0_hw_init(void *handle)
169 {
170         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
171         struct amdgpu_ring *ring = &adev->vcn.ring_dec;
172         int i, r;
173
174         ring->ready = true;
175         r = amdgpu_ring_test_ring(ring);
176         if (r) {
177                 ring->ready = false;
178                 goto done;
179         }
180
181         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
182                 ring = &adev->vcn.ring_enc[i];
183                 ring->ready = true;
184                 r = amdgpu_ring_test_ring(ring);
185                 if (r) {
186                         ring->ready = false;
187                         goto done;
188                 }
189         }
190
191         ring = &adev->vcn.ring_jpeg;
192         ring->ready = true;
193         r = amdgpu_ring_test_ring(ring);
194         if (r) {
195                 ring->ready = false;
196                 goto done;
197         }
198
199 done:
200         if (!r)
201                 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
202                         (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
203
204         return r;
205 }
206
207 /**
208  * vcn_v1_0_hw_fini - stop the hardware block
209  *
210  * @handle: amdgpu_device pointer
211  *
212  * Stop the VCN block, mark ring as not ready any more
213  */
214 static int vcn_v1_0_hw_fini(void *handle)
215 {
216         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
217         struct amdgpu_ring *ring = &adev->vcn.ring_dec;
218
219         if (RREG32_SOC15(VCN, 0, mmUVD_STATUS))
220                 vcn_v1_0_stop(adev);
221
222         ring->ready = false;
223
224         return 0;
225 }
226
227 /**
228  * vcn_v1_0_suspend - suspend VCN block
229  *
230  * @handle: amdgpu_device pointer
231  *
232  * HW fini and suspend VCN block
233  */
234 static int vcn_v1_0_suspend(void *handle)
235 {
236         int r;
237         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
238
239         r = vcn_v1_0_hw_fini(adev);
240         if (r)
241                 return r;
242
243         r = amdgpu_vcn_suspend(adev);
244
245         return r;
246 }
247
248 /**
249  * vcn_v1_0_resume - resume VCN block
250  *
251  * @handle: amdgpu_device pointer
252  *
253  * Resume firmware and hw init VCN block
254  */
255 static int vcn_v1_0_resume(void *handle)
256 {
257         int r;
258         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
259
260         r = amdgpu_vcn_resume(adev);
261         if (r)
262                 return r;
263
264         r = vcn_v1_0_hw_init(adev);
265
266         return r;
267 }
268
269 /**
270  * vcn_v1_0_mc_resume_spg_mode - memory controller programming
271  *
272  * @adev: amdgpu_device pointer
273  *
274  * Let the VCN memory controller know it's offsets
275  */
276 static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev)
277 {
278         uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
279         uint32_t offset;
280
281         /* cache window 0: fw */
282         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
283                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
284                              (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
285                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
286                              (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
287                 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
288                 offset = 0;
289         } else {
290                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
291                         lower_32_bits(adev->vcn.gpu_addr));
292                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
293                         upper_32_bits(adev->vcn.gpu_addr));
294                 offset = size;
295                 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
296                              AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
297         }
298
299         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
300
301         /* cache window 1: stack */
302         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
303                      lower_32_bits(adev->vcn.gpu_addr + offset));
304         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
305                      upper_32_bits(adev->vcn.gpu_addr + offset));
306         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
307         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
308
309         /* cache window 2: context */
310         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
311                      lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
312         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
313                      upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
314         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
315         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
316
317         WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
318                         adev->gfx.config.gb_addr_config);
319         WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
320                         adev->gfx.config.gb_addr_config);
321         WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
322                         adev->gfx.config.gb_addr_config);
323 }
324
325 static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev)
326 {
327         uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
328         uint32_t offset;
329
330         /* cache window 0: fw */
331         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
332                 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
333                              (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo),
334                              0xFFFFFFFF, 0);
335                 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
336                              (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi),
337                              0xFFFFFFFF, 0);
338                 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0,
339                              0xFFFFFFFF, 0);
340                 offset = 0;
341         } else {
342                 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
343                         lower_32_bits(adev->vcn.gpu_addr), 0xFFFFFFFF, 0);
344                 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
345                         upper_32_bits(adev->vcn.gpu_addr), 0xFFFFFFFF, 0);
346                 offset = size;
347                 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
348                              AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0xFFFFFFFF, 0);
349         }
350
351         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0);
352
353         /* cache window 1: stack */
354         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
355                      lower_32_bits(adev->vcn.gpu_addr + offset), 0xFFFFFFFF, 0);
356         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
357                      upper_32_bits(adev->vcn.gpu_addr + offset), 0xFFFFFFFF, 0);
358         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0,
359                              0xFFFFFFFF, 0);
360         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE,
361                              0xFFFFFFFF, 0);
362
363         /* cache window 2: context */
364         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
365                      lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
366                              0xFFFFFFFF, 0);
367         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
368                      upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
369                              0xFFFFFFFF, 0);
370         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0);
371         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE,
372                              0xFFFFFFFF, 0);
373
374         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
375                         adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
376         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
377                         adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
378         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
379                         adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
380         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_ADDR_CONFIG,
381                         adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
382         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG,
383                         adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
384 }
385
386 /**
387  * vcn_v1_0_disable_clock_gating - disable VCN clock gating
388  *
389  * @adev: amdgpu_device pointer
390  * @sw: enable SW clock gating
391  *
392  * Disable clock gating for VCN block
393  */
394 static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev)
395 {
396         uint32_t data;
397
398         /* JPEG disable CGC */
399         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
400
401         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
402                 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
403         else
404                 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK;
405
406         data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
407         data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
408         WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);
409
410         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
411         data &= ~(JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK);
412         WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);
413
414         /* UVD disable CGC */
415         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
416         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
417                 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
418         else
419                 data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
420
421         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
422         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
423         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
424
425         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);
426         data &= ~(UVD_CGC_GATE__SYS_MASK
427                 | UVD_CGC_GATE__UDEC_MASK
428                 | UVD_CGC_GATE__MPEG2_MASK
429                 | UVD_CGC_GATE__REGS_MASK
430                 | UVD_CGC_GATE__RBC_MASK
431                 | UVD_CGC_GATE__LMI_MC_MASK
432                 | UVD_CGC_GATE__LMI_UMC_MASK
433                 | UVD_CGC_GATE__IDCT_MASK
434                 | UVD_CGC_GATE__MPRD_MASK
435                 | UVD_CGC_GATE__MPC_MASK
436                 | UVD_CGC_GATE__LBSI_MASK
437                 | UVD_CGC_GATE__LRBBM_MASK
438                 | UVD_CGC_GATE__UDEC_RE_MASK
439                 | UVD_CGC_GATE__UDEC_CM_MASK
440                 | UVD_CGC_GATE__UDEC_IT_MASK
441                 | UVD_CGC_GATE__UDEC_DB_MASK
442                 | UVD_CGC_GATE__UDEC_MP_MASK
443                 | UVD_CGC_GATE__WCB_MASK
444                 | UVD_CGC_GATE__VCPU_MASK
445                 | UVD_CGC_GATE__SCPU_MASK);
446         WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);
447
448         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
449         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
450                 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
451                 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
452                 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
453                 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
454                 | UVD_CGC_CTRL__SYS_MODE_MASK
455                 | UVD_CGC_CTRL__UDEC_MODE_MASK
456                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
457                 | UVD_CGC_CTRL__REGS_MODE_MASK
458                 | UVD_CGC_CTRL__RBC_MODE_MASK
459                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
460                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
461                 | UVD_CGC_CTRL__IDCT_MODE_MASK
462                 | UVD_CGC_CTRL__MPRD_MODE_MASK
463                 | UVD_CGC_CTRL__MPC_MODE_MASK
464                 | UVD_CGC_CTRL__LBSI_MODE_MASK
465                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
466                 | UVD_CGC_CTRL__WCB_MODE_MASK
467                 | UVD_CGC_CTRL__VCPU_MODE_MASK
468                 | UVD_CGC_CTRL__SCPU_MODE_MASK);
469         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
470
471         /* turn on */
472         data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);
473         data |= (UVD_SUVD_CGC_GATE__SRE_MASK
474                 | UVD_SUVD_CGC_GATE__SIT_MASK
475                 | UVD_SUVD_CGC_GATE__SMP_MASK
476                 | UVD_SUVD_CGC_GATE__SCM_MASK
477                 | UVD_SUVD_CGC_GATE__SDB_MASK
478                 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
479                 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
480                 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
481                 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
482                 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
483                 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
484                 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
485                 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
486                 | UVD_SUVD_CGC_GATE__SCLR_MASK
487                 | UVD_SUVD_CGC_GATE__UVD_SC_MASK
488                 | UVD_SUVD_CGC_GATE__ENT_MASK
489                 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
490                 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
491                 | UVD_SUVD_CGC_GATE__SITE_MASK
492                 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
493                 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
494                 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
495                 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
496                 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
497         WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data);
498
499         data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
500         data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
501                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
502                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
503                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
504                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
505                 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
506                 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
507                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
508                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
509                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
510         WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
511 }
512
513 /**
514  * vcn_v1_0_enable_clock_gating - enable VCN clock gating
515  *
516  * @adev: amdgpu_device pointer
517  * @sw: enable SW clock gating
518  *
519  * Enable clock gating for VCN block
520  */
521 static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev)
522 {
523         uint32_t data = 0;
524
525         /* enable JPEG CGC */
526         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
527         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
528                 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
529         else
530                 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
531         data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
532         data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
533         WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);
534
535         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
536         data |= (JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK);
537         WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);
538
539         /* enable UVD CGC */
540         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
541         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
542                 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
543         else
544                 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
545         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
546         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
547         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
548
549         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
550         data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
551                 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
552                 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
553                 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
554                 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
555                 | UVD_CGC_CTRL__SYS_MODE_MASK
556                 | UVD_CGC_CTRL__UDEC_MODE_MASK
557                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
558                 | UVD_CGC_CTRL__REGS_MODE_MASK
559                 | UVD_CGC_CTRL__RBC_MODE_MASK
560                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
561                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
562                 | UVD_CGC_CTRL__IDCT_MODE_MASK
563                 | UVD_CGC_CTRL__MPRD_MODE_MASK
564                 | UVD_CGC_CTRL__MPC_MODE_MASK
565                 | UVD_CGC_CTRL__LBSI_MODE_MASK
566                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
567                 | UVD_CGC_CTRL__WCB_MODE_MASK
568                 | UVD_CGC_CTRL__VCPU_MODE_MASK
569                 | UVD_CGC_CTRL__SCPU_MODE_MASK);
570         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
571
572         data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
573         data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
574                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
575                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
576                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
577                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
578                 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
579                 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
580                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
581                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
582                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
583         WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
584 }
585
586 static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel)
587 {
588         uint32_t reg_data = 0;
589
590         /* disable JPEG CGC */
591         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
592                 reg_data = 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
593         else
594                 reg_data = 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
595         reg_data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
596         reg_data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
597         WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
598
599         WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel);
600
601         /* enable sw clock gating control */
602         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
603                 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
604         else
605                 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
606         reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
607         reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
608         reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
609                  UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
610                  UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
611                  UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
612                  UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
613                  UVD_CGC_CTRL__SYS_MODE_MASK |
614                  UVD_CGC_CTRL__UDEC_MODE_MASK |
615                  UVD_CGC_CTRL__MPEG2_MODE_MASK |
616                  UVD_CGC_CTRL__REGS_MODE_MASK |
617                  UVD_CGC_CTRL__RBC_MODE_MASK |
618                  UVD_CGC_CTRL__LMI_MC_MODE_MASK |
619                  UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
620                  UVD_CGC_CTRL__IDCT_MODE_MASK |
621                  UVD_CGC_CTRL__MPRD_MODE_MASK |
622                  UVD_CGC_CTRL__MPC_MODE_MASK |
623                  UVD_CGC_CTRL__LBSI_MODE_MASK |
624                  UVD_CGC_CTRL__LRBBM_MODE_MASK |
625                  UVD_CGC_CTRL__WCB_MODE_MASK |
626                  UVD_CGC_CTRL__VCPU_MODE_MASK |
627                  UVD_CGC_CTRL__SCPU_MODE_MASK);
628         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
629
630         /* turn off clock gating */
631         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel);
632
633         /* turn on SUVD clock gating */
634         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel);
635
636         /* turn on sw mode in UVD_SUVD_CGC_CTRL */
637         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel);
638 }
639
640 static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev)
641 {
642         uint32_t data = 0;
643         int ret;
644
645         if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
646                 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
647                         | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
648                         | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
649                         | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
650                         | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
651                         | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
652                         | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
653                         | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
654                         | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
655                         | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
656                         | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
657
658                 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
659                 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF, ret);
660         } else {
661                 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
662                         | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
663                         | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
664                         | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
665                         | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
666                         | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
667                         | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
668                         | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
669                         | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
670                         | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
671                         | 1 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
672                 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
673                 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0,  0xFFFFFFFF, ret);
674         }
675
676         /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS , UVDU_PWR_STATUS are 0 (power on) */
677
678         data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
679         data &= ~0x103;
680         if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
681                 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | UVD_POWER_STATUS__UVD_PG_EN_MASK;
682
683         WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
684 }
685
686 static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev)
687 {
688         uint32_t data = 0;
689         int ret;
690
691         if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
692                 /* Before power off, this indicator has to be turned on */
693                 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
694                 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
695                 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
696                 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
697
698
699                 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
700                         | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
701                         | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
702                         | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
703                         | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
704                         | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
705                         | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
706                         | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
707                         | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
708                         | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
709                         | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
710
711                 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
712
713                 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
714                         | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
715                         | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
716                         | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
717                         | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
718                         | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT
719                         | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT
720                         | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
721                         | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
722                         | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT
723                         | 2 << UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT);
724                 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF, ret);
725         }
726 }
727
728 /**
729  * vcn_v1_0_start - start VCN block
730  *
731  * @adev: amdgpu_device pointer
732  *
733  * Setup and start the VCN block
734  */
735 static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
736 {
737         struct amdgpu_ring *ring = &adev->vcn.ring_dec;
738         uint32_t rb_bufsz, tmp;
739         uint32_t lmi_swap_cntl;
740         int i, j, r;
741
742         /* disable byte swapping */
743         lmi_swap_cntl = 0;
744
745         vcn_1_0_disable_static_power_gating(adev);
746         /* disable clock gating */
747         vcn_v1_0_disable_clock_gating(adev);
748
749         vcn_v1_0_mc_resume_spg_mode(adev);
750
751         /* disable interupt */
752         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
753                         ~UVD_MASTINT_EN__VCPU_EN_MASK);
754
755         /* stall UMC and register bus before resetting VCPU */
756         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
757                         UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
758                         ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
759         mdelay(1);
760
761         /* put LMI, VCPU, RBC etc... into reset */
762         WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
763                 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
764                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
765                 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
766                 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
767                 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
768                 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
769                 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
770                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
771         mdelay(5);
772
773         /* initialize VCN memory controller */
774         WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL,
775                 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
776                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
777                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
778                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
779                 UVD_LMI_CTRL__REQ_MODE_MASK |
780                 0x00100000L);
781
782 #ifdef __BIG_ENDIAN
783         /* swap (8 in 32) RB and IB */
784         lmi_swap_cntl = 0xa;
785 #endif
786         WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
787
788         tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);
789         tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
790         tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
791         WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp);
792
793         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,
794                 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
795                 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
796                 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
797                 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
798
799         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0,
800                 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
801                 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
802                 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
803                 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
804
805         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX,
806                 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
807                 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
808                 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
809
810         /* take all subblocks out of reset, except VCPU */
811         WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
812                         UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
813         mdelay(5);
814
815         /* enable VCPU clock */
816         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL,
817                         UVD_VCPU_CNTL__CLK_EN_MASK);
818
819         /* enable UMC */
820         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
821                         ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
822
823         /* boot up the VCPU */
824         WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, 0);
825         mdelay(10);
826
827         for (i = 0; i < 10; ++i) {
828                 uint32_t status;
829
830                 for (j = 0; j < 100; ++j) {
831                         status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
832                         if (status & UVD_STATUS__IDLE)
833                                 break;
834                         mdelay(10);
835                 }
836                 r = 0;
837                 if (status & UVD_STATUS__IDLE)
838                         break;
839
840                 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
841                 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
842                                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
843                                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
844                 mdelay(10);
845                 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
846                                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
847                 mdelay(10);
848                 r = -1;
849         }
850
851         if (r) {
852                 DRM_ERROR("VCN decode not responding, giving up!!!\n");
853                 return r;
854         }
855         /* enable master interrupt */
856         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
857                 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
858                 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
859
860         /* enable system interrupt for JRBC, TODO: move to set interrupt*/
861         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN),
862                 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK,
863                 ~UVD_SYS_INT_EN__UVD_JRBC_EN_MASK);
864
865         /* clear the bit 4 of VCN_STATUS */
866         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
867                         ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
868
869         /* force RBC into idle state */
870         rb_bufsz = order_base_2(ring->ring_size);
871         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
872         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
873         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
874         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
875         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
876         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
877         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
878
879         /* set the write pointer delay */
880         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
881
882         /* set the wb address */
883         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
884                         (upper_32_bits(ring->gpu_addr) >> 2));
885
886         /* programm the RB_BASE for ring buffer */
887         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
888                         lower_32_bits(ring->gpu_addr));
889         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
890                         upper_32_bits(ring->gpu_addr));
891
892         /* Initialize the ring buffer's read and write pointers */
893         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
894
895         WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
896
897         ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
898         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
899                         lower_32_bits(ring->wptr));
900
901         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
902                         ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
903
904         ring = &adev->vcn.ring_enc[0];
905         WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
906         WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
907         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
908         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
909         WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
910
911         ring = &adev->vcn.ring_enc[1];
912         WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
913         WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
914         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
915         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
916         WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
917
918         ring = &adev->vcn.ring_jpeg;
919         WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
920         WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
921                         UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
922         WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, lower_32_bits(ring->gpu_addr));
923         WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr));
924         WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, 0);
925         WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0);
926         WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
927
928         /* initialize wptr */
929         ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
930
931         /* copy patch commands to the jpeg ring */
932         vcn_v1_0_jpeg_ring_set_patch_ring(ring,
933                 (ring->wptr + ring->max_dw * amdgpu_sched_hw_submission));
934
935         return 0;
936 }
937
938 static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
939 {
940         struct amdgpu_ring *ring = &adev->vcn.ring_dec;
941         uint32_t rb_bufsz, tmp, reg_data;
942         uint32_t lmi_swap_cntl;
943
944         /* disable byte swapping */
945         lmi_swap_cntl = 0;
946
947         vcn_1_0_enable_static_power_gating(adev);
948
949         /* enable dynamic power gating mode */
950         reg_data = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
951         reg_data |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
952         reg_data |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
953         WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data);
954
955         /* enable clock gating */
956         vcn_v1_0_clock_gating_dpg_mode(adev, 0);
957
958         /* enable VCPU clock */
959         reg_data = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
960         reg_data |= UVD_VCPU_CNTL__CLK_EN_MASK;
961         reg_data |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
962         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CNTL, reg_data, 0xFFFFFFFF, 0);
963
964         /* disable interupt */
965         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN,
966                         0, UVD_MASTINT_EN__VCPU_EN_MASK, 0);
967
968         /* stall UMC and register bus before resetting VCPU */
969         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2,
970                         UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0);
971
972         /* put LMI, VCPU, RBC etc... into reset */
973         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET,
974                 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
975                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
976                 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
977                 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
978                 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
979                 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
980                 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
981                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,
982                 0xFFFFFFFF, 0);
983
984         /* initialize VCN memory controller */
985         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL,
986                 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
987                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
988                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
989                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
990                 UVD_LMI_CTRL__REQ_MODE_MASK |
991                 0x00100000L, 0xFFFFFFFF, 0);
992
993 #ifdef __BIG_ENDIAN
994         /* swap (8 in 32) RB and IB */
995         lmi_swap_cntl = 0xa;
996 #endif
997         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0);
998
999         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_CNTL,
1000                 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0xFFFFFFFF, 0);
1001
1002         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXA0,
1003                 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1004                  (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1005                  (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1006                  (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0xFFFFFFFF, 0);
1007
1008         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXB0,
1009                 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1010                  (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1011                  (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1012                  (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0xFFFFFFFF, 0);
1013
1014         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUX,
1015                 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1016                  (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1017                  (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0xFFFFFFFF, 0);
1018
1019         vcn_v1_0_mc_resume_dpg_mode(adev);
1020
1021         /* take all subblocks out of reset, except VCPU */
1022         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET,
1023                         UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 0xFFFFFFFF, 0);
1024
1025         /* enable VCPU clock */
1026         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CNTL,
1027                         UVD_VCPU_CNTL__CLK_EN_MASK, 0xFFFFFFFF, 0);
1028
1029         /* enable UMC */
1030         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2,
1031                         0, UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0);
1032
1033         /* boot up the VCPU */
1034         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0);
1035
1036         /* enable master interrupt */
1037         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN,
1038                         (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
1039                         (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), 0);
1040
1041         vcn_v1_0_clock_gating_dpg_mode(adev, 1);
1042         /* setup mmUVD_LMI_CTRL */
1043         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL,
1044                         (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1045                                 UVD_LMI_CTRL__CRC_RESET_MASK |
1046                                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1047                                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1048                                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
1049                                 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
1050                                 0x00100000L), 0xFFFFFFFF, 1);
1051
1052         tmp = adev->gfx.config.gb_addr_config;
1053         /* setup VCN global tiling registers */
1054         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);
1055         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);
1056
1057         /* enable System Interrupt for JRBC */
1058         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SYS_INT_EN,
1059                                                                         UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 0xFFFFFFFF, 1);
1060
1061         /* force RBC into idle state */
1062         rb_bufsz = order_base_2(ring->ring_size);
1063         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1064         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1065         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1066         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
1067         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1068         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1069         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
1070
1071         /* set the write pointer delay */
1072         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
1073
1074         /* set the wb address */
1075         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
1076                                                                 (upper_32_bits(ring->gpu_addr) >> 2));
1077
1078         /* programm the RB_BASE for ring buffer */
1079         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1080                                                                 lower_32_bits(ring->gpu_addr));
1081         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1082                                                                 upper_32_bits(ring->gpu_addr));
1083
1084         /* Initialize the ring buffer's read and write pointers */
1085         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
1086
1087         WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
1088
1089         ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1090         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1091                                                                 lower_32_bits(ring->wptr));
1092
1093         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
1094                         ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
1095
1096         /* initialize wptr */
1097         ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
1098
1099         /* copy patch commands to the jpeg ring */
1100         vcn_v1_0_jpeg_ring_set_patch_ring(ring,
1101                 (ring->wptr + ring->max_dw * amdgpu_sched_hw_submission));
1102
1103         return 0;
1104 }
1105
1106 static int vcn_v1_0_start(struct amdgpu_device *adev)
1107 {
1108         int r;
1109
1110         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1111                 r = vcn_v1_0_start_dpg_mode(adev);
1112         else
1113                 r = vcn_v1_0_start_spg_mode(adev);
1114         return r;
1115 }
1116
1117 /**
1118  * vcn_v1_0_stop - stop VCN block
1119  *
1120  * @adev: amdgpu_device pointer
1121  *
1122  * stop the VCN block
1123  */
1124 static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev)
1125 {
1126         int ret_code, tmp;
1127
1128         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, ret_code);
1129
1130         tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1131                 UVD_LMI_STATUS__READ_CLEAN_MASK |
1132                 UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1133                 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1134         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code);
1135
1136         /* put VCPU into reset */
1137         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1138                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1139                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1140
1141         tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
1142                 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1143         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code);
1144
1145         /* disable VCPU clock */
1146         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
1147                 ~UVD_VCPU_CNTL__CLK_EN_MASK);
1148
1149         /* reset LMI UMC/LMI */
1150         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1151                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,
1152                 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
1153
1154         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1155                 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,
1156                 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
1157
1158         WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0);
1159
1160         vcn_v1_0_enable_clock_gating(adev);
1161         vcn_1_0_enable_static_power_gating(adev);
1162         return 0;
1163 }
1164
1165 static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev)
1166 {
1167         int ret_code;
1168
1169         /* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */
1170         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1171                         UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1172                         UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1173
1174         /* disable dynamic power gating mode */
1175         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
1176                         ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1177
1178         return 0;
1179 }
1180
1181 static int vcn_v1_0_stop(struct amdgpu_device *adev)
1182 {
1183         int r;
1184
1185         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1186                 r = vcn_v1_0_stop_dpg_mode(adev);
1187         else
1188                 r = vcn_v1_0_stop_spg_mode(adev);
1189
1190         return r;
1191 }
1192
1193 static bool vcn_v1_0_is_idle(void *handle)
1194 {
1195         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1196
1197         return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
1198 }
1199
1200 static int vcn_v1_0_wait_for_idle(void *handle)
1201 {
1202         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1203         int ret = 0;
1204
1205         SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
1206                 UVD_STATUS__IDLE, ret);
1207
1208         return ret;
1209 }
1210
1211 static int vcn_v1_0_set_clockgating_state(void *handle,
1212                                           enum amd_clockgating_state state)
1213 {
1214         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1215         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1216
1217         if (enable) {
1218                 /* wait for STATUS to clear */
1219                 if (vcn_v1_0_is_idle(handle))
1220                         return -EBUSY;
1221                 vcn_v1_0_enable_clock_gating(adev);
1222         } else {
1223                 /* disable HW gating and enable Sw gating */
1224                 vcn_v1_0_disable_clock_gating(adev);
1225         }
1226         return 0;
1227 }
1228
1229 /**
1230  * vcn_v1_0_dec_ring_get_rptr - get read pointer
1231  *
1232  * @ring: amdgpu_ring pointer
1233  *
1234  * Returns the current hardware read pointer
1235  */
1236 static uint64_t vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
1237 {
1238         struct amdgpu_device *adev = ring->adev;
1239
1240         return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1241 }
1242
1243 /**
1244  * vcn_v1_0_dec_ring_get_wptr - get write pointer
1245  *
1246  * @ring: amdgpu_ring pointer
1247  *
1248  * Returns the current hardware write pointer
1249  */
1250 static uint64_t vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
1251 {
1252         struct amdgpu_device *adev = ring->adev;
1253
1254         return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
1255 }
1256
1257 /**
1258  * vcn_v1_0_dec_ring_set_wptr - set write pointer
1259  *
1260  * @ring: amdgpu_ring pointer
1261  *
1262  * Commits the write pointer to the hardware
1263  */
1264 static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
1265 {
1266         struct amdgpu_device *adev = ring->adev;
1267
1268         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1269                 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2,
1270                         lower_32_bits(ring->wptr) | 0x80000000);
1271
1272         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1273 }
1274
1275 /**
1276  * vcn_v1_0_dec_ring_insert_start - insert a start command
1277  *
1278  * @ring: amdgpu_ring pointer
1279  *
1280  * Write a start command to the ring.
1281  */
1282 static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring)
1283 {
1284         struct amdgpu_device *adev = ring->adev;
1285
1286         amdgpu_ring_write(ring,
1287                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1288         amdgpu_ring_write(ring, 0);
1289         amdgpu_ring_write(ring,
1290                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1291         amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1);
1292 }
1293
1294 /**
1295  * vcn_v1_0_dec_ring_insert_end - insert a end command
1296  *
1297  * @ring: amdgpu_ring pointer
1298  *
1299  * Write a end command to the ring.
1300  */
1301 static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring)
1302 {
1303         struct amdgpu_device *adev = ring->adev;
1304
1305         amdgpu_ring_write(ring,
1306                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1307         amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1);
1308 }
1309
1310 /**
1311  * vcn_v1_0_dec_ring_emit_fence - emit an fence & trap command
1312  *
1313  * @ring: amdgpu_ring pointer
1314  * @fence: fence to emit
1315  *
1316  * Write a fence and a trap command to the ring.
1317  */
1318 static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1319                                      unsigned flags)
1320 {
1321         struct amdgpu_device *adev = ring->adev;
1322
1323         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1324
1325         amdgpu_ring_write(ring,
1326                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
1327         amdgpu_ring_write(ring, seq);
1328         amdgpu_ring_write(ring,
1329                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1330         amdgpu_ring_write(ring, addr & 0xffffffff);
1331         amdgpu_ring_write(ring,
1332                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1333         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1334         amdgpu_ring_write(ring,
1335                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1336         amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1);
1337
1338         amdgpu_ring_write(ring,
1339                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1340         amdgpu_ring_write(ring, 0);
1341         amdgpu_ring_write(ring,
1342                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1343         amdgpu_ring_write(ring, 0);
1344         amdgpu_ring_write(ring,
1345                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1346         amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1);
1347 }
1348
1349 /**
1350  * vcn_v1_0_dec_ring_emit_ib - execute indirect buffer
1351  *
1352  * @ring: amdgpu_ring pointer
1353  * @ib: indirect buffer to execute
1354  *
1355  * Write ring commands to execute the indirect buffer
1356  */
1357 static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
1358                                   struct amdgpu_ib *ib,
1359                                   unsigned vmid, bool ctx_switch)
1360 {
1361         struct amdgpu_device *adev = ring->adev;
1362
1363         amdgpu_ring_write(ring,
1364                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));
1365         amdgpu_ring_write(ring, vmid);
1366
1367         amdgpu_ring_write(ring,
1368                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
1369         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1370         amdgpu_ring_write(ring,
1371                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
1372         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1373         amdgpu_ring_write(ring,
1374                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0));
1375         amdgpu_ring_write(ring, ib->length_dw);
1376 }
1377
1378 static void vcn_v1_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring,
1379                                             uint32_t reg, uint32_t val,
1380                                             uint32_t mask)
1381 {
1382         struct amdgpu_device *adev = ring->adev;
1383
1384         amdgpu_ring_write(ring,
1385                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1386         amdgpu_ring_write(ring, reg << 2);
1387         amdgpu_ring_write(ring,
1388                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1389         amdgpu_ring_write(ring, val);
1390         amdgpu_ring_write(ring,
1391                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0));
1392         amdgpu_ring_write(ring, mask);
1393         amdgpu_ring_write(ring,
1394                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1395         amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1);
1396 }
1397
1398 static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
1399                                             unsigned vmid, uint64_t pd_addr)
1400 {
1401         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1402         uint32_t data0, data1, mask;
1403
1404         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1405
1406         /* wait for register write */
1407         data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
1408         data1 = lower_32_bits(pd_addr);
1409         mask = 0xffffffff;
1410         vcn_v1_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
1411 }
1412
1413 static void vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
1414                                         uint32_t reg, uint32_t val)
1415 {
1416         struct amdgpu_device *adev = ring->adev;
1417
1418         amdgpu_ring_write(ring,
1419                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1420         amdgpu_ring_write(ring, reg << 2);
1421         amdgpu_ring_write(ring,
1422                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1423         amdgpu_ring_write(ring, val);
1424         amdgpu_ring_write(ring,
1425                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1426         amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1);
1427 }
1428
1429 /**
1430  * vcn_v1_0_enc_ring_get_rptr - get enc read pointer
1431  *
1432  * @ring: amdgpu_ring pointer
1433  *
1434  * Returns the current hardware enc read pointer
1435  */
1436 static uint64_t vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
1437 {
1438         struct amdgpu_device *adev = ring->adev;
1439
1440         if (ring == &adev->vcn.ring_enc[0])
1441                 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
1442         else
1443                 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
1444 }
1445
1446  /**
1447  * vcn_v1_0_enc_ring_get_wptr - get enc write pointer
1448  *
1449  * @ring: amdgpu_ring pointer
1450  *
1451  * Returns the current hardware enc write pointer
1452  */
1453 static uint64_t vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
1454 {
1455         struct amdgpu_device *adev = ring->adev;
1456
1457         if (ring == &adev->vcn.ring_enc[0])
1458                 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1459         else
1460                 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1461 }
1462
1463  /**
1464  * vcn_v1_0_enc_ring_set_wptr - set enc write pointer
1465  *
1466  * @ring: amdgpu_ring pointer
1467  *
1468  * Commits the enc write pointer to the hardware
1469  */
1470 static void vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
1471 {
1472         struct amdgpu_device *adev = ring->adev;
1473
1474         if (ring == &adev->vcn.ring_enc[0])
1475                 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR,
1476                         lower_32_bits(ring->wptr));
1477         else
1478                 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2,
1479                         lower_32_bits(ring->wptr));
1480 }
1481
1482 /**
1483  * vcn_v1_0_enc_ring_emit_fence - emit an enc fence & trap command
1484  *
1485  * @ring: amdgpu_ring pointer
1486  * @fence: fence to emit
1487  *
1488  * Write enc a fence and a trap command to the ring.
1489  */
1490 static void vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1491                         u64 seq, unsigned flags)
1492 {
1493         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1494
1495         amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE);
1496         amdgpu_ring_write(ring, addr);
1497         amdgpu_ring_write(ring, upper_32_bits(addr));
1498         amdgpu_ring_write(ring, seq);
1499         amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP);
1500 }
1501
1502 static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1503 {
1504         amdgpu_ring_write(ring, VCN_ENC_CMD_END);
1505 }
1506
1507 /**
1508  * vcn_v1_0_enc_ring_emit_ib - enc execute indirect buffer
1509  *
1510  * @ring: amdgpu_ring pointer
1511  * @ib: indirect buffer to execute
1512  *
1513  * Write enc ring commands to execute the indirect buffer
1514  */
1515 static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1516                 struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch)
1517 {
1518         amdgpu_ring_write(ring, VCN_ENC_CMD_IB);
1519         amdgpu_ring_write(ring, vmid);
1520         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1521         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1522         amdgpu_ring_write(ring, ib->length_dw);
1523 }
1524
1525 static void vcn_v1_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring,
1526                                             uint32_t reg, uint32_t val,
1527                                             uint32_t mask)
1528 {
1529         amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
1530         amdgpu_ring_write(ring, reg << 2);
1531         amdgpu_ring_write(ring, mask);
1532         amdgpu_ring_write(ring, val);
1533 }
1534
1535 static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1536                                             unsigned int vmid, uint64_t pd_addr)
1537 {
1538         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1539
1540         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1541
1542         /* wait for reg writes */
1543         vcn_v1_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2,
1544                                         lower_32_bits(pd_addr), 0xffffffff);
1545 }
1546
1547 static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
1548                                         uint32_t reg, uint32_t val)
1549 {
1550         amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
1551         amdgpu_ring_write(ring, reg << 2);
1552         amdgpu_ring_write(ring, val);
1553 }
1554
1555
1556 /**
1557  * vcn_v1_0_jpeg_ring_get_rptr - get read pointer
1558  *
1559  * @ring: amdgpu_ring pointer
1560  *
1561  * Returns the current hardware read pointer
1562  */
1563 static uint64_t vcn_v1_0_jpeg_ring_get_rptr(struct amdgpu_ring *ring)
1564 {
1565         struct amdgpu_device *adev = ring->adev;
1566
1567         return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR);
1568 }
1569
1570 /**
1571  * vcn_v1_0_jpeg_ring_get_wptr - get write pointer
1572  *
1573  * @ring: amdgpu_ring pointer
1574  *
1575  * Returns the current hardware write pointer
1576  */
1577 static uint64_t vcn_v1_0_jpeg_ring_get_wptr(struct amdgpu_ring *ring)
1578 {
1579         struct amdgpu_device *adev = ring->adev;
1580
1581         return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
1582 }
1583
1584 /**
1585  * vcn_v1_0_jpeg_ring_set_wptr - set write pointer
1586  *
1587  * @ring: amdgpu_ring pointer
1588  *
1589  * Commits the write pointer to the hardware
1590  */
1591 static void vcn_v1_0_jpeg_ring_set_wptr(struct amdgpu_ring *ring)
1592 {
1593         struct amdgpu_device *adev = ring->adev;
1594
1595         WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
1596 }
1597
1598 /**
1599  * vcn_v1_0_jpeg_ring_insert_start - insert a start command
1600  *
1601  * @ring: amdgpu_ring pointer
1602  *
1603  * Write a start command to the ring.
1604  */
1605 static void vcn_v1_0_jpeg_ring_insert_start(struct amdgpu_ring *ring)
1606 {
1607         struct amdgpu_device *adev = ring->adev;
1608
1609         amdgpu_ring_write(ring,
1610                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
1611         amdgpu_ring_write(ring, 0x68e04);
1612
1613         amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));
1614         amdgpu_ring_write(ring, 0x80010000);
1615 }
1616
1617 /**
1618  * vcn_v1_0_jpeg_ring_insert_end - insert a end command
1619  *
1620  * @ring: amdgpu_ring pointer
1621  *
1622  * Write a end command to the ring.
1623  */
1624 static void vcn_v1_0_jpeg_ring_insert_end(struct amdgpu_ring *ring)
1625 {
1626         struct amdgpu_device *adev = ring->adev;
1627
1628         amdgpu_ring_write(ring,
1629                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
1630         amdgpu_ring_write(ring, 0x68e04);
1631
1632         amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));
1633         amdgpu_ring_write(ring, 0x00010000);
1634 }
1635
1636 /**
1637  * vcn_v1_0_jpeg_ring_emit_fence - emit an fence & trap command
1638  *
1639  * @ring: amdgpu_ring pointer
1640  * @fence: fence to emit
1641  *
1642  * Write a fence and a trap command to the ring.
1643  */
1644 static void vcn_v1_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1645                                      unsigned flags)
1646 {
1647         struct amdgpu_device *adev = ring->adev;
1648
1649         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1650
1651         amdgpu_ring_write(ring,
1652                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_DATA0), 0, 0, PACKETJ_TYPE0));
1653         amdgpu_ring_write(ring, seq);
1654
1655         amdgpu_ring_write(ring,
1656                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_DATA1), 0, 0, PACKETJ_TYPE0));
1657         amdgpu_ring_write(ring, seq);
1658
1659         amdgpu_ring_write(ring,
1660                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
1661         amdgpu_ring_write(ring, lower_32_bits(addr));
1662
1663         amdgpu_ring_write(ring,
1664                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
1665         amdgpu_ring_write(ring, upper_32_bits(addr));
1666
1667         amdgpu_ring_write(ring,
1668                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_CMD), 0, 0, PACKETJ_TYPE0));
1669         amdgpu_ring_write(ring, 0x8);
1670
1671         amdgpu_ring_write(ring,
1672                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_CMD), 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));
1673         amdgpu_ring_write(ring, 0);
1674
1675         amdgpu_ring_write(ring,
1676                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
1677         amdgpu_ring_write(ring, 0x01400200);
1678
1679         amdgpu_ring_write(ring,
1680                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
1681         amdgpu_ring_write(ring, seq);
1682
1683         amdgpu_ring_write(ring,
1684                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
1685         amdgpu_ring_write(ring, lower_32_bits(addr));
1686
1687         amdgpu_ring_write(ring,
1688                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
1689         amdgpu_ring_write(ring, upper_32_bits(addr));
1690
1691         amdgpu_ring_write(ring,
1692                 PACKETJ(0, 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE2));
1693         amdgpu_ring_write(ring, 0xffffffff);
1694
1695         amdgpu_ring_write(ring,
1696                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
1697         amdgpu_ring_write(ring, 0x3fbc);
1698
1699         amdgpu_ring_write(ring,
1700                 PACKETJ(0, 0, 0, PACKETJ_TYPE0));
1701         amdgpu_ring_write(ring, 0x1);
1702
1703         /* emit trap */
1704         amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));
1705         amdgpu_ring_write(ring, 0);
1706 }
1707
1708 /**
1709  * vcn_v1_0_jpeg_ring_emit_ib - execute indirect buffer
1710  *
1711  * @ring: amdgpu_ring pointer
1712  * @ib: indirect buffer to execute
1713  *
1714  * Write ring commands to execute the indirect buffer.
1715  */
1716 static void vcn_v1_0_jpeg_ring_emit_ib(struct amdgpu_ring *ring,
1717                                   struct amdgpu_ib *ib,
1718                                   unsigned vmid, bool ctx_switch)
1719 {
1720         struct amdgpu_device *adev = ring->adev;
1721
1722         amdgpu_ring_write(ring,
1723                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_VMID), 0, 0, PACKETJ_TYPE0));
1724         amdgpu_ring_write(ring, (vmid | (vmid << 4)));
1725
1726         amdgpu_ring_write(ring,
1727                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JPEG_VMID), 0, 0, PACKETJ_TYPE0));
1728         amdgpu_ring_write(ring, (vmid | (vmid << 4)));
1729
1730         amdgpu_ring_write(ring,
1731                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
1732         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1733
1734         amdgpu_ring_write(ring,
1735                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
1736         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1737
1738         amdgpu_ring_write(ring,
1739                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_IB_SIZE), 0, 0, PACKETJ_TYPE0));
1740         amdgpu_ring_write(ring, ib->length_dw);
1741
1742         amdgpu_ring_write(ring,
1743                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
1744         amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr));
1745
1746         amdgpu_ring_write(ring,
1747                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
1748         amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr));
1749
1750         amdgpu_ring_write(ring,
1751                 PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2));
1752         amdgpu_ring_write(ring, 0);
1753
1754         amdgpu_ring_write(ring,
1755                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
1756         amdgpu_ring_write(ring, 0x01400200);
1757
1758         amdgpu_ring_write(ring,
1759                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
1760         amdgpu_ring_write(ring, 0x2);
1761
1762         amdgpu_ring_write(ring,
1763                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_STATUS), 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3));
1764         amdgpu_ring_write(ring, 0x2);
1765 }
1766
1767 static void vcn_v1_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring,
1768                                             uint32_t reg, uint32_t val,
1769                                             uint32_t mask)
1770 {
1771         struct amdgpu_device *adev = ring->adev;
1772         uint32_t reg_offset = (reg << 2);
1773
1774         amdgpu_ring_write(ring,
1775                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
1776         amdgpu_ring_write(ring, 0x01400200);
1777
1778         amdgpu_ring_write(ring,
1779                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
1780         amdgpu_ring_write(ring, val);
1781
1782         amdgpu_ring_write(ring,
1783                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
1784         if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
1785                 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
1786                 amdgpu_ring_write(ring, 0);
1787                 amdgpu_ring_write(ring,
1788                         PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));
1789         } else {
1790                 amdgpu_ring_write(ring, reg_offset);
1791                 amdgpu_ring_write(ring,
1792                         PACKETJ(0, 0, 0, PACKETJ_TYPE3));
1793         }
1794         amdgpu_ring_write(ring, mask);
1795 }
1796
1797 static void vcn_v1_0_jpeg_ring_emit_vm_flush(struct amdgpu_ring *ring,
1798                 unsigned vmid, uint64_t pd_addr)
1799 {
1800         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1801         uint32_t data0, data1, mask;
1802
1803         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1804
1805         /* wait for register write */
1806         data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
1807         data1 = lower_32_bits(pd_addr);
1808         mask = 0xffffffff;
1809         vcn_v1_0_jpeg_ring_emit_reg_wait(ring, data0, data1, mask);
1810 }
1811
1812 static void vcn_v1_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring,
1813                                         uint32_t reg, uint32_t val)
1814 {
1815         struct amdgpu_device *adev = ring->adev;
1816         uint32_t reg_offset = (reg << 2);
1817
1818         amdgpu_ring_write(ring,
1819                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
1820         if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
1821                         ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
1822                 amdgpu_ring_write(ring, 0);
1823                 amdgpu_ring_write(ring,
1824                         PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));
1825         } else {
1826                 amdgpu_ring_write(ring, reg_offset);
1827                 amdgpu_ring_write(ring,
1828                         PACKETJ(0, 0, 0, PACKETJ_TYPE0));
1829         }
1830         amdgpu_ring_write(ring, val);
1831 }
1832
1833 static void vcn_v1_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count)
1834 {
1835         int i;
1836
1837         WARN_ON(ring->wptr % 2 || count % 2);
1838
1839         for (i = 0; i < count / 2; i++) {
1840                 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
1841                 amdgpu_ring_write(ring, 0);
1842         }
1843 }
1844
1845 static void vcn_v1_0_jpeg_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val)
1846 {
1847         struct amdgpu_device *adev = ring->adev;
1848         ring->ring[(*ptr)++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0);
1849         if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
1850                 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
1851                 ring->ring[(*ptr)++] = 0;
1852                 ring->ring[(*ptr)++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0);
1853         } else {
1854                 ring->ring[(*ptr)++] = reg_offset;
1855                 ring->ring[(*ptr)++] = PACKETJ(0, 0, 0, PACKETJ_TYPE0);
1856         }
1857         ring->ring[(*ptr)++] = val;
1858 }
1859
1860 static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr)
1861 {
1862         struct amdgpu_device *adev = ring->adev;
1863
1864         uint32_t reg, reg_offset, val, mask, i;
1865
1866         // 1st: program mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW
1867         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW);
1868         reg_offset = (reg << 2);
1869         val = lower_32_bits(ring->gpu_addr);
1870         vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1871
1872         // 2nd: program mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH
1873         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH);
1874         reg_offset = (reg << 2);
1875         val = upper_32_bits(ring->gpu_addr);
1876         vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1877
1878         // 3rd to 5th: issue MEM_READ commands
1879         for (i = 0; i <= 2; i++) {
1880                 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE2);
1881                 ring->ring[ptr++] = 0;
1882         }
1883
1884         // 6th: program mmUVD_JRBC_RB_CNTL register to enable NO_FETCH and RPTR write ability
1885         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
1886         reg_offset = (reg << 2);
1887         val = 0x13;
1888         vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1889
1890         // 7th: program mmUVD_JRBC_RB_REF_DATA
1891         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA);
1892         reg_offset = (reg << 2);
1893         val = 0x1;
1894         vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1895
1896         // 8th: issue conditional register read mmUVD_JRBC_RB_CNTL
1897         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
1898         reg_offset = (reg << 2);
1899         val = 0x1;
1900         mask = 0x1;
1901
1902         ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0);
1903         ring->ring[ptr++] = 0x01400200;
1904         ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0);
1905         ring->ring[ptr++] = val;
1906         ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0);
1907         if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
1908                 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
1909                 ring->ring[ptr++] = 0;
1910                 ring->ring[ptr++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3);
1911         } else {
1912                 ring->ring[ptr++] = reg_offset;
1913                 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE3);
1914         }
1915         ring->ring[ptr++] = mask;
1916
1917         //9th to 21st: insert no-op
1918         for (i = 0; i <= 12; i++) {
1919                 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
1920                 ring->ring[ptr++] = 0;
1921         }
1922
1923         //22nd: reset mmUVD_JRBC_RB_RPTR
1924         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_RPTR);
1925         reg_offset = (reg << 2);
1926         val = 0;
1927         vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1928
1929         //23rd: program mmUVD_JRBC_RB_CNTL to disable no_fetch
1930         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
1931         reg_offset = (reg << 2);
1932         val = 0x12;
1933         vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1934 }
1935
1936 static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev,
1937                                         struct amdgpu_irq_src *source,
1938                                         unsigned type,
1939                                         enum amdgpu_interrupt_state state)
1940 {
1941         return 0;
1942 }
1943
1944 static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev,
1945                                       struct amdgpu_irq_src *source,
1946                                       struct amdgpu_iv_entry *entry)
1947 {
1948         DRM_DEBUG("IH: VCN TRAP\n");
1949
1950         switch (entry->src_id) {
1951         case 124:
1952                 amdgpu_fence_process(&adev->vcn.ring_dec);
1953                 break;
1954         case 119:
1955                 amdgpu_fence_process(&adev->vcn.ring_enc[0]);
1956                 break;
1957         case 120:
1958                 amdgpu_fence_process(&adev->vcn.ring_enc[1]);
1959                 break;
1960         case 126:
1961                 amdgpu_fence_process(&adev->vcn.ring_jpeg);
1962                 break;
1963         default:
1964                 DRM_ERROR("Unhandled interrupt: %d %d\n",
1965                           entry->src_id, entry->src_data[0]);
1966                 break;
1967         }
1968
1969         return 0;
1970 }
1971
1972 static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1973 {
1974         struct amdgpu_device *adev = ring->adev;
1975         int i;
1976
1977         WARN_ON(ring->wptr % 2 || count % 2);
1978
1979         for (i = 0; i < count / 2; i++) {
1980                 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0));
1981                 amdgpu_ring_write(ring, 0);
1982         }
1983 }
1984
1985 static int vcn_v1_0_set_powergating_state(void *handle,
1986                                           enum amd_powergating_state state)
1987 {
1988         /* This doesn't actually powergate the VCN block.
1989          * That's done in the dpm code via the SMC.  This
1990          * just re-inits the block as necessary.  The actual
1991          * gating still happens in the dpm code.  We should
1992          * revisit this when there is a cleaner line between
1993          * the smc and the hw blocks
1994          */
1995         int ret;
1996         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1997
1998         if(state == adev->vcn.cur_state)
1999                 return 0;
2000
2001         if (state == AMD_PG_STATE_GATE)
2002                 ret = vcn_v1_0_stop(adev);
2003         else
2004                 ret = vcn_v1_0_start(adev);
2005
2006         if(!ret)
2007                 adev->vcn.cur_state = state;
2008         return ret;
2009 }
2010
2011 static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
2012         .name = "vcn_v1_0",
2013         .early_init = vcn_v1_0_early_init,
2014         .late_init = NULL,
2015         .sw_init = vcn_v1_0_sw_init,
2016         .sw_fini = vcn_v1_0_sw_fini,
2017         .hw_init = vcn_v1_0_hw_init,
2018         .hw_fini = vcn_v1_0_hw_fini,
2019         .suspend = vcn_v1_0_suspend,
2020         .resume = vcn_v1_0_resume,
2021         .is_idle = vcn_v1_0_is_idle,
2022         .wait_for_idle = vcn_v1_0_wait_for_idle,
2023         .check_soft_reset = NULL /* vcn_v1_0_check_soft_reset */,
2024         .pre_soft_reset = NULL /* vcn_v1_0_pre_soft_reset */,
2025         .soft_reset = NULL /* vcn_v1_0_soft_reset */,
2026         .post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */,
2027         .set_clockgating_state = vcn_v1_0_set_clockgating_state,
2028         .set_powergating_state = vcn_v1_0_set_powergating_state,
2029 };
2030
2031 static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
2032         .type = AMDGPU_RING_TYPE_VCN_DEC,
2033         .align_mask = 0xf,
2034         .support_64bit_ptrs = false,
2035         .vmhub = AMDGPU_MMHUB,
2036         .get_rptr = vcn_v1_0_dec_ring_get_rptr,
2037         .get_wptr = vcn_v1_0_dec_ring_get_wptr,
2038         .set_wptr = vcn_v1_0_dec_ring_set_wptr,
2039         .emit_frame_size =
2040                 6 + 6 + /* hdp invalidate / flush */
2041                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
2042                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
2043                 8 + /* vcn_v1_0_dec_ring_emit_vm_flush */
2044                 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */
2045                 6,
2046         .emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */
2047         .emit_ib = vcn_v1_0_dec_ring_emit_ib,
2048         .emit_fence = vcn_v1_0_dec_ring_emit_fence,
2049         .emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush,
2050         .test_ring = amdgpu_vcn_dec_ring_test_ring,
2051         .test_ib = amdgpu_vcn_dec_ring_test_ib,
2052         .insert_nop = vcn_v1_0_dec_ring_insert_nop,
2053         .insert_start = vcn_v1_0_dec_ring_insert_start,
2054         .insert_end = vcn_v1_0_dec_ring_insert_end,
2055         .pad_ib = amdgpu_ring_generic_pad_ib,
2056         .begin_use = amdgpu_vcn_ring_begin_use,
2057         .end_use = amdgpu_vcn_ring_end_use,
2058         .emit_wreg = vcn_v1_0_dec_ring_emit_wreg,
2059         .emit_reg_wait = vcn_v1_0_dec_ring_emit_reg_wait,
2060         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2061 };
2062
2063 static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = {
2064         .type = AMDGPU_RING_TYPE_VCN_ENC,
2065         .align_mask = 0x3f,
2066         .nop = VCN_ENC_CMD_NO_OP,
2067         .support_64bit_ptrs = false,
2068         .vmhub = AMDGPU_MMHUB,
2069         .get_rptr = vcn_v1_0_enc_ring_get_rptr,
2070         .get_wptr = vcn_v1_0_enc_ring_get_wptr,
2071         .set_wptr = vcn_v1_0_enc_ring_set_wptr,
2072         .emit_frame_size =
2073                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2074                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
2075                 4 + /* vcn_v1_0_enc_ring_emit_vm_flush */
2076                 5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */
2077                 1, /* vcn_v1_0_enc_ring_insert_end */
2078         .emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */
2079         .emit_ib = vcn_v1_0_enc_ring_emit_ib,
2080         .emit_fence = vcn_v1_0_enc_ring_emit_fence,
2081         .emit_vm_flush = vcn_v1_0_enc_ring_emit_vm_flush,
2082         .test_ring = amdgpu_vcn_enc_ring_test_ring,
2083         .test_ib = amdgpu_vcn_enc_ring_test_ib,
2084         .insert_nop = amdgpu_ring_insert_nop,
2085         .insert_end = vcn_v1_0_enc_ring_insert_end,
2086         .pad_ib = amdgpu_ring_generic_pad_ib,
2087         .begin_use = amdgpu_vcn_ring_begin_use,
2088         .end_use = amdgpu_vcn_ring_end_use,
2089         .emit_wreg = vcn_v1_0_enc_ring_emit_wreg,
2090         .emit_reg_wait = vcn_v1_0_enc_ring_emit_reg_wait,
2091         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2092 };
2093
2094 static const struct amdgpu_ring_funcs vcn_v1_0_jpeg_ring_vm_funcs = {
2095         .type = AMDGPU_RING_TYPE_VCN_JPEG,
2096         .align_mask = 0xf,
2097         .nop = PACKET0(0x81ff, 0),
2098         .support_64bit_ptrs = false,
2099         .vmhub = AMDGPU_MMHUB,
2100         .extra_dw = 64,
2101         .get_rptr = vcn_v1_0_jpeg_ring_get_rptr,
2102         .get_wptr = vcn_v1_0_jpeg_ring_get_wptr,
2103         .set_wptr = vcn_v1_0_jpeg_ring_set_wptr,
2104         .emit_frame_size =
2105                 6 + 6 + /* hdp invalidate / flush */
2106                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
2107                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
2108                 8 + /* vcn_v1_0_jpeg_ring_emit_vm_flush */
2109                 26 + 26 + /* vcn_v1_0_jpeg_ring_emit_fence x2 vm fence */
2110                 6,
2111         .emit_ib_size = 22, /* vcn_v1_0_jpeg_ring_emit_ib */
2112         .emit_ib = vcn_v1_0_jpeg_ring_emit_ib,
2113         .emit_fence = vcn_v1_0_jpeg_ring_emit_fence,
2114         .emit_vm_flush = vcn_v1_0_jpeg_ring_emit_vm_flush,
2115         .test_ring = amdgpu_vcn_jpeg_ring_test_ring,
2116         .test_ib = amdgpu_vcn_jpeg_ring_test_ib,
2117         .insert_nop = vcn_v1_0_jpeg_ring_nop,
2118         .insert_start = vcn_v1_0_jpeg_ring_insert_start,
2119         .insert_end = vcn_v1_0_jpeg_ring_insert_end,
2120         .pad_ib = amdgpu_ring_generic_pad_ib,
2121         .begin_use = amdgpu_vcn_ring_begin_use,
2122         .end_use = amdgpu_vcn_ring_end_use,
2123         .emit_wreg = vcn_v1_0_jpeg_ring_emit_wreg,
2124         .emit_reg_wait = vcn_v1_0_jpeg_ring_emit_reg_wait,
2125         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2126 };
2127
2128 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev)
2129 {
2130         adev->vcn.ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs;
2131         DRM_INFO("VCN decode is enabled in VM mode\n");
2132 }
2133
2134 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev)
2135 {
2136         int i;
2137
2138         for (i = 0; i < adev->vcn.num_enc_rings; ++i)
2139                 adev->vcn.ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs;
2140
2141         DRM_INFO("VCN encode is enabled in VM mode\n");
2142 }
2143
2144 static void vcn_v1_0_set_jpeg_ring_funcs(struct amdgpu_device *adev)
2145 {
2146         adev->vcn.ring_jpeg.funcs = &vcn_v1_0_jpeg_ring_vm_funcs;
2147         DRM_INFO("VCN jpeg decode is enabled in VM mode\n");
2148 }
2149
2150 static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = {
2151         .set = vcn_v1_0_set_interrupt_state,
2152         .process = vcn_v1_0_process_interrupt,
2153 };
2154
2155 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev)
2156 {
2157         adev->vcn.irq.num_types = adev->vcn.num_enc_rings + 2;
2158         adev->vcn.irq.funcs = &vcn_v1_0_irq_funcs;
2159 }
2160
2161 const struct amdgpu_ip_block_version vcn_v1_0_ip_block =
2162 {
2163                 .type = AMD_IP_BLOCK_TYPE_VCN,
2164                 .major = 1,
2165                 .minor = 0,
2166                 .rev = 0,
2167                 .funcs = &vcn_v1_0_ip_funcs,
2168 };