drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_vcn.h"
  28 #include "soc15.h"
  29 #include "soc15d.h"
  30 #include "soc15_common.h"
  31
  32 #include "vcn/vcn_1_0_offset.h"
  33 #include "vcn/vcn_1_0_sh_mask.h"
  34 #include "hdp/hdp_4_0_offset.h"
  35 #include "mmhub/mmhub_9_1_offset.h"
  36 #include "mmhub/mmhub_9_1_sh_mask.h"
  37
  38 #include "ivsrcid/vcn/irqsrcs_vcn_1_0.h"
  39
  40 static int vcn_v1_0_stop(struct amdgpu_device *adev);
  41 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
  42 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
  43 static void vcn_v1_0_set_jpeg_ring_funcs(struct amdgpu_device *adev);
  44 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);
  45 static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr);
  46
  47 /**
  48  * vcn_v1_0_early_init - set function pointers
  49  *
  50  * @handle: amdgpu_device pointer
  51  *
  52  * Set ring and irq function pointers
  53  */
  54 static int vcn_v1_0_early_init(void *handle)
  55 {
  56         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  57
  58         adev->vcn.num_enc_rings = 2;
  59
  60         vcn_v1_0_set_dec_ring_funcs(adev);
  61         vcn_v1_0_set_enc_ring_funcs(adev);
  62         vcn_v1_0_set_jpeg_ring_funcs(adev);
  63         vcn_v1_0_set_irq_funcs(adev);
  64
  65         return 0;
  66 }
  67
  68 /**
  69  * vcn_v1_0_sw_init - sw init for VCN block
  70  *
  71  * @handle: amdgpu_device pointer
  72  *
  73  * Load firmware and sw initialization
  74  */
  75 static int vcn_v1_0_sw_init(void *handle)
  76 {
  77         struct amdgpu_ring *ring;
  78         int i, r;
  79         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  80
  81         /* VCN DEC TRAP */
  82         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.irq);
  83         if (r)
  84                 return r;
  85
  86         /* VCN ENC TRAP */
  87         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
  88                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
  89                                         &adev->vcn.irq);
  90                 if (r)
  91                         return r;
  92         }
  93
  94         /* VCN JPEG TRAP */
  95         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 126, &adev->vcn.irq);
  96         if (r)
  97                 return r;
  98
  99         r = amdgpu_vcn_sw_init(adev);
 100         if (r)
 101                 return r;
 102
 103         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 104                 const struct common_firmware_header *hdr;
 105                 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
 106                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
 107                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
 108                 adev->firmware.fw_size +=
 109                         ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
 110                 DRM_INFO("PSP loading VCN firmware\n");
 111         }
 112
 113         r = amdgpu_vcn_resume(adev);
 114         if (r)
 115                 return r;
 116
 117         ring = &adev->vcn.ring_dec;
 118         sprintf(ring->name, "vcn_dec");
 119         r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
 120         if (r)
 121                 return r;
 122
 123         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 124                 ring = &adev->vcn.ring_enc[i];
 125                 sprintf(ring->name, "vcn_enc%d", i);
 126                 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
 127                 if (r)
 128                         return r;
 129         }
 130
 131         ring = &adev->vcn.ring_jpeg;
 132         sprintf(ring->name, "vcn_jpeg");
 133         r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
 134         if (r)
 135                 return r;
 136
 137         return r;
 138 }
 139
 140 /**
 141  * vcn_v1_0_sw_fini - sw fini for VCN block
 142  *
 143  * @handle: amdgpu_device pointer
 144  *
 145  * VCN suspend and free up sw allocation
 146  */
 147 static int vcn_v1_0_sw_fini(void *handle)
 148 {
 149         int r;
 150         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 151
 152         r = amdgpu_vcn_suspend(adev);
 153         if (r)
 154                 return r;
 155
 156         r = amdgpu_vcn_sw_fini(adev);
 157
 158         return r;
 159 }
 160
 161 /**
 162  * vcn_v1_0_hw_init - start and test VCN block
 163  *
 164  * @handle: amdgpu_device pointer
 165  *
 166  * Initialize the hardware, boot up the VCPU and do some testing
 167  */
 168 static int vcn_v1_0_hw_init(void *handle)
 169 {
 170         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 171         struct amdgpu_ring *ring = &adev->vcn.ring_dec;
 172         int i, r;
 173
 174         ring->ready = true;
 175         r = amdgpu_ring_test_ring(ring);
 176         if (r) {
 177                 ring->ready = false;
 178                 goto done;
 179         }
 180
 181         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 182                 ring = &adev->vcn.ring_enc[i];
 183                 ring->ready = true;
 184                 r = amdgpu_ring_test_ring(ring);
 185                 if (r) {
 186                         ring->ready = false;
 187                         goto done;
 188                 }
 189         }
 190
 191         ring = &adev->vcn.ring_jpeg;
 192         ring->ready = true;
 193         r = amdgpu_ring_test_ring(ring);
 194         if (r) {
 195                 ring->ready = false;
 196                 goto done;
 197         }
 198
 199 done:
 200         if (!r)
 201                 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
 202                         (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
 203
 204         return r;
 205 }
 206
 207 /**
 208  * vcn_v1_0_hw_fini - stop the hardware block
 209  *
 210  * @handle: amdgpu_device pointer
 211  *
 212  * Stop the VCN block, mark ring as not ready any more
 213  */
 214 static int vcn_v1_0_hw_fini(void *handle)
 215 {
 216         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 217         struct amdgpu_ring *ring = &adev->vcn.ring_dec;
 218
 219         if (RREG32_SOC15(VCN, 0, mmUVD_STATUS))
 220                 vcn_v1_0_stop(adev);
 221
 222         ring->ready = false;
 223
 224         return 0;
 225 }
 226
 227 /**
 228  * vcn_v1_0_suspend - suspend VCN block
 229  *
 230  * @handle: amdgpu_device pointer
 231  *
 232  * HW fini and suspend VCN block
 233  */
 234 static int vcn_v1_0_suspend(void *handle)
 235 {
 236         int r;
 237         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 238
 239         r = vcn_v1_0_hw_fini(adev);
 240         if (r)
 241                 return r;
 242
 243         r = amdgpu_vcn_suspend(adev);
 244
 245         return r;
 246 }
 247
 248 /**
 249  * vcn_v1_0_resume - resume VCN block
 250  *
 251  * @handle: amdgpu_device pointer
 252  *
 253  * Resume firmware and hw init VCN block
 254  */
 255 static int vcn_v1_0_resume(void *handle)
 256 {
 257         int r;
 258         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 259
 260         r = amdgpu_vcn_resume(adev);
 261         if (r)
 262                 return r;
 263
 264         r = vcn_v1_0_hw_init(adev);
 265
 266         return r;
 267 }
 268
 269 /**
 270  * vcn_v1_0_mc_resume_spg_mode - memory controller programming
 271  *
 272  * @adev: amdgpu_device pointer
 273  *
 274  * Let the VCN memory controller know it's offsets
 275  */
 276 static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev)
 277 {
 278         uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
 279         uint32_t offset;
 280
 281         /* cache window 0: fw */
 282         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 283                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 284                              (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
 285                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 286                              (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
 287                 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
 288                 offset = 0;
 289         } else {
 290                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 291                         lower_32_bits(adev->vcn.gpu_addr));
 292                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 293                         upper_32_bits(adev->vcn.gpu_addr));
 294                 offset = size;
 295                 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
 296                              AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 297         }
 298
 299         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
 300
 301         /* cache window 1: stack */
 302         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 303                      lower_32_bits(adev->vcn.gpu_addr + offset));
 304         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 305                      upper_32_bits(adev->vcn.gpu_addr + offset));
 306         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
 307         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
 308
 309         /* cache window 2: context */
 310         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 311                      lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 312         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 313                      upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 314         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
 315         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
 316
 317         WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
 318                         adev->gfx.config.gb_addr_config);
 319         WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
 320                         adev->gfx.config.gb_addr_config);
 321         WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
 322                         adev->gfx.config.gb_addr_config);
 323 }
 324
 325 static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev)
 326 {
 327         uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
 328         uint32_t offset;
 329
 330         /* cache window 0: fw */
 331         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 332                 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 333                              (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo),
 334                              0xFFFFFFFF, 0);
 335                 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 336                              (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi),
 337                              0xFFFFFFFF, 0);
 338                 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0,
 339                              0xFFFFFFFF, 0);
 340                 offset = 0;
 341         } else {
 342                 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 343                         lower_32_bits(adev->vcn.gpu_addr), 0xFFFFFFFF, 0);
 344                 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 345                         upper_32_bits(adev->vcn.gpu_addr), 0xFFFFFFFF, 0);
 346                 offset = size;
 347                 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
 348                              AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0xFFFFFFFF, 0);
 349         }
 350
 351         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0);
 352
 353         /* cache window 1: stack */
 354         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 355                      lower_32_bits(adev->vcn.gpu_addr + offset), 0xFFFFFFFF, 0);
 356         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 357                      upper_32_bits(adev->vcn.gpu_addr + offset), 0xFFFFFFFF, 0);
 358         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0,
 359                              0xFFFFFFFF, 0);
 360         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE,
 361                              0xFFFFFFFF, 0);
 362
 363         /* cache window 2: context */
 364         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 365                      lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
 366                              0xFFFFFFFF, 0);
 367         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 368                      upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
 369                              0xFFFFFFFF, 0);
 370         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0);
 371         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE,
 372                              0xFFFFFFFF, 0);
 373
 374         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
 375                         adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 376         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
 377                         adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 378         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
 379                         adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 380         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_ADDR_CONFIG,
 381                         adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 382         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG,
 383                         adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 384 }
 385
 386 /**
 387  * vcn_v1_0_disable_clock_gating - disable VCN clock gating
 388  *
 389  * @adev: amdgpu_device pointer
 390  * @sw: enable SW clock gating
 391  *
 392  * Disable clock gating for VCN block
 393  */
 394 static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev)
 395 {
 396         uint32_t data;
 397
 398         /* JPEG disable CGC */
 399         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
 400
 401         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 402                 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 403         else
 404                 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 405
 406         data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 407         data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 408         WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);
 409
 410         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
 411         data &= ~(JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK);
 412         WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);
 413
 414         /* UVD disable CGC */
 415         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 416         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 417                 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 418         else
 419                 data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 420
 421         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 422         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 423         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 424
 425         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);
 426         data &= ~(UVD_CGC_GATE__SYS_MASK
 427                 | UVD_CGC_GATE__UDEC_MASK
 428                 | UVD_CGC_GATE__MPEG2_MASK
 429                 | UVD_CGC_GATE__REGS_MASK
 430                 | UVD_CGC_GATE__RBC_MASK
 431                 | UVD_CGC_GATE__LMI_MC_MASK
 432                 | UVD_CGC_GATE__LMI_UMC_MASK
 433                 | UVD_CGC_GATE__IDCT_MASK
 434                 | UVD_CGC_GATE__MPRD_MASK
 435                 | UVD_CGC_GATE__MPC_MASK
 436                 | UVD_CGC_GATE__LBSI_MASK
 437                 | UVD_CGC_GATE__LRBBM_MASK
 438                 | UVD_CGC_GATE__UDEC_RE_MASK
 439                 | UVD_CGC_GATE__UDEC_CM_MASK
 440                 | UVD_CGC_GATE__UDEC_IT_MASK
 441                 | UVD_CGC_GATE__UDEC_DB_MASK
 442                 | UVD_CGC_GATE__UDEC_MP_MASK
 443                 | UVD_CGC_GATE__WCB_MASK
 444                 | UVD_CGC_GATE__VCPU_MASK
 445                 | UVD_CGC_GATE__SCPU_MASK);
 446         WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);
 447
 448         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 449         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 450                 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 451                 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 452                 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 453                 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 454                 | UVD_CGC_CTRL__SYS_MODE_MASK
 455                 | UVD_CGC_CTRL__UDEC_MODE_MASK
 456                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 457                 | UVD_CGC_CTRL__REGS_MODE_MASK
 458                 | UVD_CGC_CTRL__RBC_MODE_MASK
 459                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 460                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 461                 | UVD_CGC_CTRL__IDCT_MODE_MASK
 462                 | UVD_CGC_CTRL__MPRD_MODE_MASK
 463                 | UVD_CGC_CTRL__MPC_MODE_MASK
 464                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 465                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 466                 | UVD_CGC_CTRL__WCB_MODE_MASK
 467                 | UVD_CGC_CTRL__VCPU_MODE_MASK
 468                 | UVD_CGC_CTRL__SCPU_MODE_MASK);
 469         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 470
 471         /* turn on */
 472         data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);
 473         data |= (UVD_SUVD_CGC_GATE__SRE_MASK
 474                 | UVD_SUVD_CGC_GATE__SIT_MASK
 475                 | UVD_SUVD_CGC_GATE__SMP_MASK
 476                 | UVD_SUVD_CGC_GATE__SCM_MASK
 477                 | UVD_SUVD_CGC_GATE__SDB_MASK
 478                 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
 479                 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
 480                 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
 481                 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
 482                 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
 483                 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
 484                 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
 485                 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
 486                 | UVD_SUVD_CGC_GATE__SCLR_MASK
 487                 | UVD_SUVD_CGC_GATE__UVD_SC_MASK
 488                 | UVD_SUVD_CGC_GATE__ENT_MASK
 489                 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
 490                 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
 491                 | UVD_SUVD_CGC_GATE__SITE_MASK
 492                 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
 493                 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
 494                 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
 495                 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
 496                 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
 497         WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data);
 498
 499         data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
 500         data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 501                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 502                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 503                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 504                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 505                 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 506                 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 507                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 508                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 509                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 510         WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
 511 }
 512
 513 /**
 514  * vcn_v1_0_enable_clock_gating - enable VCN clock gating
 515  *
 516  * @adev: amdgpu_device pointer
 517  * @sw: enable SW clock gating
 518  *
 519  * Enable clock gating for VCN block
 520  */
 521 static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev)
 522 {
 523         uint32_t data = 0;
 524
 525         /* enable JPEG CGC */
 526         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
 527         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 528                 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 529         else
 530                 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 531         data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 532         data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 533         WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);
 534
 535         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
 536         data |= (JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK);
 537         WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);
 538
 539         /* enable UVD CGC */
 540         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 541         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 542                 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 543         else
 544                 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 545         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 546         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 547         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 548
 549         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 550         data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 551                 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 552                 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 553                 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 554                 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 555                 | UVD_CGC_CTRL__SYS_MODE_MASK
 556                 | UVD_CGC_CTRL__UDEC_MODE_MASK
 557                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 558                 | UVD_CGC_CTRL__REGS_MODE_MASK
 559                 | UVD_CGC_CTRL__RBC_MODE_MASK
 560                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 561                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 562                 | UVD_CGC_CTRL__IDCT_MODE_MASK
 563                 | UVD_CGC_CTRL__MPRD_MODE_MASK
 564                 | UVD_CGC_CTRL__MPC_MODE_MASK
 565                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 566                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 567                 | UVD_CGC_CTRL__WCB_MODE_MASK
 568                 | UVD_CGC_CTRL__VCPU_MODE_MASK
 569                 | UVD_CGC_CTRL__SCPU_MODE_MASK);
 570         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 571
 572         data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
 573         data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 574                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 575                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 576                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 577                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 578                 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 579                 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 580                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 581                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 582                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 583         WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
 584 }
 585
 586 static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel)
 587 {
 588         uint32_t reg_data = 0;
 589
 590         /* disable JPEG CGC */
 591         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 592                 reg_data = 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 593         else
 594                 reg_data = 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 595         reg_data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 596         reg_data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 597         WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
 598
 599         WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel);
 600
 601         /* enable sw clock gating control */
 602         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 603                 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 604         else
 605                 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 606         reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 607         reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 608         reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
 609                  UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
 610                  UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
 611                  UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
 612                  UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
 613                  UVD_CGC_CTRL__SYS_MODE_MASK |
 614                  UVD_CGC_CTRL__UDEC_MODE_MASK |
 615                  UVD_CGC_CTRL__MPEG2_MODE_MASK |
 616                  UVD_CGC_CTRL__REGS_MODE_MASK |
 617                  UVD_CGC_CTRL__RBC_MODE_MASK |
 618                  UVD_CGC_CTRL__LMI_MC_MODE_MASK |
 619                  UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
 620                  UVD_CGC_CTRL__IDCT_MODE_MASK |
 621                  UVD_CGC_CTRL__MPRD_MODE_MASK |
 622                  UVD_CGC_CTRL__MPC_MODE_MASK |
 623                  UVD_CGC_CTRL__LBSI_MODE_MASK |
 624                  UVD_CGC_CTRL__LRBBM_MODE_MASK |
 625                  UVD_CGC_CTRL__WCB_MODE_MASK |
 626                  UVD_CGC_CTRL__VCPU_MODE_MASK |
 627                  UVD_CGC_CTRL__SCPU_MODE_MASK);
 628         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
 629
 630         /* turn off clock gating */
 631         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel);
 632
 633         /* turn on SUVD clock gating */
 634         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel);
 635
 636         /* turn on sw mode in UVD_SUVD_CGC_CTRL */
 637         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel);
 638 }
 639
 640 static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev)
 641 {
 642         uint32_t data = 0;
 643         int ret;
 644
 645         if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
 646                 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 647                         | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
 648                         | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 649                         | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
 650                         | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 651                         | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
 652                         | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
 653                         | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 654                         | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 655                         | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 656                         | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
 657
 658                 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
 659                 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF, ret);
 660         } else {
 661                 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 662                         | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
 663                         | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 664                         | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
 665                         | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 666                         | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
 667                         | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
 668                         | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 669                         | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 670                         | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 671                         | 1 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
 672                 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
 673                 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0,  0xFFFFFFFF, ret);
 674         }
 675
 676         /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS , UVDU_PWR_STATUS are 0 (power on) */
 677
 678         data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
 679         data &= ~0x103;
 680         if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
 681                 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | UVD_POWER_STATUS__UVD_PG_EN_MASK;
 682
 683         WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
 684 }
 685
 686 static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev)
 687 {
 688         uint32_t data = 0;
 689         int ret;
 690
 691         if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
 692                 /* Before power off, this indicator has to be turned on */
 693                 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
 694                 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
 695                 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
 696                 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
 697
 698
 699                 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 700                         | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
 701                         | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 702                         | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
 703                         | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 704                         | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
 705                         | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
 706                         | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 707                         | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 708                         | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 709                         | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
 710
 711                 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
 712
 713                 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
 714                         | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
 715                         | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
 716                         | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
 717                         | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
 718                         | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT
 719                         | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT
 720                         | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
 721                         | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
 722                         | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT
 723                         | 2 << UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT);
 724                 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF, ret);
 725         }
 726 }
 727
 728 /**
 729  * vcn_v1_0_start - start VCN block
 730  *
 731  * @adev: amdgpu_device pointer
 732  *
 733  * Setup and start the VCN block
 734  */
 735 static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
 736 {
 737         struct amdgpu_ring *ring = &adev->vcn.ring_dec;
 738         uint32_t rb_bufsz, tmp;
 739         uint32_t lmi_swap_cntl;
 740         int i, j, r;
 741
 742         /* disable byte swapping */
 743         lmi_swap_cntl = 0;
 744
 745         vcn_1_0_disable_static_power_gating(adev);
 746         /* disable clock gating */
 747         vcn_v1_0_disable_clock_gating(adev);
 748
 749         vcn_v1_0_mc_resume_spg_mode(adev);
 750
 751         /* disable interupt */
 752         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
 753                         ~UVD_MASTINT_EN__VCPU_EN_MASK);
 754
 755         /* stall UMC and register bus before resetting VCPU */
 756         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
 757                         UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
 758                         ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 759         mdelay(1);
 760
 761         /* put LMI, VCPU, RBC etc... into reset */
 762         WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
 763                 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 764                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
 765                 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 766                 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
 767                 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 768                 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
 769                 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 770                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
 771         mdelay(5);
 772
 773         /* initialize VCN memory controller */
 774         WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL,
 775                 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 776                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 777                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 778                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 779                 UVD_LMI_CTRL__REQ_MODE_MASK |
 780                 0x00100000L);
 781
 782 #ifdef __BIG_ENDIAN
 783         /* swap (8 in 32) RB and IB */
 784         lmi_swap_cntl = 0xa;
 785 #endif
 786         WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
 787
 788         tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);
 789         tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
 790         tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
 791         WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp);
 792
 793         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,
 794                 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
 795                 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
 796                 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
 797                 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
 798
 799         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0,
 800                 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
 801                 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
 802                 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
 803                 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
 804
 805         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX,
 806                 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
 807                 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
 808                 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
 809
 810         /* take all subblocks out of reset, except VCPU */
 811         WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
 812                         UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 813         mdelay(5);
 814
 815         /* enable VCPU clock */
 816         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL,
 817                         UVD_VCPU_CNTL__CLK_EN_MASK);
 818
 819         /* enable UMC */
 820         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
 821                         ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 822
 823         /* boot up the VCPU */
 824         WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, 0);
 825         mdelay(10);
 826
 827         for (i = 0; i < 10; ++i) {
 828                 uint32_t status;
 829
 830                 for (j = 0; j < 100; ++j) {
 831                         status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
 832                         if (status & UVD_STATUS__IDLE)
 833                                 break;
 834                         mdelay(10);
 835                 }
 836                 r = 0;
 837                 if (status & UVD_STATUS__IDLE)
 838                         break;
 839
 840                 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
 841                 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
 842                                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
 843                                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 844                 mdelay(10);
 845                 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
 846                                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 847                 mdelay(10);
 848                 r = -1;
 849         }
 850
 851         if (r) {
 852                 DRM_ERROR("VCN decode not responding, giving up!!!\n");
 853                 return r;
 854         }
 855         /* enable master interrupt */
 856         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
 857                 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
 858                 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
 859
 860         /* enable system interrupt for JRBC, TODO: move to set interrupt*/
 861         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN),
 862                 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK,
 863                 ~UVD_SYS_INT_EN__UVD_JRBC_EN_MASK);
 864
 865         /* clear the bit 4 of VCN_STATUS */
 866         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
 867                         ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
 868
 869         /* force RBC into idle state */
 870         rb_bufsz = order_base_2(ring->ring_size);
 871         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
 872         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
 873         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 874         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
 875         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
 876         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
 877         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
 878
 879         /* set the write pointer delay */
 880         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
 881
 882         /* set the wb address */
 883         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
 884                         (upper_32_bits(ring->gpu_addr) >> 2));
 885
 886         /* programm the RB_BASE for ring buffer */
 887         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
 888                         lower_32_bits(ring->gpu_addr));
 889         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
 890                         upper_32_bits(ring->gpu_addr));
 891
 892         /* Initialize the ring buffer's read and write pointers */
 893         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
 894
 895         WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
 896
 897         ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
 898         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
 899                         lower_32_bits(ring->wptr));
 900
 901         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
 902                         ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
 903
 904         ring = &adev->vcn.ring_enc[0];
 905         WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
 906         WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
 907         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
 908         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
 909         WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
 910
 911         ring = &adev->vcn.ring_enc[1];
 912         WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
 913         WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
 914         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
 915         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
 916         WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
 917
 918         ring = &adev->vcn.ring_jpeg;
 919         WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
 920         WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
 921                         UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
 922         WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, lower_32_bits(ring->gpu_addr));
 923         WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr));
 924         WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, 0);
 925         WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0);
 926         WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
 927
 928         /* initialize wptr */
 929         ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
 930
 931         /* copy patch commands to the jpeg ring */
 932         vcn_v1_0_jpeg_ring_set_patch_ring(ring,
 933                 (ring->wptr + ring->max_dw * amdgpu_sched_hw_submission));
 934
 935         return 0;
 936 }
 937
 938 static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
 939 {
 940         struct amdgpu_ring *ring = &adev->vcn.ring_dec;
 941         uint32_t rb_bufsz, tmp, reg_data;
 942         uint32_t lmi_swap_cntl;
 943
 944         /* disable byte swapping */
 945         lmi_swap_cntl = 0;
 946
 947         vcn_1_0_enable_static_power_gating(adev);
 948
 949         /* enable dynamic power gating mode */
 950         reg_data = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
 951         reg_data |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
 952         reg_data |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
 953         WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data);
 954
 955         /* enable clock gating */
 956         vcn_v1_0_clock_gating_dpg_mode(adev, 0);
 957
 958         /* enable VCPU clock */
 959         reg_data = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
 960         reg_data |= UVD_VCPU_CNTL__CLK_EN_MASK;
 961         reg_data |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
 962         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CNTL, reg_data, 0xFFFFFFFF, 0);
 963
 964         /* disable interupt */
 965         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN,
 966                         0, UVD_MASTINT_EN__VCPU_EN_MASK, 0);
 967
 968         /* stall UMC and register bus before resetting VCPU */
 969         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2,
 970                         UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0);
 971
 972         /* put LMI, VCPU, RBC etc... into reset */
 973         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET,
 974                 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 975                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
 976                 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 977                 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
 978                 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 979                 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
 980                 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 981                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,
 982                 0xFFFFFFFF, 0);
 983
 984         /* initialize VCN memory controller */
 985         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL,
 986                 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 987                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 988                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 989                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 990                 UVD_LMI_CTRL__REQ_MODE_MASK |
 991                 0x00100000L, 0xFFFFFFFF, 0);
 992
 993 #ifdef __BIG_ENDIAN
 994         /* swap (8 in 32) RB and IB */
 995         lmi_swap_cntl = 0xa;
 996 #endif
 997         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0);
 998
 999         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_CNTL,
1000                 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0xFFFFFFFF, 0);
1001
1002         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXA0,
1003                 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1004                  (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1005                  (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1006                  (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0xFFFFFFFF, 0);
1007
1008         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXB0,
1009                 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1010                  (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1011                  (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1012                  (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0xFFFFFFFF, 0);
1013
1014         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUX,
1015                 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1016                  (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1017                  (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0xFFFFFFFF, 0);
1018
1019         vcn_v1_0_mc_resume_dpg_mode(adev);
1020
1021         /* take all subblocks out of reset, except VCPU */
1022         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET,
1023                         UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 0xFFFFFFFF, 0);
1024
1025         /* enable VCPU clock */
1026         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CNTL,
1027                         UVD_VCPU_CNTL__CLK_EN_MASK, 0xFFFFFFFF, 0);
1028
1029         /* enable UMC */
1030         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2,
1031                         0, UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0);
1032
1033         /* boot up the VCPU */
1034         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0);
1035
1036         /* enable master interrupt */
1037         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN,
1038                         (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
1039                         (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), 0);
1040
1041         vcn_v1_0_clock_gating_dpg_mode(adev, 1);
1042         /* setup mmUVD_LMI_CTRL */
1043         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL,
1044                         (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1045                                 UVD_LMI_CTRL__CRC_RESET_MASK |
1046                                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1047                                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1048                                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
1049                                 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
1050                                 0x00100000L), 0xFFFFFFFF, 1);
1051
1052         tmp = adev->gfx.config.gb_addr_config;
1053         /* setup VCN global tiling registers */
1054         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);
1055         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);
1056
1057         /* enable System Interrupt for JRBC */
1058         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SYS_INT_EN,
1059                                                                         UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 0xFFFFFFFF, 1);
1060
1061         /* force RBC into idle state */
1062         rb_bufsz = order_base_2(ring->ring_size);
1063         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1064         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1065         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1066         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
1067         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1068         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1069         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
1070
1071         /* set the write pointer delay */
1072         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
1073
1074         /* set the wb address */
1075         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
1076                                                                 (upper_32_bits(ring->gpu_addr) >> 2));
1077
1078         /* programm the RB_BASE for ring buffer */
1079         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1080                                                                 lower_32_bits(ring->gpu_addr));
1081         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1082                                                                 upper_32_bits(ring->gpu_addr));
1083
1084         /* Initialize the ring buffer's read and write pointers */
1085         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
1086
1087         WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
1088
1089         ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1090         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1091                                                                 lower_32_bits(ring->wptr));
1092
1093         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
1094                         ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
1095
1096         /* initialize wptr */
1097         ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
1098
1099         /* copy patch commands to the jpeg ring */
1100         vcn_v1_0_jpeg_ring_set_patch_ring(ring,
1101                 (ring->wptr + ring->max_dw * amdgpu_sched_hw_submission));
1102
1103         return 0;
1104 }
1105
1106 static int vcn_v1_0_start(struct amdgpu_device *adev)
1107 {
1108         int r;
1109
1110         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1111                 r = vcn_v1_0_start_dpg_mode(adev);
1112         else
1113                 r = vcn_v1_0_start_spg_mode(adev);
1114         return r;
1115 }
1116
1117 /**
1118  * vcn_v1_0_stop - stop VCN block
1119  *
1120  * @adev: amdgpu_device pointer
1121  *
1122  * stop the VCN block
1123  */
1124 static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev)
1125 {
1126         int ret_code, tmp;
1127
1128         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, ret_code);
1129
1130         tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1131                 UVD_LMI_STATUS__READ_CLEAN_MASK |
1132                 UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1133                 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1134         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code);
1135
1136         /* put VCPU into reset */
1137         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1138                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1139                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1140
1141         tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
1142                 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1143         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code);
1144
1145         /* disable VCPU clock */
1146         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
1147                 ~UVD_VCPU_CNTL__CLK_EN_MASK);
1148
1149         /* reset LMI UMC/LMI */
1150         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1151                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,
1152                 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
1153
1154         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1155                 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,
1156                 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
1157
1158         WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0);
1159
1160         vcn_v1_0_enable_clock_gating(adev);
1161         vcn_1_0_enable_static_power_gating(adev);
1162         return 0;
1163 }
1164
1165 static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev)
1166 {
1167         int ret_code;
1168
1169         /* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */
1170         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1171                         UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1172                         UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1173
1174         if (ret_code) {
1175                 int tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1176                 /* wait for read ptr to be equal to write ptr */
1177                 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
1178
1179                 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1180                         UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1181                         UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1182         }
1183
1184         /* disable dynamic power gating mode */
1185         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
1186                         ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1187
1188         return 0;
1189 }
1190
1191 static int vcn_v1_0_stop(struct amdgpu_device *adev)
1192 {
1193         int r;
1194
1195         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1196                 r = vcn_v1_0_stop_dpg_mode(adev);
1197         else
1198                 r = vcn_v1_0_stop_spg_mode(adev);
1199
1200         return r;
1201 }
1202
1203 static bool vcn_v1_0_is_idle(void *handle)
1204 {
1205         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1206
1207         return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
1208 }
1209
1210 static int vcn_v1_0_wait_for_idle(void *handle)
1211 {
1212         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1213         int ret = 0;
1214
1215         SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
1216                 UVD_STATUS__IDLE, ret);
1217
1218         return ret;
1219 }
1220
1221 static int vcn_v1_0_set_clockgating_state(void *handle,
1222                                           enum amd_clockgating_state state)
1223 {
1224         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1225         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1226
1227         if (enable) {
1228                 /* wait for STATUS to clear */
1229                 if (vcn_v1_0_is_idle(handle))
1230                         return -EBUSY;
1231                 vcn_v1_0_enable_clock_gating(adev);
1232         } else {
1233                 /* disable HW gating and enable Sw gating */
1234                 vcn_v1_0_disable_clock_gating(adev);
1235         }
1236         return 0;
1237 }
1238
1239 /**
1240  * vcn_v1_0_dec_ring_get_rptr - get read pointer
1241  *
1242  * @ring: amdgpu_ring pointer
1243  *
1244  * Returns the current hardware read pointer
1245  */
1246 static uint64_t vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
1247 {
1248         struct amdgpu_device *adev = ring->adev;
1249
1250         return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1251 }
1252
1253 /**
1254  * vcn_v1_0_dec_ring_get_wptr - get write pointer
1255  *
1256  * @ring: amdgpu_ring pointer
1257  *
1258  * Returns the current hardware write pointer
1259  */
1260 static uint64_t vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
1261 {
1262         struct amdgpu_device *adev = ring->adev;
1263
1264         return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
1265 }
1266
1267 /**
1268  * vcn_v1_0_dec_ring_set_wptr - set write pointer
1269  *
1270  * @ring: amdgpu_ring pointer
1271  *
1272  * Commits the write pointer to the hardware
1273  */
1274 static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
1275 {
1276         struct amdgpu_device *adev = ring->adev;
1277
1278         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1279                 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2,
1280                         lower_32_bits(ring->wptr) | 0x80000000);
1281
1282         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1283 }
1284
1285 /**
1286  * vcn_v1_0_dec_ring_insert_start - insert a start command
1287  *
1288  * @ring: amdgpu_ring pointer
1289  *
1290  * Write a start command to the ring.
1291  */
1292 static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring)
1293 {
1294         struct amdgpu_device *adev = ring->adev;
1295
1296         amdgpu_ring_write(ring,
1297                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1298         amdgpu_ring_write(ring, 0);
1299         amdgpu_ring_write(ring,
1300                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1301         amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1);
1302 }
1303
1304 /**
1305  * vcn_v1_0_dec_ring_insert_end - insert a end command
1306  *
1307  * @ring: amdgpu_ring pointer
1308  *
1309  * Write a end command to the ring.
1310  */
1311 static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring)
1312 {
1313         struct amdgpu_device *adev = ring->adev;
1314
1315         amdgpu_ring_write(ring,
1316                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1317         amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1);
1318 }
1319
1320 /**
1321  * vcn_v1_0_dec_ring_emit_fence - emit an fence & trap command
1322  *
1323  * @ring: amdgpu_ring pointer
1324  * @fence: fence to emit
1325  *
1326  * Write a fence and a trap command to the ring.
1327  */
1328 static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1329                                      unsigned flags)
1330 {
1331         struct amdgpu_device *adev = ring->adev;
1332
1333         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1334
1335         amdgpu_ring_write(ring,
1336                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
1337         amdgpu_ring_write(ring, seq);
1338         amdgpu_ring_write(ring,
1339                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1340         amdgpu_ring_write(ring, addr & 0xffffffff);
1341         amdgpu_ring_write(ring,
1342                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1343         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1344         amdgpu_ring_write(ring,
1345                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1346         amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1);
1347
1348         amdgpu_ring_write(ring,
1349                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1350         amdgpu_ring_write(ring, 0);
1351         amdgpu_ring_write(ring,
1352                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1353         amdgpu_ring_write(ring, 0);
1354         amdgpu_ring_write(ring,
1355                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1356         amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1);
1357 }
1358
1359 /**
1360  * vcn_v1_0_dec_ring_emit_ib - execute indirect buffer
1361  *
1362  * @ring: amdgpu_ring pointer
1363  * @ib: indirect buffer to execute
1364  *
1365  * Write ring commands to execute the indirect buffer
1366  */
1367 static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
1368                                   struct amdgpu_ib *ib,
1369                                   unsigned vmid, bool ctx_switch)
1370 {
1371         struct amdgpu_device *adev = ring->adev;
1372
1373         amdgpu_ring_write(ring,
1374                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));
1375         amdgpu_ring_write(ring, vmid);
1376
1377         amdgpu_ring_write(ring,
1378                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
1379         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1380         amdgpu_ring_write(ring,
1381                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
1382         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1383         amdgpu_ring_write(ring,
1384                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0));
1385         amdgpu_ring_write(ring, ib->length_dw);
1386 }
1387
1388 static void vcn_v1_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring,
1389                                             uint32_t reg, uint32_t val,
1390                                             uint32_t mask)
1391 {
1392         struct amdgpu_device *adev = ring->adev;
1393
1394         amdgpu_ring_write(ring,
1395                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1396         amdgpu_ring_write(ring, reg << 2);
1397         amdgpu_ring_write(ring,
1398                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1399         amdgpu_ring_write(ring, val);
1400         amdgpu_ring_write(ring,
1401                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0));
1402         amdgpu_ring_write(ring, mask);
1403         amdgpu_ring_write(ring,
1404                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1405         amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1);
1406 }
1407
1408 static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
1409                                             unsigned vmid, uint64_t pd_addr)
1410 {
1411         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1412         uint32_t data0, data1, mask;
1413
1414         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1415
1416         /* wait for register write */
1417         data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
1418         data1 = lower_32_bits(pd_addr);
1419         mask = 0xffffffff;
1420         vcn_v1_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
1421 }
1422
1423 static void vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
1424                                         uint32_t reg, uint32_t val)
1425 {
1426         struct amdgpu_device *adev = ring->adev;
1427
1428         amdgpu_ring_write(ring,
1429                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1430         amdgpu_ring_write(ring, reg << 2);
1431         amdgpu_ring_write(ring,
1432                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1433         amdgpu_ring_write(ring, val);
1434         amdgpu_ring_write(ring,
1435                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1436         amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1);
1437 }
1438
1439 /**
1440  * vcn_v1_0_enc_ring_get_rptr - get enc read pointer
1441  *
1442  * @ring: amdgpu_ring pointer
1443  *
1444  * Returns the current hardware enc read pointer
1445  */
1446 static uint64_t vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
1447 {
1448         struct amdgpu_device *adev = ring->adev;
1449
1450         if (ring == &adev->vcn.ring_enc[0])
1451                 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
1452         else
1453                 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
1454 }
1455
1456  /**
1457  * vcn_v1_0_enc_ring_get_wptr - get enc write pointer
1458  *
1459  * @ring: amdgpu_ring pointer
1460  *
1461  * Returns the current hardware enc write pointer
1462  */
1463 static uint64_t vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
1464 {
1465         struct amdgpu_device *adev = ring->adev;
1466
1467         if (ring == &adev->vcn.ring_enc[0])
1468                 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1469         else
1470                 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1471 }
1472
1473  /**
1474  * vcn_v1_0_enc_ring_set_wptr - set enc write pointer
1475  *
1476  * @ring: amdgpu_ring pointer
1477  *
1478  * Commits the enc write pointer to the hardware
1479  */
1480 static void vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
1481 {
1482         struct amdgpu_device *adev = ring->adev;
1483
1484         if (ring == &adev->vcn.ring_enc[0])
1485                 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR,
1486                         lower_32_bits(ring->wptr));
1487         else
1488                 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2,
1489                         lower_32_bits(ring->wptr));
1490 }
1491
1492 /**
1493  * vcn_v1_0_enc_ring_emit_fence - emit an enc fence & trap command
1494  *
1495  * @ring: amdgpu_ring pointer
1496  * @fence: fence to emit
1497  *
1498  * Write enc a fence and a trap command to the ring.
1499  */
1500 static void vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1501                         u64 seq, unsigned flags)
1502 {
1503         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1504
1505         amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE);
1506         amdgpu_ring_write(ring, addr);
1507         amdgpu_ring_write(ring, upper_32_bits(addr));
1508         amdgpu_ring_write(ring, seq);
1509         amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP);
1510 }
1511
1512 static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1513 {
1514         amdgpu_ring_write(ring, VCN_ENC_CMD_END);
1515 }
1516
1517 /**
1518  * vcn_v1_0_enc_ring_emit_ib - enc execute indirect buffer
1519  *
1520  * @ring: amdgpu_ring pointer
1521  * @ib: indirect buffer to execute
1522  *
1523  * Write enc ring commands to execute the indirect buffer
1524  */
1525 static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1526                 struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch)
1527 {
1528         amdgpu_ring_write(ring, VCN_ENC_CMD_IB);
1529         amdgpu_ring_write(ring, vmid);
1530         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1531         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1532         amdgpu_ring_write(ring, ib->length_dw);
1533 }
1534
1535 static void vcn_v1_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring,
1536                                             uint32_t reg, uint32_t val,
1537                                             uint32_t mask)
1538 {
1539         amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
1540         amdgpu_ring_write(ring, reg << 2);
1541         amdgpu_ring_write(ring, mask);
1542         amdgpu_ring_write(ring, val);
1543 }
1544
1545 static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1546                                             unsigned int vmid, uint64_t pd_addr)
1547 {
1548         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1549
1550         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1551
1552         /* wait for reg writes */
1553         vcn_v1_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2,
1554                                         lower_32_bits(pd_addr), 0xffffffff);
1555 }
1556
1557 static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
1558                                         uint32_t reg, uint32_t val)
1559 {
1560         amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
1561         amdgpu_ring_write(ring, reg << 2);
1562         amdgpu_ring_write(ring, val);
1563 }
1564
1565
1566 /**
1567  * vcn_v1_0_jpeg_ring_get_rptr - get read pointer
1568  *
1569  * @ring: amdgpu_ring pointer
1570  *
1571  * Returns the current hardware read pointer
1572  */
1573 static uint64_t vcn_v1_0_jpeg_ring_get_rptr(struct amdgpu_ring *ring)
1574 {
1575         struct amdgpu_device *adev = ring->adev;
1576
1577         return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR);
1578 }
1579
1580 /**
1581  * vcn_v1_0_jpeg_ring_get_wptr - get write pointer
1582  *
1583  * @ring: amdgpu_ring pointer
1584  *
1585  * Returns the current hardware write pointer
1586  */
1587 static uint64_t vcn_v1_0_jpeg_ring_get_wptr(struct amdgpu_ring *ring)
1588 {
1589         struct amdgpu_device *adev = ring->adev;
1590
1591         return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
1592 }
1593
1594 /**
1595  * vcn_v1_0_jpeg_ring_set_wptr - set write pointer
1596  *
1597  * @ring: amdgpu_ring pointer
1598  *
1599  * Commits the write pointer to the hardware
1600  */
1601 static void vcn_v1_0_jpeg_ring_set_wptr(struct amdgpu_ring *ring)
1602 {
1603         struct amdgpu_device *adev = ring->adev;
1604
1605         WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
1606 }
1607
1608 /**
1609  * vcn_v1_0_jpeg_ring_insert_start - insert a start command
1610  *
1611  * @ring: amdgpu_ring pointer
1612  *
1613  * Write a start command to the ring.
1614  */
1615 static void vcn_v1_0_jpeg_ring_insert_start(struct amdgpu_ring *ring)
1616 {
1617         struct amdgpu_device *adev = ring->adev;
1618
1619         amdgpu_ring_write(ring,
1620                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
1621         amdgpu_ring_write(ring, 0x68e04);
1622
1623         amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));
1624         amdgpu_ring_write(ring, 0x80010000);
1625 }
1626
1627 /**
1628  * vcn_v1_0_jpeg_ring_insert_end - insert a end command
1629  *
1630  * @ring: amdgpu_ring pointer
1631  *
1632  * Write a end command to the ring.
1633  */
1634 static void vcn_v1_0_jpeg_ring_insert_end(struct amdgpu_ring *ring)
1635 {
1636         struct amdgpu_device *adev = ring->adev;
1637
1638         amdgpu_ring_write(ring,
1639                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
1640         amdgpu_ring_write(ring, 0x68e04);
1641
1642         amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));
1643         amdgpu_ring_write(ring, 0x00010000);
1644 }
1645
1646 /**
1647  * vcn_v1_0_jpeg_ring_emit_fence - emit an fence & trap command
1648  *
1649  * @ring: amdgpu_ring pointer
1650  * @fence: fence to emit
1651  *
1652  * Write a fence and a trap command to the ring.
1653  */
1654 static void vcn_v1_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1655                                      unsigned flags)
1656 {
1657         struct amdgpu_device *adev = ring->adev;
1658
1659         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1660
1661         amdgpu_ring_write(ring,
1662                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_DATA0), 0, 0, PACKETJ_TYPE0));
1663         amdgpu_ring_write(ring, seq);
1664
1665         amdgpu_ring_write(ring,
1666                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_DATA1), 0, 0, PACKETJ_TYPE0));
1667         amdgpu_ring_write(ring, seq);
1668
1669         amdgpu_ring_write(ring,
1670                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
1671         amdgpu_ring_write(ring, lower_32_bits(addr));
1672
1673         amdgpu_ring_write(ring,
1674                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
1675         amdgpu_ring_write(ring, upper_32_bits(addr));
1676
1677         amdgpu_ring_write(ring,
1678                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_CMD), 0, 0, PACKETJ_TYPE0));
1679         amdgpu_ring_write(ring, 0x8);
1680
1681         amdgpu_ring_write(ring,
1682                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_CMD), 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));
1683         amdgpu_ring_write(ring, 0);
1684
1685         amdgpu_ring_write(ring,
1686                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
1687         amdgpu_ring_write(ring, 0x01400200);
1688
1689         amdgpu_ring_write(ring,
1690                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
1691         amdgpu_ring_write(ring, seq);
1692
1693         amdgpu_ring_write(ring,
1694                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
1695         amdgpu_ring_write(ring, lower_32_bits(addr));
1696
1697         amdgpu_ring_write(ring,
1698                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
1699         amdgpu_ring_write(ring, upper_32_bits(addr));
1700
1701         amdgpu_ring_write(ring,
1702                 PACKETJ(0, 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE2));
1703         amdgpu_ring_write(ring, 0xffffffff);
1704
1705         amdgpu_ring_write(ring,
1706                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
1707         amdgpu_ring_write(ring, 0x3fbc);
1708
1709         amdgpu_ring_write(ring,
1710                 PACKETJ(0, 0, 0, PACKETJ_TYPE0));
1711         amdgpu_ring_write(ring, 0x1);
1712
1713         /* emit trap */
1714         amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));
1715         amdgpu_ring_write(ring, 0);
1716 }
1717
1718 /**
1719  * vcn_v1_0_jpeg_ring_emit_ib - execute indirect buffer
1720  *
1721  * @ring: amdgpu_ring pointer
1722  * @ib: indirect buffer to execute
1723  *
1724  * Write ring commands to execute the indirect buffer.
1725  */
1726 static void vcn_v1_0_jpeg_ring_emit_ib(struct amdgpu_ring *ring,
1727                                   struct amdgpu_ib *ib,
1728                                   unsigned vmid, bool ctx_switch)
1729 {
1730         struct amdgpu_device *adev = ring->adev;
1731
1732         amdgpu_ring_write(ring,
1733                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_VMID), 0, 0, PACKETJ_TYPE0));
1734         amdgpu_ring_write(ring, (vmid | (vmid << 4)));
1735
1736         amdgpu_ring_write(ring,
1737                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JPEG_VMID), 0, 0, PACKETJ_TYPE0));
1738         amdgpu_ring_write(ring, (vmid | (vmid << 4)));
1739
1740         amdgpu_ring_write(ring,
1741                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
1742         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1743
1744         amdgpu_ring_write(ring,
1745                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
1746         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1747
1748         amdgpu_ring_write(ring,
1749                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_IB_SIZE), 0, 0, PACKETJ_TYPE0));
1750         amdgpu_ring_write(ring, ib->length_dw);
1751
1752         amdgpu_ring_write(ring,
1753                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
1754         amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr));
1755
1756         amdgpu_ring_write(ring,
1757                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
1758         amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr));
1759
1760         amdgpu_ring_write(ring,
1761                 PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2));
1762         amdgpu_ring_write(ring, 0);
1763
1764         amdgpu_ring_write(ring,
1765                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
1766         amdgpu_ring_write(ring, 0x01400200);
1767
1768         amdgpu_ring_write(ring,
1769                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
1770         amdgpu_ring_write(ring, 0x2);
1771
1772         amdgpu_ring_write(ring,
1773                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_STATUS), 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3));
1774         amdgpu_ring_write(ring, 0x2);
1775 }
1776
1777 static void vcn_v1_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring,
1778                                             uint32_t reg, uint32_t val,
1779                                             uint32_t mask)
1780 {
1781         struct amdgpu_device *adev = ring->adev;
1782         uint32_t reg_offset = (reg << 2);
1783
1784         amdgpu_ring_write(ring,
1785                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
1786         amdgpu_ring_write(ring, 0x01400200);
1787
1788         amdgpu_ring_write(ring,
1789                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
1790         amdgpu_ring_write(ring, val);
1791
1792         amdgpu_ring_write(ring,
1793                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
1794         if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
1795                 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
1796                 amdgpu_ring_write(ring, 0);
1797                 amdgpu_ring_write(ring,
1798                         PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));
1799         } else {
1800                 amdgpu_ring_write(ring, reg_offset);
1801                 amdgpu_ring_write(ring,
1802                         PACKETJ(0, 0, 0, PACKETJ_TYPE3));
1803         }
1804         amdgpu_ring_write(ring, mask);
1805 }
1806
1807 static void vcn_v1_0_jpeg_ring_emit_vm_flush(struct amdgpu_ring *ring,
1808                 unsigned vmid, uint64_t pd_addr)
1809 {
1810         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1811         uint32_t data0, data1, mask;
1812
1813         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1814
1815         /* wait for register write */
1816         data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
1817         data1 = lower_32_bits(pd_addr);
1818         mask = 0xffffffff;
1819         vcn_v1_0_jpeg_ring_emit_reg_wait(ring, data0, data1, mask);
1820 }
1821
1822 static void vcn_v1_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring,
1823                                         uint32_t reg, uint32_t val)
1824 {
1825         struct amdgpu_device *adev = ring->adev;
1826         uint32_t reg_offset = (reg << 2);
1827
1828         amdgpu_ring_write(ring,
1829                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
1830         if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
1831                         ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
1832                 amdgpu_ring_write(ring, 0);
1833                 amdgpu_ring_write(ring,
1834                         PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));
1835         } else {
1836                 amdgpu_ring_write(ring, reg_offset);
1837                 amdgpu_ring_write(ring,
1838                         PACKETJ(0, 0, 0, PACKETJ_TYPE0));
1839         }
1840         amdgpu_ring_write(ring, val);
1841 }
1842
1843 static void vcn_v1_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count)
1844 {
1845         int i;
1846
1847         WARN_ON(ring->wptr % 2 || count % 2);
1848
1849         for (i = 0; i < count / 2; i++) {
1850                 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
1851                 amdgpu_ring_write(ring, 0);
1852         }
1853 }
1854
1855 static void vcn_v1_0_jpeg_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val)
1856 {
1857         struct amdgpu_device *adev = ring->adev;
1858         ring->ring[(*ptr)++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0);
1859         if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
1860                 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
1861                 ring->ring[(*ptr)++] = 0;
1862                 ring->ring[(*ptr)++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0);
1863         } else {
1864                 ring->ring[(*ptr)++] = reg_offset;
1865                 ring->ring[(*ptr)++] = PACKETJ(0, 0, 0, PACKETJ_TYPE0);
1866         }
1867         ring->ring[(*ptr)++] = val;
1868 }
1869
1870 static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr)
1871 {
1872         struct amdgpu_device *adev = ring->adev;
1873
1874         uint32_t reg, reg_offset, val, mask, i;
1875
1876         // 1st: program mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW
1877         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW);
1878         reg_offset = (reg << 2);
1879         val = lower_32_bits(ring->gpu_addr);
1880         vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1881
1882         // 2nd: program mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH
1883         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH);
1884         reg_offset = (reg << 2);
1885         val = upper_32_bits(ring->gpu_addr);
1886         vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1887
1888         // 3rd to 5th: issue MEM_READ commands
1889         for (i = 0; i <= 2; i++) {
1890                 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE2);
1891                 ring->ring[ptr++] = 0;
1892         }
1893
1894         // 6th: program mmUVD_JRBC_RB_CNTL register to enable NO_FETCH and RPTR write ability
1895         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
1896         reg_offset = (reg << 2);
1897         val = 0x13;
1898         vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1899
1900         // 7th: program mmUVD_JRBC_RB_REF_DATA
1901         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA);
1902         reg_offset = (reg << 2);
1903         val = 0x1;
1904         vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1905
1906         // 8th: issue conditional register read mmUVD_JRBC_RB_CNTL
1907         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
1908         reg_offset = (reg << 2);
1909         val = 0x1;
1910         mask = 0x1;
1911
1912         ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0);
1913         ring->ring[ptr++] = 0x01400200;
1914         ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0);
1915         ring->ring[ptr++] = val;
1916         ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0);
1917         if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
1918                 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
1919                 ring->ring[ptr++] = 0;
1920                 ring->ring[ptr++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3);
1921         } else {
1922                 ring->ring[ptr++] = reg_offset;
1923                 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE3);
1924         }
1925         ring->ring[ptr++] = mask;
1926
1927         //9th to 21st: insert no-op
1928         for (i = 0; i <= 12; i++) {
1929                 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
1930                 ring->ring[ptr++] = 0;
1931         }
1932
1933         //22nd: reset mmUVD_JRBC_RB_RPTR
1934         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_RPTR);
1935         reg_offset = (reg << 2);
1936         val = 0;
1937         vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1938
1939         //23rd: program mmUVD_JRBC_RB_CNTL to disable no_fetch
1940         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
1941         reg_offset = (reg << 2);
1942         val = 0x12;
1943         vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1944 }
1945
1946 static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev,
1947                                         struct amdgpu_irq_src *source,
1948                                         unsigned type,
1949                                         enum amdgpu_interrupt_state state)
1950 {
1951         return 0;
1952 }
1953
1954 static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev,
1955                                       struct amdgpu_irq_src *source,
1956                                       struct amdgpu_iv_entry *entry)
1957 {
1958         DRM_DEBUG("IH: VCN TRAP\n");
1959
1960         switch (entry->src_id) {
1961         case 124:
1962                 amdgpu_fence_process(&adev->vcn.ring_dec);
1963                 break;
1964         case 119:
1965                 amdgpu_fence_process(&adev->vcn.ring_enc[0]);
1966                 break;
1967         case 120:
1968                 amdgpu_fence_process(&adev->vcn.ring_enc[1]);
1969                 break;
1970         case 126:
1971                 amdgpu_fence_process(&adev->vcn.ring_jpeg);
1972                 break;
1973         default:
1974                 DRM_ERROR("Unhandled interrupt: %d %d\n",
1975                           entry->src_id, entry->src_data[0]);
1976                 break;
1977         }
1978
1979         return 0;
1980 }
1981
1982 static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1983 {
1984         struct amdgpu_device *adev = ring->adev;
1985         int i;
1986
1987         WARN_ON(ring->wptr % 2 || count % 2);
1988
1989         for (i = 0; i < count / 2; i++) {
1990                 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0));
1991                 amdgpu_ring_write(ring, 0);
1992         }
1993 }
1994
1995 static int vcn_v1_0_set_powergating_state(void *handle,
1996                                           enum amd_powergating_state state)
1997 {
1998         /* This doesn't actually powergate the VCN block.
1999          * That's done in the dpm code via the SMC.  This
2000          * just re-inits the block as necessary.  The actual
2001          * gating still happens in the dpm code.  We should
2002          * revisit this when there is a cleaner line between
2003          * the smc and the hw blocks
2004          */
2005         int ret;
2006         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2007
2008         if(state == adev->vcn.cur_state)
2009                 return 0;
2010
2011         if (state == AMD_PG_STATE_GATE)
2012                 ret = vcn_v1_0_stop(adev);
2013         else
2014                 ret = vcn_v1_0_start(adev);
2015
2016         if(!ret)
2017                 adev->vcn.cur_state = state;
2018         return ret;
2019 }
2020
2021 static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
2022         .name = "vcn_v1_0",
2023         .early_init = vcn_v1_0_early_init,
2024         .late_init = NULL,
2025         .sw_init = vcn_v1_0_sw_init,
2026         .sw_fini = vcn_v1_0_sw_fini,
2027         .hw_init = vcn_v1_0_hw_init,
2028         .hw_fini = vcn_v1_0_hw_fini,
2029         .suspend = vcn_v1_0_suspend,
2030         .resume = vcn_v1_0_resume,
2031         .is_idle = vcn_v1_0_is_idle,
2032         .wait_for_idle = vcn_v1_0_wait_for_idle,
2033         .check_soft_reset = NULL /* vcn_v1_0_check_soft_reset */,
2034         .pre_soft_reset = NULL /* vcn_v1_0_pre_soft_reset */,
2035         .soft_reset = NULL /* vcn_v1_0_soft_reset */,
2036         .post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */,
2037         .set_clockgating_state = vcn_v1_0_set_clockgating_state,
2038         .set_powergating_state = vcn_v1_0_set_powergating_state,
2039 };
2040
2041 static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
2042         .type = AMDGPU_RING_TYPE_VCN_DEC,
2043         .align_mask = 0xf,
2044         .support_64bit_ptrs = false,
2045         .vmhub = AMDGPU_MMHUB,
2046         .get_rptr = vcn_v1_0_dec_ring_get_rptr,
2047         .get_wptr = vcn_v1_0_dec_ring_get_wptr,
2048         .set_wptr = vcn_v1_0_dec_ring_set_wptr,
2049         .emit_frame_size =
2050                 6 + 6 + /* hdp invalidate / flush */
2051                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
2052                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
2053                 8 + /* vcn_v1_0_dec_ring_emit_vm_flush */
2054                 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */
2055                 6,
2056         .emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */
2057         .emit_ib = vcn_v1_0_dec_ring_emit_ib,
2058         .emit_fence = vcn_v1_0_dec_ring_emit_fence,
2059         .emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush,
2060         .test_ring = amdgpu_vcn_dec_ring_test_ring,
2061         .test_ib = amdgpu_vcn_dec_ring_test_ib,
2062         .insert_nop = vcn_v1_0_dec_ring_insert_nop,
2063         .insert_start = vcn_v1_0_dec_ring_insert_start,
2064         .insert_end = vcn_v1_0_dec_ring_insert_end,
2065         .pad_ib = amdgpu_ring_generic_pad_ib,
2066         .begin_use = amdgpu_vcn_ring_begin_use,
2067         .end_use = amdgpu_vcn_ring_end_use,
2068         .emit_wreg = vcn_v1_0_dec_ring_emit_wreg,
2069         .emit_reg_wait = vcn_v1_0_dec_ring_emit_reg_wait,
2070         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2071 };
2072
2073 static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = {
2074         .type = AMDGPU_RING_TYPE_VCN_ENC,
2075         .align_mask = 0x3f,
2076         .nop = VCN_ENC_CMD_NO_OP,
2077         .support_64bit_ptrs = false,
2078         .vmhub = AMDGPU_MMHUB,
2079         .get_rptr = vcn_v1_0_enc_ring_get_rptr,
2080         .get_wptr = vcn_v1_0_enc_ring_get_wptr,
2081         .set_wptr = vcn_v1_0_enc_ring_set_wptr,
2082         .emit_frame_size =
2083                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2084                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
2085                 4 + /* vcn_v1_0_enc_ring_emit_vm_flush */
2086                 5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */
2087                 1, /* vcn_v1_0_enc_ring_insert_end */
2088         .emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */
2089         .emit_ib = vcn_v1_0_enc_ring_emit_ib,
2090         .emit_fence = vcn_v1_0_enc_ring_emit_fence,
2091         .emit_vm_flush = vcn_v1_0_enc_ring_emit_vm_flush,
2092         .test_ring = amdgpu_vcn_enc_ring_test_ring,
2093         .test_ib = amdgpu_vcn_enc_ring_test_ib,
2094         .insert_nop = amdgpu_ring_insert_nop,
2095         .insert_end = vcn_v1_0_enc_ring_insert_end,
2096         .pad_ib = amdgpu_ring_generic_pad_ib,
2097         .begin_use = amdgpu_vcn_ring_begin_use,
2098         .end_use = amdgpu_vcn_ring_end_use,
2099         .emit_wreg = vcn_v1_0_enc_ring_emit_wreg,
2100         .emit_reg_wait = vcn_v1_0_enc_ring_emit_reg_wait,
2101         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2102 };
2103
2104 static const struct amdgpu_ring_funcs vcn_v1_0_jpeg_ring_vm_funcs = {
2105         .type = AMDGPU_RING_TYPE_VCN_JPEG,
2106         .align_mask = 0xf,
2107         .nop = PACKET0(0x81ff, 0),
2108         .support_64bit_ptrs = false,
2109         .vmhub = AMDGPU_MMHUB,
2110         .extra_dw = 64,
2111         .get_rptr = vcn_v1_0_jpeg_ring_get_rptr,
2112         .get_wptr = vcn_v1_0_jpeg_ring_get_wptr,
2113         .set_wptr = vcn_v1_0_jpeg_ring_set_wptr,
2114         .emit_frame_size =
2115                 6 + 6 + /* hdp invalidate / flush */
2116                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
2117                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
2118                 8 + /* vcn_v1_0_jpeg_ring_emit_vm_flush */
2119                 26 + 26 + /* vcn_v1_0_jpeg_ring_emit_fence x2 vm fence */
2120                 6,
2121         .emit_ib_size = 22, /* vcn_v1_0_jpeg_ring_emit_ib */
2122         .emit_ib = vcn_v1_0_jpeg_ring_emit_ib,
2123         .emit_fence = vcn_v1_0_jpeg_ring_emit_fence,
2124         .emit_vm_flush = vcn_v1_0_jpeg_ring_emit_vm_flush,
2125         .test_ring = amdgpu_vcn_jpeg_ring_test_ring,
2126         .test_ib = amdgpu_vcn_jpeg_ring_test_ib,
2127         .insert_nop = vcn_v1_0_jpeg_ring_nop,
2128         .insert_start = vcn_v1_0_jpeg_ring_insert_start,
2129         .insert_end = vcn_v1_0_jpeg_ring_insert_end,
2130         .pad_ib = amdgpu_ring_generic_pad_ib,
2131         .begin_use = amdgpu_vcn_ring_begin_use,
2132         .end_use = amdgpu_vcn_ring_end_use,
2133         .emit_wreg = vcn_v1_0_jpeg_ring_emit_wreg,
2134         .emit_reg_wait = vcn_v1_0_jpeg_ring_emit_reg_wait,
2135         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2136 };
2137
2138 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev)
2139 {
2140         adev->vcn.ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs;
2141         DRM_INFO("VCN decode is enabled in VM mode\n");
2142 }
2143
2144 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev)
2145 {
2146         int i;
2147
2148         for (i = 0; i < adev->vcn.num_enc_rings; ++i)
2149                 adev->vcn.ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs;
2150
2151         DRM_INFO("VCN encode is enabled in VM mode\n");
2152 }
2153
2154 static void vcn_v1_0_set_jpeg_ring_funcs(struct amdgpu_device *adev)
2155 {
2156         adev->vcn.ring_jpeg.funcs = &vcn_v1_0_jpeg_ring_vm_funcs;
2157         DRM_INFO("VCN jpeg decode is enabled in VM mode\n");
2158 }
2159
2160 static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = {
2161         .set = vcn_v1_0_set_interrupt_state,
2162         .process = vcn_v1_0_process_interrupt,
2163 };
2164
2165 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev)
2166 {
2167         adev->vcn.irq.num_types = adev->vcn.num_enc_rings + 2;
2168         adev->vcn.irq.funcs = &vcn_v1_0_irq_funcs;
2169 }
2170
2171 const struct amdgpu_ip_block_version vcn_v1_0_ip_block =
2172 {
2173                 .type = AMD_IP_BLOCK_TYPE_VCN,
2174                 .major = 1,
2175                 .minor = 0,
2176                 .rev = 0,
2177                 .funcs = &vcn_v1_0_ip_funcs,
2178 };