Merge tag 'drm-next-2018-06-15' of git://anongit.freedesktop.org/drm/drm
[muen/linux.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm.c
1 /*
2  * Copyright 2015 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25
26 #include "dm_services_types.h"
27 #include "dc.h"
28 #include "dc/inc/core_types.h"
29
30 #include "vid.h"
31 #include "amdgpu.h"
32 #include "amdgpu_display.h"
33 #include "atom.h"
34 #include "amdgpu_dm.h"
35 #include "amdgpu_pm.h"
36
37 #include "amd_shared.h"
38 #include "amdgpu_dm_irq.h"
39 #include "dm_helpers.h"
40 #include "dm_services_types.h"
41 #include "amdgpu_dm_mst_types.h"
42
43 #include "ivsrcid/ivsrcid_vislands30.h"
44
45 #include <linux/module.h>
46 #include <linux/moduleparam.h>
47 #include <linux/version.h>
48 #include <linux/types.h>
49 #include <linux/pm_runtime.h>
50
51 #include <drm/drmP.h>
52 #include <drm/drm_atomic.h>
53 #include <drm/drm_atomic_helper.h>
54 #include <drm/drm_dp_mst_helper.h>
55 #include <drm/drm_fb_helper.h>
56 #include <drm/drm_edid.h>
57
58 #include "modules/inc/mod_freesync.h"
59
60 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
61 #include "ivsrcid/irqsrcs_dcn_1_0.h"
62
63 #include "dcn/dcn_1_0_offset.h"
64 #include "dcn/dcn_1_0_sh_mask.h"
65 #include "soc15_hw_ip.h"
66 #include "vega10_ip_offset.h"
67
68 #include "soc15_common.h"
69 #endif
70
71 #include "modules/inc/mod_freesync.h"
72
73 #include "i2caux_interface.h"
74
75 /* basic init/fini API */
76 static int amdgpu_dm_init(struct amdgpu_device *adev);
77 static void amdgpu_dm_fini(struct amdgpu_device *adev);
78
79 /* initializes drm_device display related structures, based on the information
80  * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
81  * drm_encoder, drm_mode_config
82  *
83  * Returns 0 on success
84  */
85 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
86 /* removes and deallocates the drm structures, created by the above function */
87 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
88
89 static void
90 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
91
92 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
93                                 struct amdgpu_plane *aplane,
94                                 unsigned long possible_crtcs);
95 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
96                                struct drm_plane *plane,
97                                uint32_t link_index);
98 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
99                                     struct amdgpu_dm_connector *amdgpu_dm_connector,
100                                     uint32_t link_index,
101                                     struct amdgpu_encoder *amdgpu_encoder);
102 static int amdgpu_dm_encoder_init(struct drm_device *dev,
103                                   struct amdgpu_encoder *aencoder,
104                                   uint32_t link_index);
105
106 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
107
108 static int amdgpu_dm_atomic_commit(struct drm_device *dev,
109                                    struct drm_atomic_state *state,
110                                    bool nonblock);
111
112 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
113
114 static int amdgpu_dm_atomic_check(struct drm_device *dev,
115                                   struct drm_atomic_state *state);
116
117
118
119
120 static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {
121         DRM_PLANE_TYPE_PRIMARY,
122         DRM_PLANE_TYPE_PRIMARY,
123         DRM_PLANE_TYPE_PRIMARY,
124         DRM_PLANE_TYPE_PRIMARY,
125         DRM_PLANE_TYPE_PRIMARY,
126         DRM_PLANE_TYPE_PRIMARY,
127 };
128
129 static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {
130         DRM_PLANE_TYPE_PRIMARY,
131         DRM_PLANE_TYPE_PRIMARY,
132         DRM_PLANE_TYPE_PRIMARY,
133         DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */
134 };
135
136 static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {
137         DRM_PLANE_TYPE_PRIMARY,
138         DRM_PLANE_TYPE_PRIMARY,
139         DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */
140 };
141
142 /*
143  * dm_vblank_get_counter
144  *
145  * @brief
146  * Get counter for number of vertical blanks
147  *
148  * @param
149  * struct amdgpu_device *adev - [in] desired amdgpu device
150  * int disp_idx - [in] which CRTC to get the counter from
151  *
152  * @return
153  * Counter for vertical blanks
154  */
155 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
156 {
157         if (crtc >= adev->mode_info.num_crtc)
158                 return 0;
159         else {
160                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
161                 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
162                                 acrtc->base.state);
163
164
165                 if (acrtc_state->stream == NULL) {
166                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
167                                   crtc);
168                         return 0;
169                 }
170
171                 return dc_stream_get_vblank_counter(acrtc_state->stream);
172         }
173 }
174
175 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
176                                   u32 *vbl, u32 *position)
177 {
178         uint32_t v_blank_start, v_blank_end, h_position, v_position;
179
180         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
181                 return -EINVAL;
182         else {
183                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
184                 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
185                                                 acrtc->base.state);
186
187                 if (acrtc_state->stream ==  NULL) {
188                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
189                                   crtc);
190                         return 0;
191                 }
192
193                 /*
194                  * TODO rework base driver to use values directly.
195                  * for now parse it back into reg-format
196                  */
197                 dc_stream_get_scanoutpos(acrtc_state->stream,
198                                          &v_blank_start,
199                                          &v_blank_end,
200                                          &h_position,
201                                          &v_position);
202
203                 *position = v_position | (h_position << 16);
204                 *vbl = v_blank_start | (v_blank_end << 16);
205         }
206
207         return 0;
208 }
209
210 static bool dm_is_idle(void *handle)
211 {
212         /* XXX todo */
213         return true;
214 }
215
216 static int dm_wait_for_idle(void *handle)
217 {
218         /* XXX todo */
219         return 0;
220 }
221
222 static bool dm_check_soft_reset(void *handle)
223 {
224         return false;
225 }
226
227 static int dm_soft_reset(void *handle)
228 {
229         /* XXX todo */
230         return 0;
231 }
232
233 static struct amdgpu_crtc *
234 get_crtc_by_otg_inst(struct amdgpu_device *adev,
235                      int otg_inst)
236 {
237         struct drm_device *dev = adev->ddev;
238         struct drm_crtc *crtc;
239         struct amdgpu_crtc *amdgpu_crtc;
240
241         /*
242          * following if is check inherited from both functions where this one is
243          * used now. Need to be checked why it could happen.
244          */
245         if (otg_inst == -1) {
246                 WARN_ON(1);
247                 return adev->mode_info.crtcs[0];
248         }
249
250         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
251                 amdgpu_crtc = to_amdgpu_crtc(crtc);
252
253                 if (amdgpu_crtc->otg_inst == otg_inst)
254                         return amdgpu_crtc;
255         }
256
257         return NULL;
258 }
259
260 static void dm_pflip_high_irq(void *interrupt_params)
261 {
262         struct amdgpu_crtc *amdgpu_crtc;
263         struct common_irq_params *irq_params = interrupt_params;
264         struct amdgpu_device *adev = irq_params->adev;
265         unsigned long flags;
266
267         amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
268
269         /* IRQ could occur when in initial stage */
270         /*TODO work and BO cleanup */
271         if (amdgpu_crtc == NULL) {
272                 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
273                 return;
274         }
275
276         spin_lock_irqsave(&adev->ddev->event_lock, flags);
277
278         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
279                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
280                                                  amdgpu_crtc->pflip_status,
281                                                  AMDGPU_FLIP_SUBMITTED,
282                                                  amdgpu_crtc->crtc_id,
283                                                  amdgpu_crtc);
284                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
285                 return;
286         }
287
288
289         /* wakeup usersapce */
290         if (amdgpu_crtc->event) {
291                 /* Update to correct count/ts if racing with vblank irq */
292                 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
293
294                 drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
295
296                 /* page flip completed. clean up */
297                 amdgpu_crtc->event = NULL;
298
299         } else
300                 WARN_ON(1);
301
302         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
303         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
304
305         DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n",
306                                         __func__, amdgpu_crtc->crtc_id, amdgpu_crtc);
307
308         drm_crtc_vblank_put(&amdgpu_crtc->base);
309 }
310
311 static void dm_crtc_high_irq(void *interrupt_params)
312 {
313         struct common_irq_params *irq_params = interrupt_params;
314         struct amdgpu_device *adev = irq_params->adev;
315         uint8_t crtc_index = 0;
316         struct amdgpu_crtc *acrtc;
317
318         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
319
320         if (acrtc)
321                 crtc_index = acrtc->crtc_id;
322
323         drm_handle_vblank(adev->ddev, crtc_index);
324         amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
325 }
326
327 static int dm_set_clockgating_state(void *handle,
328                   enum amd_clockgating_state state)
329 {
330         return 0;
331 }
332
333 static int dm_set_powergating_state(void *handle,
334                   enum amd_powergating_state state)
335 {
336         return 0;
337 }
338
339 /* Prototypes of private functions */
340 static int dm_early_init(void* handle);
341
342 static void hotplug_notify_work_func(struct work_struct *work)
343 {
344         struct amdgpu_display_manager *dm = container_of(work, struct amdgpu_display_manager, mst_hotplug_work);
345         struct drm_device *dev = dm->ddev;
346
347         drm_kms_helper_hotplug_event(dev);
348 }
349
350 #if defined(CONFIG_DRM_AMD_DC_FBC)
351 /* Allocate memory for FBC compressed data  */
352 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
353 {
354         struct drm_device *dev = connector->dev;
355         struct amdgpu_device *adev = dev->dev_private;
356         struct dm_comressor_info *compressor = &adev->dm.compressor;
357         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
358         struct drm_display_mode *mode;
359         unsigned long max_size = 0;
360
361         if (adev->dm.dc->fbc_compressor == NULL)
362                 return;
363
364         if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
365                 return;
366
367         if (compressor->bo_ptr)
368                 return;
369
370
371         list_for_each_entry(mode, &connector->modes, head) {
372                 if (max_size < mode->htotal * mode->vtotal)
373                         max_size = mode->htotal * mode->vtotal;
374         }
375
376         if (max_size) {
377                 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
378                             AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
379                             &compressor->gpu_addr, &compressor->cpu_addr);
380
381                 if (r)
382                         DRM_ERROR("DM: Failed to initialize FBC\n");
383                 else {
384                         adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
385                         DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
386                 }
387
388         }
389
390 }
391 #endif
392
393
394 /* Init display KMS
395  *
396  * Returns 0 on success
397  */
398 static int amdgpu_dm_init(struct amdgpu_device *adev)
399 {
400         struct dc_init_data init_data;
401         adev->dm.ddev = adev->ddev;
402         adev->dm.adev = adev;
403
404         /* Zero all the fields */
405         memset(&init_data, 0, sizeof(init_data));
406
407         if(amdgpu_dm_irq_init(adev)) {
408                 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
409                 goto error;
410         }
411
412         init_data.asic_id.chip_family = adev->family;
413
414         init_data.asic_id.pci_revision_id = adev->rev_id;
415         init_data.asic_id.hw_internal_rev = adev->external_rev_id;
416
417         init_data.asic_id.vram_width = adev->gmc.vram_width;
418         /* TODO: initialize init_data.asic_id.vram_type here!!!! */
419         init_data.asic_id.atombios_base_address =
420                 adev->mode_info.atom_context->bios;
421
422         init_data.driver = adev;
423
424         adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
425
426         if (!adev->dm.cgs_device) {
427                 DRM_ERROR("amdgpu: failed to create cgs device.\n");
428                 goto error;
429         }
430
431         init_data.cgs_device = adev->dm.cgs_device;
432
433         adev->dm.dal = NULL;
434
435         init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
436
437         /*
438          * TODO debug why this doesn't work on Raven
439          */
440         if (adev->flags & AMD_IS_APU &&
441             adev->asic_type >= CHIP_CARRIZO &&
442             adev->asic_type < CHIP_RAVEN)
443                 init_data.flags.gpu_vm_support = true;
444
445         /* Display Core create. */
446         adev->dm.dc = dc_create(&init_data);
447
448         if (adev->dm.dc) {
449                 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
450         } else {
451                 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
452                 goto error;
453         }
454
455         INIT_WORK(&adev->dm.mst_hotplug_work, hotplug_notify_work_func);
456
457         adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
458         if (!adev->dm.freesync_module) {
459                 DRM_ERROR(
460                 "amdgpu: failed to initialize freesync_module.\n");
461         } else
462                 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
463                                 adev->dm.freesync_module);
464
465         amdgpu_dm_init_color_mod();
466
467         if (amdgpu_dm_initialize_drm_device(adev)) {
468                 DRM_ERROR(
469                 "amdgpu: failed to initialize sw for display support.\n");
470                 goto error;
471         }
472
473         /* Update the actual used number of crtc */
474         adev->mode_info.num_crtc = adev->dm.display_indexes_num;
475
476         /* TODO: Add_display_info? */
477
478         /* TODO use dynamic cursor width */
479         adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
480         adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
481
482         if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
483                 DRM_ERROR(
484                 "amdgpu: failed to initialize sw for display support.\n");
485                 goto error;
486         }
487
488         DRM_DEBUG_DRIVER("KMS initialized.\n");
489
490         return 0;
491 error:
492         amdgpu_dm_fini(adev);
493
494         return -1;
495 }
496
497 static void amdgpu_dm_fini(struct amdgpu_device *adev)
498 {
499         amdgpu_dm_destroy_drm_device(&adev->dm);
500         /*
501          * TODO: pageflip, vlank interrupt
502          *
503          * amdgpu_dm_irq_fini(adev);
504          */
505
506         if (adev->dm.cgs_device) {
507                 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
508                 adev->dm.cgs_device = NULL;
509         }
510         if (adev->dm.freesync_module) {
511                 mod_freesync_destroy(adev->dm.freesync_module);
512                 adev->dm.freesync_module = NULL;
513         }
514         /* DC Destroy TODO: Replace destroy DAL */
515         if (adev->dm.dc)
516                 dc_destroy(&adev->dm.dc);
517         return;
518 }
519
520 static int dm_sw_init(void *handle)
521 {
522         return 0;
523 }
524
525 static int dm_sw_fini(void *handle)
526 {
527         return 0;
528 }
529
530 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
531 {
532         struct amdgpu_dm_connector *aconnector;
533         struct drm_connector *connector;
534         int ret = 0;
535
536         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
537
538         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
539                 aconnector = to_amdgpu_dm_connector(connector);
540                 if (aconnector->dc_link->type == dc_connection_mst_branch &&
541                     aconnector->mst_mgr.aux) {
542                         DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
543                                         aconnector, aconnector->base.base.id);
544
545                         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
546                         if (ret < 0) {
547                                 DRM_ERROR("DM_MST: Failed to start MST\n");
548                                 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
549                                 return ret;
550                                 }
551                         }
552         }
553
554         drm_modeset_unlock(&dev->mode_config.connection_mutex);
555         return ret;
556 }
557
558 static int dm_late_init(void *handle)
559 {
560         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
561
562         return detect_mst_link_for_all_connectors(adev->ddev);
563 }
564
565 static void s3_handle_mst(struct drm_device *dev, bool suspend)
566 {
567         struct amdgpu_dm_connector *aconnector;
568         struct drm_connector *connector;
569
570         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
571
572         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
573                    aconnector = to_amdgpu_dm_connector(connector);
574                    if (aconnector->dc_link->type == dc_connection_mst_branch &&
575                                    !aconnector->mst_port) {
576
577                            if (suspend)
578                                    drm_dp_mst_topology_mgr_suspend(&aconnector->mst_mgr);
579                            else
580                                    drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr);
581                    }
582         }
583
584         drm_modeset_unlock(&dev->mode_config.connection_mutex);
585 }
586
587 static int dm_hw_init(void *handle)
588 {
589         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
590         /* Create DAL display manager */
591         amdgpu_dm_init(adev);
592         amdgpu_dm_hpd_init(adev);
593
594         return 0;
595 }
596
597 static int dm_hw_fini(void *handle)
598 {
599         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
600
601         amdgpu_dm_hpd_fini(adev);
602
603         amdgpu_dm_irq_fini(adev);
604         amdgpu_dm_fini(adev);
605         return 0;
606 }
607
608 static int dm_suspend(void *handle)
609 {
610         struct amdgpu_device *adev = handle;
611         struct amdgpu_display_manager *dm = &adev->dm;
612         int ret = 0;
613
614         s3_handle_mst(adev->ddev, true);
615
616         amdgpu_dm_irq_suspend(adev);
617
618         WARN_ON(adev->dm.cached_state);
619         adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
620
621         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
622
623         return ret;
624 }
625
626 static struct amdgpu_dm_connector *
627 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
628                                              struct drm_crtc *crtc)
629 {
630         uint32_t i;
631         struct drm_connector_state *new_con_state;
632         struct drm_connector *connector;
633         struct drm_crtc *crtc_from_state;
634
635         for_each_new_connector_in_state(state, connector, new_con_state, i) {
636                 crtc_from_state = new_con_state->crtc;
637
638                 if (crtc_from_state == crtc)
639                         return to_amdgpu_dm_connector(connector);
640         }
641
642         return NULL;
643 }
644
645 static int dm_resume(void *handle)
646 {
647         struct amdgpu_device *adev = handle;
648         struct drm_device *ddev = adev->ddev;
649         struct amdgpu_display_manager *dm = &adev->dm;
650         struct amdgpu_dm_connector *aconnector;
651         struct drm_connector *connector;
652         struct drm_crtc *crtc;
653         struct drm_crtc_state *new_crtc_state;
654         struct dm_crtc_state *dm_new_crtc_state;
655         struct drm_plane *plane;
656         struct drm_plane_state *new_plane_state;
657         struct dm_plane_state *dm_new_plane_state;
658         int ret;
659         int i;
660
661         /* power on hardware */
662         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
663
664         /* program HPD filter */
665         dc_resume(dm->dc);
666
667         /* On resume we need to  rewrite the MSTM control bits to enamble MST*/
668         s3_handle_mst(ddev, false);
669
670         /*
671          * early enable HPD Rx IRQ, should be done before set mode as short
672          * pulse interrupts are used for MST
673          */
674         amdgpu_dm_irq_resume_early(adev);
675
676         /* Do detection*/
677         list_for_each_entry(connector, &ddev->mode_config.connector_list, head) {
678                 aconnector = to_amdgpu_dm_connector(connector);
679
680                 /*
681                  * this is the case when traversing through already created
682                  * MST connectors, should be skipped
683                  */
684                 if (aconnector->mst_port)
685                         continue;
686
687                 mutex_lock(&aconnector->hpd_lock);
688                 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
689
690                 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
691                         aconnector->fake_enable = false;
692
693                 aconnector->dc_sink = NULL;
694                 amdgpu_dm_update_connector_after_detect(aconnector);
695                 mutex_unlock(&aconnector->hpd_lock);
696         }
697
698         /* Force mode set in atomic comit */
699         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
700                 new_crtc_state->active_changed = true;
701
702         /*
703          * atomic_check is expected to create the dc states. We need to release
704          * them here, since they were duplicated as part of the suspend
705          * procedure.
706          */
707         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
708                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
709                 if (dm_new_crtc_state->stream) {
710                         WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
711                         dc_stream_release(dm_new_crtc_state->stream);
712                         dm_new_crtc_state->stream = NULL;
713                 }
714         }
715
716         for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
717                 dm_new_plane_state = to_dm_plane_state(new_plane_state);
718                 if (dm_new_plane_state->dc_state) {
719                         WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
720                         dc_plane_state_release(dm_new_plane_state->dc_state);
721                         dm_new_plane_state->dc_state = NULL;
722                 }
723         }
724
725         ret = drm_atomic_helper_resume(ddev, dm->cached_state);
726
727         dm->cached_state = NULL;
728
729         amdgpu_dm_irq_resume_late(adev);
730
731         return ret;
732 }
733
734 static const struct amd_ip_funcs amdgpu_dm_funcs = {
735         .name = "dm",
736         .early_init = dm_early_init,
737         .late_init = dm_late_init,
738         .sw_init = dm_sw_init,
739         .sw_fini = dm_sw_fini,
740         .hw_init = dm_hw_init,
741         .hw_fini = dm_hw_fini,
742         .suspend = dm_suspend,
743         .resume = dm_resume,
744         .is_idle = dm_is_idle,
745         .wait_for_idle = dm_wait_for_idle,
746         .check_soft_reset = dm_check_soft_reset,
747         .soft_reset = dm_soft_reset,
748         .set_clockgating_state = dm_set_clockgating_state,
749         .set_powergating_state = dm_set_powergating_state,
750 };
751
752 const struct amdgpu_ip_block_version dm_ip_block =
753 {
754         .type = AMD_IP_BLOCK_TYPE_DCE,
755         .major = 1,
756         .minor = 0,
757         .rev = 0,
758         .funcs = &amdgpu_dm_funcs,
759 };
760
761
762 static struct drm_atomic_state *
763 dm_atomic_state_alloc(struct drm_device *dev)
764 {
765         struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
766
767         if (!state)
768                 return NULL;
769
770         if (drm_atomic_state_init(dev, &state->base) < 0)
771                 goto fail;
772
773         return &state->base;
774
775 fail:
776         kfree(state);
777         return NULL;
778 }
779
780 static void
781 dm_atomic_state_clear(struct drm_atomic_state *state)
782 {
783         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
784
785         if (dm_state->context) {
786                 dc_release_state(dm_state->context);
787                 dm_state->context = NULL;
788         }
789
790         drm_atomic_state_default_clear(state);
791 }
792
793 static void
794 dm_atomic_state_alloc_free(struct drm_atomic_state *state)
795 {
796         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
797         drm_atomic_state_default_release(state);
798         kfree(dm_state);
799 }
800
801 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
802         .fb_create = amdgpu_display_user_framebuffer_create,
803         .output_poll_changed = drm_fb_helper_output_poll_changed,
804         .atomic_check = amdgpu_dm_atomic_check,
805         .atomic_commit = amdgpu_dm_atomic_commit,
806         .atomic_state_alloc = dm_atomic_state_alloc,
807         .atomic_state_clear = dm_atomic_state_clear,
808         .atomic_state_free = dm_atomic_state_alloc_free
809 };
810
811 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
812         .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
813 };
814
815 static void
816 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
817 {
818         struct drm_connector *connector = &aconnector->base;
819         struct drm_device *dev = connector->dev;
820         struct dc_sink *sink;
821
822         /* MST handled by drm_mst framework */
823         if (aconnector->mst_mgr.mst_state == true)
824                 return;
825
826
827         sink = aconnector->dc_link->local_sink;
828
829         /* Edid mgmt connector gets first update only in mode_valid hook and then
830          * the connector sink is set to either fake or physical sink depends on link status.
831          * don't do it here if u are during boot
832          */
833         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
834                         && aconnector->dc_em_sink) {
835
836                 /* For S3 resume with headless use eml_sink to fake stream
837                  * because on resume connecotr->sink is set ti NULL
838                  */
839                 mutex_lock(&dev->mode_config.mutex);
840
841                 if (sink) {
842                         if (aconnector->dc_sink) {
843                                 amdgpu_dm_remove_sink_from_freesync_module(
844                                                                 connector);
845                                 /* retain and release bellow are used for
846                                  * bump up refcount for sink because the link don't point
847                                  * to it anymore after disconnect so on next crtc to connector
848                                  * reshuffle by UMD we will get into unwanted dc_sink release
849                                  */
850                                 if (aconnector->dc_sink != aconnector->dc_em_sink)
851                                         dc_sink_release(aconnector->dc_sink);
852                         }
853                         aconnector->dc_sink = sink;
854                         amdgpu_dm_add_sink_to_freesync_module(
855                                                 connector, aconnector->edid);
856                 } else {
857                         amdgpu_dm_remove_sink_from_freesync_module(connector);
858                         if (!aconnector->dc_sink)
859                                 aconnector->dc_sink = aconnector->dc_em_sink;
860                         else if (aconnector->dc_sink != aconnector->dc_em_sink)
861                                 dc_sink_retain(aconnector->dc_sink);
862                 }
863
864                 mutex_unlock(&dev->mode_config.mutex);
865                 return;
866         }
867
868         /*
869          * TODO: temporary guard to look for proper fix
870          * if this sink is MST sink, we should not do anything
871          */
872         if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
873                 return;
874
875         if (aconnector->dc_sink == sink) {
876                 /* We got a DP short pulse (Link Loss, DP CTS, etc...).
877                  * Do nothing!! */
878                 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
879                                 aconnector->connector_id);
880                 return;
881         }
882
883         DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
884                 aconnector->connector_id, aconnector->dc_sink, sink);
885
886         mutex_lock(&dev->mode_config.mutex);
887
888         /* 1. Update status of the drm connector
889          * 2. Send an event and let userspace tell us what to do */
890         if (sink) {
891                 /* TODO: check if we still need the S3 mode update workaround.
892                  * If yes, put it here. */
893                 if (aconnector->dc_sink)
894                         amdgpu_dm_remove_sink_from_freesync_module(
895                                                         connector);
896
897                 aconnector->dc_sink = sink;
898                 if (sink->dc_edid.length == 0) {
899                         aconnector->edid = NULL;
900                 } else {
901                         aconnector->edid =
902                                 (struct edid *) sink->dc_edid.raw_edid;
903
904
905                         drm_mode_connector_update_edid_property(connector,
906                                         aconnector->edid);
907                 }
908                 amdgpu_dm_add_sink_to_freesync_module(connector, aconnector->edid);
909
910         } else {
911                 amdgpu_dm_remove_sink_from_freesync_module(connector);
912                 drm_mode_connector_update_edid_property(connector, NULL);
913                 aconnector->num_modes = 0;
914                 aconnector->dc_sink = NULL;
915                 aconnector->edid = NULL;
916         }
917
918         mutex_unlock(&dev->mode_config.mutex);
919 }
920
921 static void handle_hpd_irq(void *param)
922 {
923         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
924         struct drm_connector *connector = &aconnector->base;
925         struct drm_device *dev = connector->dev;
926
927         /* In case of failure or MST no need to update connector status or notify the OS
928          * since (for MST case) MST does this in it's own context.
929          */
930         mutex_lock(&aconnector->hpd_lock);
931
932         if (aconnector->fake_enable)
933                 aconnector->fake_enable = false;
934
935         if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
936                 amdgpu_dm_update_connector_after_detect(aconnector);
937
938
939                 drm_modeset_lock_all(dev);
940                 dm_restore_drm_connector_state(dev, connector);
941                 drm_modeset_unlock_all(dev);
942
943                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
944                         drm_kms_helper_hotplug_event(dev);
945         }
946         mutex_unlock(&aconnector->hpd_lock);
947
948 }
949
950 static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
951 {
952         uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
953         uint8_t dret;
954         bool new_irq_handled = false;
955         int dpcd_addr;
956         int dpcd_bytes_to_read;
957
958         const int max_process_count = 30;
959         int process_count = 0;
960
961         const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
962
963         if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
964                 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
965                 /* DPCD 0x200 - 0x201 for downstream IRQ */
966                 dpcd_addr = DP_SINK_COUNT;
967         } else {
968                 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
969                 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
970                 dpcd_addr = DP_SINK_COUNT_ESI;
971         }
972
973         dret = drm_dp_dpcd_read(
974                 &aconnector->dm_dp_aux.aux,
975                 dpcd_addr,
976                 esi,
977                 dpcd_bytes_to_read);
978
979         while (dret == dpcd_bytes_to_read &&
980                 process_count < max_process_count) {
981                 uint8_t retry;
982                 dret = 0;
983
984                 process_count++;
985
986                 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
987                 /* handle HPD short pulse irq */
988                 if (aconnector->mst_mgr.mst_state)
989                         drm_dp_mst_hpd_irq(
990                                 &aconnector->mst_mgr,
991                                 esi,
992                                 &new_irq_handled);
993
994                 if (new_irq_handled) {
995                         /* ACK at DPCD to notify down stream */
996                         const int ack_dpcd_bytes_to_write =
997                                 dpcd_bytes_to_read - 1;
998
999                         for (retry = 0; retry < 3; retry++) {
1000                                 uint8_t wret;
1001
1002                                 wret = drm_dp_dpcd_write(
1003                                         &aconnector->dm_dp_aux.aux,
1004                                         dpcd_addr + 1,
1005                                         &esi[1],
1006                                         ack_dpcd_bytes_to_write);
1007                                 if (wret == ack_dpcd_bytes_to_write)
1008                                         break;
1009                         }
1010
1011                         /* check if there is new irq to be handle */
1012                         dret = drm_dp_dpcd_read(
1013                                 &aconnector->dm_dp_aux.aux,
1014                                 dpcd_addr,
1015                                 esi,
1016                                 dpcd_bytes_to_read);
1017
1018                         new_irq_handled = false;
1019                 } else {
1020                         break;
1021                 }
1022         }
1023
1024         if (process_count == max_process_count)
1025                 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
1026 }
1027
1028 static void handle_hpd_rx_irq(void *param)
1029 {
1030         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
1031         struct drm_connector *connector = &aconnector->base;
1032         struct drm_device *dev = connector->dev;
1033         struct dc_link *dc_link = aconnector->dc_link;
1034         bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
1035
1036         /* TODO:Temporary add mutex to protect hpd interrupt not have a gpio
1037          * conflict, after implement i2c helper, this mutex should be
1038          * retired.
1039          */
1040         if (dc_link->type != dc_connection_mst_branch)
1041                 mutex_lock(&aconnector->hpd_lock);
1042
1043         if (dc_link_handle_hpd_rx_irq(dc_link, NULL) &&
1044                         !is_mst_root_connector) {
1045                 /* Downstream Port status changed. */
1046                 if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
1047
1048                         if (aconnector->fake_enable)
1049                                 aconnector->fake_enable = false;
1050
1051                         amdgpu_dm_update_connector_after_detect(aconnector);
1052
1053
1054                         drm_modeset_lock_all(dev);
1055                         dm_restore_drm_connector_state(dev, connector);
1056                         drm_modeset_unlock_all(dev);
1057
1058                         drm_kms_helper_hotplug_event(dev);
1059                 }
1060         }
1061         if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
1062             (dc_link->type == dc_connection_mst_branch))
1063                 dm_handle_hpd_rx_irq(aconnector);
1064
1065         if (dc_link->type != dc_connection_mst_branch)
1066                 mutex_unlock(&aconnector->hpd_lock);
1067 }
1068
1069 static void register_hpd_handlers(struct amdgpu_device *adev)
1070 {
1071         struct drm_device *dev = adev->ddev;
1072         struct drm_connector *connector;
1073         struct amdgpu_dm_connector *aconnector;
1074         const struct dc_link *dc_link;
1075         struct dc_interrupt_params int_params = {0};
1076
1077         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1078         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1079
1080         list_for_each_entry(connector,
1081                         &dev->mode_config.connector_list, head) {
1082
1083                 aconnector = to_amdgpu_dm_connector(connector);
1084                 dc_link = aconnector->dc_link;
1085
1086                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1087                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1088                         int_params.irq_source = dc_link->irq_source_hpd;
1089
1090                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
1091                                         handle_hpd_irq,
1092                                         (void *) aconnector);
1093                 }
1094
1095                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1096
1097                         /* Also register for DP short pulse (hpd_rx). */
1098                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1099                         int_params.irq_source = dc_link->irq_source_hpd_rx;
1100
1101                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
1102                                         handle_hpd_rx_irq,
1103                                         (void *) aconnector);
1104                 }
1105         }
1106 }
1107
1108 /* Register IRQ sources and initialize IRQ callbacks */
1109 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1110 {
1111         struct dc *dc = adev->dm.dc;
1112         struct common_irq_params *c_irq_params;
1113         struct dc_interrupt_params int_params = {0};
1114         int r;
1115         int i;
1116         unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY;
1117
1118         if (adev->asic_type == CHIP_VEGA10 ||
1119             adev->asic_type == CHIP_VEGA12 ||
1120             adev->asic_type == CHIP_VEGA20 ||
1121             adev->asic_type == CHIP_RAVEN)
1122                 client_id = SOC15_IH_CLIENTID_DCE;
1123
1124         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1125         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1126
1127         /* Actions of amdgpu_irq_add_id():
1128          * 1. Register a set() function with base driver.
1129          *    Base driver will call set() function to enable/disable an
1130          *    interrupt in DC hardware.
1131          * 2. Register amdgpu_dm_irq_handler().
1132          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1133          *    coming from DC hardware.
1134          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1135          *    for acknowledging and handling. */
1136
1137         /* Use VBLANK interrupt */
1138         for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
1139                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
1140                 if (r) {
1141                         DRM_ERROR("Failed to add crtc irq id!\n");
1142                         return r;
1143                 }
1144
1145                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1146                 int_params.irq_source =
1147                         dc_interrupt_to_irq_source(dc, i, 0);
1148
1149                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1150
1151                 c_irq_params->adev = adev;
1152                 c_irq_params->irq_src = int_params.irq_source;
1153
1154                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1155                                 dm_crtc_high_irq, c_irq_params);
1156         }
1157
1158         /* Use GRPH_PFLIP interrupt */
1159         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1160                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
1161                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
1162                 if (r) {
1163                         DRM_ERROR("Failed to add page flip irq id!\n");
1164                         return r;
1165                 }
1166
1167                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1168                 int_params.irq_source =
1169                         dc_interrupt_to_irq_source(dc, i, 0);
1170
1171                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1172
1173                 c_irq_params->adev = adev;
1174                 c_irq_params->irq_src = int_params.irq_source;
1175
1176                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1177                                 dm_pflip_high_irq, c_irq_params);
1178
1179         }
1180
1181         /* HPD */
1182         r = amdgpu_irq_add_id(adev, client_id,
1183                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
1184         if (r) {
1185                 DRM_ERROR("Failed to add hpd irq id!\n");
1186                 return r;
1187         }
1188
1189         register_hpd_handlers(adev);
1190
1191         return 0;
1192 }
1193
1194 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1195 /* Register IRQ sources and initialize IRQ callbacks */
1196 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1197 {
1198         struct dc *dc = adev->dm.dc;
1199         struct common_irq_params *c_irq_params;
1200         struct dc_interrupt_params int_params = {0};
1201         int r;
1202         int i;
1203
1204         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1205         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1206
1207         /* Actions of amdgpu_irq_add_id():
1208          * 1. Register a set() function with base driver.
1209          *    Base driver will call set() function to enable/disable an
1210          *    interrupt in DC hardware.
1211          * 2. Register amdgpu_dm_irq_handler().
1212          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1213          *    coming from DC hardware.
1214          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1215          *    for acknowledging and handling.
1216          * */
1217
1218         /* Use VSTARTUP interrupt */
1219         for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1220                         i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1221                         i++) {
1222                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
1223
1224                 if (r) {
1225                         DRM_ERROR("Failed to add crtc irq id!\n");
1226                         return r;
1227                 }
1228
1229                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1230                 int_params.irq_source =
1231                         dc_interrupt_to_irq_source(dc, i, 0);
1232
1233                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1234
1235                 c_irq_params->adev = adev;
1236                 c_irq_params->irq_src = int_params.irq_source;
1237
1238                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1239                                 dm_crtc_high_irq, c_irq_params);
1240         }
1241
1242         /* Use GRPH_PFLIP interrupt */
1243         for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1244                         i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1245                         i++) {
1246                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
1247                 if (r) {
1248                         DRM_ERROR("Failed to add page flip irq id!\n");
1249                         return r;
1250                 }
1251
1252                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1253                 int_params.irq_source =
1254                         dc_interrupt_to_irq_source(dc, i, 0);
1255
1256                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1257
1258                 c_irq_params->adev = adev;
1259                 c_irq_params->irq_src = int_params.irq_source;
1260
1261                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1262                                 dm_pflip_high_irq, c_irq_params);
1263
1264         }
1265
1266         /* HPD */
1267         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
1268                         &adev->hpd_irq);
1269         if (r) {
1270                 DRM_ERROR("Failed to add hpd irq id!\n");
1271                 return r;
1272         }
1273
1274         register_hpd_handlers(adev);
1275
1276         return 0;
1277 }
1278 #endif
1279
1280 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
1281 {
1282         int r;
1283
1284         adev->mode_info.mode_config_initialized = true;
1285
1286         adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
1287         adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
1288
1289         adev->ddev->mode_config.max_width = 16384;
1290         adev->ddev->mode_config.max_height = 16384;
1291
1292         adev->ddev->mode_config.preferred_depth = 24;
1293         adev->ddev->mode_config.prefer_shadow = 1;
1294         /* indicate support of immediate flip */
1295         adev->ddev->mode_config.async_page_flip = true;
1296
1297         adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
1298
1299         r = amdgpu_display_modeset_create_props(adev);
1300         if (r)
1301                 return r;
1302
1303         return 0;
1304 }
1305
1306 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1307         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1308
1309 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
1310 {
1311         struct amdgpu_display_manager *dm = bl_get_data(bd);
1312
1313         if (dc_link_set_backlight_level(dm->backlight_link,
1314                         bd->props.brightness, 0, 0))
1315                 return 0;
1316         else
1317                 return 1;
1318 }
1319
1320 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
1321 {
1322         return bd->props.brightness;
1323 }
1324
1325 static const struct backlight_ops amdgpu_dm_backlight_ops = {
1326         .get_brightness = amdgpu_dm_backlight_get_brightness,
1327         .update_status  = amdgpu_dm_backlight_update_status,
1328 };
1329
1330 static void
1331 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
1332 {
1333         char bl_name[16];
1334         struct backlight_properties props = { 0 };
1335
1336         props.max_brightness = AMDGPU_MAX_BL_LEVEL;
1337         props.type = BACKLIGHT_RAW;
1338
1339         snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
1340                         dm->adev->ddev->primary->index);
1341
1342         dm->backlight_dev = backlight_device_register(bl_name,
1343                         dm->adev->ddev->dev,
1344                         dm,
1345                         &amdgpu_dm_backlight_ops,
1346                         &props);
1347
1348         if (IS_ERR(dm->backlight_dev))
1349                 DRM_ERROR("DM: Backlight registration failed!\n");
1350         else
1351                 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
1352 }
1353
1354 #endif
1355
1356 static int initialize_plane(struct amdgpu_display_manager *dm,
1357                              struct amdgpu_mode_info *mode_info,
1358                              int plane_id)
1359 {
1360         struct amdgpu_plane *plane;
1361         unsigned long possible_crtcs;
1362         int ret = 0;
1363
1364         plane = kzalloc(sizeof(struct amdgpu_plane), GFP_KERNEL);
1365         mode_info->planes[plane_id] = plane;
1366
1367         if (!plane) {
1368                 DRM_ERROR("KMS: Failed to allocate plane\n");
1369                 return -ENOMEM;
1370         }
1371         plane->base.type = mode_info->plane_type[plane_id];
1372
1373         /*
1374          * HACK: IGT tests expect that each plane can only have one
1375          * one possible CRTC. For now, set one CRTC for each
1376          * plane that is not an underlay, but still allow multiple
1377          * CRTCs for underlay planes.
1378          */
1379         possible_crtcs = 1 << plane_id;
1380         if (plane_id >= dm->dc->caps.max_streams)
1381                 possible_crtcs = 0xff;
1382
1383         ret = amdgpu_dm_plane_init(dm, mode_info->planes[plane_id], possible_crtcs);
1384
1385         if (ret) {
1386                 DRM_ERROR("KMS: Failed to initialize plane\n");
1387                 return ret;
1388         }
1389
1390         return ret;
1391 }
1392
1393
1394 static void register_backlight_device(struct amdgpu_display_manager *dm,
1395                                       struct dc_link *link)
1396 {
1397 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1398         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1399
1400         if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
1401             link->type != dc_connection_none) {
1402                 /* Event if registration failed, we should continue with
1403                  * DM initialization because not having a backlight control
1404                  * is better then a black screen.
1405                  */
1406                 amdgpu_dm_register_backlight_device(dm);
1407
1408                 if (dm->backlight_dev)
1409                         dm->backlight_link = link;
1410         }
1411 #endif
1412 }
1413
1414
1415 /* In this architecture, the association
1416  * connector -> encoder -> crtc
1417  * id not really requried. The crtc and connector will hold the
1418  * display_index as an abstraction to use with DAL component
1419  *
1420  * Returns 0 on success
1421  */
1422 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
1423 {
1424         struct amdgpu_display_manager *dm = &adev->dm;
1425         int32_t i;
1426         struct amdgpu_dm_connector *aconnector = NULL;
1427         struct amdgpu_encoder *aencoder = NULL;
1428         struct amdgpu_mode_info *mode_info = &adev->mode_info;
1429         uint32_t link_cnt;
1430         int32_t total_overlay_planes, total_primary_planes;
1431
1432         link_cnt = dm->dc->caps.max_links;
1433         if (amdgpu_dm_mode_config_init(dm->adev)) {
1434                 DRM_ERROR("DM: Failed to initialize mode config\n");
1435                 return -1;
1436         }
1437
1438         /* Identify the number of planes to be initialized */
1439         total_overlay_planes = dm->dc->caps.max_slave_planes;
1440         total_primary_planes = dm->dc->caps.max_planes - dm->dc->caps.max_slave_planes;
1441
1442         /* First initialize overlay planes, index starting after primary planes */
1443         for (i = (total_overlay_planes - 1); i >= 0; i--) {
1444                 if (initialize_plane(dm, mode_info, (total_primary_planes + i))) {
1445                         DRM_ERROR("KMS: Failed to initialize overlay plane\n");
1446                         goto fail;
1447                 }
1448         }
1449
1450         /* Initialize primary planes */
1451         for (i = (total_primary_planes - 1); i >= 0; i--) {
1452                 if (initialize_plane(dm, mode_info, i)) {
1453                         DRM_ERROR("KMS: Failed to initialize primary plane\n");
1454                         goto fail;
1455                 }
1456         }
1457
1458         for (i = 0; i < dm->dc->caps.max_streams; i++)
1459                 if (amdgpu_dm_crtc_init(dm, &mode_info->planes[i]->base, i)) {
1460                         DRM_ERROR("KMS: Failed to initialize crtc\n");
1461                         goto fail;
1462                 }
1463
1464         dm->display_indexes_num = dm->dc->caps.max_streams;
1465
1466         /* loops over all connectors on the board */
1467         for (i = 0; i < link_cnt; i++) {
1468                 struct dc_link *link = NULL;
1469
1470                 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
1471                         DRM_ERROR(
1472                                 "KMS: Cannot support more than %d display indexes\n",
1473                                         AMDGPU_DM_MAX_DISPLAY_INDEX);
1474                         continue;
1475                 }
1476
1477                 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
1478                 if (!aconnector)
1479                         goto fail;
1480
1481                 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
1482                 if (!aencoder)
1483                         goto fail;
1484
1485                 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
1486                         DRM_ERROR("KMS: Failed to initialize encoder\n");
1487                         goto fail;
1488                 }
1489
1490                 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
1491                         DRM_ERROR("KMS: Failed to initialize connector\n");
1492                         goto fail;
1493                 }
1494
1495                 link = dc_get_link_at_index(dm->dc, i);
1496
1497                 if (dc_link_detect(link, DETECT_REASON_BOOT)) {
1498                         amdgpu_dm_update_connector_after_detect(aconnector);
1499                         register_backlight_device(dm, link);
1500                 }
1501
1502
1503         }
1504
1505         /* Software is initialized. Now we can register interrupt handlers. */
1506         switch (adev->asic_type) {
1507         case CHIP_BONAIRE:
1508         case CHIP_HAWAII:
1509         case CHIP_KAVERI:
1510         case CHIP_KABINI:
1511         case CHIP_MULLINS:
1512         case CHIP_TONGA:
1513         case CHIP_FIJI:
1514         case CHIP_CARRIZO:
1515         case CHIP_STONEY:
1516         case CHIP_POLARIS11:
1517         case CHIP_POLARIS10:
1518         case CHIP_POLARIS12:
1519         case CHIP_VEGAM:
1520         case CHIP_VEGA10:
1521         case CHIP_VEGA12:
1522         case CHIP_VEGA20:
1523                 if (dce110_register_irq_handlers(dm->adev)) {
1524                         DRM_ERROR("DM: Failed to initialize IRQ\n");
1525                         goto fail;
1526                 }
1527                 break;
1528 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1529         case CHIP_RAVEN:
1530                 if (dcn10_register_irq_handlers(dm->adev)) {
1531                         DRM_ERROR("DM: Failed to initialize IRQ\n");
1532                         goto fail;
1533                 }
1534                 /*
1535                  * Temporary disable until pplib/smu interaction is implemented
1536                  */
1537                 dm->dc->debug.disable_stutter = true;
1538                 break;
1539 #endif
1540         default:
1541                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
1542                 goto fail;
1543         }
1544
1545         return 0;
1546 fail:
1547         kfree(aencoder);
1548         kfree(aconnector);
1549         for (i = 0; i < dm->dc->caps.max_planes; i++)
1550                 kfree(mode_info->planes[i]);
1551         return -1;
1552 }
1553
1554 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
1555 {
1556         drm_mode_config_cleanup(dm->ddev);
1557         return;
1558 }
1559
1560 /******************************************************************************
1561  * amdgpu_display_funcs functions
1562  *****************************************************************************/
1563
1564 /**
1565  * dm_bandwidth_update - program display watermarks
1566  *
1567  * @adev: amdgpu_device pointer
1568  *
1569  * Calculate and program the display watermarks and line buffer allocation.
1570  */
1571 static void dm_bandwidth_update(struct amdgpu_device *adev)
1572 {
1573         /* TODO: implement later */
1574 }
1575
1576 static void dm_set_backlight_level(struct amdgpu_encoder *amdgpu_encoder,
1577                                      u8 level)
1578 {
1579         /* TODO: translate amdgpu_encoder to display_index and call DAL */
1580 }
1581
1582 static u8 dm_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder)
1583 {
1584         /* TODO: translate amdgpu_encoder to display_index and call DAL */
1585         return 0;
1586 }
1587
1588 static int amdgpu_notify_freesync(struct drm_device *dev, void *data,
1589                                 struct drm_file *filp)
1590 {
1591         struct mod_freesync_params freesync_params;
1592         uint8_t num_streams;
1593         uint8_t i;
1594
1595         struct amdgpu_device *adev = dev->dev_private;
1596         int r = 0;
1597
1598         /* Get freesync enable flag from DRM */
1599
1600         num_streams = dc_get_current_stream_count(adev->dm.dc);
1601
1602         for (i = 0; i < num_streams; i++) {
1603                 struct dc_stream_state *stream;
1604                 stream = dc_get_stream_at_index(adev->dm.dc, i);
1605
1606                 mod_freesync_update_state(adev->dm.freesync_module,
1607                                           &stream, 1, &freesync_params);
1608         }
1609
1610         return r;
1611 }
1612
1613 static const struct amdgpu_display_funcs dm_display_funcs = {
1614         .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
1615         .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
1616         .backlight_set_level =
1617                 dm_set_backlight_level,/* called unconditionally */
1618         .backlight_get_level =
1619                 dm_get_backlight_level,/* called unconditionally */
1620         .hpd_sense = NULL,/* called unconditionally */
1621         .hpd_set_polarity = NULL, /* called unconditionally */
1622         .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
1623         .page_flip_get_scanoutpos =
1624                 dm_crtc_get_scanoutpos,/* called unconditionally */
1625         .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
1626         .add_connector = NULL, /* VBIOS parsing. DAL does it. */
1627         .notify_freesync = amdgpu_notify_freesync,
1628
1629 };
1630
1631 #if defined(CONFIG_DEBUG_KERNEL_DC)
1632
1633 static ssize_t s3_debug_store(struct device *device,
1634                               struct device_attribute *attr,
1635                               const char *buf,
1636                               size_t count)
1637 {
1638         int ret;
1639         int s3_state;
1640         struct pci_dev *pdev = to_pci_dev(device);
1641         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1642         struct amdgpu_device *adev = drm_dev->dev_private;
1643
1644         ret = kstrtoint(buf, 0, &s3_state);
1645
1646         if (ret == 0) {
1647                 if (s3_state) {
1648                         dm_resume(adev);
1649                         drm_kms_helper_hotplug_event(adev->ddev);
1650                 } else
1651                         dm_suspend(adev);
1652         }
1653
1654         return ret == 0 ? count : 0;
1655 }
1656
1657 DEVICE_ATTR_WO(s3_debug);
1658
1659 #endif
1660
1661 static int dm_early_init(void *handle)
1662 {
1663         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1664
1665         switch (adev->asic_type) {
1666         case CHIP_BONAIRE:
1667         case CHIP_HAWAII:
1668                 adev->mode_info.num_crtc = 6;
1669                 adev->mode_info.num_hpd = 6;
1670                 adev->mode_info.num_dig = 6;
1671                 adev->mode_info.plane_type = dm_plane_type_default;
1672                 break;
1673         case CHIP_KAVERI:
1674                 adev->mode_info.num_crtc = 4;
1675                 adev->mode_info.num_hpd = 6;
1676                 adev->mode_info.num_dig = 7;
1677                 adev->mode_info.plane_type = dm_plane_type_default;
1678                 break;
1679         case CHIP_KABINI:
1680         case CHIP_MULLINS:
1681                 adev->mode_info.num_crtc = 2;
1682                 adev->mode_info.num_hpd = 6;
1683                 adev->mode_info.num_dig = 6;
1684                 adev->mode_info.plane_type = dm_plane_type_default;
1685                 break;
1686         case CHIP_FIJI:
1687         case CHIP_TONGA:
1688                 adev->mode_info.num_crtc = 6;
1689                 adev->mode_info.num_hpd = 6;
1690                 adev->mode_info.num_dig = 7;
1691                 adev->mode_info.plane_type = dm_plane_type_default;
1692                 break;
1693         case CHIP_CARRIZO:
1694                 adev->mode_info.num_crtc = 3;
1695                 adev->mode_info.num_hpd = 6;
1696                 adev->mode_info.num_dig = 9;
1697                 adev->mode_info.plane_type = dm_plane_type_carizzo;
1698                 break;
1699         case CHIP_STONEY:
1700                 adev->mode_info.num_crtc = 2;
1701                 adev->mode_info.num_hpd = 6;
1702                 adev->mode_info.num_dig = 9;
1703                 adev->mode_info.plane_type = dm_plane_type_stoney;
1704                 break;
1705         case CHIP_POLARIS11:
1706         case CHIP_POLARIS12:
1707                 adev->mode_info.num_crtc = 5;
1708                 adev->mode_info.num_hpd = 5;
1709                 adev->mode_info.num_dig = 5;
1710                 adev->mode_info.plane_type = dm_plane_type_default;
1711                 break;
1712         case CHIP_POLARIS10:
1713         case CHIP_VEGAM:
1714                 adev->mode_info.num_crtc = 6;
1715                 adev->mode_info.num_hpd = 6;
1716                 adev->mode_info.num_dig = 6;
1717                 adev->mode_info.plane_type = dm_plane_type_default;
1718                 break;
1719         case CHIP_VEGA10:
1720         case CHIP_VEGA12:
1721         case CHIP_VEGA20:
1722                 adev->mode_info.num_crtc = 6;
1723                 adev->mode_info.num_hpd = 6;
1724                 adev->mode_info.num_dig = 6;
1725                 adev->mode_info.plane_type = dm_plane_type_default;
1726                 break;
1727 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1728         case CHIP_RAVEN:
1729                 adev->mode_info.num_crtc = 4;
1730                 adev->mode_info.num_hpd = 4;
1731                 adev->mode_info.num_dig = 4;
1732                 adev->mode_info.plane_type = dm_plane_type_default;
1733                 break;
1734 #endif
1735         default:
1736                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
1737                 return -EINVAL;
1738         }
1739
1740         amdgpu_dm_set_irq_funcs(adev);
1741
1742         if (adev->mode_info.funcs == NULL)
1743                 adev->mode_info.funcs = &dm_display_funcs;
1744
1745         /* Note: Do NOT change adev->audio_endpt_rreg and
1746          * adev->audio_endpt_wreg because they are initialised in
1747          * amdgpu_device_init() */
1748 #if defined(CONFIG_DEBUG_KERNEL_DC)
1749         device_create_file(
1750                 adev->ddev->dev,
1751                 &dev_attr_s3_debug);
1752 #endif
1753
1754         return 0;
1755 }
1756
1757 static bool modeset_required(struct drm_crtc_state *crtc_state,
1758                              struct dc_stream_state *new_stream,
1759                              struct dc_stream_state *old_stream)
1760 {
1761         if (!drm_atomic_crtc_needs_modeset(crtc_state))
1762                 return false;
1763
1764         if (!crtc_state->enable)
1765                 return false;
1766
1767         return crtc_state->active;
1768 }
1769
1770 static bool modereset_required(struct drm_crtc_state *crtc_state)
1771 {
1772         if (!drm_atomic_crtc_needs_modeset(crtc_state))
1773                 return false;
1774
1775         return !crtc_state->enable || !crtc_state->active;
1776 }
1777
1778 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
1779 {
1780         drm_encoder_cleanup(encoder);
1781         kfree(encoder);
1782 }
1783
1784 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
1785         .destroy = amdgpu_dm_encoder_destroy,
1786 };
1787
1788 static bool fill_rects_from_plane_state(const struct drm_plane_state *state,
1789                                         struct dc_plane_state *plane_state)
1790 {
1791         plane_state->src_rect.x = state->src_x >> 16;
1792         plane_state->src_rect.y = state->src_y >> 16;
1793         /*we ignore for now mantissa and do not to deal with floating pixels :(*/
1794         plane_state->src_rect.width = state->src_w >> 16;
1795
1796         if (plane_state->src_rect.width == 0)
1797                 return false;
1798
1799         plane_state->src_rect.height = state->src_h >> 16;
1800         if (plane_state->src_rect.height == 0)
1801                 return false;
1802
1803         plane_state->dst_rect.x = state->crtc_x;
1804         plane_state->dst_rect.y = state->crtc_y;
1805
1806         if (state->crtc_w == 0)
1807                 return false;
1808
1809         plane_state->dst_rect.width = state->crtc_w;
1810
1811         if (state->crtc_h == 0)
1812                 return false;
1813
1814         plane_state->dst_rect.height = state->crtc_h;
1815
1816         plane_state->clip_rect = plane_state->dst_rect;
1817
1818         switch (state->rotation & DRM_MODE_ROTATE_MASK) {
1819         case DRM_MODE_ROTATE_0:
1820                 plane_state->rotation = ROTATION_ANGLE_0;
1821                 break;
1822         case DRM_MODE_ROTATE_90:
1823                 plane_state->rotation = ROTATION_ANGLE_90;
1824                 break;
1825         case DRM_MODE_ROTATE_180:
1826                 plane_state->rotation = ROTATION_ANGLE_180;
1827                 break;
1828         case DRM_MODE_ROTATE_270:
1829                 plane_state->rotation = ROTATION_ANGLE_270;
1830                 break;
1831         default:
1832                 plane_state->rotation = ROTATION_ANGLE_0;
1833                 break;
1834         }
1835
1836         return true;
1837 }
1838 static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
1839                        uint64_t *tiling_flags)
1840 {
1841         struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
1842         int r = amdgpu_bo_reserve(rbo, false);
1843
1844         if (unlikely(r)) {
1845                 // Don't show error msg. when return -ERESTARTSYS
1846                 if (r != -ERESTARTSYS)
1847                         DRM_ERROR("Unable to reserve buffer: %d\n", r);
1848                 return r;
1849         }
1850
1851         if (tiling_flags)
1852                 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
1853
1854         amdgpu_bo_unreserve(rbo);
1855
1856         return r;
1857 }
1858
1859 static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
1860                                          struct dc_plane_state *plane_state,
1861                                          const struct amdgpu_framebuffer *amdgpu_fb)
1862 {
1863         uint64_t tiling_flags;
1864         unsigned int awidth;
1865         const struct drm_framebuffer *fb = &amdgpu_fb->base;
1866         int ret = 0;
1867         struct drm_format_name_buf format_name;
1868
1869         ret = get_fb_info(
1870                 amdgpu_fb,
1871                 &tiling_flags);
1872
1873         if (ret)
1874                 return ret;
1875
1876         switch (fb->format->format) {
1877         case DRM_FORMAT_C8:
1878                 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
1879                 break;
1880         case DRM_FORMAT_RGB565:
1881                 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
1882                 break;
1883         case DRM_FORMAT_XRGB8888:
1884         case DRM_FORMAT_ARGB8888:
1885                 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
1886                 break;
1887         case DRM_FORMAT_XRGB2101010:
1888         case DRM_FORMAT_ARGB2101010:
1889                 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
1890                 break;
1891         case DRM_FORMAT_XBGR2101010:
1892         case DRM_FORMAT_ABGR2101010:
1893                 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
1894                 break;
1895         case DRM_FORMAT_NV21:
1896                 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
1897                 break;
1898         case DRM_FORMAT_NV12:
1899                 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
1900                 break;
1901         default:
1902                 DRM_ERROR("Unsupported screen format %s\n",
1903                           drm_get_format_name(fb->format->format, &format_name));
1904                 return -EINVAL;
1905         }
1906
1907         if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1908                 plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS;
1909                 plane_state->plane_size.grph.surface_size.x = 0;
1910                 plane_state->plane_size.grph.surface_size.y = 0;
1911                 plane_state->plane_size.grph.surface_size.width = fb->width;
1912                 plane_state->plane_size.grph.surface_size.height = fb->height;
1913                 plane_state->plane_size.grph.surface_pitch =
1914                                 fb->pitches[0] / fb->format->cpp[0];
1915                 /* TODO: unhardcode */
1916                 plane_state->color_space = COLOR_SPACE_SRGB;
1917
1918         } else {
1919                 awidth = ALIGN(fb->width, 64);
1920                 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
1921                 plane_state->plane_size.video.luma_size.x = 0;
1922                 plane_state->plane_size.video.luma_size.y = 0;
1923                 plane_state->plane_size.video.luma_size.width = awidth;
1924                 plane_state->plane_size.video.luma_size.height = fb->height;
1925                 /* TODO: unhardcode */
1926                 plane_state->plane_size.video.luma_pitch = awidth;
1927
1928                 plane_state->plane_size.video.chroma_size.x = 0;
1929                 plane_state->plane_size.video.chroma_size.y = 0;
1930                 plane_state->plane_size.video.chroma_size.width = awidth;
1931                 plane_state->plane_size.video.chroma_size.height = fb->height;
1932                 plane_state->plane_size.video.chroma_pitch = awidth / 2;
1933
1934                 /* TODO: unhardcode */
1935                 plane_state->color_space = COLOR_SPACE_YCBCR709;
1936         }
1937
1938         memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info));
1939
1940         /* Fill GFX8 params */
1941         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
1942                 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
1943
1944                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1945                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1946                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1947                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1948                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1949
1950                 /* XXX fix me for VI */
1951                 plane_state->tiling_info.gfx8.num_banks = num_banks;
1952                 plane_state->tiling_info.gfx8.array_mode =
1953                                 DC_ARRAY_2D_TILED_THIN1;
1954                 plane_state->tiling_info.gfx8.tile_split = tile_split;
1955                 plane_state->tiling_info.gfx8.bank_width = bankw;
1956                 plane_state->tiling_info.gfx8.bank_height = bankh;
1957                 plane_state->tiling_info.gfx8.tile_aspect = mtaspect;
1958                 plane_state->tiling_info.gfx8.tile_mode =
1959                                 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
1960         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
1961                         == DC_ARRAY_1D_TILED_THIN1) {
1962                 plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
1963         }
1964
1965         plane_state->tiling_info.gfx8.pipe_config =
1966                         AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1967
1968         if (adev->asic_type == CHIP_VEGA10 ||
1969             adev->asic_type == CHIP_VEGA12 ||
1970             adev->asic_type == CHIP_VEGA20 ||
1971             adev->asic_type == CHIP_RAVEN) {
1972                 /* Fill GFX9 params */
1973                 plane_state->tiling_info.gfx9.num_pipes =
1974                         adev->gfx.config.gb_addr_config_fields.num_pipes;
1975                 plane_state->tiling_info.gfx9.num_banks =
1976                         adev->gfx.config.gb_addr_config_fields.num_banks;
1977                 plane_state->tiling_info.gfx9.pipe_interleave =
1978                         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
1979                 plane_state->tiling_info.gfx9.num_shader_engines =
1980                         adev->gfx.config.gb_addr_config_fields.num_se;
1981                 plane_state->tiling_info.gfx9.max_compressed_frags =
1982                         adev->gfx.config.gb_addr_config_fields.max_compress_frags;
1983                 plane_state->tiling_info.gfx9.num_rb_per_se =
1984                         adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
1985                 plane_state->tiling_info.gfx9.swizzle =
1986                         AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
1987                 plane_state->tiling_info.gfx9.shaderEnable = 1;
1988         }
1989
1990         plane_state->visible = true;
1991         plane_state->scaling_quality.h_taps_c = 0;
1992         plane_state->scaling_quality.v_taps_c = 0;
1993
1994         /* is this needed? is plane_state zeroed at allocation? */
1995         plane_state->scaling_quality.h_taps = 0;
1996         plane_state->scaling_quality.v_taps = 0;
1997         plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE;
1998
1999         return ret;
2000
2001 }
2002
2003 static int fill_plane_attributes(struct amdgpu_device *adev,
2004                                  struct dc_plane_state *dc_plane_state,
2005                                  struct drm_plane_state *plane_state,
2006                                  struct drm_crtc_state *crtc_state)
2007 {
2008         const struct amdgpu_framebuffer *amdgpu_fb =
2009                 to_amdgpu_framebuffer(plane_state->fb);
2010         const struct drm_crtc *crtc = plane_state->crtc;
2011         int ret = 0;
2012
2013         if (!fill_rects_from_plane_state(plane_state, dc_plane_state))
2014                 return -EINVAL;
2015
2016         ret = fill_plane_attributes_from_fb(
2017                 crtc->dev->dev_private,
2018                 dc_plane_state,
2019                 amdgpu_fb);
2020
2021         if (ret)
2022                 return ret;
2023
2024         /*
2025          * Always set input transfer function, since plane state is refreshed
2026          * every time.
2027          */
2028         ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state);
2029         if (ret) {
2030                 dc_transfer_func_release(dc_plane_state->in_transfer_func);
2031                 dc_plane_state->in_transfer_func = NULL;
2032         }
2033
2034         return ret;
2035 }
2036
2037 /*****************************************************************************/
2038
2039 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
2040                                            const struct dm_connector_state *dm_state,
2041                                            struct dc_stream_state *stream)
2042 {
2043         enum amdgpu_rmx_type rmx_type;
2044
2045         struct rect src = { 0 }; /* viewport in composition space*/
2046         struct rect dst = { 0 }; /* stream addressable area */
2047
2048         /* no mode. nothing to be done */
2049         if (!mode)
2050                 return;
2051
2052         /* Full screen scaling by default */
2053         src.width = mode->hdisplay;
2054         src.height = mode->vdisplay;
2055         dst.width = stream->timing.h_addressable;
2056         dst.height = stream->timing.v_addressable;
2057
2058         if (dm_state) {
2059                 rmx_type = dm_state->scaling;
2060                 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
2061                         if (src.width * dst.height <
2062                                         src.height * dst.width) {
2063                                 /* height needs less upscaling/more downscaling */
2064                                 dst.width = src.width *
2065                                                 dst.height / src.height;
2066                         } else {
2067                                 /* width needs less upscaling/more downscaling */
2068                                 dst.height = src.height *
2069                                                 dst.width / src.width;
2070                         }
2071                 } else if (rmx_type == RMX_CENTER) {
2072                         dst = src;
2073                 }
2074
2075                 dst.x = (stream->timing.h_addressable - dst.width) / 2;
2076                 dst.y = (stream->timing.v_addressable - dst.height) / 2;
2077
2078                 if (dm_state->underscan_enable) {
2079                         dst.x += dm_state->underscan_hborder / 2;
2080                         dst.y += dm_state->underscan_vborder / 2;
2081                         dst.width -= dm_state->underscan_hborder;
2082                         dst.height -= dm_state->underscan_vborder;
2083                 }
2084         }
2085
2086         stream->src = src;
2087         stream->dst = dst;
2088
2089         DRM_DEBUG_DRIVER("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
2090                         dst.x, dst.y, dst.width, dst.height);
2091
2092 }
2093
2094 static enum dc_color_depth
2095 convert_color_depth_from_display_info(const struct drm_connector *connector)
2096 {
2097         uint32_t bpc = connector->display_info.bpc;
2098
2099         switch (bpc) {
2100         case 0:
2101                 /* Temporary Work around, DRM don't parse color depth for
2102                  * EDID revision before 1.4
2103                  * TODO: Fix edid parsing
2104                  */
2105                 return COLOR_DEPTH_888;
2106         case 6:
2107                 return COLOR_DEPTH_666;
2108         case 8:
2109                 return COLOR_DEPTH_888;
2110         case 10:
2111                 return COLOR_DEPTH_101010;
2112         case 12:
2113                 return COLOR_DEPTH_121212;
2114         case 14:
2115                 return COLOR_DEPTH_141414;
2116         case 16:
2117                 return COLOR_DEPTH_161616;
2118         default:
2119                 return COLOR_DEPTH_UNDEFINED;
2120         }
2121 }
2122
2123 static enum dc_aspect_ratio
2124 get_aspect_ratio(const struct drm_display_mode *mode_in)
2125 {
2126         int32_t width = mode_in->crtc_hdisplay * 9;
2127         int32_t height = mode_in->crtc_vdisplay * 16;
2128
2129         if ((width - height) < 10 && (width - height) > -10)
2130                 return ASPECT_RATIO_16_9;
2131         else
2132                 return ASPECT_RATIO_4_3;
2133 }
2134
2135 static enum dc_color_space
2136 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
2137 {
2138         enum dc_color_space color_space = COLOR_SPACE_SRGB;
2139
2140         switch (dc_crtc_timing->pixel_encoding) {
2141         case PIXEL_ENCODING_YCBCR422:
2142         case PIXEL_ENCODING_YCBCR444:
2143         case PIXEL_ENCODING_YCBCR420:
2144         {
2145                 /*
2146                  * 27030khz is the separation point between HDTV and SDTV
2147                  * according to HDMI spec, we use YCbCr709 and YCbCr601
2148                  * respectively
2149                  */
2150                 if (dc_crtc_timing->pix_clk_khz > 27030) {
2151                         if (dc_crtc_timing->flags.Y_ONLY)
2152                                 color_space =
2153                                         COLOR_SPACE_YCBCR709_LIMITED;
2154                         else
2155                                 color_space = COLOR_SPACE_YCBCR709;
2156                 } else {
2157                         if (dc_crtc_timing->flags.Y_ONLY)
2158                                 color_space =
2159                                         COLOR_SPACE_YCBCR601_LIMITED;
2160                         else
2161                                 color_space = COLOR_SPACE_YCBCR601;
2162                 }
2163
2164         }
2165         break;
2166         case PIXEL_ENCODING_RGB:
2167                 color_space = COLOR_SPACE_SRGB;
2168                 break;
2169
2170         default:
2171                 WARN_ON(1);
2172                 break;
2173         }
2174
2175         return color_space;
2176 }
2177
2178 /*****************************************************************************/
2179
2180 static void
2181 fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
2182                                              const struct drm_display_mode *mode_in,
2183                                              const struct drm_connector *connector)
2184 {
2185         struct dc_crtc_timing *timing_out = &stream->timing;
2186
2187         memset(timing_out, 0, sizeof(struct dc_crtc_timing));
2188
2189         timing_out->h_border_left = 0;
2190         timing_out->h_border_right = 0;
2191         timing_out->v_border_top = 0;
2192         timing_out->v_border_bottom = 0;
2193         /* TODO: un-hardcode */
2194
2195         if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
2196                         && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2197                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
2198         else
2199                 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
2200
2201         timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
2202         timing_out->display_color_depth = convert_color_depth_from_display_info(
2203                         connector);
2204         timing_out->scan_type = SCANNING_TYPE_NODATA;
2205         timing_out->hdmi_vic = 0;
2206         timing_out->vic = drm_match_cea_mode(mode_in);
2207
2208         timing_out->h_addressable = mode_in->crtc_hdisplay;
2209         timing_out->h_total = mode_in->crtc_htotal;
2210         timing_out->h_sync_width =
2211                 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
2212         timing_out->h_front_porch =
2213                 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
2214         timing_out->v_total = mode_in->crtc_vtotal;
2215         timing_out->v_addressable = mode_in->crtc_vdisplay;
2216         timing_out->v_front_porch =
2217                 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
2218         timing_out->v_sync_width =
2219                 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
2220         timing_out->pix_clk_khz = mode_in->crtc_clock;
2221         timing_out->aspect_ratio = get_aspect_ratio(mode_in);
2222         if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
2223                 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
2224         if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
2225                 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
2226
2227         stream->output_color_space = get_output_color_space(timing_out);
2228
2229         stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
2230         stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
2231 }
2232
2233 static void fill_audio_info(struct audio_info *audio_info,
2234                             const struct drm_connector *drm_connector,
2235                             const struct dc_sink *dc_sink)
2236 {
2237         int i = 0;
2238         int cea_revision = 0;
2239         const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
2240
2241         audio_info->manufacture_id = edid_caps->manufacturer_id;
2242         audio_info->product_id = edid_caps->product_id;
2243
2244         cea_revision = drm_connector->display_info.cea_rev;
2245
2246         strncpy(audio_info->display_name,
2247                 edid_caps->display_name,
2248                 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS - 1);
2249
2250         if (cea_revision >= 3) {
2251                 audio_info->mode_count = edid_caps->audio_mode_count;
2252
2253                 for (i = 0; i < audio_info->mode_count; ++i) {
2254                         audio_info->modes[i].format_code =
2255                                         (enum audio_format_code)
2256                                         (edid_caps->audio_modes[i].format_code);
2257                         audio_info->modes[i].channel_count =
2258                                         edid_caps->audio_modes[i].channel_count;
2259                         audio_info->modes[i].sample_rates.all =
2260                                         edid_caps->audio_modes[i].sample_rate;
2261                         audio_info->modes[i].sample_size =
2262                                         edid_caps->audio_modes[i].sample_size;
2263                 }
2264         }
2265
2266         audio_info->flags.all = edid_caps->speaker_flags;
2267
2268         /* TODO: We only check for the progressive mode, check for interlace mode too */
2269         if (drm_connector->latency_present[0]) {
2270                 audio_info->video_latency = drm_connector->video_latency[0];
2271                 audio_info->audio_latency = drm_connector->audio_latency[0];
2272         }
2273
2274         /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
2275
2276 }
2277
2278 static void
2279 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
2280                                       struct drm_display_mode *dst_mode)
2281 {
2282         dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
2283         dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
2284         dst_mode->crtc_clock = src_mode->crtc_clock;
2285         dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
2286         dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
2287         dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
2288         dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
2289         dst_mode->crtc_htotal = src_mode->crtc_htotal;
2290         dst_mode->crtc_hskew = src_mode->crtc_hskew;
2291         dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
2292         dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
2293         dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
2294         dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
2295         dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
2296 }
2297
2298 static void
2299 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
2300                                         const struct drm_display_mode *native_mode,
2301                                         bool scale_enabled)
2302 {
2303         if (scale_enabled) {
2304                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2305         } else if (native_mode->clock == drm_mode->clock &&
2306                         native_mode->htotal == drm_mode->htotal &&
2307                         native_mode->vtotal == drm_mode->vtotal) {
2308                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2309         } else {
2310                 /* no scaling nor amdgpu inserted, no need to patch */
2311         }
2312 }
2313
2314 static struct dc_sink *
2315 create_fake_sink(struct amdgpu_dm_connector *aconnector)
2316 {
2317         struct dc_sink_init_data sink_init_data = { 0 };
2318         struct dc_sink *sink = NULL;
2319         sink_init_data.link = aconnector->dc_link;
2320         sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
2321
2322         sink = dc_sink_create(&sink_init_data);
2323         if (!sink) {
2324                 DRM_ERROR("Failed to create sink!\n");
2325                 return NULL;
2326         }
2327         sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
2328
2329         return sink;
2330 }
2331
2332 static void set_multisync_trigger_params(
2333                 struct dc_stream_state *stream)
2334 {
2335         if (stream->triggered_crtc_reset.enabled) {
2336                 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
2337                 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
2338         }
2339 }
2340
2341 static void set_master_stream(struct dc_stream_state *stream_set[],
2342                               int stream_count)
2343 {
2344         int j, highest_rfr = 0, master_stream = 0;
2345
2346         for (j = 0;  j < stream_count; j++) {
2347                 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
2348                         int refresh_rate = 0;
2349
2350                         refresh_rate = (stream_set[j]->timing.pix_clk_khz*1000)/
2351                                 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
2352                         if (refresh_rate > highest_rfr) {
2353                                 highest_rfr = refresh_rate;
2354                                 master_stream = j;
2355                         }
2356                 }
2357         }
2358         for (j = 0;  j < stream_count; j++) {
2359                 if (stream_set[j])
2360                         stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
2361         }
2362 }
2363
2364 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
2365 {
2366         int i = 0;
2367
2368         if (context->stream_count < 2)
2369                 return;
2370         for (i = 0; i < context->stream_count ; i++) {
2371                 if (!context->streams[i])
2372                         continue;
2373                 /* TODO: add a function to read AMD VSDB bits and will set
2374                  * crtc_sync_master.multi_sync_enabled flag
2375                  * For now its set to false
2376                  */
2377                 set_multisync_trigger_params(context->streams[i]);
2378         }
2379         set_master_stream(context->streams, context->stream_count);
2380 }
2381
2382 static struct dc_stream_state *
2383 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
2384                        const struct drm_display_mode *drm_mode,
2385                        const struct dm_connector_state *dm_state)
2386 {
2387         struct drm_display_mode *preferred_mode = NULL;
2388         struct drm_connector *drm_connector;
2389         struct dc_stream_state *stream = NULL;
2390         struct drm_display_mode mode = *drm_mode;
2391         bool native_mode_found = false;
2392         struct dc_sink *sink = NULL;
2393         if (aconnector == NULL) {
2394                 DRM_ERROR("aconnector is NULL!\n");
2395                 return stream;
2396         }
2397
2398         drm_connector = &aconnector->base;
2399
2400         if (!aconnector->dc_sink) {
2401                 /*
2402                  * Create dc_sink when necessary to MST
2403                  * Don't apply fake_sink to MST
2404                  */
2405                 if (aconnector->mst_port) {
2406                         dm_dp_mst_dc_sink_create(drm_connector);
2407                         return stream;
2408                 }
2409
2410                 sink = create_fake_sink(aconnector);
2411                 if (!sink)
2412                         return stream;
2413         } else {
2414                 sink = aconnector->dc_sink;
2415         }
2416
2417         stream = dc_create_stream_for_sink(sink);
2418
2419         if (stream == NULL) {
2420                 DRM_ERROR("Failed to create stream for sink!\n");
2421                 goto finish;
2422         }
2423
2424         list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
2425                 /* Search for preferred mode */
2426                 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
2427                         native_mode_found = true;
2428                         break;
2429                 }
2430         }
2431         if (!native_mode_found)
2432                 preferred_mode = list_first_entry_or_null(
2433                                 &aconnector->base.modes,
2434                                 struct drm_display_mode,
2435                                 head);
2436
2437         if (preferred_mode == NULL) {
2438                 /* This may not be an error, the use case is when we we have no
2439                  * usermode calls to reset and set mode upon hotplug. In this
2440                  * case, we call set mode ourselves to restore the previous mode
2441                  * and the modelist may not be filled in in time.
2442                  */
2443                 DRM_DEBUG_DRIVER("No preferred mode found\n");
2444         } else {
2445                 decide_crtc_timing_for_drm_display_mode(
2446                                 &mode, preferred_mode,
2447                                 dm_state ? (dm_state->scaling != RMX_OFF) : false);
2448         }
2449
2450         if (!dm_state)
2451                 drm_mode_set_crtcinfo(&mode, 0);
2452
2453         fill_stream_properties_from_drm_display_mode(stream,
2454                         &mode, &aconnector->base);
2455         update_stream_scaling_settings(&mode, dm_state, stream);
2456
2457         fill_audio_info(
2458                 &stream->audio_info,
2459                 drm_connector,
2460                 sink);
2461
2462         update_stream_signal(stream);
2463
2464         if (dm_state && dm_state->freesync_capable)
2465                 stream->ignore_msa_timing_param = true;
2466 finish:
2467         if (sink && sink->sink_signal == SIGNAL_TYPE_VIRTUAL)
2468                 dc_sink_release(sink);
2469
2470         return stream;
2471 }
2472
2473 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
2474 {
2475         drm_crtc_cleanup(crtc);
2476         kfree(crtc);
2477 }
2478
2479 static void dm_crtc_destroy_state(struct drm_crtc *crtc,
2480                                   struct drm_crtc_state *state)
2481 {
2482         struct dm_crtc_state *cur = to_dm_crtc_state(state);
2483
2484         /* TODO Destroy dc_stream objects are stream object is flattened */
2485         if (cur->stream)
2486                 dc_stream_release(cur->stream);
2487
2488
2489         __drm_atomic_helper_crtc_destroy_state(state);
2490
2491
2492         kfree(state);
2493 }
2494
2495 static void dm_crtc_reset_state(struct drm_crtc *crtc)
2496 {
2497         struct dm_crtc_state *state;
2498
2499         if (crtc->state)
2500                 dm_crtc_destroy_state(crtc, crtc->state);
2501
2502         state = kzalloc(sizeof(*state), GFP_KERNEL);
2503         if (WARN_ON(!state))
2504                 return;
2505
2506         crtc->state = &state->base;
2507         crtc->state->crtc = crtc;
2508
2509 }
2510
2511 static struct drm_crtc_state *
2512 dm_crtc_duplicate_state(struct drm_crtc *crtc)
2513 {
2514         struct dm_crtc_state *state, *cur;
2515
2516         cur = to_dm_crtc_state(crtc->state);
2517
2518         if (WARN_ON(!crtc->state))
2519                 return NULL;
2520
2521         state = kzalloc(sizeof(*state), GFP_KERNEL);
2522         if (!state)
2523                 return NULL;
2524
2525         __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
2526
2527         if (cur->stream) {
2528                 state->stream = cur->stream;
2529                 dc_stream_retain(state->stream);
2530         }
2531
2532         /* TODO Duplicate dc_stream after objects are stream object is flattened */
2533
2534         return &state->base;
2535 }
2536
2537
2538 static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
2539 {
2540         enum dc_irq_source irq_source;
2541         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2542         struct amdgpu_device *adev = crtc->dev->dev_private;
2543
2544         irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
2545         return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2546 }
2547
2548 static int dm_enable_vblank(struct drm_crtc *crtc)
2549 {
2550         return dm_set_vblank(crtc, true);
2551 }
2552
2553 static void dm_disable_vblank(struct drm_crtc *crtc)
2554 {
2555         dm_set_vblank(crtc, false);
2556 }
2557
2558 /* Implemented only the options currently availible for the driver */
2559 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
2560         .reset = dm_crtc_reset_state,
2561         .destroy = amdgpu_dm_crtc_destroy,
2562         .gamma_set = drm_atomic_helper_legacy_gamma_set,
2563         .set_config = drm_atomic_helper_set_config,
2564         .page_flip = drm_atomic_helper_page_flip,
2565         .atomic_duplicate_state = dm_crtc_duplicate_state,
2566         .atomic_destroy_state = dm_crtc_destroy_state,
2567         .set_crc_source = amdgpu_dm_crtc_set_crc_source,
2568         .enable_vblank = dm_enable_vblank,
2569         .disable_vblank = dm_disable_vblank,
2570 };
2571
2572 static enum drm_connector_status
2573 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
2574 {
2575         bool connected;
2576         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2577
2578         /* Notes:
2579          * 1. This interface is NOT called in context of HPD irq.
2580          * 2. This interface *is called* in context of user-mode ioctl. Which
2581          * makes it a bad place for *any* MST-related activit. */
2582
2583         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
2584             !aconnector->fake_enable)
2585                 connected = (aconnector->dc_sink != NULL);
2586         else
2587                 connected = (aconnector->base.force == DRM_FORCE_ON);
2588
2589         return (connected ? connector_status_connected :
2590                         connector_status_disconnected);
2591 }
2592
2593 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
2594                                             struct drm_connector_state *connector_state,
2595                                             struct drm_property *property,
2596                                             uint64_t val)
2597 {
2598         struct drm_device *dev = connector->dev;
2599         struct amdgpu_device *adev = dev->dev_private;
2600         struct dm_connector_state *dm_old_state =
2601                 to_dm_connector_state(connector->state);
2602         struct dm_connector_state *dm_new_state =
2603                 to_dm_connector_state(connector_state);
2604
2605         int ret = -EINVAL;
2606
2607         if (property == dev->mode_config.scaling_mode_property) {
2608                 enum amdgpu_rmx_type rmx_type;
2609
2610                 switch (val) {
2611                 case DRM_MODE_SCALE_CENTER:
2612                         rmx_type = RMX_CENTER;
2613                         break;
2614                 case DRM_MODE_SCALE_ASPECT:
2615                         rmx_type = RMX_ASPECT;
2616                         break;
2617                 case DRM_MODE_SCALE_FULLSCREEN:
2618                         rmx_type = RMX_FULL;
2619                         break;
2620                 case DRM_MODE_SCALE_NONE:
2621                 default:
2622                         rmx_type = RMX_OFF;
2623                         break;
2624                 }
2625
2626                 if (dm_old_state->scaling == rmx_type)
2627                         return 0;
2628
2629                 dm_new_state->scaling = rmx_type;
2630                 ret = 0;
2631         } else if (property == adev->mode_info.underscan_hborder_property) {
2632                 dm_new_state->underscan_hborder = val;
2633                 ret = 0;
2634         } else if (property == adev->mode_info.underscan_vborder_property) {
2635                 dm_new_state->underscan_vborder = val;
2636                 ret = 0;
2637         } else if (property == adev->mode_info.underscan_property) {
2638                 dm_new_state->underscan_enable = val;
2639                 ret = 0;
2640         }
2641
2642         return ret;
2643 }
2644
2645 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
2646                                             const struct drm_connector_state *state,
2647                                             struct drm_property *property,
2648                                             uint64_t *val)
2649 {
2650         struct drm_device *dev = connector->dev;
2651         struct amdgpu_device *adev = dev->dev_private;
2652         struct dm_connector_state *dm_state =
2653                 to_dm_connector_state(state);
2654         int ret = -EINVAL;
2655
2656         if (property == dev->mode_config.scaling_mode_property) {
2657                 switch (dm_state->scaling) {
2658                 case RMX_CENTER:
2659                         *val = DRM_MODE_SCALE_CENTER;
2660                         break;
2661                 case RMX_ASPECT:
2662                         *val = DRM_MODE_SCALE_ASPECT;
2663                         break;
2664                 case RMX_FULL:
2665                         *val = DRM_MODE_SCALE_FULLSCREEN;
2666                         break;
2667                 case RMX_OFF:
2668                 default:
2669                         *val = DRM_MODE_SCALE_NONE;
2670                         break;
2671                 }
2672                 ret = 0;
2673         } else if (property == adev->mode_info.underscan_hborder_property) {
2674                 *val = dm_state->underscan_hborder;
2675                 ret = 0;
2676         } else if (property == adev->mode_info.underscan_vborder_property) {
2677                 *val = dm_state->underscan_vborder;
2678                 ret = 0;
2679         } else if (property == adev->mode_info.underscan_property) {
2680                 *val = dm_state->underscan_enable;
2681                 ret = 0;
2682         }
2683         return ret;
2684 }
2685
2686 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
2687 {
2688         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2689         const struct dc_link *link = aconnector->dc_link;
2690         struct amdgpu_device *adev = connector->dev->dev_private;
2691         struct amdgpu_display_manager *dm = &adev->dm;
2692
2693 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2694         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2695
2696         if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
2697             link->type != dc_connection_none &&
2698             dm->backlight_dev) {
2699                 backlight_device_unregister(dm->backlight_dev);
2700                 dm->backlight_dev = NULL;
2701         }
2702 #endif
2703         drm_connector_unregister(connector);
2704         drm_connector_cleanup(connector);
2705         kfree(connector);
2706 }
2707
2708 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
2709 {
2710         struct dm_connector_state *state =
2711                 to_dm_connector_state(connector->state);
2712
2713         if (connector->state)
2714                 __drm_atomic_helper_connector_destroy_state(connector->state);
2715
2716         kfree(state);
2717
2718         state = kzalloc(sizeof(*state), GFP_KERNEL);
2719
2720         if (state) {
2721                 state->scaling = RMX_OFF;
2722                 state->underscan_enable = false;
2723                 state->underscan_hborder = 0;
2724                 state->underscan_vborder = 0;
2725
2726                 __drm_atomic_helper_connector_reset(connector, &state->base);
2727         }
2728 }
2729
2730 struct drm_connector_state *
2731 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
2732 {
2733         struct dm_connector_state *state =
2734                 to_dm_connector_state(connector->state);
2735
2736         struct dm_connector_state *new_state =
2737                         kmemdup(state, sizeof(*state), GFP_KERNEL);
2738
2739         if (new_state) {
2740                 __drm_atomic_helper_connector_duplicate_state(connector,
2741                                                               &new_state->base);
2742                 return &new_state->base;
2743         }
2744
2745         return NULL;
2746 }
2747
2748 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
2749         .reset = amdgpu_dm_connector_funcs_reset,
2750         .detect = amdgpu_dm_connector_detect,
2751         .fill_modes = drm_helper_probe_single_connector_modes,
2752         .destroy = amdgpu_dm_connector_destroy,
2753         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
2754         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2755         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
2756         .atomic_get_property = amdgpu_dm_connector_atomic_get_property
2757 };
2758
2759 static struct drm_encoder *best_encoder(struct drm_connector *connector)
2760 {
2761         int enc_id = connector->encoder_ids[0];
2762         struct drm_mode_object *obj;
2763         struct drm_encoder *encoder;
2764
2765         DRM_DEBUG_DRIVER("Finding the best encoder\n");
2766
2767         /* pick the encoder ids */
2768         if (enc_id) {
2769                 obj = drm_mode_object_find(connector->dev, NULL, enc_id, DRM_MODE_OBJECT_ENCODER);
2770                 if (!obj) {
2771                         DRM_ERROR("Couldn't find a matching encoder for our connector\n");
2772                         return NULL;
2773                 }
2774                 encoder = obj_to_encoder(obj);
2775                 return encoder;
2776         }
2777         DRM_ERROR("No encoder id\n");
2778         return NULL;
2779 }
2780
2781 static int get_modes(struct drm_connector *connector)
2782 {
2783         return amdgpu_dm_connector_get_modes(connector);
2784 }
2785
2786 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
2787 {
2788         struct dc_sink_init_data init_params = {
2789                         .link = aconnector->dc_link,
2790                         .sink_signal = SIGNAL_TYPE_VIRTUAL
2791         };
2792         struct edid *edid;
2793
2794         if (!aconnector->base.edid_blob_ptr) {
2795                 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
2796                                 aconnector->base.name);
2797
2798                 aconnector->base.force = DRM_FORCE_OFF;
2799                 aconnector->base.override_edid = false;
2800                 return;
2801         }
2802
2803         edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
2804
2805         aconnector->edid = edid;
2806
2807         aconnector->dc_em_sink = dc_link_add_remote_sink(
2808                 aconnector->dc_link,
2809                 (uint8_t *)edid,
2810                 (edid->extensions + 1) * EDID_LENGTH,
2811                 &init_params);
2812
2813         if (aconnector->base.force == DRM_FORCE_ON)
2814                 aconnector->dc_sink = aconnector->dc_link->local_sink ?
2815                 aconnector->dc_link->local_sink :
2816                 aconnector->dc_em_sink;
2817 }
2818
2819 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
2820 {
2821         struct dc_link *link = (struct dc_link *)aconnector->dc_link;
2822
2823         /* In case of headless boot with force on for DP managed connector
2824          * Those settings have to be != 0 to get initial modeset
2825          */
2826         if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
2827                 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
2828                 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
2829         }
2830
2831
2832         aconnector->base.override_edid = true;
2833         create_eml_sink(aconnector);
2834 }
2835
2836 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
2837                                    struct drm_display_mode *mode)
2838 {
2839         int result = MODE_ERROR;
2840         struct dc_sink *dc_sink;
2841         struct amdgpu_device *adev = connector->dev->dev_private;
2842         /* TODO: Unhardcode stream count */
2843         struct dc_stream_state *stream;
2844         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2845         enum dc_status dc_result = DC_OK;
2846
2847         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
2848                         (mode->flags & DRM_MODE_FLAG_DBLSCAN))
2849                 return result;
2850
2851         /* Only run this the first time mode_valid is called to initilialize
2852          * EDID mgmt
2853          */
2854         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
2855                 !aconnector->dc_em_sink)
2856                 handle_edid_mgmt(aconnector);
2857
2858         dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
2859
2860         if (dc_sink == NULL) {
2861                 DRM_ERROR("dc_sink is NULL!\n");
2862                 goto fail;
2863         }
2864
2865         stream = create_stream_for_sink(aconnector, mode, NULL);
2866         if (stream == NULL) {
2867                 DRM_ERROR("Failed to create stream for sink!\n");
2868                 goto fail;
2869         }
2870
2871         dc_result = dc_validate_stream(adev->dm.dc, stream);
2872
2873         if (dc_result == DC_OK)
2874                 result = MODE_OK;
2875         else
2876                 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
2877                               mode->vdisplay,
2878                               mode->hdisplay,
2879                               mode->clock,
2880                               dc_result);
2881
2882         dc_stream_release(stream);
2883
2884 fail:
2885         /* TODO: error handling*/
2886         return result;
2887 }
2888
2889 static const struct drm_connector_helper_funcs
2890 amdgpu_dm_connector_helper_funcs = {
2891         /*
2892          * If hotplug a second bigger display in FB Con mode, bigger resolution
2893          * modes will be filtered by drm_mode_validate_size(), and those modes
2894          * is missing after user start lightdm. So we need to renew modes list.
2895          * in get_modes call back, not just return the modes count
2896          */
2897         .get_modes = get_modes,
2898         .mode_valid = amdgpu_dm_connector_mode_valid,
2899         .best_encoder = best_encoder
2900 };
2901
2902 static void dm_crtc_helper_disable(struct drm_crtc *crtc)
2903 {
2904 }
2905
2906 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
2907                                        struct drm_crtc_state *state)
2908 {
2909         struct amdgpu_device *adev = crtc->dev->dev_private;
2910         struct dc *dc = adev->dm.dc;
2911         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
2912         int ret = -EINVAL;
2913
2914         if (unlikely(!dm_crtc_state->stream &&
2915                      modeset_required(state, NULL, dm_crtc_state->stream))) {
2916                 WARN_ON(1);
2917                 return ret;
2918         }
2919
2920         /* In some use cases, like reset, no stream  is attached */
2921         if (!dm_crtc_state->stream)
2922                 return 0;
2923
2924         if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
2925                 return 0;
2926
2927         return ret;
2928 }
2929
2930 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
2931                                       const struct drm_display_mode *mode,
2932                                       struct drm_display_mode *adjusted_mode)
2933 {
2934         return true;
2935 }
2936
2937 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
2938         .disable = dm_crtc_helper_disable,
2939         .atomic_check = dm_crtc_helper_atomic_check,
2940         .mode_fixup = dm_crtc_helper_mode_fixup
2941 };
2942
2943 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
2944 {
2945
2946 }
2947
2948 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
2949                                           struct drm_crtc_state *crtc_state,
2950                                           struct drm_connector_state *conn_state)
2951 {
2952         return 0;
2953 }
2954
2955 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
2956         .disable = dm_encoder_helper_disable,
2957         .atomic_check = dm_encoder_helper_atomic_check
2958 };
2959
2960 static void dm_drm_plane_reset(struct drm_plane *plane)
2961 {
2962         struct dm_plane_state *amdgpu_state = NULL;
2963
2964         if (plane->state)
2965                 plane->funcs->atomic_destroy_state(plane, plane->state);
2966
2967         amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
2968         WARN_ON(amdgpu_state == NULL);
2969         
2970         if (amdgpu_state) {
2971                 plane->state = &amdgpu_state->base;
2972                 plane->state->plane = plane;
2973                 plane->state->rotation = DRM_MODE_ROTATE_0;
2974         }
2975 }
2976
2977 static struct drm_plane_state *
2978 dm_drm_plane_duplicate_state(struct drm_plane *plane)
2979 {
2980         struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
2981
2982         old_dm_plane_state = to_dm_plane_state(plane->state);
2983         dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
2984         if (!dm_plane_state)
2985                 return NULL;
2986
2987         __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
2988
2989         if (old_dm_plane_state->dc_state) {
2990                 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
2991                 dc_plane_state_retain(dm_plane_state->dc_state);
2992         }
2993
2994         return &dm_plane_state->base;
2995 }
2996
2997 void dm_drm_plane_destroy_state(struct drm_plane *plane,
2998                                 struct drm_plane_state *state)
2999 {
3000         struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3001
3002         if (dm_plane_state->dc_state)
3003                 dc_plane_state_release(dm_plane_state->dc_state);
3004
3005         drm_atomic_helper_plane_destroy_state(plane, state);
3006 }
3007
3008 static const struct drm_plane_funcs dm_plane_funcs = {
3009         .update_plane   = drm_atomic_helper_update_plane,
3010         .disable_plane  = drm_atomic_helper_disable_plane,
3011         .destroy        = drm_plane_cleanup,
3012         .reset = dm_drm_plane_reset,
3013         .atomic_duplicate_state = dm_drm_plane_duplicate_state,
3014         .atomic_destroy_state = dm_drm_plane_destroy_state,
3015 };
3016
3017 static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
3018                                       struct drm_plane_state *new_state)
3019 {
3020         struct amdgpu_framebuffer *afb;
3021         struct drm_gem_object *obj;
3022         struct amdgpu_device *adev;
3023         struct amdgpu_bo *rbo;
3024         uint64_t chroma_addr = 0;
3025         struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
3026         unsigned int awidth;
3027         uint32_t domain;
3028         int r;
3029
3030         dm_plane_state_old = to_dm_plane_state(plane->state);
3031         dm_plane_state_new = to_dm_plane_state(new_state);
3032
3033         if (!new_state->fb) {
3034                 DRM_DEBUG_DRIVER("No FB bound\n");
3035                 return 0;
3036         }
3037
3038         afb = to_amdgpu_framebuffer(new_state->fb);
3039         obj = new_state->fb->obj[0];
3040         rbo = gem_to_amdgpu_bo(obj);
3041         adev = amdgpu_ttm_adev(rbo->tbo.bdev);
3042         r = amdgpu_bo_reserve(rbo, false);
3043         if (unlikely(r != 0))
3044                 return r;
3045
3046         if (plane->type != DRM_PLANE_TYPE_CURSOR)
3047                 domain = amdgpu_display_supported_domains(adev);
3048         else
3049                 domain = AMDGPU_GEM_DOMAIN_VRAM;
3050
3051         r = amdgpu_bo_pin(rbo, domain, &afb->address);
3052         amdgpu_bo_unreserve(rbo);
3053
3054         if (unlikely(r != 0)) {
3055                 if (r != -ERESTARTSYS)
3056                         DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
3057                 return r;
3058         }
3059
3060         amdgpu_bo_ref(rbo);
3061
3062         if (dm_plane_state_new->dc_state &&
3063                         dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
3064                 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
3065
3066                 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
3067                         plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);
3068                         plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);
3069                 } else {
3070                         awidth = ALIGN(new_state->fb->width, 64);
3071                         plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3072                         plane_state->address.video_progressive.luma_addr.low_part
3073                                                         = lower_32_bits(afb->address);
3074                         plane_state->address.video_progressive.luma_addr.high_part
3075                                                         = upper_32_bits(afb->address);
3076                         chroma_addr = afb->address + (u64)awidth * new_state->fb->height;
3077                         plane_state->address.video_progressive.chroma_addr.low_part
3078                                                         = lower_32_bits(chroma_addr);
3079                         plane_state->address.video_progressive.chroma_addr.high_part
3080                                                         = upper_32_bits(chroma_addr);
3081                 }
3082         }
3083
3084         return 0;
3085 }
3086
3087 static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
3088                                        struct drm_plane_state *old_state)
3089 {
3090         struct amdgpu_bo *rbo;
3091         int r;
3092
3093         if (!old_state->fb)
3094                 return;
3095
3096         rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
3097         r = amdgpu_bo_reserve(rbo, false);
3098         if (unlikely(r)) {
3099                 DRM_ERROR("failed to reserve rbo before unpin\n");
3100                 return;
3101         }
3102
3103         amdgpu_bo_unpin(rbo);
3104         amdgpu_bo_unreserve(rbo);
3105         amdgpu_bo_unref(&rbo);
3106 }
3107
3108 static int dm_plane_atomic_check(struct drm_plane *plane,
3109                                  struct drm_plane_state *state)
3110 {
3111         struct amdgpu_device *adev = plane->dev->dev_private;
3112         struct dc *dc = adev->dm.dc;
3113         struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3114
3115         if (!dm_plane_state->dc_state)
3116                 return 0;
3117
3118         if (!fill_rects_from_plane_state(state, dm_plane_state->dc_state))
3119                 return -EINVAL;
3120
3121         if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
3122                 return 0;
3123
3124         return -EINVAL;
3125 }
3126
3127 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
3128         .prepare_fb = dm_plane_helper_prepare_fb,
3129         .cleanup_fb = dm_plane_helper_cleanup_fb,
3130         .atomic_check = dm_plane_atomic_check,
3131 };
3132
3133 /*
3134  * TODO: these are currently initialized to rgb formats only.
3135  * For future use cases we should either initialize them dynamically based on
3136  * plane capabilities, or initialize this array to all formats, so internal drm
3137  * check will succeed, and let DC to implement proper check
3138  */
3139 static const uint32_t rgb_formats[] = {
3140         DRM_FORMAT_RGB888,
3141         DRM_FORMAT_XRGB8888,
3142         DRM_FORMAT_ARGB8888,
3143         DRM_FORMAT_RGBA8888,
3144         DRM_FORMAT_XRGB2101010,
3145         DRM_FORMAT_XBGR2101010,
3146         DRM_FORMAT_ARGB2101010,
3147         DRM_FORMAT_ABGR2101010,
3148 };
3149