378f4b6b43da6821d080d07b8587e89d15457e24
[muen/linux.git] / drivers / gpu / drm / amd / include / asic_reg / uvd / uvd_6_0_d.h
1 /*
2  * UVD_6_0 Register documentation
3  *
4  * Copyright (C) 2014  Advanced Micro Devices, Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included
14  * in all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22  */
23
24 #ifndef UVD_6_0_D_H
25 #define UVD_6_0_D_H
26
27 #define mmUVD_SEMA_ADDR_LOW                                                     0x3bc0
28 #define mmUVD_SEMA_ADDR_HIGH                                                    0x3bc1
29 #define mmUVD_SEMA_CMD                                                          0x3bc2
30 #define mmUVD_GPCOM_VCPU_CMD                                                    0x3bc3
31 #define mmUVD_GPCOM_VCPU_DATA0                                                  0x3bc4
32 #define mmUVD_GPCOM_VCPU_DATA1                                                  0x3bc5
33 #define mmUVD_ENGINE_CNTL                                                       0x3bc6
34 #define mmUVD_UDEC_ADDR_CONFIG                                                  0x3bd3
35 #define mmUVD_UDEC_DB_ADDR_CONFIG                                               0x3bd4
36 #define mmUVD_UDEC_DBW_ADDR_CONFIG                                              0x3bd5
37 #define mmUVD_POWER_STATUS_U                                                    0x3bfd
38 #define mmUVD_NO_OP                                                             0x3bff
39 #define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW                                          0x3c69
40 #define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH                                         0x3c68
41 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW                                          0x3c67
42 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH                                         0x3c66
43 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW                                      0x3c5f
44 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH                                     0x3c5e
45 #define mmUVD_SEMA_CNTL                                                         0x3d00
46 #define mmUVD_LMI_EXT40_ADDR                                                    0x3d26
47 #define mmUVD_CTX_INDEX                                                         0x3d28
48 #define mmUVD_CTX_DATA                                                          0x3d29
49 #define mmUVD_CGC_GATE                                                          0x3d2a
50 #define mmUVD_CGC_STATUS                                                        0x3d2b
51 #define mmUVD_CGC_CTRL                                                          0x3d2c
52 #define mmUVD_CGC_UDEC_STATUS                                                   0x3d2d
53 #define mmUVD_LMI_CTRL2                                                         0x3d3d
54 #define mmUVD_MASTINT_EN                                                        0x3d40
55 #define mmUVD_LMI_ADDR_EXT                                                      0x3d65
56 #define mmUVD_LMI_CTRL                                                          0x3d66
57 #define mmUVD_LMI_STATUS                                                        0x3d67
58 #define mmUVD_LMI_SWAP_CNTL                                                     0x3d6d
59 #define mmUVD_MP_SWAP_CNTL                                                      0x3d6f
60 #define mmUVD_MPC_CNTL                                                          0x3d77
61 #define mmUVD_MPC_SET_MUXA0                                                     0x3d79
62 #define mmUVD_MPC_SET_MUXA1                                                     0x3d7a
63 #define mmUVD_MPC_SET_MUXB0                                                     0x3d7b
64 #define mmUVD_MPC_SET_MUXB1                                                     0x3d7c
65 #define mmUVD_MPC_SET_MUX                                                       0x3d7d
66 #define mmUVD_MPC_SET_ALU                                                       0x3d7e
67 #define mmUVD_VCPU_CACHE_OFFSET0                                                0x3d82
68 #define mmUVD_VCPU_CACHE_SIZE0                                                  0x3d83
69 #define mmUVD_VCPU_CACHE_OFFSET1                                                0x3d84
70 #define mmUVD_VCPU_CACHE_SIZE1                                                  0x3d85
71 #define mmUVD_VCPU_CACHE_OFFSET2                                                0x3d86
72 #define mmUVD_VCPU_CACHE_SIZE2                                                  0x3d87
73 #define mmUVD_VCPU_CNTL                                                         0x3d98
74 #define mmUVD_SOFT_RESET                                                        0x3da0
75 #define mmUVD_LMI_RBC_IB_VMID                                                   0x3da1
76 #define mmUVD_RBC_IB_SIZE                                                       0x3da2
77 #define mmUVD_LMI_RBC_RB_VMID                                                   0x3da3
78 #define mmUVD_RBC_RB_RPTR                                                       0x3da4
79 #define mmUVD_RBC_RB_WPTR                                                       0x3da5
80 #define mmUVD_RBC_RB_WPTR_CNTL                                                  0x3da6
81 #define mmUVD_RBC_RB_CNTL                                                       0x3da9
82 #define mmUVD_RBC_RB_RPTR_ADDR                                                  0x3daa
83 #define mmUVD_STATUS                                                            0x3daf
84 #define mmUVD_SEMA_TIMEOUT_STATUS                                               0x3db0
85 #define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL                                 0x3db1
86 #define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL                                      0x3db2
87 #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL                               0x3db3
88 #define mmUVD_CONTEXT_ID                                                        0x3dbd
89 #define mmUVD_RBC_IB_SIZE_UPDATE                                                0x3df1
90 #define mmUVD_SUVD_CGC_GATE                                                     0x3be4
91 #define mmUVD_SUVD_CGC_STATUS                                                   0x3be5
92 #define mmUVD_SUVD_CGC_CTRL                                                     0x3be6
93 #define ixUVD_LMI_VMID_INTERNAL                                                 0x99
94 #define ixUVD_LMI_VMID_INTERNAL2                                                0x9a
95 #define ixUVD_LMI_CACHE_CTRL                                                    0x9b
96 #define ixUVD_LMI_SWAP_CNTL2                                                    0xaa
97 #define ixUVD_LMI_ADDR_EXT2                                                     0xab
98 #define ixUVD_CGC_MEM_CTRL                                                      0xc0
99 #define ixUVD_CGC_CTRL2                                                         0xc1
100 #define ixUVD_LMI_VMID_INTERNAL3                                                0x162
101 #define mmUVD_PGFSM_CONFIG                                                      0x38c0
102 #define mmUVD_PGFSM_READ_TILE1                                                  0x38c2
103 #define mmUVD_PGFSM_READ_TILE2                                                  0x38c3
104 #define mmUVD_POWER_STATUS                                                      0x38c4
105 #define mmUVD_PGFSM_READ_TILE3                                                  0x38c5
106 #define mmUVD_PGFSM_READ_TILE4                                                  0x38c6
107 #define mmUVD_PGFSM_READ_TILE5                                                  0x38c8
108 #define mmUVD_PGFSM_READ_TILE6                                                  0x38ee
109 #define mmUVD_PGFSM_READ_TILE7                                                  0x38ef
110 #define mmUVD_MIF_CURR_ADDR_CONFIG                                              0x3992
111 #define mmUVD_MIF_REF_ADDR_CONFIG                                               0x3993
112 #define mmUVD_MIF_RECON1_ADDR_CONFIG                                            0x39c5
113 #define ixUVD_MIF_SCLR_ADDR_CONFIG                                              0x4
114 #define mmUVD_JPEG_ADDR_CONFIG                                                  0x3a1f
115 #define mmUVD_GP_SCRATCH8                                                       0x3c0a
116 #define mmUVD_GP_SCRATCH9                                                       0x3c0b
117 #define mmUVD_GP_SCRATCH4                                                       0x3d38
118
119 #endif /* UVD_6_0_D_H */