drm/amdgpu:Add new register offset/mask to support VCN DPG mode
[muen/linux.git] / drivers / gpu / drm / amd / include / asic_reg / vcn / vcn_1_0_offset.h
1 /*
2  * Copyright (C) 2017  Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included
12  * in all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20  */
21 #ifndef _vcn_1_0_OFFSET_HEADER
22 #define _vcn_1_0_OFFSET_HEADER
23
24
25
26 // addressBlock: uvd_uvd_pg_dec
27 // base address: 0x1fb00
28 #define mmUVD_PGFSM_CONFIG                                                                             0x00c0
29 #define mmUVD_PGFSM_CONFIG_BASE_IDX                                                                    1
30 #define mmUVD_PGFSM_STATUS                                                                             0x00c1
31 #define mmUVD_PGFSM_STATUS_BASE_IDX                                                                    1
32 #define mmUVD_POWER_STATUS                                                                             0x00c4
33 #define mmUVD_POWER_STATUS_BASE_IDX                                                                    1
34 #define mmCC_UVD_HARVESTING                                                                            0x00c7
35 #define mmCC_UVD_HARVESTING_BASE_IDX                                                                   1
36 #define mmUVD_DPG_LMA_CTL                                                                              0x00d1
37 #define mmUVD_DPG_LMA_CTL_BASE_IDX                                                                     1
38 #define mmUVD_DPG_LMA_DATA                                                                             0x00d2
39 #define mmUVD_DPG_LMA_DATA_BASE_IDX                                                                    1
40 #define mmUVD_DPG_LMA_MASK                                                                             0x00d3
41 #define mmUVD_DPG_LMA_MASK_BASE_IDX                                                                    1
42 #define mmUVD_DPG_PAUSE                                                                                0x00d4
43 #define mmUVD_DPG_PAUSE_BASE_IDX                                                                       1
44 #define mmUVD_SCRATCH1                                                                                 0x00d5
45 #define mmUVD_SCRATCH1_BASE_IDX                                                                        1
46 #define mmUVD_SCRATCH2                                                                                 0x00d6
47 #define mmUVD_SCRATCH2_BASE_IDX                                                                        1
48 #define mmUVD_SCRATCH3                                                                                 0x00d7
49 #define mmUVD_SCRATCH3_BASE_IDX                                                                        1
50 #define mmUVD_SCRATCH4                                                                                 0x00d8
51 #define mmUVD_SCRATCH4_BASE_IDX                                                                        1
52 #define mmUVD_SCRATCH5                                                                                 0x00d9
53 #define mmUVD_SCRATCH5_BASE_IDX                                                                        1
54 #define mmUVD_SCRATCH6                                                                                 0x00da
55 #define mmUVD_SCRATCH6_BASE_IDX                                                                        1
56 #define mmUVD_SCRATCH7                                                                                 0x00db
57 #define mmUVD_SCRATCH7_BASE_IDX                                                                        1
58 #define mmUVD_SCRATCH8                                                                                 0x00dc
59 #define mmUVD_SCRATCH8_BASE_IDX                                                                        1
60 #define mmUVD_SCRATCH9                                                                                 0x00dd
61 #define mmUVD_SCRATCH9_BASE_IDX                                                                        1
62 #define mmUVD_SCRATCH10                                                                                0x00de
63 #define mmUVD_SCRATCH10_BASE_IDX                                                                       1
64 #define mmUVD_SCRATCH11                                                                                0x00df
65 #define mmUVD_SCRATCH11_BASE_IDX                                                                       1
66 #define mmUVD_SCRATCH12                                                                                0x00e0
67 #define mmUVD_SCRATCH12_BASE_IDX                                                                       1
68 #define mmUVD_SCRATCH13                                                                                0x00e1
69 #define mmUVD_SCRATCH13_BASE_IDX                                                                       1
70 #define mmUVD_SCRATCH14                                                                                0x00e2
71 #define mmUVD_SCRATCH14_BASE_IDX                                                                       1
72 #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW                                                         0x00e5
73 #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX                                                1
74 #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH                                                        0x00e6
75 #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX                                               1
76 #define mmUVD_DPG_VCPU_CACHE_OFFSET0                                                                   0x00e7
77 #define mmUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX                                                          1
78
79
80 // addressBlock: uvd_uvdgendec
81 // base address: 0x1fc00
82 #define mmUVD_LCM_CGC_CNTRL                                                                            0x0123
83 #define mmUVD_LCM_CGC_CNTRL_BASE_IDX                                                                   1
84
85
86 // addressBlock: uvd_uvdnpdec
87 // base address: 0x20000
88 #define mmUVD_JPEG_CNTL                                                                                0x0200
89 #define mmUVD_JPEG_CNTL_BASE_IDX                                                                       1
90 #define mmUVD_JPEG_RB_BASE                                                                             0x0201
91 #define mmUVD_JPEG_RB_BASE_BASE_IDX                                                                    1
92 #define mmUVD_JPEG_RB_WPTR                                                                             0x0202
93 #define mmUVD_JPEG_RB_WPTR_BASE_IDX                                                                    1
94 #define mmUVD_JPEG_RB_RPTR                                                                             0x0203
95 #define mmUVD_JPEG_RB_RPTR_BASE_IDX                                                                    1
96 #define mmUVD_JPEG_RB_SIZE                                                                             0x0204
97 #define mmUVD_JPEG_RB_SIZE_BASE_IDX                                                                    1
98 #define mmUVD_JPEG_ADDR_CONFIG                                                                         0x021f
99 #define mmUVD_JPEG_ADDR_CONFIG_BASE_IDX                                                                1
100 #define mmUVD_JPEG_PITCH                                                                               0x0222
101 #define mmUVD_JPEG_PITCH_BASE_IDX                                                                      1
102 #define mmUVD_JPEG_GPCOM_CMD                                                                           0x022c
103 #define mmUVD_JPEG_GPCOM_CMD_BASE_IDX                                                                  1
104 #define mmUVD_JPEG_GPCOM_DATA0                                                                         0x022d
105 #define mmUVD_JPEG_GPCOM_DATA0_BASE_IDX                                                                1
106 #define mmUVD_JPEG_GPCOM_DATA1                                                                         0x022e
107 #define mmUVD_JPEG_GPCOM_DATA1_BASE_IDX                                                                1
108 #define mmUVD_JPEG_JRB_BASE_LO                                                                         0x022f
109 #define mmUVD_JPEG_JRB_BASE_LO_BASE_IDX                                                                1
110 #define mmUVD_JPEG_JRB_BASE_HI                                                                         0x0230
111 #define mmUVD_JPEG_JRB_BASE_HI_BASE_IDX                                                                1
112 #define mmUVD_JPEG_JRB_SIZE                                                                            0x0232
113 #define mmUVD_JPEG_JRB_SIZE_BASE_IDX                                                                   1
114 #define mmUVD_JPEG_JRB_RPTR                                                                            0x0233
115 #define mmUVD_JPEG_JRB_RPTR_BASE_IDX                                                                   1
116 #define mmUVD_JPEG_JRB_WPTR                                                                            0x0234
117 #define mmUVD_JPEG_JRB_WPTR_BASE_IDX                                                                   1
118 #define mmUVD_JPEG_UV_ADDR_CONFIG                                                                      0x0238
119 #define mmUVD_JPEG_UV_ADDR_CONFIG_BASE_IDX                                                             1
120 #define mmUVD_SEMA_ADDR_LOW                                                                            0x03c0
121 #define mmUVD_SEMA_ADDR_LOW_BASE_IDX                                                                   1
122 #define mmUVD_SEMA_ADDR_HIGH                                                                           0x03c1
123 #define mmUVD_SEMA_ADDR_HIGH_BASE_IDX                                                                  1
124 #define mmUVD_SEMA_CMD                                                                                 0x03c2
125 #define mmUVD_SEMA_CMD_BASE_IDX                                                                        1
126 #define mmUVD_GPCOM_VCPU_CMD                                                                           0x03c3
127 #define mmUVD_GPCOM_VCPU_CMD_BASE_IDX                                                                  1
128 #define mmUVD_GPCOM_VCPU_DATA0                                                                         0x03c4
129 #define mmUVD_GPCOM_VCPU_DATA0_BASE_IDX                                                                1
130 #define mmUVD_GPCOM_VCPU_DATA1                                                                         0x03c5
131 #define mmUVD_GPCOM_VCPU_DATA1_BASE_IDX                                                                1
132 #define mmUVD_UDEC_DBW_UV_ADDR_CONFIG                                                                  0x03d2
133 #define mmUVD_UDEC_DBW_UV_ADDR_CONFIG_BASE_IDX                                                         1
134 #define mmUVD_UDEC_ADDR_CONFIG                                                                         0x03d3
135 #define mmUVD_UDEC_ADDR_CONFIG_BASE_IDX                                                                1
136 #define mmUVD_UDEC_DB_ADDR_CONFIG                                                                      0x03d4
137 #define mmUVD_UDEC_DB_ADDR_CONFIG_BASE_IDX                                                             1
138 #define mmUVD_UDEC_DBW_ADDR_CONFIG                                                                     0x03d5
139 #define mmUVD_UDEC_DBW_ADDR_CONFIG_BASE_IDX                                                            1
140 #define mmUVD_SUVD_CGC_GATE                                                                            0x03e4
141 #define mmUVD_SUVD_CGC_GATE_BASE_IDX                                                                   1
142 #define mmUVD_SUVD_CGC_STATUS                                                                          0x03e5
143 #define mmUVD_SUVD_CGC_STATUS_BASE_IDX                                                                 1
144 #define mmUVD_SUVD_CGC_CTRL                                                                            0x03e6
145 #define mmUVD_SUVD_CGC_CTRL_BASE_IDX                                                                   1
146 #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW                                                            0x03ec
147 #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_BASE_IDX                                                   1
148 #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH                                                           0x03ed
149 #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_BASE_IDX                                                  1
150 #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW                                                            0x03f0
151 #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_BASE_IDX                                                   1
152 #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH                                                           0x03f1
153 #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_BASE_IDX                                                  1
154 #define mmUVD_NO_OP                                                                                    0x03ff
155 #define mmUVD_NO_OP_BASE_IDX                                                                           1
156 #define mmUVD_JPEG_CNTL2                                                                               0x0404
157 #define mmUVD_JPEG_CNTL2_BASE_IDX                                                                      1
158 #define mmUVD_VERSION                                                                                  0x0409
159 #define mmUVD_VERSION_BASE_IDX                                                                         1
160 #define mmUVD_GP_SCRATCH8                                                                              0x040a
161 #define mmUVD_GP_SCRATCH8_BASE_IDX                                                                     1
162 #define mmUVD_GP_SCRATCH9                                                                              0x040b
163 #define mmUVD_GP_SCRATCH9_BASE_IDX                                                                     1
164 #define mmUVD_GP_SCRATCH10                                                                             0x040c
165 #define mmUVD_GP_SCRATCH10_BASE_IDX                                                                    1
166 #define mmUVD_GP_SCRATCH11                                                                             0x040d
167 #define mmUVD_GP_SCRATCH11_BASE_IDX                                                                    1
168 #define mmUVD_GP_SCRATCH12                                                                             0x040e
169 #define mmUVD_GP_SCRATCH12_BASE_IDX                                                                    1
170 #define mmUVD_GP_SCRATCH13                                                                             0x040f
171 #define mmUVD_GP_SCRATCH13_BASE_IDX                                                                    1
172 #define mmUVD_GP_SCRATCH14                                                                             0x0410
173 #define mmUVD_GP_SCRATCH14_BASE_IDX                                                                    1
174 #define mmUVD_GP_SCRATCH15                                                                             0x0411
175 #define mmUVD_GP_SCRATCH15_BASE_IDX                                                                    1
176 #define mmUVD_GP_SCRATCH16                                                                             0x0412
177 #define mmUVD_GP_SCRATCH16_BASE_IDX                                                                    1
178 #define mmUVD_GP_SCRATCH17                                                                             0x0413
179 #define mmUVD_GP_SCRATCH17_BASE_IDX                                                                    1
180 #define mmUVD_GP_SCRATCH18                                                                             0x0414
181 #define mmUVD_GP_SCRATCH18_BASE_IDX                                                                    1
182 #define mmUVD_GP_SCRATCH19                                                                             0x0415
183 #define mmUVD_GP_SCRATCH19_BASE_IDX                                                                    1
184 #define mmUVD_GP_SCRATCH20                                                                             0x0416
185 #define mmUVD_GP_SCRATCH20_BASE_IDX                                                                    1
186 #define mmUVD_GP_SCRATCH21                                                                             0x0417
187 #define mmUVD_GP_SCRATCH21_BASE_IDX                                                                    1
188 #define mmUVD_GP_SCRATCH22                                                                             0x0418
189 #define mmUVD_GP_SCRATCH22_BASE_IDX                                                                    1
190 #define mmUVD_GP_SCRATCH23                                                                             0x0419
191 #define mmUVD_GP_SCRATCH23_BASE_IDX                                                                    1
192 #define mmUVD_RB_BASE_LO2                                                                              0x0421
193 #define mmUVD_RB_BASE_LO2_BASE_IDX                                                                     1
194 #define mmUVD_RB_BASE_HI2                                                                              0x0422
195 #define mmUVD_RB_BASE_HI2_BASE_IDX                                                                     1
196 #define mmUVD_RB_SIZE2                                                                                 0x0423
197 #define mmUVD_RB_SIZE2_BASE_IDX                                                                        1
198 #define mmUVD_RB_RPTR2                                                                                 0x0424
199 #define mmUVD_RB_RPTR2_BASE_IDX                                                                        1
200 #define mmUVD_RB_WPTR2                                                                                 0x0425
201 #define mmUVD_RB_WPTR2_BASE_IDX                                                                        1
202 #define mmUVD_RB_BASE_LO                                                                               0x0426
203 #define mmUVD_RB_BASE_LO_BASE_IDX                                                                      1
204 #define mmUVD_RB_BASE_HI                                                                               0x0427
205 #define mmUVD_RB_BASE_HI_BASE_IDX                                                                      1
206 #define mmUVD_RB_SIZE                                                                                  0x0428
207 #define mmUVD_RB_SIZE_BASE_IDX                                                                         1
208 #define mmUVD_RB_RPTR                                                                                  0x0429
209 #define mmUVD_RB_RPTR_BASE_IDX                                                                         1
210 #define mmUVD_RB_WPTR                                                                                  0x042a
211 #define mmUVD_RB_WPTR_BASE_IDX                                                                         1
212 #define mmUVD_RB_WPTR4                                                                                 0x0456
213 #define mmUVD_RB_WPTR4_BASE_IDX                                                                        1
214 #define mmUVD_JRBC_RB_RPTR                                                                             0x0457
215 #define mmUVD_JRBC_RB_RPTR_BASE_IDX                                                                    1
216 #define mmUVD_LMI_JPEG_VMID                                                                            0x045d
217 #define mmUVD_LMI_JPEG_VMID_BASE_IDX                                                                   1
218 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH                                                            0x045e
219 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX                                                   1
220 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW                                                             0x045f
221 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX                                                    1
222 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH                                                                0x0466
223 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_BASE_IDX                                                       1
224 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW                                                                 0x0467
225 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_BASE_IDX                                                        1
226 #define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH                                                                0x0468
227 #define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH_BASE_IDX                                                       1
228 #define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW                                                                 0x0469
229 #define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW_BASE_IDX                                                        1
230
231
232 // addressBlock: uvd_uvddec
233 // base address: 0x20c00
234 #define mmUVD_SEMA_CNTL                                                                                0x0500
235 #define mmUVD_SEMA_CNTL_BASE_IDX                                                                       1
236 #define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW                                                                0x0503
237 #define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX                                                       1
238 #define mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH                                                               0x0504
239 #define mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX                                                      1
240 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW                                                                0x0505
241 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX                                                       1
242 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH                                                               0x0506
243 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX                                                      1
244 #define mmUVD_LMI_JRBC_IB_VMID                                                                         0x0507
245 #define mmUVD_LMI_JRBC_IB_VMID_BASE_IDX                                                                1
246 #define mmUVD_LMI_JRBC_RB_VMID                                                                         0x0508
247 #define mmUVD_LMI_JRBC_RB_VMID_BASE_IDX                                                                1
248 #define mmUVD_JRBC_RB_WPTR                                                                             0x0509
249 #define mmUVD_JRBC_RB_WPTR_BASE_IDX                                                                    1
250 #define mmUVD_JRBC_RB_CNTL                                                                             0x050a
251 #define mmUVD_JRBC_RB_CNTL_BASE_IDX                                                                    1
252 #define mmUVD_JRBC_IB_SIZE                                                                             0x050b
253 #define mmUVD_JRBC_IB_SIZE_BASE_IDX                                                                    1
254 #define mmUVD_JRBC_LMI_SWAP_CNTL                                                                       0x050d
255 #define mmUVD_JRBC_LMI_SWAP_CNTL_BASE_IDX                                                              1
256 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW                                                         0x050e
257 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX                                                1
258 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH                                                        0x050f
259 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX                                               1
260 #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW                                                         0x0510
261 #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX                                                1
262 #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH                                                        0x0511
263 #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX                                               1
264 #define mmUVD_JRBC_RB_REF_DATA                                                                         0x0512
265 #define mmUVD_JRBC_RB_REF_DATA_BASE_IDX                                                                1
266 #define mmUVD_JRBC_RB_COND_RD_TIMER                                                                    0x0513
267 #define mmUVD_JRBC_RB_COND_RD_TIMER_BASE_IDX                                                           1
268 #define mmUVD_JRBC_EXTERNAL_REG_BASE                                                                   0x0517
269 #define mmUVD_JRBC_EXTERNAL_REG_BASE_BASE_IDX                                                          1
270 #define mmUVD_JRBC_SOFT_RESET                                                                          0x0519
271 #define mmUVD_JRBC_SOFT_RESET_BASE_IDX                                                                 1
272 #define mmUVD_JRBC_STATUS                                                                              0x051a
273 #define mmUVD_JRBC_STATUS_BASE_IDX                                                                     1
274 #define mmUVD_RB_RPTR3                                                                                 0x051b
275 #define mmUVD_RB_RPTR3_BASE_IDX                                                                        1
276 #define mmUVD_RB_WPTR3                                                                                 0x051c
277 #define mmUVD_RB_WPTR3_BASE_IDX                                                                        1
278 #define mmUVD_RB_BASE_LO3                                                                              0x051d
279 #define mmUVD_RB_BASE_LO3_BASE_IDX                                                                     1
280 #define mmUVD_RB_BASE_HI3                                                                              0x051e
281 #define mmUVD_RB_BASE_HI3_BASE_IDX                                                                     1
282 #define mmUVD_RB_SIZE3                                                                                 0x051f
283 #define mmUVD_RB_SIZE3_BASE_IDX                                                                        1
284 #define mmJPEG_CGC_GATE                                                                                0x0526
285 #define mmJPEG_CGC_GATE_BASE_IDX                                                                       1
286 #define mmUVD_CTX_INDEX                                                                                0x0528
287 #define mmUVD_CTX_INDEX_BASE_IDX                                                                       1
288 #define mmUVD_CTX_DATA                                                                                 0x0529
289 #define mmUVD_CTX_DATA_BASE_IDX                                                                        1
290 #define mmUVD_CGC_GATE                                                                                 0x052a
291 #define mmUVD_CGC_GATE_BASE_IDX                                                                        1
292 #define mmUVD_CGC_STATUS                                                                               0x052b
293 #define mmUVD_CGC_STATUS_BASE_IDX                                                                      1
294 #define mmUVD_CGC_CTRL                                                                                 0x052c
295 #define mmUVD_CGC_CTRL_BASE_IDX                                                                        1
296 #define mmUVD_GP_SCRATCH0                                                                              0x0534
297 #define mmUVD_GP_SCRATCH0_BASE_IDX                                                                     1
298 #define mmUVD_GP_SCRATCH1                                                                              0x0535
299 #define mmUVD_GP_SCRATCH1_BASE_IDX                                                                     1
300 #define mmUVD_GP_SCRATCH2                                                                              0x0536
301 #define mmUVD_GP_SCRATCH2_BASE_IDX                                                                     1
302 #define mmUVD_GP_SCRATCH3                                                                              0x0537
303 #define mmUVD_GP_SCRATCH3_BASE_IDX                                                                     1
304 #define mmUVD_GP_SCRATCH4                                                                              0x0538
305 #define mmUVD_GP_SCRATCH4_BASE_IDX                                                                     1
306 #define mmUVD_GP_SCRATCH5                                                                              0x0539
307 #define mmUVD_GP_SCRATCH5_BASE_IDX                                                                     1
308 #define mmUVD_GP_SCRATCH6                                                                              0x053a
309 #define mmUVD_GP_SCRATCH6_BASE_IDX                                                                     1
310 #define mmUVD_GP_SCRATCH7                                                                              0x053b
311 #define mmUVD_GP_SCRATCH7_BASE_IDX                                                                     1
312 #define mmUVD_LMI_VCPU_CACHE_VMID                                                                      0x053c
313 #define mmUVD_LMI_VCPU_CACHE_VMID_BASE_IDX                                                             1
314 #define mmUVD_LMI_CTRL2                                                                                0x053d
315 #define mmUVD_LMI_CTRL2_BASE_IDX                                                                       1
316 #define mmUVD_MASTINT_EN                                                                               0x0540
317 #define mmUVD_MASTINT_EN_BASE_IDX                                                                      1
318 #define mmUVD_SYS_INT_EN                                                                               0x0541
319 #define mmUVD_SYS_INT_EN_BASE_IDX                                                                      1
320 #define mmJPEG_CGC_CTRL                                                                                0x0565
321 #define mmJPEG_CGC_CTRL_BASE_IDX                                                                       1
322 #define mmUVD_LMI_CTRL                                                                                 0x0566
323 #define mmUVD_LMI_CTRL_BASE_IDX                                                                        1
324 #define mmUVD_LMI_STATUS                                                                               0x0567
325 #define mmUVD_LMI_STATUS_BASE_IDX                                                                      1
326 #define mmUVD_LMI_VM_CTRL                                                                              0x0568
327 #define mmUVD_LMI_VM_CTRL_BASE_IDX                                                                     1
328 #define mmUVD_LMI_SWAP_CNTL                                                                            0x056d
329 #define mmUVD_LMI_SWAP_CNTL_BASE_IDX                                                                   1
330 #define mmUVD_MPC_SET_MUXA0                                                                            0x0579
331 #define mmUVD_MPC_SET_MUXA0_BASE_IDX                                                                   1
332 #define mmUVD_MPC_SET_MUXA1                                                                            0x057a
333 #define mmUVD_MPC_SET_MUXA1_BASE_IDX                                                                   1
334 #define mmUVD_MPC_SET_MUXB0                                                                            0x057b
335 #define mmUVD_MPC_SET_MUXB0_BASE_IDX                                                                   1
336 #define mmUVD_MPC_SET_MUXB1                                                                            0x057c
337 #define mmUVD_MPC_SET_MUXB1_BASE_IDX                                                                   1
338 #define mmUVD_MPC_SET_MUX                                                                              0x057d
339 #define mmUVD_MPC_SET_MUX_BASE_IDX                                                                     1
340 #define mmUVD_MPC_SET_ALU                                                                              0x057e
341 #define mmUVD_MPC_SET_ALU_BASE_IDX                                                                     1
342 #define mmUVD_GPCOM_SYS_CMD                                                                            0x057f
343 #define mmUVD_GPCOM_SYS_CMD_BASE_IDX                                                                   1
344 #define mmUVD_GPCOM_SYS_DATA0                                                                          0x0580
345 #define mmUVD_GPCOM_SYS_DATA0_BASE_IDX                                                                 1
346 #define mmUVD_GPCOM_SYS_DATA1                                                                          0x0581
347 #define mmUVD_GPCOM_SYS_DATA1_BASE_IDX                                                                 1
348 #define mmUVD_VCPU_CACHE_OFFSET0                                                                       0x0582
349 #define mmUVD_VCPU_CACHE_OFFSET0_BASE_IDX                                                              1
350 #define mmUVD_VCPU_CACHE_SIZE0                                                                         0x0583
351 #define mmUVD_VCPU_CACHE_SIZE0_BASE_IDX                                                                1
352 #define mmUVD_VCPU_CACHE_OFFSET1                                                                       0x0584
353 #define mmUVD_VCPU_CACHE_OFFSET1_BASE_IDX                                                              1
354 #define mmUVD_VCPU_CACHE_SIZE1                                                                         0x0585
355 #define mmUVD_VCPU_CACHE_SIZE1_BASE_IDX                                                                1
356 #define mmUVD_VCPU_CACHE_OFFSET2                                                                       0x0586
357 #define mmUVD_VCPU_CACHE_OFFSET2_BASE_IDX                                                              1
358 #define mmUVD_VCPU_CACHE_SIZE2                                                                         0x0587
359 #define mmUVD_VCPU_CACHE_SIZE2_BASE_IDX                                                                1
360 #define mmUVD_VCPU_CNTL                                                                                0x0598
361 #define mmUVD_VCPU_CNTL_BASE_IDX                                                                       1
362 #define mmUVD_SOFT_RESET                                                                               0x05a0
363 #define mmUVD_SOFT_RESET_BASE_IDX                                                                      1
364 #define mmUVD_LMI_RBC_IB_VMID                                                                          0x05a1
365 #define mmUVD_LMI_RBC_IB_VMID_BASE_IDX                                                                 1
366 #define mmUVD_RBC_IB_SIZE                                                                              0x05a2
367 #define mmUVD_RBC_IB_SIZE_BASE_IDX                                                                     1
368 #define mmUVD_RBC_RB_RPTR                                                                              0x05a4
369 #define mmUVD_RBC_RB_RPTR_BASE_IDX                                                                     1
370 #define mmUVD_RBC_RB_WPTR                                                                              0x05a5
371 #define mmUVD_RBC_RB_WPTR_BASE_IDX                                                                     1
372 #define mmUVD_RBC_RB_WPTR_CNTL                                                                         0x05a6
373 #define mmUVD_RBC_RB_WPTR_CNTL_BASE_IDX                                                                1
374 #define mmUVD_RBC_RB_CNTL                                                                              0x05a9
375 #define mmUVD_RBC_RB_CNTL_BASE_IDX                                                                     1
376 #define mmUVD_RBC_RB_RPTR_ADDR                                                                         0x05aa
377 #define mmUVD_RBC_RB_RPTR_ADDR_BASE_IDX                                                                1
378 #define mmUVD_STATUS                                                                                   0x05af
379 #define mmUVD_STATUS_BASE_IDX                                                                          1
380 #define mmUVD_SEMA_TIMEOUT_STATUS                                                                      0x05b0
381 #define mmUVD_SEMA_TIMEOUT_STATUS_BASE_IDX                                                             1
382 #define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL                                                        0x05b1
383 #define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX                                               1
384 #define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL                                                             0x05b2
385 #define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL_BASE_IDX                                                    1
386 #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL                                                      0x05b3
387 #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX                                             1
388 #define mmUVD_CONTEXT_ID                                                                               0x05bd
389 #define mmUVD_CONTEXT_ID_BASE_IDX                                                                      1
390 #define mmUVD_CONTEXT_ID2                                                                              0x05bf
391 #define mmUVD_CONTEXT_ID2_BASE_IDX                                                                     1
392 #define mmUVD_RBC_WPTR_POLL_CNTL                                                                       0x05d8
393 #define mmUVD_RBC_WPTR_POLL_CNTL_BASE_IDX                                                              1
394 #define mmUVD_RBC_WPTR_POLL_ADDR                                                                       0x05d9
395 #define mmUVD_RBC_WPTR_POLL_ADDR_BASE_IDX                                                              1
396 #define mmUVD_RB_BASE_LO4                                                                              0x05df
397 #define mmUVD_RB_BASE_LO4_BASE_IDX                                                                     1
398 #define mmUVD_RB_BASE_HI4                                                                              0x05e0
399 #define mmUVD_RB_BASE_HI4_BASE_IDX                                                                     1
400 #define mmUVD_RB_SIZE4                                                                                 0x05e1
401 #define mmUVD_RB_SIZE4_BASE_IDX                                                                        1
402 #define mmUVD_RB_RPTR4                                                                                 0x05e2
403 #define mmUVD_RB_RPTR4_BASE_IDX                                                                        1
404
405
406 #endif