drm/amdgpu:Add new register offset/mask to support VCN DPG mode
[muen/linux.git] / drivers / gpu / drm / amd / include / asic_reg / vcn / vcn_1_0_sh_mask.h
1 /*
2  * Copyright (C) 2017  Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included
12  * in all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20  */
21 #ifndef _vcn_1_0_SH_MASK_HEADER
22 #define _vcn_1_0_SH_MASK_HEADER
23
24
25 // addressBlock: uvd_uvd_pg_dec
26 //UVD_PGFSM_CONFIG
27 #define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT                                                              0x0
28 #define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT                                                              0x2
29 #define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT                                                              0x4
30 #define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT                                                              0x6
31 #define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT                                                              0x8
32 #define UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT                                                             0xa
33 #define UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT                                                             0xc
34 #define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT                                                             0xe
35 #define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT                                                             0x10
36 #define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT                                                              0x12
37 #define UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT                                                              0x14
38 #define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG_MASK                                                                0x00000003L
39 #define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG_MASK                                                                0x0000000CL
40 #define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG_MASK                                                                0x00000030L
41 #define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG_MASK                                                                0x000000C0L
42 #define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG_MASK                                                                0x00000300L
43 #define UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG_MASK                                                               0x00000C00L
44 #define UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG_MASK                                                               0x00003000L
45 #define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG_MASK                                                               0x0000C000L
46 #define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG_MASK                                                               0x00030000L
47 #define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG_MASK                                                                0x000C0000L
48 #define UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG_MASK                                                                0x00300000L
49 //UVD_PGFSM_STATUS
50 #define UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT                                                              0x0
51 #define UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT                                                              0x2
52 #define UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT                                                              0x4
53 #define UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT                                                              0x6
54 #define UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT                                                              0x8
55 #define UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT                                                             0xa
56 #define UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT                                                             0xc
57 #define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT                                                             0xe
58 #define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT                                                             0x10
59 #define UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT                                                              0x12
60 #define UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT                                                              0x14
61 #define UVD_PGFSM_STATUS__UVDM_PWR_STATUS_MASK                                                                0x00000003L
62 #define UVD_PGFSM_STATUS__UVDU_PWR_STATUS_MASK                                                                0x0000000CL
63 #define UVD_PGFSM_STATUS__UVDF_PWR_STATUS_MASK                                                                0x00000030L
64 #define UVD_PGFSM_STATUS__UVDC_PWR_STATUS_MASK                                                                0x000000C0L
65 #define UVD_PGFSM_STATUS__UVDB_PWR_STATUS_MASK                                                                0x00000300L
66 #define UVD_PGFSM_STATUS__UVDIL_PWR_STATUS_MASK                                                               0x00000C00L
67 #define UVD_PGFSM_STATUS__UVDIR_PWR_STATUS_MASK                                                               0x00003000L
68 #define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS_MASK                                                               0x0000C000L
69 #define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS_MASK                                                               0x00030000L
70 #define UVD_PGFSM_STATUS__UVDE_PWR_STATUS_MASK                                                                0x000C0000L
71 #define UVD_PGFSM_STATUS__UVDW_PWR_STATUS_MASK                                                                0x00300000L
72 //UVD_POWER_STATUS
73 #define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT                                                             0x0
74 #define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT                                                                  0x2
75 #define UVD_POWER_STATUS__UVD_CG_MODE__SHIFT                                                                  0x4
76 #define UVD_POWER_STATUS__UVD_PG_EN__SHIFT                                                                    0x8
77 #define UVD_POWER_STATUS__RBC_SNOOP_DIS__SHIFT                                                                0x9
78 #define UVD_POWER_STATUS__JRBC_SNOOP_DIS__SHIFT                                                               0xa
79 #define UVD_POWER_STATUS__SW_RB_SNOOP_DIS__SHIFT                                                              0xb
80 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK                                                               0x00000003L
81 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK                                                                    0x00000004L
82 #define UVD_POWER_STATUS__UVD_CG_MODE_MASK                                                                    0x00000030L
83 #define UVD_POWER_STATUS__UVD_PG_EN_MASK                                                                      0x00000100L
84 #define UVD_POWER_STATUS__RBC_SNOOP_DIS_MASK                                                                  0x00000200L
85 #define UVD_POWER_STATUS__JRBC_SNOOP_DIS_MASK                                                                 0x00000400L
86 #define UVD_POWER_STATUS__SW_RB_SNOOP_DIS_MASK                                                                0x00000800L
87 //CC_UVD_HARVESTING
88 #define CC_UVD_HARVESTING__UVD_DISABLE__SHIFT                                                                 0x1
89 #define CC_UVD_HARVESTING__UVD_DISABLE_MASK                                                                   0x00000002L
90 //UVD_DPG_LMA_CTL
91 #define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT                                                                    0x0
92 #define UVD_DPG_LMA_CTL__MASK_EN__SHIFT                                                                       0x1
93 #define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT__SHIFT                                                           0x2
94 #define UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT                                                                      0x4
95 #define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT                                                               0x10
96 #define UVD_DPG_LMA_CTL__READ_WRITE_MASK                                                                      0x00000001L
97 #define UVD_DPG_LMA_CTL__MASK_EN_MASK                                                                         0x00000002L
98 #define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT_MASK                                                             0x00000004L
99 #define UVD_DPG_LMA_CTL__SRAM_SEL_MASK                                                                        0x00000010L
100 #define UVD_DPG_LMA_CTL__READ_WRITE_ADDR_MASK                                                                 0xFFFF0000L
101 //UVD_DPG_PAUSE
102 #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ__SHIFT                                                              0x0
103 #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK__SHIFT                                                              0x1
104 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ__SHIFT                                                                0x2
105 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK__SHIFT                                                                0x3
106 #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK                                                                0x00000001L
107 #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK                                                                0x00000002L
108 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK                                                                  0x00000004L
109 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK                                                                  0x00000008L
110 //UVD_SCRATCH1
111 #define UVD_SCRATCH1__SCRATCH1_DATA__SHIFT                                                                    0x0
112 #define UVD_SCRATCH1__SCRATCH1_DATA_MASK                                                                      0xFFFFFFFFL
113 //UVD_SCRATCH2
114 #define UVD_SCRATCH2__SCRATCH2_DATA__SHIFT                                                                    0x0
115 #define UVD_SCRATCH2__SCRATCH2_DATA_MASK                                                                      0xFFFFFFFFL
116 //UVD_SCRATCH3
117 #define UVD_SCRATCH3__SCRATCH3_DATA__SHIFT                                                                    0x0
118 #define UVD_SCRATCH3__SCRATCH3_DATA_MASK                                                                      0xFFFFFFFFL
119 //UVD_SCRATCH4
120 #define UVD_SCRATCH4__SCRATCH4_DATA__SHIFT                                                                    0x0
121 #define UVD_SCRATCH4__SCRATCH4_DATA_MASK                                                                      0xFFFFFFFFL
122 //UVD_SCRATCH5
123 #define UVD_SCRATCH5__SCRATCH5_DATA__SHIFT                                                                    0x0
124 #define UVD_SCRATCH5__SCRATCH5_DATA_MASK                                                                      0xFFFFFFFFL
125 //UVD_SCRATCH6
126 #define UVD_SCRATCH6__SCRATCH6_DATA__SHIFT                                                                    0x0
127 #define UVD_SCRATCH6__SCRATCH6_DATA_MASK                                                                      0xFFFFFFFFL
128 //UVD_SCRATCH7
129 #define UVD_SCRATCH7__SCRATCH7_DATA__SHIFT                                                                    0x0
130 #define UVD_SCRATCH7__SCRATCH7_DATA_MASK                                                                      0xFFFFFFFFL
131 //UVD_SCRATCH8
132 #define UVD_SCRATCH8__SCRATCH8_DATA__SHIFT                                                                    0x0
133 #define UVD_SCRATCH8__SCRATCH8_DATA_MASK                                                                      0xFFFFFFFFL
134 //UVD_SCRATCH9
135 #define UVD_SCRATCH9__SCRATCH9_DATA__SHIFT                                                                    0x0
136 #define UVD_SCRATCH9__SCRATCH9_DATA_MASK                                                                      0xFFFFFFFFL
137 //UVD_SCRATCH10
138 #define UVD_SCRATCH10__SCRATCH10_DATA__SHIFT                                                                  0x0
139 #define UVD_SCRATCH10__SCRATCH10_DATA_MASK                                                                    0xFFFFFFFFL
140 //UVD_SCRATCH11
141 #define UVD_SCRATCH11__SCRATCH11_DATA__SHIFT                                                                  0x0
142 #define UVD_SCRATCH11__SCRATCH11_DATA_MASK                                                                    0xFFFFFFFFL
143 //UVD_SCRATCH12
144 #define UVD_SCRATCH12__SCRATCH12_DATA__SHIFT                                                                  0x0
145 #define UVD_SCRATCH12__SCRATCH12_DATA_MASK                                                                    0xFFFFFFFFL
146 //UVD_SCRATCH13
147 #define UVD_SCRATCH13__SCRATCH13_DATA__SHIFT                                                                  0x0
148 #define UVD_SCRATCH13__SCRATCH13_DATA_MASK                                                                    0xFFFFFFFFL
149 //UVD_SCRATCH14
150 #define UVD_SCRATCH14__SCRATCH14_DATA__SHIFT                                                                  0x0
151 #define UVD_SCRATCH14__SCRATCH14_DATA_MASK                                                                    0xFFFFFFFFL
152 //UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW
153 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                0x0
154 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK                                                  0xFFFFFFFFL
155 //UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH
156 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                              0x0
157 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK                                                0xFFFFFFFFL
158 //UVD_DPG_VCPU_CACHE_OFFSET0
159 #define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT                                                      0x0
160 #define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK                                                        0x01FFFFFFL
161
162
163 // addressBlock: uvd_uvdgendec
164 //UVD_LCM_CGC_CNTRL
165 #define UVD_LCM_CGC_CNTRL__FORCE_OFF__SHIFT                                                                   0x12
166 #define UVD_LCM_CGC_CNTRL__FORCE_ON__SHIFT                                                                    0x13
167 #define UVD_LCM_CGC_CNTRL__OFF_DELAY__SHIFT                                                                   0x14
168 #define UVD_LCM_CGC_CNTRL__ON_DELAY__SHIFT                                                                    0x1c
169 #define UVD_LCM_CGC_CNTRL__FORCE_OFF_MASK                                                                     0x00040000L
170 #define UVD_LCM_CGC_CNTRL__FORCE_ON_MASK                                                                      0x00080000L
171 #define UVD_LCM_CGC_CNTRL__OFF_DELAY_MASK                                                                     0x0FF00000L
172 #define UVD_LCM_CGC_CNTRL__ON_DELAY_MASK                                                                      0xF0000000L
173
174
175 // addressBlock: uvd_uvdnpdec
176 //UVD_JPEG_CNTL
177 #define UVD_JPEG_CNTL__SOFT_RESET__SHIFT                                                                      0x0
178 #define UVD_JPEG_CNTL__REQUEST_EN__SHIFT                                                                      0x1
179 #define UVD_JPEG_CNTL__ERR_RST_EN__SHIFT                                                                      0x2
180 #define UVD_JPEG_CNTL__HUFF_SPEED_EN__SHIFT                                                                   0x3
181 #define UVD_JPEG_CNTL__HUFF_SPEED_STATUS__SHIFT                                                               0x4
182 #define UVD_JPEG_CNTL__DBG_MUX_SEL__SHIFT                                                                     0x8
183 #define UVD_JPEG_CNTL__SOFT_RESET_MASK                                                                        0x00000001L
184 #define UVD_JPEG_CNTL__REQUEST_EN_MASK                                                                        0x00000002L
185 #define UVD_JPEG_CNTL__ERR_RST_EN_MASK                                                                        0x00000004L
186 #define UVD_JPEG_CNTL__HUFF_SPEED_EN_MASK                                                                     0x00000008L
187 #define UVD_JPEG_CNTL__HUFF_SPEED_STATUS_MASK                                                                 0x00000010L
188 #define UVD_JPEG_CNTL__DBG_MUX_SEL_MASK                                                                       0x00007F00L
189 //UVD_JPEG_RB_BASE
190 #define UVD_JPEG_RB_BASE__RB_BYTE_OFF__SHIFT                                                                  0x0
191 #define UVD_JPEG_RB_BASE__RB_BASE__SHIFT                                                                      0x6
192 #define UVD_JPEG_RB_BASE__RB_BYTE_OFF_MASK                                                                    0x0000003FL
193 #define UVD_JPEG_RB_BASE__RB_BASE_MASK                                                                        0xFFFFFFC0L
194 //UVD_JPEG_RB_WPTR
195 #define UVD_JPEG_RB_WPTR__RB_WPTR__SHIFT                                                                      0x4
196 #define UVD_JPEG_RB_WPTR__RB_WPTR_MASK                                                                        0x3FFFFFF0L
197 //UVD_JPEG_RB_RPTR
198 #define UVD_JPEG_RB_RPTR__RB_RPTR__SHIFT                                                                      0x4
199 #define UVD_JPEG_RB_RPTR__RB_RPTR_MASK                                                                        0x3FFFFFF0L
200 //UVD_JPEG_RB_SIZE
201 #define UVD_JPEG_RB_SIZE__RB_SIZE__SHIFT                                                                      0x4
202 #define UVD_JPEG_RB_SIZE__RB_SIZE_MASK                                                                        0x3FFFFFF0L
203 //UVD_JPEG_ADDR_CONFIG
204 #define UVD_JPEG_ADDR_CONFIG__NUM_PIPES__SHIFT                                                                0x0
205 #define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                     0x3
206 #define UVD_JPEG_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                     0x6
207 #define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT                                                     0x8
208 #define UVD_JPEG_ADDR_CONFIG__NUM_BANKS__SHIFT                                                                0xc
209 #define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT                                                  0x10
210 #define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT                                                       0x13
211 #define UVD_JPEG_ADDR_CONFIG__NUM_GPUS__SHIFT                                                                 0x15
212 #define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT                                                      0x18
213 #define UVD_JPEG_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT                                                            0x1a
214 #define UVD_JPEG_ADDR_CONFIG__ROW_SIZE__SHIFT                                                                 0x1c
215 #define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT                                                          0x1e
216 #define UVD_JPEG_ADDR_CONFIG__SE_ENABLE__SHIFT                                                                0x1f
217 #define UVD_JPEG_ADDR_CONFIG__NUM_PIPES_MASK                                                                  0x00000007L
218 #define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                       0x00000038L
219 #define UVD_JPEG_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                       0x000000C0L
220 #define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK                                                       0x00000700L
221 #define UVD_JPEG_ADDR_CONFIG__NUM_BANKS_MASK                                                                  0x00007000L
222 #define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK                                                    0x00070000L
223 #define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK                                                         0x00180000L
224 #define UVD_JPEG_ADDR_CONFIG__NUM_GPUS_MASK                                                                   0x00E00000L
225 #define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK                                                        0x03000000L
226 #define UVD_JPEG_ADDR_CONFIG__NUM_RB_PER_SE_MASK                                                              0x0C000000L
227 #define UVD_JPEG_ADDR_CONFIG__ROW_SIZE_MASK                                                                   0x30000000L
228 #define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES_MASK                                                            0x40000000L
229 #define UVD_JPEG_ADDR_CONFIG__SE_ENABLE_MASK                                                                  0x80000000L
230 //UVD_JPEG_GPCOM_CMD
231 #define UVD_JPEG_GPCOM_CMD__CMD_SEND__SHIFT                                                                   0x0
232 #define UVD_JPEG_GPCOM_CMD__CMD__SHIFT                                                                        0x1
233 #define UVD_JPEG_GPCOM_CMD__CMD_SOURCE__SHIFT                                                                 0x1f
234 #define UVD_JPEG_GPCOM_CMD__CMD_SEND_MASK                                                                     0x00000001L
235 #define UVD_JPEG_GPCOM_CMD__CMD_MASK                                                                          0x7FFFFFFEL
236 #define UVD_JPEG_GPCOM_CMD__CMD_SOURCE_MASK                                                                   0x80000000L
237 //UVD_JPEG_GPCOM_DATA0
238 #define UVD_JPEG_GPCOM_DATA0__DATA0__SHIFT                                                                    0x0
239 #define UVD_JPEG_GPCOM_DATA0__DATA0_MASK                                                                      0xFFFFFFFFL
240 //UVD_JPEG_GPCOM_DATA1
241 #define UVD_JPEG_GPCOM_DATA1__DATA1__SHIFT                                                                    0x0
242 #define UVD_JPEG_GPCOM_DATA1__DATA1_MASK                                                                      0xFFFFFFFFL
243 //UVD_JPEG_JRB_BASE_LO
244 #define UVD_JPEG_JRB_BASE_LO__JRB_BASE_LO__SHIFT                                                              0x6
245 #define UVD_JPEG_JRB_BASE_LO__JRB_BASE_LO_MASK                                                                0xFFFFFFC0L
246 //UVD_JPEG_JRB_BASE_HI
247 #define UVD_JPEG_JRB_BASE_HI__JRB_BASE_HI__SHIFT                                                              0x0
248 #define UVD_JPEG_JRB_BASE_HI__JRB_BASE_HI_MASK                                                                0xFFFFFFFFL
249 //UVD_JPEG_JRB_SIZE
250 #define UVD_JPEG_JRB_SIZE__JRB_SIZE__SHIFT                                                                    0x4
251 #define UVD_JPEG_JRB_SIZE__JRB_SIZE_MASK                                                                      0x007FFFF0L
252 //UVD_JPEG_JRB_RPTR
253 #define UVD_JPEG_JRB_RPTR__JRB_RPTR__SHIFT                                                                    0x4
254 #define UVD_JPEG_JRB_RPTR__JRB_RPTR_MASK                                                                      0x007FFFF0L
255 //UVD_JPEG_JRB_WPTR
256 #define UVD_JPEG_JRB_WPTR__JRB_WPTR__SHIFT                                                                    0x4
257 #define UVD_JPEG_JRB_WPTR__JRB_WPTR_MASK                                                                      0x007FFFF0L
258 //UVD_JPEG_UV_ADDR_CONFIG
259 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_PIPES__SHIFT                                                             0x0
260 #define UVD_JPEG_UV_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                  0x3
261 #define UVD_JPEG_UV_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                  0x6
262 #define UVD_JPEG_UV_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT                                                  0x8
263 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_BANKS__SHIFT                                                             0xc
264 #define UVD_JPEG_UV_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT                                               0x10
265 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT                                                    0x13
266 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_GPUS__SHIFT                                                              0x15
267 #define UVD_JPEG_UV_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT                                                   0x18
268 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT                                                         0x1a
269 #define UVD_JPEG_UV_ADDR_CONFIG__ROW_SIZE__SHIFT                                                              0x1c
270 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT                                                       0x1e
271 #define UVD_JPEG_UV_ADDR_CONFIG__SE_ENABLE__SHIFT                                                             0x1f
272 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_PIPES_MASK                                                               0x00000007L
273 #define UVD_JPEG_UV_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                    0x00000038L
274 #define UVD_JPEG_UV_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                    0x000000C0L
275 #define UVD_JPEG_UV_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK                                                    0x00000700L
276 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_BANKS_MASK                                                               0x00007000L
277 #define UVD_JPEG_UV_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK                                                 0x00070000L
278 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK                                                      0x00180000L
279 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_GPUS_MASK                                                                0x00E00000L
280 #define UVD_JPEG_UV_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK                                                     0x03000000L
281 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_RB_PER_SE_MASK                                                           0x0C000000L
282 #define UVD_JPEG_UV_ADDR_CONFIG__ROW_SIZE_MASK                                                                0x30000000L
283 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_LOWER_PIPES_MASK                                                         0x40000000L
284 #define UVD_JPEG_UV_ADDR_CONFIG__SE_ENABLE_MASK                                                               0x80000000L
285 //UVD_SEMA_ADDR_LOW
286 #define UVD_SEMA_ADDR_LOW__ADDR_26_3__SHIFT                                                                   0x0
287 #define UVD_SEMA_ADDR_LOW__ADDR_26_3_MASK                                                                     0x00FFFFFFL
288 //UVD_SEMA_ADDR_HIGH
289 #define UVD_SEMA_ADDR_HIGH__ADDR_47_27__SHIFT                                                                 0x0
290 #define UVD_SEMA_ADDR_HIGH__ADDR_47_27_MASK                                                                   0x001FFFFFL
291 //UVD_SEMA_CMD
292 #define UVD_SEMA_CMD__REQ_CMD__SHIFT                                                                          0x0
293 #define UVD_SEMA_CMD__WR_PHASE__SHIFT                                                                         0x4
294 #define UVD_SEMA_CMD__MODE__SHIFT                                                                             0x6
295 #define UVD_SEMA_CMD__VMID_EN__SHIFT                                                                          0x7
296 #define UVD_SEMA_CMD__VMID__SHIFT                                                                             0x8
297 #define UVD_SEMA_CMD__REQ_CMD_MASK                                                                            0x0000000FL
298 #define UVD_SEMA_CMD__WR_PHASE_MASK                                                                           0x00000030L
299 #define UVD_SEMA_CMD__MODE_MASK                                                                               0x00000040L
300 #define UVD_SEMA_CMD__VMID_EN_MASK                                                                            0x00000080L
301 #define UVD_SEMA_CMD__VMID_MASK                                                                               0x00000F00L
302 //UVD_GPCOM_VCPU_CMD
303 #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT                                                                   0x0
304 #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT                                                                        0x1
305 #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT                                                                 0x1f
306 #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK                                                                     0x00000001L
307 #define UVD_GPCOM_VCPU_CMD__CMD_MASK                                                                          0x7FFFFFFEL
308 #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK                                                                   0x80000000L
309 //UVD_GPCOM_VCPU_DATA0
310 #define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT                                                                    0x0
311 #define UVD_GPCOM_VCPU_DATA0__DATA0_MASK                                                                      0xFFFFFFFFL
312 //UVD_GPCOM_VCPU_DATA1
313 #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT                                                                    0x0
314 #define UVD_GPCOM_VCPU_DATA1__DATA1_MASK                                                                      0xFFFFFFFFL
315 //UVD_UDEC_DBW_UV_ADDR_CONFIG
316 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_PIPES__SHIFT                                                         0x0
317 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                              0x3
318 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                              0x6
319 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT                                              0x8
320 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_BANKS__SHIFT                                                         0xc
321 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT                                           0x10
322 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT                                                0x13
323 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_GPUS__SHIFT                                                          0x15
324 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT                                               0x18
325 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT                                                     0x1a
326 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__ROW_SIZE__SHIFT                                                          0x1c
327 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT                                                   0x1e
328 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__SE_ENABLE__SHIFT                                                         0x1f
329 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_PIPES_MASK                                                           0x00000007L
330 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                0x00000038L
331 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                0x000000C0L
332 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK                                                0x00000700L
333 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_BANKS_MASK                                                           0x00007000L
334 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK                                             0x00070000L
335 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK                                                  0x00180000L
336 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_GPUS_MASK                                                            0x00E00000L
337 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK                                                 0x03000000L
338 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_RB_PER_SE_MASK                                                       0x0C000000L
339 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__ROW_SIZE_MASK                                                            0x30000000L
340 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_LOWER_PIPES_MASK                                                     0x40000000L
341 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__SE_ENABLE_MASK                                                           0x80000000L
342 //UVD_UDEC_ADDR_CONFIG
343 #define UVD_UDEC_ADDR_CONFIG__NUM_PIPES__SHIFT                                                                0x0
344 #define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                     0x3
345 #define UVD_UDEC_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                     0x6
346 #define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT                                                     0x8
347 #define UVD_UDEC_ADDR_CONFIG__NUM_BANKS__SHIFT                                                                0xc
348 #define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT                                                  0x10
349 #define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT                                                       0x13
350 #define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT                                                                 0x15
351 #define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT                                                      0x18
352 #define UVD_UDEC_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT                                                            0x1a
353 #define UVD_UDEC_ADDR_CONFIG__ROW_SIZE__SHIFT                                                                 0x1c
354 #define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT                                                          0x1e
355 #define UVD_UDEC_ADDR_CONFIG__SE_ENABLE__SHIFT                                                                0x1f
356 #define UVD_UDEC_ADDR_CONFIG__NUM_PIPES_MASK                                                                  0x00000007L
357 #define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                       0x00000038L
358 #define UVD_UDEC_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                       0x000000C0L
359 #define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK                                                       0x00000700L
360 #define UVD_UDEC_ADDR_CONFIG__NUM_BANKS_MASK                                                                  0x00007000L
361 #define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK                                                    0x00070000L
362 #define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK                                                         0x00180000L
363 #define UVD_UDEC_ADDR_CONFIG__NUM_GPUS_MASK                                                                   0x00E00000L
364 #define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK                                                        0x03000000L
365 #define UVD_UDEC_ADDR_CONFIG__NUM_RB_PER_SE_MASK                                                              0x0C000000L
366 #define UVD_UDEC_ADDR_CONFIG__ROW_SIZE_MASK                                                                   0x30000000L
367 #define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES_MASK                                                            0x40000000L
368 #define UVD_UDEC_ADDR_CONFIG__SE_ENABLE_MASK                                                                  0x80000000L
369 //UVD_UDEC_DB_ADDR_CONFIG
370 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES__SHIFT                                                             0x0
371 #define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                  0x3
372 #define UVD_UDEC_DB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                  0x6
373 #define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT                                                  0x8
374 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_BANKS__SHIFT                                                             0xc
375 #define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT                                               0x10
376 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT                                                    0x13
377 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT                                                              0x15
378 #define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT                                                   0x18
379 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT                                                         0x1a
380 #define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE__SHIFT                                                              0x1c
381 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT                                                       0x1e
382 #define UVD_UDEC_DB_ADDR_CONFIG__SE_ENABLE__SHIFT                                                             0x1f
383 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES_MASK                                                               0x00000007L
384 #define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                    0x00000038L
385 #define UVD_UDEC_DB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                    0x000000C0L
386 #define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK                                                    0x00000700L
387 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_BANKS_MASK                                                               0x00007000L
388 #define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK                                                 0x00070000L
389 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK                                                      0x00180000L
390 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS_MASK                                                                0x00E00000L
391 #define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK                                                     0x03000000L
392 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_RB_PER_SE_MASK                                                           0x0C000000L
393 #define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE_MASK                                                                0x30000000L
394 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK                                                         0x40000000L
395 #define UVD_UDEC_DB_ADDR_CONFIG__SE_ENABLE_MASK                                                               0x80000000L
396 //UVD_UDEC_DBW_ADDR_CONFIG
397 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0
398 #define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                 0x3
399 #define UVD_UDEC_DBW_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0x6
400 #define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT                                                 0x8
401 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_BANKS__SHIFT                                                            0xc
402 #define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT                                              0x10
403 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT                                                   0x13
404 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT                                                             0x15
405 #define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT                                                  0x18
406 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT                                                        0x1a
407 #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE__SHIFT                                                             0x1c
408 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT                                                      0x1e
409 #define UVD_UDEC_DBW_ADDR_CONFIG__SE_ENABLE__SHIFT                                                            0x1f
410 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L
411 #define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                   0x00000038L
412 #define UVD_UDEC_DBW_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x000000C0L
413 #define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK                                                   0x00000700L
414 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_BANKS_MASK                                                              0x00007000L
415 #define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK                                                0x00070000L
416 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK                                                     0x00180000L
417 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK                                                               0x00E00000L
418 #define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK                                                    0x03000000L
419 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_RB_PER_SE_MASK                                                          0x0C000000L
420 #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK                                                               0x30000000L
421 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES_MASK                                                        0x40000000L
422 #define UVD_UDEC_DBW_ADDR_CONFIG__SE_ENABLE_MASK                                                              0x80000000L
423 //UVD_SUVD_CGC_GATE
424 #define UVD_SUVD_CGC_GATE__SRE__SHIFT                                                                         0x0
425 #define UVD_SUVD_CGC_GATE__SIT__SHIFT                                                                         0x1
426 #define UVD_SUVD_CGC_GATE__SMP__SHIFT                                                                         0x2
427 #define UVD_SUVD_CGC_GATE__SCM__SHIFT                                                                         0x3
428 #define UVD_SUVD_CGC_GATE__SDB__SHIFT                                                                         0x4
429 #define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT                                                                    0x5
430 #define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT                                                                    0x6
431 #define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT                                                                    0x7
432 #define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT                                                                    0x8
433 #define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT                                                                    0x9
434 #define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT                                                                    0xa
435 #define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT                                                                    0xb
436 #define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT                                                                    0xc
437 #define UVD_SUVD_CGC_GATE__SCLR__SHIFT                                                                        0xd
438 #define UVD_SUVD_CGC_GATE__UVD_SC__SHIFT                                                                      0xe
439 #define UVD_SUVD_CGC_GATE__ENT__SHIFT                                                                         0xf
440 #define UVD_SUVD_CGC_GATE__IME__SHIFT                                                                         0x10
441 #define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT                                                                0x11
442 #define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT                                                                0x12
443 #define UVD_SUVD_CGC_GATE__SITE__SHIFT                                                                        0x13
444 #define UVD_SUVD_CGC_GATE__SRE_VP9__SHIFT                                                                     0x14
445 #define UVD_SUVD_CGC_GATE__SCM_VP9__SHIFT                                                                     0x15
446 #define UVD_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT                                                                 0x16
447 #define UVD_SUVD_CGC_GATE__SDB_VP9__SHIFT                                                                     0x17
448 #define UVD_SUVD_CGC_GATE__IME_HEVC__SHIFT                                                                    0x18
449 #define UVD_SUVD_CGC_GATE__SRE_MASK                                                                           0x00000001L
450 #define UVD_SUVD_CGC_GATE__SIT_MASK                                                                           0x00000002L
451 #define UVD_SUVD_CGC_GATE__SMP_MASK                                                                           0x00000004L
452 #define UVD_SUVD_CGC_GATE__SCM_MASK                                                                           0x00000008L
453 #define UVD_SUVD_CGC_GATE__SDB_MASK                                                                           0x00000010L
454 #define UVD_SUVD_CGC_GATE__SRE_H264_MASK                                                                      0x00000020L
455 #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK                                                                      0x00000040L
456 #define UVD_SUVD_CGC_GATE__SIT_H264_MASK                                                                      0x00000080L
457 #define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK                                                                      0x00000100L
458 #define UVD_SUVD_CGC_GATE__SCM_H264_MASK                                                                      0x00000200L
459 #define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK                                                                      0x00000400L
460 #define UVD_SUVD_CGC_GATE__SDB_H264_MASK                                                                      0x00000800L
461 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK                                                                      0x00001000L
462 #define UVD_SUVD_CGC_GATE__SCLR_MASK                                                                          0x00002000L
463 #define UVD_SUVD_CGC_GATE__UVD_SC_MASK                                                                        0x00004000L
464 #define UVD_SUVD_CGC_GATE__ENT_MASK                                                                           0x00008000L
465 #define UVD_SUVD_CGC_GATE__IME_MASK                                                                           0x00010000L
466 #define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK                                                                  0x00020000L
467 #define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK                                                                  0x00040000L
468 #define UVD_SUVD_CGC_GATE__SITE_MASK                                                                          0x00080000L
469 #define UVD_SUVD_CGC_GATE__SRE_VP9_MASK                                                                       0x00100000L
470 #define UVD_SUVD_CGC_GATE__SCM_VP9_MASK                                                                       0x00200000L
471 #define UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK                                                                   0x00400000L
472 #define UVD_SUVD_CGC_GATE__SDB_VP9_MASK                                                                       0x00800000L
473 #define UVD_SUVD_CGC_GATE__IME_HEVC_MASK                                                                      0x01000000L
474 //UVD_SUVD_CGC_STATUS
475 #define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT                                                                  0x0
476 #define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT                                                                  0x1
477 #define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT                                                                  0x2
478 #define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT                                                                  0x3
479 #define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT                                                                  0x4
480 #define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT                                                                  0x5
481 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT                                                             0x6
482 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT                                                             0x7
483 #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT                                                             0x8
484 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT                                                             0x9
485 #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT                                                             0xa
486 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT                                                             0xb
487 #define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT                                                             0xc
488 #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT                                                             0xd
489 #define UVD_SUVD_CGC_STATUS__SCLR_DCLK__SHIFT                                                                 0xe
490 #define UVD_SUVD_CGC_STATUS__UVD_SC__SHIFT                                                                    0xf
491 #define UVD_SUVD_CGC_STATUS__ENT_DCLK__SHIFT                                                                  0x10
492 #define UVD_SUVD_CGC_STATUS__IME_DCLK__SHIFT                                                                  0x11
493 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK__SHIFT                                                         0x12
494 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK__SHIFT                                                         0x13
495 #define UVD_SUVD_CGC_STATUS__SITE_DCLK__SHIFT                                                                 0x14
496 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK__SHIFT                                                            0x15
497 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK__SHIFT                                                        0x16
498 #define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK__SHIFT                                                              0x17
499 #define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK__SHIFT                                                              0x18
500 #define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK__SHIFT                                                          0x19
501 #define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK__SHIFT                                                              0x1a
502 #define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK__SHIFT                                                             0x1b
503 #define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK                                                                    0x00000001L
504 #define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK                                                                    0x00000002L
505 #define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK                                                                    0x00000004L
506 #define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK                                                                    0x00000008L
507 #define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK                                                                    0x00000010L
508 #define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK                                                                    0x00000020L
509 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK                                                               0x00000040L
510 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK                                                               0x00000080L
511 #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK                                                               0x00000100L
512 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK                                                               0x00000200L
513 #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK                                                               0x00000400L
514 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK                                                               0x00000800L
515 #define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK                                                               0x00001000L
516 #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK                                                               0x00002000L
517 #define UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK                                                                   0x00004000L
518 #define UVD_SUVD_CGC_STATUS__UVD_SC_MASK                                                                      0x00008000L
519 #define UVD_SUVD_CGC_STATUS__ENT_DCLK_MASK                                                                    0x00010000L
520 #define UVD_SUVD_CGC_STATUS__IME_DCLK_MASK                                                                    0x00020000L
521 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK_MASK                                                           0x00040000L
522 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK_MASK                                                           0x00080000L
523 #define UVD_SUVD_CGC_STATUS__SITE_DCLK_MASK                                                                   0x00100000L
524 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK_MASK                                                              0x00200000L
525 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK_MASK                                                          0x00400000L
526 #define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK_MASK                                                                0x00800000L
527 #define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK_MASK                                                                0x01000000L
528 #define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK_MASK                                                            0x02000000L
529 #define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK_MASK                                                                0x04000000L
530 #define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK_MASK                                                               0x08000000L
531 //UVD_SUVD_CGC_CTRL
532 #define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT                                                                    0x0
533 #define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT                                                                    0x1
534 #define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT                                                                    0x2
535 #define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT                                                                    0x3
536 #define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT                                                                    0x4
537 #define UVD_SUVD_CGC_CTRL__SCLR_MODE__SHIFT                                                                   0x5
538 #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT                                                                 0x6
539 #define UVD_SUVD_CGC_CTRL__ENT_MODE__SHIFT                                                                    0x7
540 #define UVD_SUVD_CGC_CTRL__IME_MODE__SHIFT                                                                    0x8
541 #define UVD_SUVD_CGC_CTRL__SITE_MODE__SHIFT                                                                   0x9
542 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK                                                                      0x00000001L
543 #define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK                                                                      0x00000002L
544 #define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK                                                                      0x00000004L
545 #define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK                                                                      0x00000008L
546 #define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK                                                                      0x00000010L
547 #define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK                                                                     0x00000020L
548 #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK                                                                   0x00000040L
549 #define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK                                                                      0x00000080L
550 #define UVD_SUVD_CGC_CTRL__IME_MODE_MASK                                                                      0x00000100L
551 #define UVD_SUVD_CGC_CTRL__SITE_MODE_MASK                                                                     0x00000200L
552 //UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW
553 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                   0x0
554 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0_MASK                                                     0xFFFFFFFFL
555 //UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH
556 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                 0x0
557 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32_MASK                                                   0xFFFFFFFFL
558 //UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW
559 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                   0x0
560 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0_MASK                                                     0xFFFFFFFFL
561 //UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH
562 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                 0x0
563 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32_MASK                                                   0xFFFFFFFFL
564 //UVD_NO_OP
565 #define UVD_NO_OP__NO_OP__SHIFT                                                                               0x0
566 #define UVD_NO_OP__NO_OP_MASK                                                                                 0xFFFFFFFFL
567 //UVD_VERSION
568 #define UVD_VERSION__MINOR_VERSION__SHIFT                                                                     0x0
569 #define UVD_VERSION__MAJOR_VERSION__SHIFT                                                                     0x10
570 #define UVD_VERSION__MINOR_VERSION_MASK                                                                       0x0000FFFFL
571 #define UVD_VERSION__MAJOR_VERSION_MASK                                                                       0xFFFF0000L
572 //UVD_GP_SCRATCH8
573 #define UVD_GP_SCRATCH8__DATA__SHIFT                                                                          0x0
574 #define UVD_GP_SCRATCH8__DATA_MASK                                                                            0xFFFFFFFFL
575 //UVD_GP_SCRATCH9
576 #define UVD_GP_SCRATCH9__DATA__SHIFT                                                                          0x0
577 #define UVD_GP_SCRATCH9__DATA_MASK                                                                            0xFFFFFFFFL
578 //UVD_GP_SCRATCH10
579 #define UVD_GP_SCRATCH10__DATA__SHIFT                                                                         0x0
580 #define UVD_GP_SCRATCH10__DATA_MASK                                                                           0xFFFFFFFFL
581 //UVD_GP_SCRATCH11
582 #define UVD_GP_SCRATCH11__DATA__SHIFT                                                                         0x0
583 #define UVD_GP_SCRATCH11__DATA_MASK                                                                           0xFFFFFFFFL
584 //UVD_GP_SCRATCH12
585 #define UVD_GP_SCRATCH12__DATA__SHIFT                                                                         0x0
586 #define UVD_GP_SCRATCH12__DATA_MASK                                                                           0xFFFFFFFFL
587 //UVD_GP_SCRATCH13
588 #define UVD_GP_SCRATCH13__DATA__SHIFT                                                                         0x0
589 #define UVD_GP_SCRATCH13__DATA_MASK                                                                           0xFFFFFFFFL
590 //UVD_GP_SCRATCH14
591 #define UVD_GP_SCRATCH14__DATA__SHIFT                                                                         0x0
592 #define UVD_GP_SCRATCH14__DATA_MASK                                                                           0xFFFFFFFFL
593 //UVD_GP_SCRATCH15
594 #define UVD_GP_SCRATCH15__DATA__SHIFT                                                                         0x0
595 #define UVD_GP_SCRATCH15__DATA_MASK                                                                           0xFFFFFFFFL
596 //UVD_GP_SCRATCH16
597 #define UVD_GP_SCRATCH16__DATA__SHIFT                                                                         0x0
598 #define UVD_GP_SCRATCH16__DATA_MASK                                                                           0xFFFFFFFFL
599 //UVD_GP_SCRATCH17
600 #define UVD_GP_SCRATCH17__DATA__SHIFT                                                                         0x0
601 #define UVD_GP_SCRATCH17__DATA_MASK                                                                           0xFFFFFFFFL
602 //UVD_GP_SCRATCH18
603 #define UVD_GP_SCRATCH18__DATA__SHIFT                                                                         0x0
604 #define UVD_GP_SCRATCH18__DATA_MASK                                                                           0xFFFFFFFFL
605 //UVD_GP_SCRATCH19
606 #define UVD_GP_SCRATCH19__DATA__SHIFT                                                                         0x0
607 #define UVD_GP_SCRATCH19__DATA_MASK                                                                           0xFFFFFFFFL
608 //UVD_GP_SCRATCH20
609 #define UVD_GP_SCRATCH20__DATA__SHIFT                                                                         0x0
610 #define UVD_GP_SCRATCH20__DATA_MASK                                                                           0xFFFFFFFFL
611 //UVD_GP_SCRATCH21
612 #define UVD_GP_SCRATCH21__DATA__SHIFT                                                                         0x0
613 #define UVD_GP_SCRATCH21__DATA_MASK                                                                           0xFFFFFFFFL
614 //UVD_GP_SCRATCH22
615 #define UVD_GP_SCRATCH22__DATA__SHIFT                                                                         0x0
616 #define UVD_GP_SCRATCH22__DATA_MASK                                                                           0xFFFFFFFFL
617 //UVD_GP_SCRATCH23
618 #define UVD_GP_SCRATCH23__DATA__SHIFT                                                                         0x0
619 #define UVD_GP_SCRATCH23__DATA_MASK                                                                           0xFFFFFFFFL
620 //UVD_RB_BASE_LO2
621 #define UVD_RB_BASE_LO2__RB_BASE_LO__SHIFT                                                                    0x6
622 #define UVD_RB_BASE_LO2__RB_BASE_LO_MASK                                                                      0xFFFFFFC0L
623 //UVD_RB_BASE_HI2
624 #define UVD_RB_BASE_HI2__RB_BASE_HI__SHIFT                                                                    0x0
625 #define UVD_RB_BASE_HI2__RB_BASE_HI_MASK                                                                      0xFFFFFFFFL
626 //UVD_RB_SIZE2
627 #define UVD_RB_SIZE2__RB_SIZE__SHIFT                                                                          0x4
628 #define UVD_RB_SIZE2__RB_SIZE_MASK                                                                            0x007FFFF0L
629 //UVD_RB_RPTR2
630 #define UVD_RB_RPTR2__RB_RPTR__SHIFT                                                                          0x4
631 #define UVD_RB_RPTR2__RB_RPTR_MASK                                                                            0x007FFFF0L
632 //UVD_RB_WPTR2
633 #define UVD_RB_WPTR2__RB_WPTR__SHIFT                                                                          0x4
634 #define UVD_RB_WPTR2__RB_WPTR_MASK                                                                            0x007FFFF0L
635 //UVD_RB_BASE_LO
636 #define UVD_RB_BASE_LO__RB_BASE_LO__SHIFT                                                                     0x6
637 #define UVD_RB_BASE_LO__RB_BASE_LO_MASK                                                                       0xFFFFFFC0L
638 //UVD_RB_BASE_HI
639 #define UVD_RB_BASE_HI__RB_BASE_HI__SHIFT                                                                     0x0
640 #define UVD_RB_BASE_HI__RB_BASE_HI_MASK                                                                       0xFFFFFFFFL
641 //UVD_RB_SIZE
642 #define UVD_RB_SIZE__RB_SIZE__SHIFT                                                                           0x4
643 #define UVD_RB_SIZE__RB_SIZE_MASK                                                                             0x007FFFF0L
644 //UVD_RB_RPTR
645 #define UVD_RB_RPTR__RB_RPTR__SHIFT                                                                           0x4
646 #define UVD_RB_RPTR__RB_RPTR_MASK                                                                             0x007FFFF0L
647 //UVD_RB_WPTR
648 #define UVD_RB_WPTR__RB_WPTR__SHIFT                                                                           0x4
649 #define UVD_RB_WPTR__RB_WPTR_MASK                                                                             0x007FFFF0L
650 //UVD_RB_WPTR4
651 #define UVD_RB_WPTR4__RB_WPTR__SHIFT                                                                          0x4
652 #define UVD_RB_WPTR4__RB_WPTR_MASK                                                                            0x007FFFF0L
653 //UVD_JRBC_RB_RPTR
654 #define UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT                                                                      0x4
655 #define UVD_JRBC_RB_RPTR__RB_RPTR_MASK                                                                        0x007FFFF0L
656 //UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH
657 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                  0x0
658 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK                                                    0xFFFFFFFFL
659 //UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW
660 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                    0x0
661 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK                                                      0xFFFFFFFFL
662 //UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH
663 #define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                    0x0
664 #define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK                                                      0xFFFFFFFFL
665 //UVD_LMI_VCPU_NC1_64BIT_BAR_LOW
666 #define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                      0x0
667 #define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0_MASK                                                        0xFFFFFFFFL
668 //UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH
669 #define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                    0x0
670 #define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK                                                      0xFFFFFFFFL
671 //UVD_LMI_VCPU_NC0_64BIT_BAR_LOW
672 #define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                      0x0
673 #define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0_MASK                                                        0xFFFFFFFFL
674 //UVD_LMI_LBSI_64BIT_BAR_HIGH
675 #define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                        0x0
676 #define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32_MASK                                                          0xFFFFFFFFL
677 //UVD_LMI_LBSI_64BIT_BAR_LOW
678 #define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                          0x0
679 #define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0_MASK                                                            0xFFFFFFFFL
680 //UVD_LMI_RBC_IB_64BIT_BAR_HIGH
681 #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                      0x0
682 #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK                                                        0xFFFFFFFFL
683 //UVD_LMI_RBC_IB_64BIT_BAR_LOW
684 #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                        0x0
685 #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK                                                          0xFFFFFFFFL
686 //UVD_LMI_RBC_RB_64BIT_BAR_HIGH
687 #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                      0x0
688 #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK                                                        0xFFFFFFFFL
689 //UVD_LMI_RBC_RB_64BIT_BAR_LOW
690 #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                        0x0
691 #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK                                                          0xFFFFFFFFL
692
693
694 // addressBlock: uvd_uvddec
695 //UVD_SEMA_CNTL
696 #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT                                                                    0x0
697 #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT                                                               0x1
698 #define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK                                                                      0x00000001L
699 #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK                                                                 0x00000002L
700 //UVD_LMI_JRBC_RB_64BIT_BAR_LOW
701 #define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                       0x0
702 #define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK                                                         0xFFFFFFFFL
703 //UVD_LMI_JRBC_RB_64BIT_BAR_HIGH
704 #define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                     0x0
705 #define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK                                                       0xFFFFFFFFL
706 //UVD_LMI_JRBC_IB_64BIT_BAR_LOW
707 #define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                       0x0
708 #define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK                                                         0xFFFFFFFFL
709 //UVD_LMI_JRBC_IB_64BIT_BAR_HIGH
710 #define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                     0x0
711 #define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK                                                       0xFFFFFFFFL
712 //UVD_LMI_JRBC_IB_VMID
713 #define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID__SHIFT                                                               0x0
714 #define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID__SHIFT                                                               0x4
715 #define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID_MASK                                                                 0x0000000FL
716 #define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID_MASK                                                                 0x000000F0L
717 //UVD_JRBC_RB_WPTR
718 #define UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT                                                                      0x4
719 #define UVD_JRBC_RB_WPTR__RB_WPTR_MASK                                                                        0x007FFFF0L
720 //UVD_JRBC_RB_CNTL
721 #define UVD_JRBC_RB_CNTL__RB_NO_FETCH__SHIFT                                                                  0x0
722 #define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT                                                                0x1
723 #define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT                                                           0x4
724 #define UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK                                                                    0x00000001L
725 #define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK                                                                  0x00000002L
726 #define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK                                                             0x0007FFF0L
727 //UVD_JRBC_IB_SIZE
728 #define UVD_JRBC_IB_SIZE__IB_SIZE__SHIFT                                                                      0x4
729 #define UVD_JRBC_IB_SIZE__IB_SIZE_MASK                                                                        0x007FFFF0L
730 //UVD_JRBC_LMI_SWAP_CNTL
731 #define UVD_JRBC_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT                                                             0x0
732 #define UVD_JRBC_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT                                                             0x2
733 #define UVD_JRBC_LMI_SWAP_CNTL__RB_MC_SWAP_MASK                                                               0x00000003L
734 #define UVD_JRBC_LMI_SWAP_CNTL__IB_MC_SWAP_MASK                                                               0x0000000CL
735 //UVD_JRBC_SOFT_RESET
736 #define UVD_JRBC_SOFT_RESET__RESET__SHIFT                                                                     0x0
737 #define UVD_JRBC_SOFT_RESET__VCLK_RESET_STATUS__SHIFT                                                         0x10
738 #define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT                                                         0x11
739 #define UVD_JRBC_SOFT_RESET__RESET_MASK                                                                       0x00000001L
740 #define UVD_JRBC_SOFT_RESET__VCLK_RESET_STATUS_MASK                                                           0x00010000L
741 #define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS_MASK                                                           0x00020000L
742 //UVD_JRBC_STATUS
743 #define UVD_JRBC_STATUS__RB_JOB_DONE__SHIFT                                                                   0x0
744 #define UVD_JRBC_STATUS__IB_JOB_DONE__SHIFT                                                                   0x1
745 #define UVD_JRBC_STATUS__RB_ILLEGAL_CMD__SHIFT                                                                0x2
746 #define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT                                                        0x3
747 #define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT                                                             0x4
748 #define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT                                                             0x5
749 #define UVD_JRBC_STATUS__IB_ILLEGAL_CMD__SHIFT                                                                0x6
750 #define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT                                                        0x7
751 #define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT                                                             0x8
752 #define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT                                                             0x9
753 #define UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT                                                                0xa
754 #define UVD_JRBC_STATUS__PREEMPT_STATUS__SHIFT                                                                0xb
755 #define UVD_JRBC_STATUS__IB_TRAP_STATUS__SHIFT                                                                0xc
756 #define UVD_JRBC_STATUS__INT_EN__SHIFT                                                                        0x10
757 #define UVD_JRBC_STATUS__INT_ACK__SHIFT                                                                       0x11
758 #define UVD_JRBC_STATUS__RB_JOB_DONE_MASK                                                                     0x00000001L
759 #define UVD_JRBC_STATUS__IB_JOB_DONE_MASK                                                                     0x00000002L
760 #define UVD_JRBC_STATUS__RB_ILLEGAL_CMD_MASK                                                                  0x00000004L
761 #define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK                                                          0x00000008L
762 #define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK                                                               0x00000010L
763 #define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT_MASK                                                               0x00000020L
764 #define UVD_JRBC_STATUS__IB_ILLEGAL_CMD_MASK                                                                  0x00000040L
765 #define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK                                                          0x00000080L
766 #define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT_MASK                                                               0x00000100L
767 #define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT_MASK                                                               0x00000200L
768 #define UVD_JRBC_STATUS__RB_TRAP_STATUS_MASK                                                                  0x00000400L
769 #define UVD_JRBC_STATUS__PREEMPT_STATUS_MASK                                                                  0x00000800L
770 #define UVD_JRBC_STATUS__IB_TRAP_STATUS_MASK                                                                  0x00001000L
771 #define UVD_JRBC_STATUS__INT_EN_MASK                                                                          0x00010000L
772 #define UVD_JRBC_STATUS__INT_ACK_MASK                                                                         0x00020000L
773 //UVD_RB_RPTR3
774 #define UVD_RB_RPTR3__RB_RPTR__SHIFT                                                                          0x4
775 #define UVD_RB_RPTR3__RB_RPTR_MASK                                                                            0x007FFFF0L
776 //UVD_RB_WPTR3
777 #define UVD_RB_WPTR3__RB_WPTR__SHIFT                                                                          0x4
778 #define UVD_RB_WPTR3__RB_WPTR_MASK                                                                            0x007FFFF0L
779 //UVD_RB_BASE_LO3
780 #define UVD_RB_BASE_LO3__RB_BASE_LO__SHIFT                                                                    0x6
781 #define UVD_RB_BASE_LO3__RB_BASE_LO_MASK                                                                      0xFFFFFFC0L
782 //UVD_RB_BASE_HI3
783 #define UVD_RB_BASE_HI3__RB_BASE_HI__SHIFT                                                                    0x0
784 #define UVD_RB_BASE_HI3__RB_BASE_HI_MASK                                                                      0xFFFFFFFFL
785 //UVD_RB_SIZE3
786 #define UVD_RB_SIZE3__RB_SIZE__SHIFT                                                                          0x4
787 #define UVD_RB_SIZE3__RB_SIZE_MASK                                                                            0x007FFFF0L
788 //JPEG_CGC_GATE
789 #define JPEG_CGC_GATE__JPEG__SHIFT                                                                            0x14
790 #define JPEG_CGC_GATE__JPEG2__SHIFT                                                                           0x15
791 #define JPEG_CGC_GATE__JPEG_MASK                                                                              0x00100000L
792 #define JPEG_CGC_GATE__JPEG2_MASK                                                                             0x00200000L
793 //UVD_CTX_INDEX
794 #define UVD_CTX_INDEX__INDEX__SHIFT                                                                           0x0
795 #define UVD_CTX_INDEX__INDEX_MASK                                                                             0x000001FFL
796 //UVD_CTX_DATA
797 #define UVD_CTX_DATA__DATA__SHIFT                                                                             0x0
798 #define UVD_CTX_DATA__DATA_MASK                                                                               0xFFFFFFFFL
799 //UVD_CGC_GATE
800 #define UVD_CGC_GATE__SYS__SHIFT                                                                              0x0
801 #define UVD_CGC_GATE__UDEC__SHIFT                                                                             0x1
802 #define UVD_CGC_GATE__MPEG2__SHIFT                                                                            0x2
803 #define UVD_CGC_GATE__REGS__SHIFT                                                                             0x3
804 #define UVD_CGC_GATE__RBC__SHIFT                                                                              0x4
805 #define UVD_CGC_GATE__LMI_MC__SHIFT                                                                           0x5
806 #define UVD_CGC_GATE__LMI_UMC__SHIFT                                                                          0x6
807 #define UVD_CGC_GATE__IDCT__SHIFT                                                                             0x7
808 #define UVD_CGC_GATE__MPRD__SHIFT                                                                             0x8
809 #define UVD_CGC_GATE__MPC__SHIFT                                                                              0x9
810 #define UVD_CGC_GATE__LBSI__SHIFT                                                                             0xa
811 #define UVD_CGC_GATE__LRBBM__SHIFT                                                                            0xb
812 #define UVD_CGC_GATE__UDEC_RE__SHIFT                                                                          0xc
813 #define UVD_CGC_GATE__UDEC_CM__SHIFT                                                                          0xd
814 #define UVD_CGC_GATE__UDEC_IT__SHIFT                                                                          0xe
815 #define UVD_CGC_GATE__UDEC_DB__SHIFT                                                                          0xf
816 #define UVD_CGC_GATE__UDEC_MP__SHIFT                                                                          0x10
817 #define UVD_CGC_GATE__WCB__SHIFT                                                                              0x11
818 #define UVD_CGC_GATE__VCPU__SHIFT                                                                             0x12
819 #define UVD_CGC_GATE__SCPU__SHIFT                                                                             0x13
820 #define UVD_CGC_GATE__SYS_MASK                                                                                0x00000001L
821 #define UVD_CGC_GATE__UDEC_MASK                                                                               0x00000002L
822 #define UVD_CGC_GATE__MPEG2_MASK                                                                              0x00000004L
823 #define UVD_CGC_GATE__REGS_MASK                                                                               0x00000008L
824 #define UVD_CGC_GATE__RBC_MASK                                                                                0x00000010L
825 #define UVD_CGC_GATE__LMI_MC_MASK                                                                             0x00000020L
826 #define UVD_CGC_GATE__LMI_UMC_MASK                                                                            0x00000040L
827 #define UVD_CGC_GATE__IDCT_MASK                                                                               0x00000080L
828 #define UVD_CGC_GATE__MPRD_MASK                                                                               0x00000100L
829 #define UVD_CGC_GATE__MPC_MASK                                                                                0x00000200L
830 #define UVD_CGC_GATE__LBSI_MASK                                                                               0x00000400L
831 #define UVD_CGC_GATE__LRBBM_MASK                                                                              0x00000800L
832 #define UVD_CGC_GATE__UDEC_RE_MASK                                                                            0x00001000L
833 #define UVD_CGC_GATE__UDEC_CM_MASK                                                                            0x00002000L
834 #define UVD_CGC_GATE__UDEC_IT_MASK                                                                            0x00004000L
835 #define UVD_CGC_GATE__UDEC_DB_MASK                                                                            0x00008000L
836 #define UVD_CGC_GATE__UDEC_MP_MASK                                                                            0x00010000L
837 #define UVD_CGC_GATE__WCB_MASK                                                                                0x00020000L
838 #define UVD_CGC_GATE__VCPU_MASK                                                                               0x00040000L
839 #define UVD_CGC_GATE__SCPU_MASK                                                                               0x00080000L
840 //UVD_CGC_STATUS
841 #define UVD_CGC_STATUS__SYS_SCLK__SHIFT                                                                       0x0
842 #define UVD_CGC_STATUS__SYS_DCLK__SHIFT                                                                       0x1
843 #define UVD_CGC_STATUS__SYS_VCLK__SHIFT                                                                       0x2
844 #define UVD_CGC_STATUS__UDEC_SCLK__SHIFT                                                                      0x3
845 #define UVD_CGC_STATUS__UDEC_DCLK__SHIFT                                                                      0x4
846 #define UVD_CGC_STATUS__UDEC_VCLK__SHIFT                                                                      0x5
847 #define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT                                                                     0x6
848 #define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT                                                                     0x7
849 #define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT                                                                     0x8
850 #define UVD_CGC_STATUS__REGS_SCLK__SHIFT                                                                      0x9
851 #define UVD_CGC_STATUS__REGS_VCLK__SHIFT                                                                      0xa
852 #define UVD_CGC_STATUS__RBC_SCLK__SHIFT                                                                       0xb
853 #define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT                                                                    0xc
854 #define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT                                                                   0xd
855 #define UVD_CGC_STATUS__IDCT_SCLK__SHIFT                                                                      0xe
856 #define UVD_CGC_STATUS__IDCT_VCLK__SHIFT                                                                      0xf
857 #define UVD_CGC_STATUS__MPRD_SCLK__SHIFT                                                                      0x10
858 #define UVD_CGC_STATUS__MPRD_DCLK__SHIFT                                                                      0x11
859 #define UVD_CGC_STATUS__MPRD_VCLK__SHIFT                                                                      0x12
860 #define UVD_CGC_STATUS__MPC_SCLK__SHIFT                                                                       0x13
861 #define UVD_CGC_STATUS__MPC_DCLK__SHIFT                                                                       0x14
862 #define UVD_CGC_STATUS__LBSI_SCLK__SHIFT                                                                      0x15
863 #define UVD_CGC_STATUS__LBSI_VCLK__SHIFT                                                                      0x16
864 #define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT                                                                     0x17
865 #define UVD_CGC_STATUS__WCB_SCLK__SHIFT                                                                       0x18
866 #define UVD_CGC_STATUS__VCPU_SCLK__SHIFT                                                                      0x19
867 #define UVD_CGC_STATUS__VCPU_VCLK__SHIFT                                                                      0x1a
868 #define UVD_CGC_STATUS__SCPU_SCLK__SHIFT                                                                      0x1b
869 #define UVD_CGC_STATUS__SCPU_VCLK__SHIFT                                                                      0x1c
870 #define UVD_CGC_STATUS__ALL_ENC_ACTIVE__SHIFT                                                                 0x1d
871 #define UVD_CGC_STATUS__JPEG_ACTIVE__SHIFT                                                                    0x1e
872 #define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT                                                                 0x1f
873 #define UVD_CGC_STATUS__SYS_SCLK_MASK                                                                         0x00000001L
874 #define UVD_CGC_STATUS__SYS_DCLK_MASK                                                                         0x00000002L
875 #define UVD_CGC_STATUS__SYS_VCLK_MASK                                                                         0x00000004L
876 #define UVD_CGC_STATUS__UDEC_SCLK_MASK                                                                        0x00000008L
877 #define UVD_CGC_STATUS__UDEC_DCLK_MASK                                                                        0x00000010L
878 #define UVD_CGC_STATUS__UDEC_VCLK_MASK                                                                        0x00000020L
879 #define UVD_CGC_STATUS__MPEG2_SCLK_MASK                                                                       0x00000040L
880 #define UVD_CGC_STATUS__MPEG2_DCLK_MASK                                                                       0x00000080L
881 #define UVD_CGC_STATUS__MPEG2_VCLK_MASK                                                                       0x00000100L
882 #define UVD_CGC_STATUS__REGS_SCLK_MASK                                                                        0x00000200L
883 #define UVD_CGC_STATUS__REGS_VCLK_MASK                                                                        0x00000400L
884 #define UVD_CGC_STATUS__RBC_SCLK_MASK                                                                         0x00000800L
885 #define UVD_CGC_STATUS__LMI_MC_SCLK_MASK                                                                      0x00001000L
886 #define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK                                                                     0x00002000L
887 #define UVD_CGC_STATUS__IDCT_SCLK_MASK                                                                        0x00004000L
888 #define UVD_CGC_STATUS__IDCT_VCLK_MASK                                                                        0x00008000L
889 #define UVD_CGC_STATUS__MPRD_SCLK_MASK                                                                        0x00010000L
890 #define UVD_CGC_STATUS__MPRD_DCLK_MASK                                                                        0x00020000L
891 #define UVD_CGC_STATUS__MPRD_VCLK_MASK                                                                        0x00040000L
892 #define UVD_CGC_STATUS__MPC_SCLK_MASK                                                                         0x00080000L
893 #define UVD_CGC_STATUS__MPC_DCLK_MASK                                                                         0x00100000L
894 #define UVD_CGC_STATUS__LBSI_SCLK_MASK                                                                        0x00200000L
895 #define UVD_CGC_STATUS__LBSI_VCLK_MASK                                                                        0x00400000L
896 #define UVD_CGC_STATUS__LRBBM_SCLK_MASK                                                                       0x00800000L
897 #define UVD_CGC_STATUS__WCB_SCLK_MASK                                                                         0x01000000L
898 #define UVD_CGC_STATUS__VCPU_SCLK_MASK                                                                        0x02000000L
899 #define UVD_CGC_STATUS__VCPU_VCLK_MASK                                                                        0x04000000L
900 #define UVD_CGC_STATUS__SCPU_SCLK_MASK                                                                        0x08000000L
901 #define UVD_CGC_STATUS__SCPU_VCLK_MASK                                                                        0x10000000L
902 #define UVD_CGC_STATUS__ALL_ENC_ACTIVE_MASK                                                                   0x20000000L
903 #define UVD_CGC_STATUS__JPEG_ACTIVE_MASK                                                                      0x40000000L
904 #define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK                                                                   0x80000000L
905 //UVD_CGC_CTRL
906 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT                                                                   0x0
907 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT                                                               0x2
908 #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT                                                                    0x6
909 #define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT                                                                     0xb
910 #define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT                                                                     0xc
911 #define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT                                                                     0xd
912 #define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT                                                                     0xe
913 #define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT                                                                     0xf
914 #define UVD_CGC_CTRL__SYS_MODE__SHIFT                                                                         0x10
915 #define UVD_CGC_CTRL__UDEC_MODE__SHIFT                                                                        0x11
916 #define UVD_CGC_CTRL__MPEG2_MODE__SHIFT                                                                       0x12
917 #define UVD_CGC_CTRL__REGS_MODE__SHIFT                                                                        0x13
918 #define UVD_CGC_CTRL__RBC_MODE__SHIFT                                                                         0x14
919 #define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT                                                                      0x15
920 #define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT                                                                     0x16
921 #define UVD_CGC_CTRL__IDCT_MODE__SHIFT                                                                        0x17
922 #define UVD_CGC_CTRL__MPRD_MODE__SHIFT                                                                        0x18
923 #define UVD_CGC_CTRL__MPC_MODE__SHIFT                                                                         0x19
924 #define UVD_CGC_CTRL__LBSI_MODE__SHIFT                                                                        0x1a
925 #define UVD_CGC_CTRL__LRBBM_MODE__SHIFT                                                                       0x1b
926 #define UVD_CGC_CTRL__WCB_MODE__SHIFT                                                                         0x1c
927 #define UVD_CGC_CTRL__VCPU_MODE__SHIFT                                                                        0x1d
928 #define UVD_CGC_CTRL__SCPU_MODE__SHIFT                                                                        0x1e
929 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK                                                                     0x00000001L
930 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK                                                                 0x0000003CL
931 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK                                                                      0x000007C0L
932 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK                                                                       0x00000800L
933 #define UVD_CGC_CTRL__UDEC_CM_MODE_MASK                                                                       0x00001000L
934 #define UVD_CGC_CTRL__UDEC_IT_MODE_MASK                                                                       0x00002000L
935 #define UVD_CGC_CTRL__UDEC_DB_MODE_MASK                                                                       0x00004000L
936 #define UVD_CGC_CTRL__UDEC_MP_MODE_MASK                                                                       0x00008000L
937 #define UVD_CGC_CTRL__SYS_MODE_MASK                                                                           0x00010000L
938 #define UVD_CGC_CTRL__UDEC_MODE_MASK                                                                          0x00020000L
939 #define UVD_CGC_CTRL__MPEG2_MODE_MASK                                                                         0x00040000L
940 #define UVD_CGC_CTRL__REGS_MODE_MASK                                                                          0x00080000L
941 #define UVD_CGC_CTRL__RBC_MODE_MASK                                                                           0x00100000L
942 #define UVD_CGC_CTRL__LMI_MC_MODE_MASK                                                                        0x00200000L
943 #define UVD_CGC_CTRL__LMI_UMC_MODE_MASK                                                                       0x00400000L
944 #define UVD_CGC_CTRL__IDCT_MODE_MASK                                                                          0x00800000L
945 #define UVD_CGC_CTRL__MPRD_MODE_MASK                                                                          0x01000000L
946 #define UVD_CGC_CTRL__MPC_MODE_MASK                                                                           0x02000000L
947 #define UVD_CGC_CTRL__LBSI_MODE_MASK                                                                          0x04000000L
948 #define UVD_CGC_CTRL__LRBBM_MODE_MASK                                                                         0x08000000L
949 #define UVD_CGC_CTRL__WCB_MODE_MASK                                                                           0x10000000L
950 #define UVD_CGC_CTRL__VCPU_MODE_MASK                                                                          0x20000000L
951 #define UVD_CGC_CTRL__SCPU_MODE_MASK                                                                          0x40000000L
952 //UVD_GP_SCRATCH0
953 #define UVD_GP_SCRATCH0__DATA__SHIFT                                                                          0x0
954 #define UVD_GP_SCRATCH0__DATA_MASK                                                                            0xFFFFFFFFL
955 //UVD_GP_SCRATCH1
956 #define UVD_GP_SCRATCH1__DATA__SHIFT                                                                          0x0
957 #define UVD_GP_SCRATCH1__DATA_MASK                                                                            0xFFFFFFFFL
958 //UVD_GP_SCRATCH2
959 #define UVD_GP_SCRATCH2__DATA__SHIFT                                                                          0x0
960 #define UVD_GP_SCRATCH2__DATA_MASK                                                                            0xFFFFFFFFL
961 //UVD_GP_SCRATCH3
962 #define UVD_GP_SCRATCH3__DATA__SHIFT                                                                          0x0
963 #define UVD_GP_SCRATCH3__DATA_MASK                                                                            0xFFFFFFFFL
964 //UVD_GP_SCRATCH4
965 #define UVD_GP_SCRATCH4__DATA__SHIFT                                                                          0x0
966 #define UVD_GP_SCRATCH4__DATA_MASK                                                                            0xFFFFFFFFL
967 //UVD_GP_SCRATCH5
968 #define UVD_GP_SCRATCH5__DATA__SHIFT                                                                          0x0
969 #define UVD_GP_SCRATCH5__DATA_MASK                                                                            0xFFFFFFFFL
970 //UVD_GP_SCRATCH6
971 #define UVD_GP_SCRATCH6__DATA__SHIFT                                                                          0x0
972 #define UVD_GP_SCRATCH6__DATA_MASK                                                                            0xFFFFFFFFL
973 //UVD_GP_SCRATCH7
974 #define UVD_GP_SCRATCH7__DATA__SHIFT                                                                          0x0
975 #define UVD_GP_SCRATCH7__DATA_MASK                                                                            0xFFFFFFFFL
976 //UVD_LMI_VCPU_CACHE_VMID
977 #define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT                                                       0x0
978 #define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK                                                         0x0000000FL
979 //UVD_LMI_CTRL2
980 #define UVD_LMI_CTRL2__SPH_DIS__SHIFT                                                                         0x0
981 #define UVD_LMI_CTRL2__STALL_ARB__SHIFT                                                                       0x1
982 #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT                                                               0x2
983 #define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT                                                                 0x3
984 #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT                                                           0x7
985 #define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT                                                                   0x8
986 #define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT                                                                  0x9
987 #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT                                                                 0xb
988 #define UVD_LMI_CTRL2__SPH_DIS_MASK                                                                           0x00000001L
989 #define UVD_LMI_CTRL2__STALL_ARB_MASK                                                                         0x00000002L
990 #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK                                                                 0x00000004L
991 #define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK                                                                   0x00000008L
992 #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK                                                             0x00000080L
993 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK                                                                     0x00000100L
994 #define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK                                                                    0x00000600L
995 #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK                                                                   0x00001800L
996 //UVD_MASTINT_EN
997 #define UVD_MASTINT_EN__OVERRUN_RST__SHIFT                                                                    0x0
998 #define UVD_MASTINT_EN__VCPU_EN__SHIFT                                                                        0x1
999 #define UVD_MASTINT_EN__SYS_EN__SHIFT                                                                         0x2
1000 #define UVD_MASTINT_EN__INT_OVERRUN__SHIFT                                                                    0x4
1001 #define UVD_MASTINT_EN__OVERRUN_RST_MASK                                                                      0x00000001L
1002 #define UVD_MASTINT_EN__VCPU_EN_MASK                                                                          0x00000002L
1003 #define UVD_MASTINT_EN__SYS_EN_MASK                                                                           0x00000004L
1004 #define UVD_MASTINT_EN__INT_OVERRUN_MASK                                                                      0x007FFFF0L
1005 //UVD_SYS_INT_EN
1006 #define UVD_SYS_INT_EN__UVD_JRBC_EN__SHIFT                                                                    0x4
1007 #define UVD_SYS_INT_EN__UVD_JRBC_EN_MASK                                                                      0x00000010L
1008 //JPEG_CGC_CTRL
1009 #define JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT                                                                  0x0
1010 #define JPEG_CGC_CTRL__JPEG2_MODE__SHIFT                                                                      0x1
1011 #define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT                                                              0x2
1012 #define JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT                                                                   0x6
1013 #define JPEG_CGC_CTRL__JPEG_MODE__SHIFT                                                                       0x1f
1014 #define JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK                                                                    0x00000001L
1015 #define JPEG_CGC_CTRL__JPEG2_MODE_MASK                                                                        0x00000002L
1016 #define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK                                                                0x0000003CL
1017 #define JPEG_CGC_CTRL__CLK_OFF_DELAY_MASK                                                                     0x000007C0L
1018 #define JPEG_CGC_CTRL__JPEG_MODE_MASK                                                                         0x80000000L
1019 //UVD_LMI_CTRL
1020 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT                                                                0x0
1021 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT                                                             0x8
1022 #define UVD_LMI_CTRL__REQ_MODE__SHIFT                                                                         0x9
1023 #define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT                                                                 0xb
1024 #define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT                                                                   0xc
1025 #define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT                                                                0xd
1026 #define UVD_LMI_CTRL__CRC_RESET__SHIFT                                                                        0xe
1027 #define UVD_LMI_CTRL__CRC_SEL__SHIFT                                                                          0xf
1028 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT                                                           0x15
1029 #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT                                                             0x16
1030 #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT                                                          0x17
1031 #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT                                                          0x18
1032 #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT                                                          0x19
1033 #define UVD_LMI_CTRL__RFU__SHIFT                                                                              0x1b
1034 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK                                                                  0x000000FFL
1035 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK                                                               0x00000100L
1036 #define UVD_LMI_CTRL__REQ_MODE_MASK                                                                           0x00000200L
1037 #define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK                                                                   0x00000800L
1038 #define UVD_LMI_CTRL__MASK_MC_URGENT_MASK                                                                     0x00001000L
1039 #define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK                                                                  0x00002000L
1040 #define UVD_LMI_CTRL__CRC_RESET_MASK                                                                          0x00004000L
1041 #define UVD_LMI_CTRL__CRC_SEL_MASK                                                                            0x000F8000L
1042 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK                                                             0x00200000L
1043 #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK                                                               0x00400000L
1044 #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK                                                            0x00800000L
1045 #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK                                                            0x01000000L
1046 #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK                                                            0x02000000L
1047 #define UVD_LMI_CTRL__RFU_MASK                                                                                0xF8000000L
1048 //UVD_LMI_SWAP_CNTL
1049 #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT                                                                  0x0
1050 #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT                                                                  0x2
1051 #define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT                                                             0x4
1052 #define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT                                                              0x6
1053 #define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT                                                              0x8
1054 #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT                                                                  0xa
1055 #define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT                                                                  0xc
1056 #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT                                                                0xe
1057 #define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT                                                                0x10
1058 #define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT                                                                 0x12
1059 #define UVD_LMI_SWAP_CNTL__ACAP_MC_SWAP__SHIFT                                                                0x14
1060 #define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT                                                            0x16
1061 #define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT                                                                 0x18
1062 #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT                                                               0x1a
1063 #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT                                                                  0x1c
1064 #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT                                                                  0x1e
1065 #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK                                                                    0x00000003L
1066 #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK                                                                    0x0000000CL
1067 #define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK                                                               0x00000030L
1068 #define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK                                                                0x000000C0L
1069 #define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK                                                                0x00000300L
1070 #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK                                                                    0x00000C00L
1071 #define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK                                                                    0x00003000L
1072 #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK                                                                  0x0000C000L
1073 #define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK                                                                  0x00030000L
1074 #define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK                                                                   0x000C0000L
1075 #define UVD_LMI_SWAP_CNTL__ACAP_MC_SWAP_MASK                                                                  0x00300000L
1076 #define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK                                                              0x00C00000L
1077 #define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK                                                                   0x03000000L
1078 #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK                                                                 0x0C000000L
1079 #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK                                                                    0x30000000L
1080 #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK                                                                    0xC0000000L
1081 //UVD_MPC_SET_MUXA0
1082 #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT                                                                      0x0
1083 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT                                                                      0x6
1084 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT                                                                      0xc
1085 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT                                                                      0x12
1086 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT                                                                      0x18
1087 #define UVD_MPC_SET_MUXA0__VARA_0_MASK                                                                        0x0000003FL
1088 #define UVD_MPC_SET_MUXA0__VARA_1_MASK                                                                        0x00000FC0L
1089 #define UVD_MPC_SET_MUXA0__VARA_2_MASK                                                                        0x0003F000L
1090 #define UVD_MPC_SET_MUXA0__VARA_3_MASK                                                                        0x00FC0000L
1091 #define UVD_MPC_SET_MUXA0__VARA_4_MASK                                                                        0x3F000000L
1092 //UVD_MPC_SET_MUXA1
1093 #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT                                                                      0x0
1094 #define UVD_MPC_SET_MUXA1__VARA_6__SHIFT                                                                      0x6
1095 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT                                                                      0xc
1096 #define UVD_MPC_SET_MUXA1__VARA_5_MASK                                                                        0x0000003FL
1097 #define UVD_MPC_SET_MUXA1__VARA_6_MASK                                                                        0x00000FC0L
1098 #define UVD_MPC_SET_MUXA1__VARA_7_MASK                                                                        0x0003F000L
1099 //UVD_MPC_SET_MUXB0
1100 #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT                                                                      0x0
1101 #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT                                                                      0x6
1102 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT                                                                      0xc
1103 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT                                                                      0x12
1104 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT                                                                      0x18
1105 #define UVD_MPC_SET_MUXB0__VARB_0_MASK                                                                        0x0000003FL
1106 #define UVD_MPC_SET_MUXB0__VARB_1_MASK                                                                        0x00000FC0L
1107 #define UVD_MPC_SET_MUXB0__VARB_2_MASK                                                                        0x0003F000L
1108 #define UVD_MPC_SET_MUXB0__VARB_3_MASK                                                                        0x00FC0000L
1109 #define UVD_MPC_SET_MUXB0__VARB_4_MASK                                                                        0x3F000000L
1110 //UVD_MPC_SET_MUXB1
1111 #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT                                                                      0x0
1112 #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT                                                                      0x6
1113 #define UVD_MPC_SET_MUXB1__VARB_7__SHIFT                                                                      0xc
1114 #define UVD_MPC_SET_MUXB1__VARB_5_MASK                                                                        0x0000003FL
1115 #define UVD_MPC_SET_MUXB1__VARB_6_MASK                                                                        0x00000FC0L
1116 #define UVD_MPC_SET_MUXB1__VARB_7_MASK                                                                        0x0003F000L
1117 //UVD_MPC_SET_MUX
1118 #define UVD_MPC_SET_MUX__SET_0__SHIFT                                                                         0x0
1119 #define UVD_MPC_SET_MUX__SET_1__SHIFT                                                                         0x3
1120 #define UVD_MPC_SET_MUX__SET_2__SHIFT                                                                         0x6
1121 #define UVD_MPC_SET_MUX__SET_0_MASK                                                                           0x00000007L
1122 #define UVD_MPC_SET_MUX__SET_1_MASK                                                                           0x00000038L
1123 #define UVD_MPC_SET_MUX__SET_2_MASK                                                                           0x000001C0L
1124 //UVD_MPC_SET_ALU
1125 #define UVD_MPC_SET_ALU__FUNCT__SHIFT                                                                         0x0
1126 #define UVD_MPC_SET_ALU__OPERAND__SHIFT                                                                       0x4
1127 #define UVD_MPC_SET_ALU__FUNCT_MASK                                                                           0x00000007L
1128 #define UVD_MPC_SET_ALU__OPERAND_MASK                                                                         0x00000FF0L
1129 //UVD_GPCOM_SYS_CMD
1130 #define UVD_GPCOM_SYS_CMD__CMD_SEND__SHIFT                                                                    0x0
1131 #define UVD_GPCOM_SYS_CMD__CMD__SHIFT                                                                         0x1
1132 #define UVD_GPCOM_SYS_CMD__CMD_SOURCE__SHIFT                                                                  0x1f
1133 #define UVD_GPCOM_SYS_CMD__CMD_SEND_MASK                                                                      0x00000001L
1134 #define UVD_GPCOM_SYS_CMD__CMD_MASK                                                                           0x7FFFFFFEL
1135 #define UVD_GPCOM_SYS_CMD__CMD_SOURCE_MASK                                                                    0x80000000L
1136 //UVD_GPCOM_SYS_DATA0
1137 #define UVD_GPCOM_SYS_DATA0__DATA0__SHIFT                                                                     0x0
1138 #define UVD_GPCOM_SYS_DATA0__DATA0_MASK                                                                       0xFFFFFFFFL
1139 //UVD_GPCOM_SYS_DATA1
1140 #define UVD_GPCOM_SYS_DATA1__DATA1__SHIFT                                                                     0x0
1141 #define UVD_GPCOM_SYS_DATA1__DATA1_MASK                                                                       0xFFFFFFFFL
1142 //UVD_VCPU_CACHE_OFFSET0
1143 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT                                                          0x0
1144 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK                                                            0x001FFFFFL
1145 //UVD_VCPU_CACHE_SIZE0
1146 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT                                                              0x0
1147 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK                                                                0x001FFFFFL
1148 //UVD_VCPU_CACHE_OFFSET1
1149 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT                                                          0x0
1150 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK                                                            0x001FFFFFL
1151 //UVD_VCPU_CACHE_SIZE1
1152 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT                                                              0x0
1153 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK                                                                0x001FFFFFL
1154 //UVD_VCPU_CACHE_OFFSET2
1155 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT                                                          0x0
1156 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK                                                            0x001FFFFFL
1157 //UVD_VCPU_CACHE_SIZE2
1158 #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT                                                              0x0
1159 #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK                                                                0x001FFFFFL
1160 //UVD_VCPU_CNTL
1161 #define UVD_VCPU_CNTL__CLK_EN__SHIFT                                                                          0x9
1162 #define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP__SHIFT                                                         0x11
1163 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT                                                                 0x14
1164 #define UVD_VCPU_CNTL__CLK_EN_MASK                                                                            0x00000200L
1165 #define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK                                                           0x00020000L
1166 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK                                                                   0x0FF00000L
1167 //UVD_SOFT_RESET
1168 #define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT                                                                 0x0
1169 #define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT                                                                0x1
1170 #define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT                                                                 0x2
1171 #define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT                                                                0x3
1172 #define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT                                                                0x4
1173 #define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT                                                                 0x5
1174 #define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT                                                                 0x6
1175 #define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT                                                                 0x7
1176 #define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT                                                                 0x8
1177 #define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT                                                                  0xa
1178 #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT                                                             0xd
1179 #define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT                                                                 0xe
1180 #define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT                                                                 0xf
1181 #define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT                                                                 0x10
1182 #define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT                                                                0x11
1183 #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT                                                         0x12
1184 #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT                                                         0x13
1185 #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT                                                         0x14
1186 #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT                                                         0x15
1187 #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT                                                          0x16
1188 #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT                                                          0x1a
1189 #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT                                                          0x1b
1190 #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT                                                         0x1c
1191 #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT                                                         0x1d
1192 #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT                                                           0x1e
1193 #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT                                                          0x1f
1194 #define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK                                                                   0x00000001L
1195 #define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK                                                                  0x00000002L
1196 #define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK                                                                   0x00000004L
1197 #define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK                                                                  0x00000008L
1198 #define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK                                                                  0x00000010L
1199 #define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK                                                                   0x00000020L
1200 #define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK                                                                   0x00000040L
1201 #define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK                                                                   0x00000080L
1202 #define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK                                                                   0x00000100L
1203 #define UVD_SOFT_RESET__IH_SOFT_RESET_MASK                                                                    0x00000400L
1204 #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK                                                               0x00002000L
1205 #define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK                                                                   0x00004000L
1206 #define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK                                                                   0x00008000L
1207 #define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK                                                                   0x00010000L
1208 #define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK                                                                  0x00020000L
1209 #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK                                                           0x00040000L
1210 #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK                                                           0x00080000L
1211 #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK                                                           0x00100000L
1212 #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK                                                           0x00200000L
1213 #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK                                                            0x00400000L
1214 #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK                                                            0x04000000L
1215 #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK                                                            0x08000000L
1216 #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK                                                           0x10000000L
1217 #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK                                                           0x20000000L
1218 #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK                                                             0x40000000L
1219 #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK                                                            0x80000000L
1220 //UVD_LMI_RBC_IB_VMID
1221 #define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT                                                                   0x0
1222 #define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK                                                                     0x0000000FL
1223 //UVD_RBC_IB_SIZE
1224 #define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT                                                                       0x4
1225 #define UVD_RBC_IB_SIZE__IB_SIZE_MASK                                                                         0x007FFFF0L
1226 //UVD_RBC_RB_RPTR
1227 #define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT                                                                       0x4
1228 #define UVD_RBC_RB_RPTR__RB_RPTR_MASK                                                                         0x007FFFF0L
1229 //UVD_RBC_RB_WPTR
1230 #define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT                                                                       0x4
1231 #define UVD_RBC_RB_WPTR__RB_WPTR_MASK                                                                         0x007FFFF0L
1232 //UVD_RBC_RB_WPTR_CNTL
1233 #define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER__SHIFT                                                       0x0
1234 #define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK                                                         0x00007FFFL
1235 //UVD_RBC_WPTR_STATUS
1236 #define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE__SHIFT                                                            0x4
1237 #define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE_MASK                                                              0x007FFFF0L
1238 //UVD_RBC_RB_CNTL
1239 #define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT                                                                      0x0
1240 #define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT                                                                      0x8
1241 #define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT                                                                   0x10
1242 #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT                                                               0x14
1243 #define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT                                                                  0x18
1244 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT                                                                 0x1c
1245 #define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK                                                                        0x0000001FL
1246 #define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK                                                                        0x00001F00L
1247 #define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK                                                                     0x00010000L
1248 #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK                                                                 0x00100000L
1249 #define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK                                                                    0x01000000L
1250 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK                                                                   0x10000000L
1251 //UVD_RBC_RB_RPTR_ADDR
1252 #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT                                                             0x0
1253 #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK                                                               0xFFFFFFFFL
1254 //UVD_STATUS
1255 #define UVD_STATUS__RBC_BUSY__SHIFT                                                                           0x0
1256 #define UVD_STATUS__VCPU_REPORT__SHIFT                                                                        0x1
1257 #define UVD_STATUS__AVP_BUSY__SHIFT                                                                           0x8
1258 #define UVD_STATUS__IDCT_BUSY__SHIFT                                                                          0x9
1259 #define UVD_STATUS__IDCT_CTL_ACK__SHIFT                                                                       0xb
1260 #define UVD_STATUS__UVD_CTL_ACK__SHIFT                                                                        0xc
1261 #define UVD_STATUS__AVP_BLOCK_ACK__SHIFT                                                                      0xd
1262 #define UVD_STATUS__IDCT_BLOCK_ACK__SHIFT                                                                     0xe
1263 #define UVD_STATUS__UVD_BLOCK_ACK__SHIFT                                                                      0xf
1264 #define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT                                                                   0x10
1265 #define UVD_STATUS__SYS_GPCOM_REQ__SHIFT                                                                      0x1f
1266 #define UVD_STATUS__RBC_BUSY_MASK                                                                             0x00000001L
1267 #define UVD_STATUS__VCPU_REPORT_MASK                                                                          0x000000FEL
1268 #define UVD_STATUS__AVP_BUSY_MASK                                                                             0x00000100L
1269 #define UVD_STATUS__IDCT_BUSY_MASK                                                                            0x00000200L
1270 #define UVD_STATUS__IDCT_CTL_ACK_MASK                                                                         0x00000800L
1271 #define UVD_STATUS__UVD_CTL_ACK_MASK                                                                          0x00001000L
1272 #define UVD_STATUS__AVP_BLOCK_ACK_MASK                                                                        0x00002000L
1273 #define UVD_STATUS__IDCT_BLOCK_ACK_MASK                                                                       0x00004000L
1274 #define UVD_STATUS__UVD_BLOCK_ACK_MASK                                                                        0x00008000L
1275 #define UVD_STATUS__RBC_ACCESS_GPCOM_MASK                                                                     0x00010000L
1276 #define UVD_STATUS__SYS_GPCOM_REQ_MASK                                                                        0x80000000L
1277 //UVD_SEMA_TIMEOUT_STATUS
1278 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT                                0x0
1279 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT                                     0x1
1280 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT                              0x2
1281 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT                                               0x3
1282 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK                                  0x00000001L
1283 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK                                       0x00000002L
1284 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK                                0x00000004L
1285 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK                                                 0x00000008L
1286 //UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL
1287 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT                                      0x0
1288 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT                                   0x1
1289 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT                                            0x18
1290 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK                                        0x00000001L
1291 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK                                     0x001FFFFEL
1292 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK                                              0x07000000L
1293 //UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL
1294 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT                                                0x0
1295 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT                                             0x1
1296 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT                                                 0x18
1297 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK                                                  0x00000001L
1298 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK                                               0x001FFFFEL
1299 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK                                                   0x07000000L
1300 //UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL
1301 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT                                  0x0
1302 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT                               0x1
1303 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT                                          0x18
1304 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK                                    0x00000001L
1305 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK                                 0x001FFFFEL
1306 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK                                            0x07000000L
1307 //UVD_CONTEXT_ID
1308 #define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT                                                                     0x0
1309 #define UVD_CONTEXT_ID__CONTEXT_ID_MASK                                                                       0xFFFFFFFFL
1310 //UVD_CONTEXT_ID2
1311 #define UVD_CONTEXT_ID2__CONTEXT_ID2__SHIFT                                                                   0x0
1312 #define UVD_CONTEXT_ID2__CONTEXT_ID2_MASK                                                                     0xFFFFFFFFL
1313 //UVD_RBC_WPTR_POLL_CNTL
1314 #define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ__SHIFT                                                              0x0
1315 #define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                        0x10
1316 #define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ_MASK                                                                0x0000FFFFL
1317 #define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                          0xFFFF0000L
1318 //UVD_RBC_WPTR_POLL_ADDR
1319 #define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR__SHIFT                                                              0x2
1320 #define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR_MASK                                                                0xFFFFFFFCL
1321 //UVD_RB_BASE_LO4
1322 #define UVD_RB_BASE_LO4__RB_BASE_LO__SHIFT                                                                    0x6
1323 #define UVD_RB_BASE_LO4__RB_BASE_LO_MASK                                                                      0xFFFFFFC0L
1324 //UVD_RB_BASE_HI4
1325 #define UVD_RB_BASE_HI4__RB_BASE_HI__SHIFT                                                                    0x0
1326 #define UVD_RB_BASE_HI4__RB_BASE_HI_MASK                                                                      0xFFFFFFFFL
1327 //UVD_RB_SIZE4
1328 #define UVD_RB_SIZE4__RB_SIZE__SHIFT                                                                          0x4
1329 #define UVD_RB_SIZE4__RB_SIZE_MASK                                                                            0x007FFFF0L
1330 //UVD_RB_RPTR4
1331 #define UVD_RB_RPTR4__RB_RPTR__SHIFT                                                                          0x4
1332 #define UVD_RB_RPTR4__RB_RPTR_MASK                                                                            0x007FFFF0L
1333
1334
1335 #endif