drm/amd/powerplay: refine code in amd_powerplay.c (v2)
[muen/linux.git] / drivers / gpu / drm / amd / powerplay / amd_powerplay.c
1 /*
2  * Copyright 2015 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #include "pp_debug.h"
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/gfp.h>
27 #include <linux/slab.h>
28 #include "amd_shared.h"
29 #include "amd_powerplay.h"
30 #include "pp_instance.h"
31 #include "power_state.h"
32
33 #define PP_DPM_DISABLED 0xCCCC
34
35 static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
36                 void *input, void *output);
37
38 static inline int pp_check(struct pp_instance *handle)
39 {
40         if (handle == NULL || handle->pp_valid != PP_VALID)
41                 return -EINVAL;
42
43         if (handle->hwmgr == NULL || handle->hwmgr->smumgr_funcs == NULL)
44                 return -EINVAL;
45
46         if (handle->pm_en == 0)
47                 return PP_DPM_DISABLED;
48
49         if (handle->hwmgr->hwmgr_func == NULL)
50                 return PP_DPM_DISABLED;
51
52         return 0;
53 }
54
55 static int amd_powerplay_create(struct amd_pp_init *pp_init,
56                                 void **handle)
57 {
58         struct pp_instance *instance;
59
60         if (pp_init == NULL || handle == NULL)
61                 return -EINVAL;
62
63         instance = kzalloc(sizeof(struct pp_instance), GFP_KERNEL);
64         if (instance == NULL)
65                 return -ENOMEM;
66
67         instance->pp_valid = PP_VALID;
68         instance->chip_family = pp_init->chip_family;
69         instance->chip_id = pp_init->chip_id;
70         instance->pm_en = pp_init->pm_en;
71         instance->feature_mask = pp_init->feature_mask;
72         instance->device = pp_init->device;
73         mutex_init(&instance->pp_lock);
74         *handle = instance;
75         return 0;
76 }
77
78 static int amd_powerplay_destroy(void *handle)
79 {
80         struct pp_instance *instance = (struct pp_instance *)handle;
81
82         kfree(instance->hwmgr);
83         instance->hwmgr = NULL;
84
85         kfree(instance);
86         instance = NULL;
87         return 0;
88 }
89
90 static int pp_early_init(void *handle)
91 {
92         int ret;
93         struct pp_instance *pp_handle = NULL;
94
95         pp_handle = cgs_register_pp_handle(handle, amd_powerplay_create);
96
97         if (!pp_handle)
98                 return -EINVAL;
99
100         ret = hwmgr_early_init(pp_handle);
101         if (ret)
102                 return -EINVAL;
103
104         return 0;
105 }
106
107 static int pp_sw_init(void *handle)
108 {
109         struct pp_hwmgr *hwmgr;
110         int ret = 0;
111         struct pp_instance *pp_handle = (struct pp_instance *)handle;
112
113         ret = pp_check(pp_handle);
114
115         if (ret >= 0) {
116                 hwmgr = pp_handle->hwmgr;
117
118                 if (hwmgr->smumgr_funcs->smu_init == NULL)
119                         return -EINVAL;
120
121                 ret = hwmgr->smumgr_funcs->smu_init(hwmgr);
122
123                 pr_info("amdgpu: powerplay sw initialized\n");
124         }
125         return ret;
126 }
127
128 static int pp_sw_fini(void *handle)
129 {
130         struct pp_hwmgr *hwmgr;
131         int ret = 0;
132         struct pp_instance *pp_handle = (struct pp_instance *)handle;
133
134         ret = pp_check(pp_handle);
135         if (ret >= 0) {
136                 hwmgr = pp_handle->hwmgr;
137
138                 if (hwmgr->smumgr_funcs->smu_fini == NULL)
139                         return -EINVAL;
140
141                 ret = hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
142         }
143         return ret;
144 }
145
146 static int pp_hw_init(void *handle)
147 {
148         int ret = 0;
149         struct pp_instance *pp_handle = (struct pp_instance *)handle;
150         struct pp_hwmgr *hwmgr;
151
152         ret = pp_check(pp_handle);
153
154         if (ret >= 0) {
155                 hwmgr = pp_handle->hwmgr;
156
157                 if (hwmgr->smumgr_funcs->start_smu == NULL)
158                         return -EINVAL;
159
160                 if(hwmgr->smumgr_funcs->start_smu(pp_handle->hwmgr)) {
161                         pr_err("smc start failed\n");
162                         hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
163                         return -EINVAL;;
164                 }
165                 if (ret == PP_DPM_DISABLED)
166                         goto exit;
167                 ret = hwmgr_hw_init(pp_handle);
168                 if (ret)
169                         goto exit;
170         }
171         return ret;
172 exit:
173         pp_handle->pm_en = 0;
174         cgs_notify_dpm_enabled(hwmgr->device, false);
175         return 0;
176
177 }
178
179 static int pp_hw_fini(void *handle)
180 {
181         struct pp_instance *pp_handle = (struct pp_instance *)handle;
182         int ret = 0;
183
184         ret = pp_check(pp_handle);
185         if (ret == 0)
186                 hwmgr_hw_fini(pp_handle);
187
188         return 0;
189 }
190
191 static int pp_late_init(void *handle)
192 {
193         struct pp_instance *pp_handle = (struct pp_instance *)handle;
194         int ret = 0;
195
196         ret = pp_check(pp_handle);
197         if (ret == 0)
198                 pp_dpm_dispatch_tasks(pp_handle,
199                                         AMD_PP_TASK_COMPLETE_INIT, NULL, NULL);
200
201         return 0;
202 }
203
204 static void pp_late_fini(void *handle)
205 {
206         amd_powerplay_destroy(handle);
207 }
208
209
210 static bool pp_is_idle(void *handle)
211 {
212         return false;
213 }
214
215 static int pp_wait_for_idle(void *handle)
216 {
217         return 0;
218 }
219
220 static int pp_sw_reset(void *handle)
221 {
222         return 0;
223 }
224
225
226 int amd_set_clockgating_by_smu(void *handle, uint32_t msg_id)
227 {
228         struct pp_hwmgr  *hwmgr;
229         struct pp_instance *pp_handle = (struct pp_instance *)handle;
230         int ret = 0;
231
232         ret = pp_check(pp_handle);
233
234         if (ret != 0)
235                 return ret;
236
237         hwmgr = pp_handle->hwmgr;
238
239         if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
240                 pr_info("%s was not implemented.\n", __func__);
241                 return 0;
242         }
243
244         return hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
245 }
246
247 static int pp_set_powergating_state(void *handle,
248                                     enum amd_powergating_state state)
249 {
250         struct pp_hwmgr  *hwmgr;
251         struct pp_instance *pp_handle = (struct pp_instance *)handle;
252         int ret = 0;
253
254         ret = pp_check(pp_handle);
255
256         if (ret != 0)
257                 return ret;
258
259         hwmgr = pp_handle->hwmgr;
260
261         if (hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL) {
262                 pr_info("%s was not implemented.\n", __func__);
263                 return 0;
264         }
265
266         /* Enable/disable GFX per cu powergating through SMU */
267         return hwmgr->hwmgr_func->enable_per_cu_power_gating(hwmgr,
268                         state == AMD_PG_STATE_GATE);
269 }
270
271 static int pp_suspend(void *handle)
272 {
273         struct pp_instance *pp_handle = (struct pp_instance *)handle;
274         int ret = 0;
275
276         ret = pp_check(pp_handle);
277         if (ret == 0)
278                 hwmgr_hw_suspend(pp_handle);
279         return 0;
280 }
281
282 static int pp_resume(void *handle)
283 {
284         struct pp_hwmgr  *hwmgr;
285         int ret;
286         struct pp_instance *pp_handle = (struct pp_instance *)handle;
287
288         ret = pp_check(pp_handle);
289
290         if (ret < 0)
291                 return ret;
292
293         hwmgr = pp_handle->hwmgr;
294
295         if (hwmgr->smumgr_funcs->start_smu == NULL)
296                 return -EINVAL;
297
298         if (hwmgr->smumgr_funcs->start_smu(pp_handle->hwmgr)) {
299                 pr_err("smc start failed\n");
300                 hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
301                 return -EINVAL;
302         }
303
304         if (ret == PP_DPM_DISABLED)
305                 return 0;
306
307         return hwmgr_hw_resume(pp_handle);
308 }
309
310 const struct amd_ip_funcs pp_ip_funcs = {
311         .name = "powerplay",
312         .early_init = pp_early_init,
313         .late_init = pp_late_init,
314         .sw_init = pp_sw_init,
315         .sw_fini = pp_sw_fini,
316         .hw_init = pp_hw_init,
317         .hw_fini = pp_hw_fini,
318         .late_fini = pp_late_fini,
319         .suspend = pp_suspend,
320         .resume = pp_resume,
321         .is_idle = pp_is_idle,
322         .wait_for_idle = pp_wait_for_idle,
323         .soft_reset = pp_sw_reset,
324         .set_clockgating_state = NULL,
325         .set_powergating_state = pp_set_powergating_state,
326 };
327
328 static int pp_dpm_load_fw(void *handle)
329 {
330         return 0;
331 }
332
333 static int pp_dpm_fw_loading_complete(void *handle)
334 {
335         return 0;
336 }
337
338 static void pp_dpm_en_umd_pstate(struct pp_hwmgr  *hwmgr,
339                                                 enum amd_dpm_forced_level *level)
340 {
341         uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
342                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
343                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
344                                         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
345
346         if (!(hwmgr->dpm_level & profile_mode_mask)) {
347                 /* enter umd pstate, save current level, disable gfx cg*/
348                 if (*level & profile_mode_mask) {
349                         hwmgr->saved_dpm_level = hwmgr->dpm_level;
350                         hwmgr->en_umd_pstate = true;
351                         cgs_set_clockgating_state(hwmgr->device,
352                                                 AMD_IP_BLOCK_TYPE_GFX,
353                                                 AMD_CG_STATE_UNGATE);
354                         cgs_set_powergating_state(hwmgr->device,
355                                         AMD_IP_BLOCK_TYPE_GFX,
356                                         AMD_PG_STATE_UNGATE);
357                 }
358         } else {
359                 /* exit umd pstate, restore level, enable gfx cg*/
360                 if (!(*level & profile_mode_mask)) {
361                         if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
362                                 *level = hwmgr->saved_dpm_level;
363                         hwmgr->en_umd_pstate = false;
364                         cgs_set_clockgating_state(hwmgr->device,
365                                         AMD_IP_BLOCK_TYPE_GFX,
366                                         AMD_CG_STATE_GATE);
367                         cgs_set_powergating_state(hwmgr->device,
368                                         AMD_IP_BLOCK_TYPE_GFX,
369                                         AMD_PG_STATE_GATE);
370                 }
371         }
372 }
373
374 static int pp_dpm_force_performance_level(void *handle,
375                                         enum amd_dpm_forced_level level)
376 {
377         struct pp_hwmgr  *hwmgr;
378         struct pp_instance *pp_handle = (struct pp_instance *)handle;
379         int ret = 0;
380
381         ret = pp_check(pp_handle);
382
383         if (ret != 0)
384                 return ret;
385
386         hwmgr = pp_handle->hwmgr;
387
388         if (level == hwmgr->dpm_level)
389                 return 0;
390
391         if (hwmgr->hwmgr_func->force_dpm_level == NULL) {
392                 pr_info("%s was not implemented.\n", __func__);
393                 return 0;
394         }
395
396         mutex_lock(&pp_handle->pp_lock);
397         pp_dpm_en_umd_pstate(hwmgr, &level);
398         hwmgr->request_dpm_level = level;
399         hwmgr_handle_task(pp_handle, AMD_PP_TASK_READJUST_POWER_STATE, NULL, NULL);
400         ret = hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
401         if (!ret)
402                 hwmgr->dpm_level = hwmgr->request_dpm_level;
403
404         mutex_unlock(&pp_handle->pp_lock);
405         return 0;
406 }
407
408 static enum amd_dpm_forced_level pp_dpm_get_performance_level(
409                                                                 void *handle)
410 {
411         struct pp_hwmgr  *hwmgr;
412         struct pp_instance *pp_handle = (struct pp_instance *)handle;
413         int ret = 0;
414         enum amd_dpm_forced_level level;
415
416         ret = pp_check(pp_handle);
417
418         if (ret != 0)
419                 return ret;
420
421         hwmgr = pp_handle->hwmgr;
422         mutex_lock(&pp_handle->pp_lock);
423         level = hwmgr->dpm_level;
424         mutex_unlock(&pp_handle->pp_lock);
425         return level;
426 }
427
428 static uint32_t pp_dpm_get_sclk(void *handle, bool low)
429 {
430         struct pp_hwmgr  *hwmgr;
431         struct pp_instance *pp_handle = (struct pp_instance *)handle;
432         int ret = 0;
433         uint32_t clk = 0;
434
435         ret = pp_check(pp_handle);
436
437         if (ret != 0)
438                 return ret;
439
440         hwmgr = pp_handle->hwmgr;
441
442         if (hwmgr->hwmgr_func->get_sclk == NULL) {
443                 pr_info("%s was not implemented.\n", __func__);
444                 return 0;
445         }
446         mutex_lock(&pp_handle->pp_lock);
447         clk = hwmgr->hwmgr_func->get_sclk(hwmgr, low);
448         mutex_unlock(&pp_handle->pp_lock);
449         return clk;
450 }
451
452 static uint32_t pp_dpm_get_mclk(void *handle, bool low)
453 {
454         struct pp_hwmgr  *hwmgr;
455         struct pp_instance *pp_handle = (struct pp_instance *)handle;
456         int ret = 0;
457         uint32_t clk = 0;
458
459         ret = pp_check(pp_handle);
460
461         if (ret != 0)
462                 return ret;
463
464         hwmgr = pp_handle->hwmgr;
465
466         if (hwmgr->hwmgr_func->get_mclk == NULL) {
467                 pr_info("%s was not implemented.\n", __func__);
468                 return 0;
469         }
470         mutex_lock(&pp_handle->pp_lock);
471         clk = hwmgr->hwmgr_func->get_mclk(hwmgr, low);
472         mutex_unlock(&pp_handle->pp_lock);
473         return clk;
474 }
475
476 static void pp_dpm_powergate_vce(void *handle, bool gate)
477 {
478         struct pp_hwmgr  *hwmgr;
479         struct pp_instance *pp_handle = (struct pp_instance *)handle;
480         int ret = 0;
481
482         ret = pp_check(pp_handle);
483
484         if (ret != 0)
485                 return;
486
487         hwmgr = pp_handle->hwmgr;
488
489         if (hwmgr->hwmgr_func->powergate_vce == NULL) {
490                 pr_info("%s was not implemented.\n", __func__);
491                 return;
492         }
493         mutex_lock(&pp_handle->pp_lock);
494         hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
495         mutex_unlock(&pp_handle->pp_lock);
496 }
497
498 static void pp_dpm_powergate_uvd(void *handle, bool gate)
499 {
500         struct pp_hwmgr  *hwmgr;
501         struct pp_instance *pp_handle = (struct pp_instance *)handle;
502         int ret = 0;
503
504         ret = pp_check(pp_handle);
505
506         if (ret != 0)
507                 return;
508
509         hwmgr = pp_handle->hwmgr;
510
511         if (hwmgr->hwmgr_func->powergate_uvd == NULL) {
512                 pr_info("%s was not implemented.\n", __func__);
513                 return;
514         }
515         mutex_lock(&pp_handle->pp_lock);
516         hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
517         mutex_unlock(&pp_handle->pp_lock);
518 }
519
520 static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
521                 void *input, void *output)
522 {
523         int ret = 0;
524         struct pp_instance *pp_handle = (struct pp_instance *)handle;
525
526         ret = pp_check(pp_handle);
527
528         if (ret != 0)
529                 return ret;
530
531         mutex_lock(&pp_handle->pp_lock);
532         ret = hwmgr_handle_task(pp_handle, task_id, input, output);
533         mutex_unlock(&pp_handle->pp_lock);
534
535         return ret;
536 }
537
538 static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
539 {
540         struct pp_hwmgr *hwmgr;
541         struct pp_power_state *state;
542         struct pp_instance *pp_handle = (struct pp_instance *)handle;
543         int ret = 0;
544         enum amd_pm_state_type pm_type;
545
546         ret = pp_check(pp_handle);
547
548         if (ret != 0)
549                 return ret;
550
551         hwmgr = pp_handle->hwmgr;
552
553         if (hwmgr->current_ps == NULL)
554                 return -EINVAL;
555
556         mutex_lock(&pp_handle->pp_lock);
557
558         state = hwmgr->current_ps;
559
560         switch (state->classification.ui_label) {
561         case PP_StateUILabel_Battery:
562                 pm_type = POWER_STATE_TYPE_BATTERY;
563                 break;
564         case PP_StateUILabel_Balanced:
565                 pm_type = POWER_STATE_TYPE_BALANCED;
566                 break;
567         case PP_StateUILabel_Performance:
568                 pm_type = POWER_STATE_TYPE_PERFORMANCE;
569                 break;
570         default:
571                 if (state->classification.flags & PP_StateClassificationFlag_Boot)
572                         pm_type = POWER_STATE_TYPE_INTERNAL_BOOT;
573                 else
574                         pm_type = POWER_STATE_TYPE_DEFAULT;
575                 break;
576         }
577         mutex_unlock(&pp_handle->pp_lock);
578
579         return pm_type;
580 }
581
582 static void pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
583 {
584         struct pp_hwmgr  *hwmgr;
585         struct pp_instance *pp_handle = (struct pp_instance *)handle;
586         int ret = 0;
587
588         ret = pp_check(pp_handle);
589
590         if (ret != 0)
591                 return;
592
593         hwmgr = pp_handle->hwmgr;
594
595         if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) {
596                 pr_info("%s was not implemented.\n", __func__);
597                 return;
598         }
599         mutex_lock(&pp_handle->pp_lock);
600         hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode);
601         mutex_unlock(&pp_handle->pp_lock);
602 }
603
604 static uint32_t pp_dpm_get_fan_control_mode(void *handle)
605 {
606         struct pp_hwmgr  *hwmgr;
607         struct pp_instance *pp_handle = (struct pp_instance *)handle;
608         int ret = 0;
609         uint32_t mode = 0;
610
611         ret = pp_check(pp_handle);
612
613         if (ret != 0)
614                 return ret;
615
616         hwmgr = pp_handle->hwmgr;
617
618         if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) {
619                 pr_info("%s was not implemented.\n", __func__);
620                 return 0;
621         }
622         mutex_lock(&pp_handle->pp_lock);
623         mode = hwmgr->hwmgr_func->get_fan_control_mode(hwmgr);
624         mutex_unlock(&pp_handle->pp_lock);
625         return mode;
626 }
627
628 static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent)
629 {
630         struct pp_hwmgr  *hwmgr;
631         struct pp_instance *pp_handle = (struct pp_instance *)handle;
632         int ret = 0;
633
634         ret = pp_check(pp_handle);
635
636         if (ret != 0)
637                 return ret;
638
639         hwmgr = pp_handle->hwmgr;
640
641         if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) {
642                 pr_info("%s was not implemented.\n", __func__);
643                 return 0;
644         }
645         mutex_lock(&pp_handle->pp_lock);
646         ret = hwmgr->hwmgr_func->set_fan_speed_percent(hwmgr, percent);
647         mutex_unlock(&pp_handle->pp_lock);
648         return ret;
649 }
650
651 static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed)
652 {
653         struct pp_hwmgr  *hwmgr;
654         struct pp_instance *pp_handle = (struct pp_instance *)handle;
655         int ret = 0;
656
657         ret = pp_check(pp_handle);
658
659         if (ret != 0)
660                 return ret;
661
662         hwmgr = pp_handle->hwmgr;
663
664         if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) {
665                 pr_info("%s was not implemented.\n", __func__);
666                 return 0;
667         }
668
669         mutex_lock(&pp_handle->pp_lock);
670         ret = hwmgr->hwmgr_func->get_fan_speed_percent(hwmgr, speed);
671         mutex_unlock(&pp_handle->pp_lock);
672         return ret;
673 }
674
675 static int pp_dpm_get_fan_speed_rpm(void *handle, uint32_t *rpm)
676 {
677         struct pp_hwmgr *hwmgr;
678         struct pp_instance *pp_handle = (struct pp_instance *)handle;
679         int ret = 0;
680
681         ret = pp_check(pp_handle);
682
683         if (ret != 0)
684                 return ret;
685
686         hwmgr = pp_handle->hwmgr;
687
688         if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL)
689                 return -EINVAL;
690
691         mutex_lock(&pp_handle->pp_lock);
692         ret = hwmgr->hwmgr_func->get_fan_speed_rpm(hwmgr, rpm);
693         mutex_unlock(&pp_handle->pp_lock);
694         return ret;
695 }
696
697 static int pp_dpm_get_temperature(void *handle)
698 {
699         struct pp_hwmgr  *hwmgr;
700         struct pp_instance *pp_handle = (struct pp_instance *)handle;
701         int ret = 0;
702
703         ret = pp_check(pp_handle);
704
705         if (ret != 0)
706                 return ret;
707
708         hwmgr = pp_handle->hwmgr;
709
710         if (hwmgr->hwmgr_func->get_temperature == NULL) {
711                 pr_info("%s was not implemented.\n", __func__);
712                 return 0;
713         }
714         mutex_lock(&pp_handle->pp_lock);
715         ret = hwmgr->hwmgr_func->get_temperature(hwmgr);
716         mutex_unlock(&pp_handle->pp_lock);
717         return ret;
718 }
719
720 static int pp_dpm_get_pp_num_states(void *handle,
721                 struct pp_states_info *data)
722 {
723         struct pp_hwmgr *hwmgr;
724         int i;
725         struct pp_instance *pp_handle = (struct pp_instance *)handle;
726         int ret = 0;
727
728         ret = pp_check(pp_handle);
729
730         if (ret != 0)
731                 return ret;
732
733         hwmgr = pp_handle->hwmgr;
734
735         if (hwmgr->ps == NULL)
736                 return -EINVAL;
737
738         mutex_lock(&pp_handle->pp_lock);
739
740         data->nums = hwmgr->num_ps;
741
742         for (i = 0; i < hwmgr->num_ps; i++) {
743                 struct pp_power_state *state = (struct pp_power_state *)
744                                 ((unsigned long)hwmgr->ps + i * hwmgr->ps_size);
745                 switch (state->classification.ui_label) {
746                 case PP_StateUILabel_Battery:
747                         data->states[i] = POWER_STATE_TYPE_BATTERY;
748                         break;
749                 case PP_StateUILabel_Balanced:
750                         data->states[i] = POWER_STATE_TYPE_BALANCED;
751                         break;
752                 case PP_StateUILabel_Performance:
753                         data->states[i] = POWER_STATE_TYPE_PERFORMANCE;
754                         break;
755                 default:
756                         if (state->classification.flags & PP_StateClassificationFlag_Boot)
757                                 data->states[i] = POWER_STATE_TYPE_INTERNAL_BOOT;
758                         else
759                                 data->states[i] = POWER_STATE_TYPE_DEFAULT;
760                 }
761         }
762         mutex_unlock(&pp_handle->pp_lock);
763         return 0;
764 }
765
766 static int pp_dpm_get_pp_table(void *handle, char **table)
767 {
768         struct pp_hwmgr *hwmgr;
769         struct pp_instance *pp_handle = (struct pp_instance *)handle;
770         int ret = 0;
771         int size = 0;
772
773         ret = pp_check(pp_handle);
774
775         if (ret != 0)
776                 return ret;
777
778         hwmgr = pp_handle->hwmgr;
779
780         if (!hwmgr->soft_pp_table)
781                 return -EINVAL;
782
783         mutex_lock(&pp_handle->pp_lock);
784         *table = (char *)hwmgr->soft_pp_table;
785         size = hwmgr->soft_pp_table_size;
786         mutex_unlock(&pp_handle->pp_lock);
787         return size;
788 }
789
790 static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
791 {
792         struct pp_hwmgr *hwmgr;
793         struct pp_instance *pp_handle = (struct pp_instance *)handle;
794         int ret = 0;
795
796         ret = pp_check(pp_handle);
797
798         if (ret != 0)
799                 return ret;
800
801         hwmgr = pp_handle->hwmgr;
802         mutex_lock(&pp_handle->pp_lock);
803         if (!hwmgr->hardcode_pp_table) {
804                 hwmgr->hardcode_pp_table = kmemdup(hwmgr->soft_pp_table,
805                                                    hwmgr->soft_pp_table_size,
806                                                    GFP_KERNEL);
807                 if (!hwmgr->hardcode_pp_table) {
808                         mutex_unlock(&pp_handle->pp_lock);
809                         return -ENOMEM;
810                 }
811         }
812
813         memcpy(hwmgr->hardcode_pp_table, buf, size);
814
815         hwmgr->soft_pp_table = hwmgr->hardcode_pp_table;
816         mutex_unlock(&pp_handle->pp_lock);
817
818         ret = amd_powerplay_reset(handle);
819         if (ret)
820                 return ret;
821
822         if (hwmgr->hwmgr_func->avfs_control) {
823                 ret = hwmgr->hwmgr_func->avfs_control(hwmgr, false);
824                 if (ret)
825                         return ret;
826         }
827
828         return 0;
829 }
830
831 static int pp_dpm_force_clock_level(void *handle,
832                 enum pp_clock_type type, uint32_t mask)
833 {
834         struct pp_hwmgr *hwmgr;
835         struct pp_instance *pp_handle = (struct pp_instance *)handle;
836         int ret = 0;
837
838         ret = pp_check(pp_handle);
839
840         if (ret != 0)
841                 return ret;
842
843         hwmgr = pp_handle->hwmgr;
844
845         if (hwmgr->hwmgr_func->force_clock_level == NULL) {
846                 pr_info("%s was not implemented.\n", __func__);
847                 return 0;
848         }
849         mutex_lock(&pp_handle->pp_lock);
850         hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
851         mutex_unlock(&pp_handle->pp_lock);
852         return ret;
853 }
854
855 static int pp_dpm_print_clock_levels(void *handle,
856                 enum pp_clock_type type, char *buf)
857 {
858         struct pp_hwmgr *hwmgr;
859         struct pp_instance *pp_handle = (struct pp_instance *)handle;
860         int ret = 0;
861
862         ret = pp_check(pp_handle);
863
864         if (ret != 0)
865                 return ret;
866
867         hwmgr = pp_handle->hwmgr;
868
869         if (hwmgr->hwmgr_func->print_clock_levels == NULL) {
870                 pr_info("%s was not implemented.\n", __func__);
871                 return 0;
872         }
873         mutex_lock(&pp_handle->pp_lock);
874         ret = hwmgr->hwmgr_func->print_clock_levels(hwmgr, type, buf);
875         mutex_unlock(&pp_handle->pp_lock);
876         return ret;
877 }
878
879 static int pp_dpm_get_sclk_od(void *handle)
880 {
881         struct pp_hwmgr *hwmgr;
882         struct pp_instance *pp_handle = (struct pp_instance *)handle;
883         int ret = 0;
884
885         ret = pp_check(pp_handle);
886
887         if (ret != 0)
888                 return ret;
889
890         hwmgr = pp_handle->hwmgr;
891
892         if (hwmgr->hwmgr_func->get_sclk_od == NULL) {
893                 pr_info("%s was not implemented.\n", __func__);
894                 return 0;
895         }
896         mutex_lock(&pp_handle->pp_lock);
897         ret = hwmgr->hwmgr_func->get_sclk_od(hwmgr);
898         mutex_unlock(&pp_handle->pp_lock);
899         return ret;
900 }
901
902 static int pp_dpm_set_sclk_od(void *handle, uint32_t value)
903 {
904         struct pp_hwmgr *hwmgr;
905         struct pp_instance *pp_handle = (struct pp_instance *)handle;
906         int ret = 0;
907
908         ret = pp_check(pp_handle);
909
910         if (ret != 0)
911                 return ret;
912
913         hwmgr = pp_handle->hwmgr;
914
915         if (hwmgr->hwmgr_func->set_sclk_od == NULL) {
916                 pr_info("%s was not implemented.\n", __func__);
917                 return 0;
918         }
919
920         mutex_lock(&pp_handle->pp_lock);
921         ret = hwmgr->hwmgr_func->set_sclk_od(hwmgr, value);
922         mutex_unlock(&pp_handle->pp_lock);
923         return ret;
924 }
925
926 static int pp_dpm_get_mclk_od(void *handle)
927 {
928         struct pp_hwmgr *hwmgr;
929         struct pp_instance *pp_handle = (struct pp_instance *)handle;
930         int ret = 0;
931
932         ret = pp_check(pp_handle);
933
934         if (ret != 0)
935                 return ret;
936
937         hwmgr = pp_handle->hwmgr;
938
939         if (hwmgr->hwmgr_func->get_mclk_od == NULL) {
940                 pr_info("%s was not implemented.\n", __func__);
941                 return 0;
942         }
943         mutex_lock(&pp_handle->pp_lock);
944         ret = hwmgr->hwmgr_func->get_mclk_od(hwmgr);
945         mutex_unlock(&pp_handle->pp_lock);
946         return ret;
947 }
948
949 static int pp_dpm_set_mclk_od(void *handle, uint32_t value)
950 {
951         struct pp_hwmgr *hwmgr;
952         struct pp_instance *pp_handle = (struct pp_instance *)handle;
953         int ret = 0;
954
955         ret = pp_check(pp_handle);
956
957         if (ret != 0)
958                 return ret;
959
960         hwmgr = pp_handle->hwmgr;
961
962         if (hwmgr->hwmgr_func->set_mclk_od == NULL) {
963                 pr_info("%s was not implemented.\n", __func__);
964                 return 0;
965         }
966         mutex_lock(&pp_handle->pp_lock);
967         ret = hwmgr->hwmgr_func->set_mclk_od(hwmgr, value);
968         mutex_unlock(&pp_handle->pp_lock);
969         return ret;
970 }
971
972 static int pp_dpm_read_sensor(void *handle, int idx,
973                               void *value, int *size)
974 {
975         struct pp_hwmgr *hwmgr;
976         struct pp_instance *pp_handle = (struct pp_instance *)handle;
977         int ret = 0;
978
979         ret = pp_check(pp_handle);
980
981         if (ret != 0)
982                 return ret;
983
984         hwmgr = pp_handle->hwmgr;
985
986         if (hwmgr->hwmgr_func->read_sensor == NULL) {
987                 pr_info("%s was not implemented.\n", __func__);
988                 return 0;
989         }
990
991         mutex_lock(&pp_handle->pp_lock);
992         ret = hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value, size);
993         mutex_unlock(&pp_handle->pp_lock);
994
995         return ret;
996 }
997
998 static struct amd_vce_state*
999 pp_dpm_get_vce_clock_state(void *handle, unsigned idx)
1000 {
1001         struct pp_hwmgr *hwmgr;
1002         struct pp_instance *pp_handle = (struct pp_instance *)handle;
1003         int ret = 0;
1004
1005         ret = pp_check(pp_handle);
1006
1007         if (ret != 0)
1008                 return NULL;
1009
1010         hwmgr = pp_handle->hwmgr;
1011
1012         if (hwmgr && idx < hwmgr->num_vce_state_tables)
1013                 return &hwmgr->vce_states[idx];
1014         return NULL;
1015 }
1016
1017 static int pp_dpm_reset_power_profile_state(void *handle,
1018                 struct amd_pp_profile *request)
1019 {
1020         struct pp_hwmgr *hwmgr;
1021         struct pp_instance *pp_handle = (struct pp_instance *)handle;
1022
1023         if (!request || pp_check(pp_handle))
1024                 return -EINVAL;
1025
1026         hwmgr = pp_handle->hwmgr;
1027
1028         if (hwmgr->hwmgr_func->set_power_profile_state == NULL) {
1029                 pr_info("%s was not implemented.\n", __func__);
1030                 return 0;
1031         }
1032
1033         if (request->type == AMD_PP_GFX_PROFILE) {
1034                 hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile;
1035                 return hwmgr->hwmgr_func->set_power_profile_state(hwmgr,
1036                                 &hwmgr->gfx_power_profile);
1037         } else if (request->type == AMD_PP_COMPUTE_PROFILE) {
1038                 hwmgr->compute_power_profile =
1039                                 hwmgr->default_compute_power_profile;
1040                 return hwmgr->hwmgr_func->set_power_profile_state(hwmgr,
1041                                 &hwmgr->compute_power_profile);
1042         } else
1043                 return -EINVAL;
1044 }
1045
1046 static int pp_dpm_get_power_profile_state(void *handle,
1047                 struct amd_pp_profile *query)
1048 {
1049         struct pp_hwmgr *hwmgr;
1050         struct pp_instance *pp_handle = (struct pp_instance *)handle;
1051
1052         if (!query || pp_check(pp_handle))
1053                 return -EINVAL;
1054
1055         hwmgr = pp_handle->hwmgr;
1056
1057         if (query->type == AMD_PP_GFX_PROFILE)
1058                 memcpy(query, &hwmgr->gfx_power_profile,
1059                                 sizeof(struct amd_pp_profile));
1060         else if (query->type == AMD_PP_COMPUTE_PROFILE)
1061                 memcpy(query, &hwmgr->compute_power_profile,
1062                                 sizeof(struct amd_pp_profile));
1063         else
1064                 return -EINVAL;
1065
1066         return 0;
1067 }
1068
1069 static int pp_dpm_set_power_profile_state(void *handle,
1070                 struct amd_pp_profile *request)
1071 {
1072         struct pp_hwmgr *hwmgr;
1073         struct pp_instance *pp_handle = (struct pp_instance *)handle;
1074         int ret = -1;
1075
1076         if (!request || pp_check(pp_handle))
1077                 return -EINVAL;
1078
1079         hwmgr = pp_handle->hwmgr;
1080
1081         if (hwmgr->hwmgr_func->set_power_profile_state == NULL) {
1082                 pr_info("%s was not implemented.\n", __func__);
1083                 return 0;
1084         }
1085
1086         if (request->min_sclk ||
1087                 request->min_mclk ||
1088                 request->activity_threshold ||
1089                 request->up_hyst ||
1090                 request->down_hyst) {
1091                 if (request->type == AMD_PP_GFX_PROFILE)
1092                         memcpy(&hwmgr->gfx_power_profile, request,
1093                                         sizeof(struct amd_pp_profile));
1094                 else if (request->type == AMD_PP_COMPUTE_PROFILE)
1095                         memcpy(&hwmgr->compute_power_profile, request,
1096                                         sizeof(struct amd_pp_profile));
1097                 else
1098                         return -EINVAL;
1099
1100                 if (request->type == hwmgr->current_power_profile)
1101                         ret = hwmgr->hwmgr_func->set_power_profile_state(
1102                                         hwmgr,
1103                                         request);
1104         } else {
1105                 /* set power profile if it exists */
1106                 switch (request->type) {
1107                 case AMD_PP_GFX_PROFILE:
1108                         ret = hwmgr->hwmgr_func->set_power_profile_state(
1109                                         hwmgr,
1110                                         &hwmgr->gfx_power_profile);
1111                         break;
1112                 case AMD_PP_COMPUTE_PROFILE:
1113                         ret = hwmgr->hwmgr_func->set_power_profile_state(
1114                                         hwmgr,
1115                                         &hwmgr->compute_power_profile);
1116                         break;
1117                 default:
1118                         return -EINVAL;
1119                 }
1120         }
1121
1122         if (!ret)
1123                 hwmgr->current_power_profile = request->type;
1124
1125         return 0;
1126 }
1127
1128 static int pp_dpm_switch_power_profile(void *handle,
1129                 enum amd_pp_profile_type type)
1130 {
1131         struct pp_hwmgr *hwmgr;
1132         struct amd_pp_profile request = {0};
1133         struct pp_instance *pp_handle = (struct pp_instance *)handle;
1134
1135         if (pp_check(pp_handle))
1136                 return -EINVAL;
1137
1138         hwmgr = pp_handle->hwmgr;
1139
1140         if (hwmgr->current_power_profile != type) {
1141                 request.type = type;
1142                 pp_dpm_set_power_profile_state(handle, &request);
1143         }
1144
1145         return 0;
1146 }
1147
1148 const struct amd_pm_funcs pp_dpm_funcs = {
1149         .get_temperature = pp_dpm_get_temperature,
1150         .load_firmware = pp_dpm_load_fw,
1151         .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
1152         .force_performance_level = pp_dpm_force_performance_level,
1153         .get_performance_level = pp_dpm_get_performance_level,
1154         .get_current_power_state = pp_dpm_get_current_power_state,
1155         .get_sclk = pp_dpm_get_sclk,
1156         .get_mclk = pp_dpm_get_mclk,
1157         .powergate_vce = pp_dpm_powergate_vce,
1158         .powergate_uvd = pp_dpm_powergate_uvd,
1159         .dispatch_tasks = pp_dpm_dispatch_tasks,
1160         .set_fan_control_mode = pp_dpm_set_fan_control_mode,
1161         .get_fan_control_mode = pp_dpm_get_fan_control_mode,
1162         .set_fan_speed_percent = pp_dpm_set_fan_speed_percent,
1163         .get_fan_speed_percent = pp_dpm_get_fan_speed_percent,
1164         .get_fan_speed_rpm = pp_dpm_get_fan_speed_rpm,
1165         .get_pp_num_states = pp_dpm_get_pp_num_states,
1166         .get_pp_table = pp_dpm_get_pp_table,
1167         .set_pp_table = pp_dpm_set_pp_table,
1168         .force_clock_level = pp_dpm_force_clock_level,
1169         .print_clock_levels = pp_dpm_print_clock_levels,
1170         .get_sclk_od = pp_dpm_get_sclk_od,
1171         .set_sclk_od = pp_dpm_set_sclk_od,
1172         .get_mclk_od = pp_dpm_get_mclk_od,
1173         .set_mclk_od = pp_dpm_set_mclk_od,
1174         .read_sensor = pp_dpm_read_sensor,
1175         .get_vce_clock_state = pp_dpm_get_vce_clock_state,
1176         .reset_power_profile_state = pp_dpm_reset_power_profile_state,
1177         .get_power_profile_state = pp_dpm_get_power_profile_state,
1178         .set_power_profile_state = pp_dpm_set_power_profile_state,
1179         .switch_power_profile = pp_dpm_switch_power_profile,
1180 };
1181
1182 int amd_powerplay_reset(void *handle)
1183 {
1184         struct pp_instance *instance = (struct pp_instance *)handle;
1185         int ret;
1186
1187         ret = pp_check(instance);
1188         if (ret != 0)
1189                 return ret;
1190
1191         ret = pp_hw_fini(instance);
1192         if (ret)
1193                 return ret;
1194
1195         ret = hwmgr_hw_init(instance);
1196         if (ret)
1197                 return ret;
1198
1199         return hwmgr_handle_task(instance, AMD_PP_TASK_COMPLETE_INIT, NULL, NULL);
1200 }
1201
1202 /* export this function to DAL */
1203
1204 int amd_powerplay_display_configuration_change(void *handle,
1205         const struct amd_pp_display_configuration *display_config)
1206 {
1207         struct pp_hwmgr  *hwmgr;
1208         struct pp_instance *pp_handle = (struct pp_instance *)handle;
1209         int ret = 0;
1210
1211         ret = pp_check(pp_handle);
1212
1213         if (ret != 0)
1214                 return ret;
1215
1216         hwmgr = pp_handle->hwmgr;
1217         mutex_lock(&pp_handle->pp_lock);
1218         phm_store_dal_configuration_data(hwmgr, display_config);
1219         mutex_unlock(&pp_handle->pp_lock);
1220         return 0;
1221 }
1222
1223 int amd_powerplay_get_display_power_level(void *handle,
1224                 struct amd_pp_simple_clock_info *output)
1225 {
1226         struct pp_hwmgr  *hwmgr;
1227         struct pp_instance *pp_handle = (struct pp_instance *)handle;
1228         int ret = 0;
1229
1230         ret = pp_check(pp_handle);
1231
1232         if (ret != 0)
1233                 return ret;
1234
1235         hwmgr = pp_handle->hwmgr;
1236
1237         if (output == NULL)
1238                 return -EINVAL;
1239
1240         mutex_lock(&pp_handle->pp_lock);
1241         ret = phm_get_dal_power_level(hwmgr, output);
1242         mutex_unlock(&pp_handle->pp_lock);
1243         return ret;
1244 }
1245
1246 int amd_powerplay_get_current_clocks(void *handle,
1247                 struct amd_pp_clock_info *clocks)
1248 {
1249         struct amd_pp_simple_clock_info simple_clocks;
1250         struct pp_clock_info hw_clocks;
1251         struct pp_hwmgr  *hwmgr;
1252         struct pp_instance *pp_handle = (struct pp_instance *)handle;
1253         int ret = 0;
1254
1255         ret = pp_check(pp_handle);
1256
1257         if (ret != 0)
1258                 return ret;
1259
1260         hwmgr = pp_handle->hwmgr;
1261
1262         mutex_lock(&pp_handle->pp_lock);
1263
1264         phm_get_dal_power_level(hwmgr, &simple_clocks);
1265
1266         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1267                                         PHM_PlatformCaps_PowerContainment))
1268                 ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware,
1269                                         &hw_clocks, PHM_PerformanceLevelDesignation_PowerContainment);
1270         else
1271                 ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware,
1272                                         &hw_clocks, PHM_PerformanceLevelDesignation_Activity);
1273
1274         if (ret != 0) {
1275                 pr_info("Error in phm_get_clock_info \n");
1276                 mutex_unlock(&pp_handle->pp_lock);
1277                 return -EINVAL;
1278         }
1279
1280         clocks->min_engine_clock = hw_clocks.min_eng_clk;
1281         clocks->max_engine_clock = hw_clocks.max_eng_clk;
1282         clocks->min_memory_clock = hw_clocks.min_mem_clk;
1283         clocks->max_memory_clock = hw_clocks.max_mem_clk;
1284         clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1285         clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1286
1287         clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1288         clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1289
1290         clocks->max_clocks_state = simple_clocks.level;
1291
1292         if (0 == phm_get_current_shallow_sleep_clocks(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks)) {
1293                 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1294                 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1295         }
1296         mutex_unlock(&pp_handle->pp_lock);
1297         return 0;
1298 }
1299
1300 int amd_powerplay_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
1301 {
1302         struct pp_hwmgr  *hwmgr;
1303         struct pp_instance *pp_handle = (struct pp_instance *)handle;
1304         int ret = 0;
1305
1306         ret = pp_check(pp_handle);
1307
1308         if (ret != 0)
1309                 return ret;
1310
1311         hwmgr = pp_handle->hwmgr;
1312
1313         if (clocks == NULL)
1314                 return -EINVAL;
1315
1316         mutex_lock(&pp_handle->pp_lock);
1317         ret = phm_get_clock_by_type(hwmgr, type, clocks);
1318         mutex_unlock(&pp_handle->pp_lock);
1319         return ret;
1320 }
1321
1322 int amd_powerplay_get_clock_by_type_with_latency(void *handle,
1323                 enum amd_pp_clock_type type,
1324                 struct pp_clock_levels_with_latency *clocks)
1325 {
1326         struct pp_hwmgr *hwmgr;
1327         struct pp_instance *pp_handle = (struct pp_instance *)handle;
1328         int ret = 0;
1329
1330         ret = pp_check(pp_handle);
1331         if (ret != 0)
1332                 return ret;
1333
1334         if (!clocks)
1335                 return -EINVAL;
1336
1337         mutex_lock(&pp_handle->pp_lock);
1338         hwmgr = ((struct pp_instance *)handle)->hwmgr;
1339         ret = phm_get_clock_by_type_with_latency(hwmgr, type, clocks);
1340         mutex_unlock(&pp_handle->pp_lock);
1341         return ret;
1342 }
1343
1344 int amd_powerplay_get_clock_by_type_with_voltage(void *handle,
1345                 enum amd_pp_clock_type type,
1346                 struct pp_clock_levels_with_voltage *clocks)
1347 {
1348         struct pp_hwmgr *hwmgr;
1349         struct pp_instance *pp_handle = (struct pp_instance *)handle;
1350         int ret = 0;
1351
1352         ret = pp_check(pp_handle);
1353         if (ret != 0)
1354                 return ret;
1355
1356         if (!clocks)
1357                 return -EINVAL;
1358
1359         hwmgr = ((struct pp_instance *)handle)->hwmgr;
1360
1361         mutex_lock(&pp_handle->pp_lock);
1362
1363         ret = phm_get_clock_by_type_with_voltage(hwmgr, type, clocks);
1364
1365         mutex_unlock(&pp_handle->pp_lock);
1366         return ret;
1367 }
1368
1369 int amd_powerplay_set_watermarks_for_clocks_ranges(void *handle,
1370                 struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
1371 {
1372         struct pp_hwmgr *hwmgr;
1373         struct pp_instance *pp_handle = (struct pp_instance *)handle;
1374         int ret = 0;
1375
1376         ret = pp_check(pp_handle);
1377         if (ret != 0)
1378                 return ret;
1379
1380         if (!wm_with_clock_ranges)
1381                 return -EINVAL;
1382
1383         hwmgr = ((struct pp_instance *)handle)->hwmgr;
1384
1385         mutex_lock(&pp_handle->pp_lock);
1386         ret = phm_set_watermarks_for_clocks_ranges(hwmgr,
1387                         wm_with_clock_ranges);
1388         mutex_unlock(&pp_handle->pp_lock);
1389
1390         return ret;
1391 }
1392
1393 int amd_powerplay_display_clock_voltage_request(void *handle,
1394                 struct pp_display_clock_request *clock)
1395 {
1396         struct pp_hwmgr *hwmgr;
1397         struct pp_instance *pp_handle = (struct pp_instance *)handle;
1398         int ret = 0;
1399
1400         ret = pp_check(pp_handle);
1401         if (ret != 0)
1402                 return ret;
1403
1404         if (!clock)
1405                 return -EINVAL;
1406
1407         hwmgr = ((struct pp_instance *)handle)->hwmgr;
1408
1409         mutex_lock(&pp_handle->pp_lock);
1410         ret = phm_display_clock_voltage_request(hwmgr, clock);
1411         mutex_unlock(&pp_handle->pp_lock);
1412
1413         return ret;
1414 }
1415
1416 int amd_powerplay_get_display_mode_validation_clocks(void *handle,
1417                 struct amd_pp_simple_clock_info *clocks)
1418 {
1419         struct pp_hwmgr  *hwmgr;
1420         struct pp_instance *pp_handle = (struct pp_instance *)handle;
1421         int ret = 0;
1422
1423         ret = pp_check(pp_handle);
1424
1425         if (ret != 0)
1426                 return ret;
1427
1428         hwmgr = pp_handle->hwmgr;
1429
1430         if (clocks == NULL)
1431                 return -EINVAL;
1432
1433         mutex_lock(&pp_handle->pp_lock);
1434
1435         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState))
1436                 ret = phm_get_max_high_clocks(hwmgr, clocks);
1437
1438         mutex_unlock(&pp_handle->pp_lock);
1439         return ret;
1440 }
1441