drm/amd/powerplay: delete dead code in hwmgr.h
[muen/linux.git] / drivers / gpu / drm / amd / powerplay / inc / hwmgr.h
1 /*
2  * Copyright 2015 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #ifndef _HWMGR_H_
24 #define _HWMGR_H_
25
26 #include <linux/seq_file.h>
27 #include "amd_powerplay.h"
28 #include "pp_instance.h"
29 #include "hardwaremanager.h"
30 #include "pp_power_source.h"
31 #include "hwmgr_ppt.h"
32 #include "ppatomctrl.h"
33 #include "hwmgr_ppt.h"
34 #include "power_state.h"
35 #include "cgs_linux.h"
36
37 struct pp_instance;
38 struct pp_hwmgr;
39 struct phm_fan_speed_info;
40 struct pp_atomctrl_voltage_table;
41
42 #define VOLTAGE_SCALE 4
43
44 uint8_t convert_to_vid(uint16_t vddc);
45
46 enum DISPLAY_GAP {
47         DISPLAY_GAP_VBLANK_OR_WM = 0,   /* Wait for vblank or MCHG watermark. */
48         DISPLAY_GAP_VBLANK       = 1,   /* Wait for vblank. */
49         DISPLAY_GAP_WATERMARK    = 2,   /* Wait for MCHG watermark. (Note that HW may deassert WM in VBI depending on DC_STUTTER_CNTL.) */
50         DISPLAY_GAP_IGNORE       = 3    /* Do not wait. */
51 };
52 typedef enum DISPLAY_GAP DISPLAY_GAP;
53
54 struct vi_dpm_level {
55         bool enabled;
56         uint32_t value;
57         uint32_t param1;
58 };
59
60 struct vi_dpm_table {
61         uint32_t count;
62         struct vi_dpm_level dpm_level[1];
63 };
64
65 #define PCIE_PERF_REQ_REMOVE_REGISTRY   0
66 #define PCIE_PERF_REQ_FORCE_LOWPOWER    1
67 #define PCIE_PERF_REQ_GEN1         2
68 #define PCIE_PERF_REQ_GEN2         3
69 #define PCIE_PERF_REQ_GEN3         4
70
71 enum PP_FEATURE_MASK {
72         PP_SCLK_DPM_MASK = 0x1,
73         PP_MCLK_DPM_MASK = 0x2,
74         PP_PCIE_DPM_MASK = 0x4,
75         PP_SCLK_DEEP_SLEEP_MASK = 0x8,
76         PP_POWER_CONTAINMENT_MASK = 0x10,
77         PP_UVD_HANDSHAKE_MASK = 0x20,
78         PP_SMC_VOLTAGE_CONTROL_MASK = 0x40,
79         PP_VBI_TIME_SUPPORT_MASK = 0x80,
80         PP_ULV_MASK = 0x100,
81         PP_ENABLE_GFX_CG_THRU_SMU = 0x200,
82         PP_CLOCK_STRETCH_MASK = 0x400,
83         PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800,
84         PP_SOCCLK_DPM_MASK = 0x1000,
85         PP_DCEFCLK_DPM_MASK = 0x2000,
86 };
87
88 enum PHM_BackEnd_Magic {
89         PHM_Dummy_Magic       = 0xAA5555AA,
90         PHM_RV770_Magic       = 0xDCBAABCD,
91         PHM_Kong_Magic        = 0x239478DF,
92         PHM_NIslands_Magic    = 0x736C494E,
93         PHM_Sumo_Magic        = 0x8339FA11,
94         PHM_SIslands_Magic    = 0x369431AC,
95         PHM_Trinity_Magic     = 0x96751873,
96         PHM_CIslands_Magic    = 0x38AC78B0,
97         PHM_Kv_Magic          = 0xDCBBABC0,
98         PHM_VIslands_Magic    = 0x20130307,
99         PHM_Cz_Magic          = 0x67DCBA25,
100         PHM_Rv_Magic          = 0x20161121
101 };
102
103 struct phm_set_power_state_input {
104         const struct pp_hw_power_state *pcurrent_state;
105         const struct pp_hw_power_state *pnew_state;
106 };
107
108 struct phm_acp_arbiter {
109         uint32_t acpclk;
110 };
111
112 struct phm_uvd_arbiter {
113         uint32_t vclk;
114         uint32_t dclk;
115         uint32_t vclk_ceiling;
116         uint32_t dclk_ceiling;
117         uint32_t vclk_soft_min;
118         uint32_t dclk_soft_min;
119 };
120
121 struct phm_vce_arbiter {
122         uint32_t   evclk;
123         uint32_t   ecclk;
124 };
125
126 struct phm_gfx_arbiter {
127         uint32_t sclk;
128         uint32_t sclk_hard_min;
129         uint32_t mclk;
130         uint32_t sclk_over_drive;
131         uint32_t mclk_over_drive;
132         uint32_t sclk_threshold;
133         uint32_t num_cus;
134         uint32_t gfxclk;
135         uint32_t fclk;
136 };
137
138 struct phm_clock_array {
139         uint32_t count;
140         uint32_t values[1];
141 };
142
143 struct phm_clock_voltage_dependency_record {
144         uint32_t clk;
145         uint32_t v;
146 };
147
148 struct phm_vceclock_voltage_dependency_record {
149         uint32_t ecclk;
150         uint32_t evclk;
151         uint32_t v;
152 };
153
154 struct phm_uvdclock_voltage_dependency_record {
155         uint32_t vclk;
156         uint32_t dclk;
157         uint32_t v;
158 };
159
160 struct phm_samuclock_voltage_dependency_record {
161         uint32_t samclk;
162         uint32_t v;
163 };
164
165 struct phm_acpclock_voltage_dependency_record {
166         uint32_t acpclk;
167         uint32_t v;
168 };
169
170 struct phm_clock_voltage_dependency_table {
171         uint32_t count;                                                                         /* Number of entries. */
172         struct phm_clock_voltage_dependency_record entries[1];          /* Dynamically allocate count entries. */
173 };
174
175 struct phm_phase_shedding_limits_record {
176         uint32_t  Voltage;
177         uint32_t    Sclk;
178         uint32_t    Mclk;
179 };
180
181 struct phm_uvd_clock_voltage_dependency_record {
182         uint32_t vclk;
183         uint32_t dclk;
184         uint32_t v;
185 };
186
187 struct phm_uvd_clock_voltage_dependency_table {
188         uint8_t count;
189         struct phm_uvd_clock_voltage_dependency_record entries[1];
190 };
191
192 struct phm_acp_clock_voltage_dependency_record {
193         uint32_t acpclk;
194         uint32_t v;
195 };
196
197 struct phm_acp_clock_voltage_dependency_table {
198         uint32_t count;
199         struct phm_acp_clock_voltage_dependency_record entries[1];
200 };
201
202 struct phm_vce_clock_voltage_dependency_record {
203         uint32_t ecclk;
204         uint32_t evclk;
205         uint32_t v;
206 };
207
208 struct phm_phase_shedding_limits_table {
209         uint32_t                           count;
210         struct phm_phase_shedding_limits_record  entries[1];
211 };
212
213 struct phm_vceclock_voltage_dependency_table {
214         uint8_t count;                                    /* Number of entries. */
215         struct phm_vceclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
216 };
217
218 struct phm_uvdclock_voltage_dependency_table {
219         uint8_t count;                                    /* Number of entries. */
220         struct phm_uvdclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
221 };
222
223 struct phm_samuclock_voltage_dependency_table {
224         uint8_t count;                                    /* Number of entries. */
225         struct phm_samuclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
226 };
227
228 struct phm_acpclock_voltage_dependency_table {
229         uint32_t count;                                    /* Number of entries. */
230         struct phm_acpclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
231 };
232
233 struct phm_vce_clock_voltage_dependency_table {
234         uint8_t count;
235         struct phm_vce_clock_voltage_dependency_record entries[1];
236 };
237
238 struct pp_hwmgr_func {
239         int (*backend_init)(struct pp_hwmgr *hw_mgr);
240         int (*backend_fini)(struct pp_hwmgr *hw_mgr);
241         int (*asic_setup)(struct pp_hwmgr *hw_mgr);
242         int (*get_power_state_size)(struct pp_hwmgr *hw_mgr);
243
244         int (*apply_state_adjust_rules)(struct pp_hwmgr *hwmgr,
245                                 struct pp_power_state  *prequest_ps,
246                         const struct pp_power_state *pcurrent_ps);
247
248         int (*force_dpm_level)(struct pp_hwmgr *hw_mgr,
249                                         enum amd_dpm_forced_level level);
250
251         int (*dynamic_state_management_enable)(
252                                                 struct pp_hwmgr *hw_mgr);
253         int (*dynamic_state_management_disable)(
254                                                 struct pp_hwmgr *hw_mgr);
255
256         int (*patch_boot_state)(struct pp_hwmgr *hwmgr,
257                                      struct pp_hw_power_state *hw_ps);
258
259         int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr,
260                             unsigned long, struct pp_power_state *);
261         int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr);
262         int (*powerdown_uvd)(struct pp_hwmgr *hwmgr);
263         void (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate);
264         void (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate);
265         uint32_t (*get_mclk)(struct pp_hwmgr *hwmgr, bool low);
266         uint32_t (*get_sclk)(struct pp_hwmgr *hwmgr, bool low);
267         int (*power_state_set)(struct pp_hwmgr *hwmgr,
268                                                 const void *state);
269         int (*enable_clock_power_gating)(struct pp_hwmgr *hwmgr);
270         int (*notify_smc_display_config_after_ps_adjustment)(struct pp_hwmgr *hwmgr);
271         int (*display_config_changed)(struct pp_hwmgr *hwmgr);
272         int (*disable_clock_power_gating)(struct pp_hwmgr *hwmgr);
273         int (*update_clock_gatings)(struct pp_hwmgr *hwmgr,
274                                                 const uint32_t *msg_id);
275         int (*set_max_fan_rpm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
276         int (*set_max_fan_pwm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
277         int (*get_temperature)(struct pp_hwmgr *hwmgr);
278         int (*stop_thermal_controller)(struct pp_hwmgr *hwmgr);
279         int (*get_fan_speed_info)(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
280         void (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode);
281         uint32_t (*get_fan_control_mode)(struct pp_hwmgr *hwmgr);
282         int (*set_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t percent);
283         int (*get_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t *speed);
284         int (*set_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t percent);
285         int (*get_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t *speed);
286         int (*reset_fan_speed_to_default)(struct pp_hwmgr *hwmgr);
287         int (*uninitialize_thermal_controller)(struct pp_hwmgr *hwmgr);
288         int (*register_internal_thermal_interrupt)(struct pp_hwmgr *hwmgr,
289                                         const void *thermal_interrupt_info);
290         bool (*check_smc_update_required_for_display_configuration)(struct pp_hwmgr *hwmgr);
291         int (*check_states_equal)(struct pp_hwmgr *hwmgr,
292                                         const struct pp_hw_power_state *pstate1,
293                                         const struct pp_hw_power_state *pstate2,
294                                         bool *equal);
295         int (*set_cpu_power_state)(struct pp_hwmgr *hwmgr);
296         int (*store_cc6_data)(struct pp_hwmgr *hwmgr, uint32_t separation_time,
297                                 bool cc6_disable, bool pstate_disable,
298                                 bool pstate_switch_disable);
299         int (*get_dal_power_level)(struct pp_hwmgr *hwmgr,
300                         struct amd_pp_simple_clock_info *info);
301         int (*get_performance_level)(struct pp_hwmgr *, const struct pp_hw_power_state *,
302                         PHM_PerformanceLevelDesignation, uint32_t, PHM_PerformanceLevel *);
303         int (*get_current_shallow_sleep_clocks)(struct pp_hwmgr *hwmgr,
304                                 const struct pp_hw_power_state *state, struct pp_clock_info *clock_info);
305         int (*get_clock_by_type)(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
306         int (*get_clock_by_type_with_latency)(struct pp_hwmgr *hwmgr,
307                         enum amd_pp_clock_type type,
308                         struct pp_clock_levels_with_latency *clocks);
309         int (*get_clock_by_type_with_voltage)(struct pp_hwmgr *hwmgr,
310                         enum amd_pp_clock_type type,
311                         struct pp_clock_levels_with_voltage *clocks);
312         int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr,
313                         struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
314         int (*display_clock_voltage_request)(struct pp_hwmgr *hwmgr,
315                         struct pp_display_clock_request *clock);
316         int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
317         int (*power_off_asic)(struct pp_hwmgr *hwmgr);
318         int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask);
319         int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf);
320         int (*enable_per_cu_power_gating)(struct pp_hwmgr *hwmgr, bool enable);
321         int (*get_sclk_od)(struct pp_hwmgr *hwmgr);
322         int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
323         int (*get_mclk_od)(struct pp_hwmgr *hwmgr);
324         int (*set_mclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
325         int (*read_sensor)(struct pp_hwmgr *hwmgr, int idx, void *value, int *size);
326         int (*set_power_profile_state)(struct pp_hwmgr *hwmgr,
327                         struct amd_pp_profile *request);
328         int (*avfs_control)(struct pp_hwmgr *hwmgr, bool enable);
329         int (*disable_smc_firmware_ctf)(struct pp_hwmgr *hwmgr);
330         int (*set_active_display_count)(struct pp_hwmgr *hwmgr, uint32_t count);
331         int (*set_deep_sleep_dcefclk)(struct pp_hwmgr *hwmgr, uint32_t clock);
332         int (*start_thermal_controller)(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *range);
333 };
334
335 struct pp_table_func {
336         int (*pptable_init)(struct pp_hwmgr *hw_mgr);
337         int (*pptable_fini)(struct pp_hwmgr *hw_mgr);
338         int (*pptable_get_number_of_vce_state_table_entries)(struct pp_hwmgr *hw_mgr);
339         int (*pptable_get_vce_state_table_entry)(
340                                                 struct pp_hwmgr *hwmgr,
341                                                 unsigned long i,
342                                                 struct amd_vce_state *vce_state,
343                                                 void **clock_info,
344                                                 unsigned long *flag);
345 };
346
347 union phm_cac_leakage_record {
348         struct {
349                 uint16_t Vddc;          /* in CI, we use it for StdVoltageHiSidd */
350                 uint32_t Leakage;       /* in CI, we use it for StdVoltageLoSidd */
351         };
352         struct {
353                 uint16_t Vddc1;
354                 uint16_t Vddc2;
355                 uint16_t Vddc3;
356         };
357 };
358
359 struct phm_cac_leakage_table {
360         uint32_t count;
361         union phm_cac_leakage_record entries[1];
362 };
363
364 struct phm_samu_clock_voltage_dependency_record {
365         uint32_t samclk;
366         uint32_t v;
367 };
368
369
370 struct phm_samu_clock_voltage_dependency_table {
371         uint8_t count;
372         struct phm_samu_clock_voltage_dependency_record entries[1];
373 };
374
375 struct phm_cac_tdp_table {
376         uint16_t usTDP;
377         uint16_t usConfigurableTDP;
378         uint16_t usTDC;
379         uint16_t usBatteryPowerLimit;
380         uint16_t usSmallPowerLimit;
381         uint16_t usLowCACLeakage;
382         uint16_t usHighCACLeakage;
383         uint16_t usMaximumPowerDeliveryLimit;
384         uint16_t usEDCLimit;
385         uint16_t usOperatingTempMinLimit;
386         uint16_t usOperatingTempMaxLimit;
387         uint16_t usOperatingTempStep;
388         uint16_t usOperatingTempHyst;
389         uint16_t usDefaultTargetOperatingTemp;
390         uint16_t usTargetOperatingTemp;
391         uint16_t usPowerTuneDataSetID;
392         uint16_t usSoftwareShutdownTemp;
393         uint16_t usClockStretchAmount;
394         uint16_t usTemperatureLimitHotspot;
395         uint16_t usTemperatureLimitLiquid1;
396         uint16_t usTemperatureLimitLiquid2;
397         uint16_t usTemperatureLimitVrVddc;
398         uint16_t usTemperatureLimitVrMvdd;
399         uint16_t usTemperatureLimitPlx;
400         uint8_t  ucLiquid1_I2C_address;
401         uint8_t  ucLiquid2_I2C_address;
402         uint8_t  ucLiquid_I2C_Line;
403         uint8_t  ucVr_I2C_address;
404         uint8_t  ucVr_I2C_Line;
405         uint8_t  ucPlx_I2C_address;
406         uint8_t  ucPlx_I2C_Line;
407         uint32_t usBoostPowerLimit;
408         uint8_t  ucCKS_LDO_REFSEL;
409 };
410
411 struct phm_tdp_table {
412         uint16_t usTDP;
413         uint16_t usConfigurableTDP;
414         uint16_t usTDC;
415         uint16_t usBatteryPowerLimit;
416         uint16_t usSmallPowerLimit;
417         uint16_t usLowCACLeakage;
418         uint16_t usHighCACLeakage;
419         uint16_t usMaximumPowerDeliveryLimit;
420         uint16_t usEDCLimit;
421         uint16_t usOperatingTempMinLimit;
422         uint16_t usOperatingTempMaxLimit;
423         uint16_t usOperatingTempStep;
424         uint16_t usOperatingTempHyst;
425         uint16_t usDefaultTargetOperatingTemp;
426         uint16_t usTargetOperatingTemp;
427         uint16_t usPowerTuneDataSetID;
428         uint16_t usSoftwareShutdownTemp;
429         uint16_t usClockStretchAmount;
430         uint16_t usTemperatureLimitTedge;
431         uint16_t usTemperatureLimitHotspot;
432         uint16_t usTemperatureLimitLiquid1;
433         uint16_t usTemperatureLimitLiquid2;
434         uint16_t usTemperatureLimitHBM;
435         uint16_t usTemperatureLimitVrVddc;
436         uint16_t usTemperatureLimitVrMvdd;
437         uint16_t usTemperatureLimitPlx;
438         uint8_t  ucLiquid1_I2C_address;
439         uint8_t  ucLiquid2_I2C_address;
440         uint8_t  ucLiquid_I2C_Line;
441         uint8_t  ucVr_I2C_address;
442         uint8_t  ucVr_I2C_Line;
443         uint8_t  ucPlx_I2C_address;
444         uint8_t  ucPlx_I2C_Line;
445         uint8_t  ucLiquid_I2C_LineSDA;
446         uint8_t  ucVr_I2C_LineSDA;
447         uint8_t  ucPlx_I2C_LineSDA;
448         uint32_t usBoostPowerLimit;
449         uint16_t usBoostStartTemperature;
450         uint16_t usBoostStopTemperature;
451         uint32_t  ulBoostClock;
452 };
453
454 struct phm_ppm_table {
455         uint8_t   ppm_design;
456         uint16_t  cpu_core_number;
457         uint32_t  platform_tdp;
458         uint32_t  small_ac_platform_tdp;
459         uint32_t  platform_tdc;
460         uint32_t  small_ac_platform_tdc;
461         uint32_t  apu_tdp;
462         uint32_t  dgpu_tdp;
463         uint32_t  dgpu_ulv_power;
464         uint32_t  tj_max;
465 };
466
467 struct phm_vq_budgeting_record {
468         uint32_t ulCUs;
469         uint32_t ulSustainableSOCPowerLimitLow;
470         uint32_t ulSustainableSOCPowerLimitHigh;
471         uint32_t ulMinSclkLow;
472         uint32_t ulMinSclkHigh;
473         uint8_t  ucDispConfig;
474         uint32_t ulDClk;
475         uint32_t ulEClk;
476         uint32_t ulSustainableSclk;
477         uint32_t ulSustainableCUs;
478 };
479
480 struct phm_vq_budgeting_table {
481         uint8_t numEntries;
482         struct phm_vq_budgeting_record entries[1];
483 };
484
485 struct phm_clock_and_voltage_limits {
486         uint32_t sclk;
487         uint32_t mclk;
488         uint32_t gfxclk;
489         uint16_t vddc;
490         uint16_t vddci;
491         uint16_t vddgfx;
492         uint16_t vddmem;
493 };
494
495 /* Structure to hold PPTable information */
496
497 struct phm_ppt_v1_information {
498         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
499         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
500         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
501         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
502         struct phm_clock_array *valid_sclk_values;
503         struct phm_clock_array *valid_mclk_values;
504         struct phm_clock_array *valid_socclk_values;
505         struct phm_clock_array *valid_dcefclk_values;
506         struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
507         struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
508         struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
509         struct phm_ppm_table *ppm_parameter_table;
510         struct phm_cac_tdp_table *cac_dtp_table;
511         struct phm_tdp_table *tdp_table;
512         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
513         struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
514         struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
515         struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
516         struct phm_ppt_v1_pcie_table *pcie_table;
517         struct phm_ppt_v1_gpio_table *gpio_table;
518         uint16_t us_ulv_voltage_offset;
519         uint16_t us_ulv_smnclk_did;
520         uint16_t us_ulv_mp1clk_did;
521         uint16_t us_ulv_gfxclk_bypass;
522         uint16_t us_gfxclk_slew_rate;
523         uint16_t us_min_gfxclk_freq_limit;
524 };
525
526 struct phm_ppt_v2_information {
527         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
528         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
529         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
530         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
531         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_pixclk;
532         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dispclk;
533         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_phyclk;
534         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
535
536         struct phm_clock_voltage_dependency_table *vddc_dep_on_dalpwrl;
537
538         struct phm_clock_array *valid_sclk_values;
539         struct phm_clock_array *valid_mclk_values;
540         struct phm_clock_array *valid_socclk_values;
541         struct phm_clock_array *valid_dcefclk_values;
542
543         struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
544         struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
545
546         struct phm_ppm_table *ppm_parameter_table;
547         struct phm_cac_tdp_table *cac_dtp_table;
548         struct phm_tdp_table *tdp_table;
549
550         struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
551         struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
552         struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
553         struct phm_ppt_v1_voltage_lookup_table *vddci_lookup_table;
554
555         struct phm_ppt_v1_pcie_table *pcie_table;
556
557         uint16_t us_ulv_voltage_offset;
558         uint16_t us_ulv_smnclk_did;
559         uint16_t us_ulv_mp1clk_did;
560         uint16_t us_ulv_gfxclk_bypass;
561         uint16_t us_gfxclk_slew_rate;
562         uint16_t us_min_gfxclk_freq_limit;
563
564         uint8_t  uc_gfx_dpm_voltage_mode;
565         uint8_t  uc_soc_dpm_voltage_mode;
566         uint8_t  uc_uclk_dpm_voltage_mode;
567         uint8_t  uc_uvd_dpm_voltage_mode;
568         uint8_t  uc_vce_dpm_voltage_mode;
569         uint8_t  uc_mp0_dpm_voltage_mode;
570         uint8_t  uc_dcef_dpm_voltage_mode;
571 };
572
573 struct phm_dynamic_state_info {
574         struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk;
575         struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk;
576         struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk;
577         struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk;
578         struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
579         struct phm_clock_array                    *valid_sclk_values;
580         struct phm_clock_array                    *valid_mclk_values;
581         struct phm_clock_and_voltage_limits       max_clock_voltage_on_dc;
582         struct phm_clock_and_voltage_limits       max_clock_voltage_on_ac;
583         uint32_t                                  mclk_sclk_ratio;
584         uint32_t                                  sclk_mclk_delta;
585         uint32_t                                  vddc_vddci_delta;
586         uint32_t                                  min_vddc_for_pcie_gen2;
587         struct phm_cac_leakage_table              *cac_leakage_table;
588         struct phm_phase_shedding_limits_table  *vddc_phase_shed_limits_table;
589
590         struct phm_vce_clock_voltage_dependency_table
591                                             *vce_clock_voltage_dependency_table;
592         struct phm_uvd_clock_voltage_dependency_table
593                                             *uvd_clock_voltage_dependency_table;
594         struct phm_acp_clock_voltage_dependency_table
595                                             *acp_clock_voltage_dependency_table;
596         struct phm_samu_clock_voltage_dependency_table
597                                            *samu_clock_voltage_dependency_table;
598
599         struct phm_ppm_table                          *ppm_parameter_table;
600         struct phm_cac_tdp_table                      *cac_dtp_table;
601         struct phm_clock_voltage_dependency_table       *vdd_gfx_dependency_on_sclk;
602         struct phm_vq_budgeting_table                           *vq_budgeting_table;
603 };
604
605 struct pp_fan_info {
606         bool bNoFan;
607         uint8_t   ucTachometerPulsesPerRevolution;
608         uint32_t   ulMinRPM;
609         uint32_t   ulMaxRPM;
610 };
611
612 struct pp_advance_fan_control_parameters {
613         uint16_t  usTMin;                          /* The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. */
614         uint16_t  usTMed;                          /* The middle temperature where we change slopes. */
615         uint16_t  usTHigh;                         /* The high temperature for setting the second slope. */
616         uint16_t  usPWMMin;                        /* The minimum PWM value in percent (0.01% increments). */
617         uint16_t  usPWMMed;                        /* The PWM value (in percent) at TMed. */
618         uint16_t  usPWMHigh;                       /* The PWM value at THigh. */
619         uint8_t   ucTHyst;                         /* Temperature hysteresis. Integer. */
620         uint32_t   ulCycleDelay;                   /* The time between two invocations of the fan control routine in microseconds. */
621         uint16_t  usTMax;                          /* The max temperature */
622         uint8_t   ucFanControlMode;
623         uint16_t  usFanPWMMinLimit;
624         uint16_t  usFanPWMMaxLimit;
625         uint16_t  usFanPWMStep;
626         uint16_t  usDefaultMaxFanPWM;
627         uint16_t  usFanOutputSensitivity;
628         uint16_t  usDefaultFanOutputSensitivity;
629         uint16_t  usMaxFanPWM;                     /* The max Fan PWM value for Fuzzy Fan Control feature */
630         uint16_t  usFanRPMMinLimit;                /* Minimum limit range in percentage, need to calculate based on minRPM/MaxRpm */
631         uint16_t  usFanRPMMaxLimit;                /* Maximum limit range in percentage, usually set to 100% by default */
632         uint16_t  usFanRPMStep;                    /* Step increments/decerements, in percent */
633         uint16_t  usDefaultMaxFanRPM;              /* The max Fan RPM value for Fuzzy Fan Control feature, default from PPTable */
634         uint16_t  usMaxFanRPM;                     /* The max Fan RPM value for Fuzzy Fan Control feature, user defined */
635         uint16_t  usFanCurrentLow;                 /* Low current */
636         uint16_t  usFanCurrentHigh;                /* High current */
637         uint16_t  usFanRPMLow;                     /* Low RPM */
638         uint16_t  usFanRPMHigh;                    /* High RPM */
639         uint32_t   ulMinFanSCLKAcousticLimit;      /* Minimum Fan Controller SCLK Frequency Acoustic Limit. */
640         uint8_t   ucTargetTemperature;             /* Advanced fan controller target temperature. */
641         uint8_t   ucMinimumPWMLimit;               /* The minimum PWM that the advanced fan controller can set.  This should be set to the highest PWM that will run the fan at its lowest RPM. */
642         uint16_t  usFanGainEdge;                   /* The following is added for Fiji */
643         uint16_t  usFanGainHotspot;
644         uint16_t  usFanGainLiquid;
645         uint16_t  usFanGainVrVddc;
646         uint16_t  usFanGainVrMvdd;
647         uint16_t  usFanGainPlx;
648         uint16_t  usFanGainHbm;
649         uint8_t   ucEnableZeroRPM;
650         uint8_t   ucFanStopTemperature;
651         uint8_t   ucFanStartTemperature;
652         uint32_t  ulMaxFanSCLKAcousticLimit;       /* Maximum Fan Controller SCLK Frequency Acoustic Limit. */
653         uint32_t  ulTargetGfxClk;
654         uint16_t  usZeroRPMStartTemperature;
655         uint16_t  usZeroRPMStopTemperature;
656 };
657
658 struct pp_thermal_controller_info {
659         uint8_t ucType;
660         uint8_t ucI2cLine;
661         uint8_t ucI2cAddress;
662         struct pp_fan_info fanInfo;
663         struct pp_advance_fan_control_parameters advanceFanControlParameters;
664 };
665
666 struct phm_microcode_version_info {
667         uint32_t SMC;
668         uint32_t DMCU;
669         uint32_t MC;
670         uint32_t NB;
671 };
672
673 enum PP_TABLE_VERSION {
674         PP_TABLE_V0 = 0,
675         PP_TABLE_V1,
676         PP_TABLE_V2,
677         PP_TABLE_MAX
678 };
679
680 /**
681  * The main hardware manager structure.
682  */
683 struct pp_hwmgr {
684         uint32_t chip_family;
685         uint32_t chip_id;
686
687         uint32_t pp_table_version;
688         void *device;
689         struct pp_smumgr *smumgr;
690         const void *soft_pp_table;
691         uint32_t soft_pp_table_size;
692         void *hardcode_pp_table;
693         bool need_pp_table_upload;
694
695         struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
696         uint32_t num_vce_state_tables;
697
698         enum amd_dpm_forced_level dpm_level;
699         enum amd_dpm_forced_level saved_dpm_level;
700         enum amd_dpm_forced_level request_dpm_level;
701         struct phm_gfx_arbiter gfx_arbiter;
702         struct phm_acp_arbiter acp_arbiter;
703         struct phm_uvd_arbiter uvd_arbiter;
704         struct phm_vce_arbiter vce_arbiter;
705         uint32_t usec_timeout;
706         void *pptable;
707         struct phm_platform_descriptor platform_descriptor;
708         void *backend;
709         enum PP_DAL_POWERLEVEL dal_power_level;
710         struct phm_dynamic_state_info dyn_state;
711         const struct pp_hwmgr_func *hwmgr_func;
712         const struct pp_table_func *pptable_func;
713         struct pp_power_state    *ps;
714         enum pp_power_source  power_source;
715         uint32_t num_ps;
716         struct pp_thermal_controller_info thermal_controller;
717         bool fan_ctrl_is_in_default_mode;
718         uint32_t fan_ctrl_default_mode;
719         bool fan_ctrl_enabled;
720         uint32_t tmin;
721         struct phm_microcode_version_info microcode_version_info;
722         uint32_t ps_size;
723         struct pp_power_state    *current_ps;
724         struct pp_power_state    *request_ps;
725         struct pp_power_state    *boot_ps;
726         struct pp_power_state    *uvd_ps;
727         struct amd_pp_display_configuration display_config;
728         uint32_t feature_mask;
729
730         /* UMD Pstate */
731         struct amd_pp_profile gfx_power_profile;
732         struct amd_pp_profile compute_power_profile;
733         struct amd_pp_profile default_gfx_power_profile;
734         struct amd_pp_profile default_compute_power_profile;
735         enum amd_pp_profile_type current_power_profile;
736         bool en_umd_pstate;
737 };
738
739 struct cgs_irq_src_funcs {
740         cgs_irq_source_set_func_t set;
741         cgs_irq_handler_func_t handler;
742 };
743
744 extern int hwmgr_early_init(struct pp_instance *handle);
745 extern int hwmgr_hw_init(struct pp_instance *handle);
746 extern int hwmgr_hw_fini(struct pp_instance *handle);
747 extern int hwmgr_hw_suspend(struct pp_instance *handle);
748 extern int hwmgr_hw_resume(struct pp_instance *handle);
749 extern int hwmgr_handle_task(struct pp_instance *handle,
750                                 enum amd_pp_task task_id,
751                                 void *input, void *output);
752 extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
753                                 uint32_t value, uint32_t mask);
754
755 extern void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
756                                 uint32_t indirect_port,
757                                 uint32_t index,
758                                 uint32_t value,
759                                 uint32_t mask);
760
761
762
763 extern bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr);
764 extern bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr);
765 extern bool phm_cf_want_microcode_fan_ctrl(struct pp_hwmgr *hwmgr);
766
767 extern int phm_trim_voltage_table(struct pp_atomctrl_voltage_table *vol_table);
768 extern int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
769 extern int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
770 extern int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_voltage_lookup_table *lookup_table);
771 extern void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table);
772 extern int phm_reset_single_dpm_table(void *table, uint32_t count, int max);
773 extern void phm_setup_pcie_table_entry(void *table, uint32_t index, uint32_t pcie_gen, uint32_t pcie_lanes);
774 extern int32_t phm_get_dpm_level_enable_mask_value(void *table);
775 extern uint8_t phm_get_voltage_id(struct pp_atomctrl_voltage_table *voltage_table,
776                 uint32_t voltage);
777 extern uint8_t phm_get_voltage_index(struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage);
778 extern uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, uint16_t vddci);
779 extern int phm_find_boot_level(void *table, uint32_t value, uint32_t *boot_level);
780 extern int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, phm_ppt_v1_voltage_lookup_table *lookup_table,
781                                                                 uint16_t virtual_voltage_id, int32_t *sclk);
782 extern int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr);
783 extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask);
784 extern void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr);
785
786 extern int smu7_init_function_pointers(struct pp_hwmgr *hwmgr);
787 extern int vega10_hwmgr_init(struct pp_hwmgr *hwmgr);
788 extern int rv_init_function_pointers(struct pp_hwmgr *hwmgr);
789
790 extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
791                                 uint32_t sclk, uint16_t id, uint16_t *voltage);
792
793 #define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU
794
795 #define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
796 #define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK
797
798 #define PHM_SET_FIELD(origval, reg, field, fieldval)    \
799         (((origval) & ~PHM_FIELD_MASK(reg, field)) |    \
800          (PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field))))
801
802 #define PHM_GET_FIELD(value, reg, field)        \
803         (((value) & PHM_FIELD_MASK(reg, field)) >>      \
804          PHM_FIELD_SHIFT(reg, field))
805
806
807 /* Operations on named fields. */
808
809 #define PHM_READ_FIELD(device, reg, field)      \
810         PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)
811
812 #define PHM_READ_INDIRECT_FIELD(device, port, reg, field)       \
813         PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
814                         reg, field)
815
816 #define PHM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field)  \
817         PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
818                         reg, field)
819
820 #define PHM_WRITE_FIELD(device, reg, field, fieldval)   \
821         cgs_write_register(device, mm##reg, PHM_SET_FIELD(      \
822                                 cgs_read_register(device, mm##reg), reg, field, fieldval))
823
824 #define PHM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval)    \
825         cgs_write_ind_register(device, port, ix##reg,   \
826                         PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
827                                 reg, field, fieldval))
828
829 #define PHM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval)       \
830         cgs_write_ind_register(device, port, ix##reg,   \
831                         PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
832                                 reg, field, fieldval))
833
834 #define PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask)        \
835        phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX, index, value, mask)
836
837
838 #define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask)      \
839        PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
840
841 #define PHM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval)      \
842         PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \
843                         << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
844
845
846 #endif /* _HWMGR_H_ */