fa83e69ba9e1387de7f6d97da8e9570b1fedea42
[muen/linux.git] / drivers / gpu / drm / amd / powerplay / inc / hwmgr.h
1 /*
2  * Copyright 2015 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #ifndef _HWMGR_H_
24 #define _HWMGR_H_
25
26 #include <linux/seq_file.h>
27 #include "amd_powerplay.h"
28 #include "pp_instance.h"
29 #include "hardwaremanager.h"
30 #include "pp_power_source.h"
31 #include "hwmgr_ppt.h"
32 #include "ppatomctrl.h"
33 #include "hwmgr_ppt.h"
34 #include "power_state.h"
35 #include "cgs_linux.h"
36
37 struct pp_instance;
38 struct pp_hwmgr;
39 struct phm_fan_speed_info;
40 struct pp_atomctrl_voltage_table;
41
42 #define VOLTAGE_SCALE 4
43
44 uint8_t convert_to_vid(uint16_t vddc);
45
46 enum DISPLAY_GAP {
47         DISPLAY_GAP_VBLANK_OR_WM = 0,   /* Wait for vblank or MCHG watermark. */
48         DISPLAY_GAP_VBLANK       = 1,   /* Wait for vblank. */
49         DISPLAY_GAP_WATERMARK    = 2,   /* Wait for MCHG watermark. (Note that HW may deassert WM in VBI depending on DC_STUTTER_CNTL.) */
50         DISPLAY_GAP_IGNORE       = 3    /* Do not wait. */
51 };
52 typedef enum DISPLAY_GAP DISPLAY_GAP;
53
54 struct vi_dpm_level {
55         bool enabled;
56         uint32_t value;
57         uint32_t param1;
58 };
59
60 struct vi_dpm_table {
61         uint32_t count;
62         struct vi_dpm_level dpm_level[1];
63 };
64
65 enum PP_Result {
66         PP_Result_TableImmediateExit = 0x13,
67 };
68
69 #define PCIE_PERF_REQ_REMOVE_REGISTRY   0
70 #define PCIE_PERF_REQ_FORCE_LOWPOWER    1
71 #define PCIE_PERF_REQ_GEN1         2
72 #define PCIE_PERF_REQ_GEN2         3
73 #define PCIE_PERF_REQ_GEN3         4
74
75 enum PP_FEATURE_MASK {
76         PP_SCLK_DPM_MASK = 0x1,
77         PP_MCLK_DPM_MASK = 0x2,
78         PP_PCIE_DPM_MASK = 0x4,
79         PP_SCLK_DEEP_SLEEP_MASK = 0x8,
80         PP_POWER_CONTAINMENT_MASK = 0x10,
81         PP_UVD_HANDSHAKE_MASK = 0x20,
82         PP_SMC_VOLTAGE_CONTROL_MASK = 0x40,
83         PP_VBI_TIME_SUPPORT_MASK = 0x80,
84         PP_ULV_MASK = 0x100,
85         PP_ENABLE_GFX_CG_THRU_SMU = 0x200,
86         PP_CLOCK_STRETCH_MASK = 0x400,
87         PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800,
88         PP_SOCCLK_DPM_MASK = 0x1000,
89         PP_DCEFCLK_DPM_MASK = 0x2000,
90 };
91
92 enum PHM_BackEnd_Magic {
93         PHM_Dummy_Magic       = 0xAA5555AA,
94         PHM_RV770_Magic       = 0xDCBAABCD,
95         PHM_Kong_Magic        = 0x239478DF,
96         PHM_NIslands_Magic    = 0x736C494E,
97         PHM_Sumo_Magic        = 0x8339FA11,
98         PHM_SIslands_Magic    = 0x369431AC,
99         PHM_Trinity_Magic     = 0x96751873,
100         PHM_CIslands_Magic    = 0x38AC78B0,
101         PHM_Kv_Magic          = 0xDCBBABC0,
102         PHM_VIslands_Magic    = 0x20130307,
103         PHM_Cz_Magic          = 0x67DCBA25,
104         PHM_Rv_Magic          = 0x20161121
105 };
106
107
108 #define PHM_PCIE_POWERGATING_TARGET_GFX            0
109 #define PHM_PCIE_POWERGATING_TARGET_DDI            1
110 #define PHM_PCIE_POWERGATING_TARGET_PLLCASCADE     2
111 #define PHM_PCIE_POWERGATING_TARGET_PHY            3
112
113
114 struct phm_set_power_state_input {
115         const struct pp_hw_power_state *pcurrent_state;
116         const struct pp_hw_power_state *pnew_state;
117 };
118
119 struct phm_acp_arbiter {
120         uint32_t acpclk;
121 };
122
123 struct phm_uvd_arbiter {
124         uint32_t vclk;
125         uint32_t dclk;
126         uint32_t vclk_ceiling;
127         uint32_t dclk_ceiling;
128         uint32_t vclk_soft_min;
129         uint32_t dclk_soft_min;
130 };
131
132 struct phm_vce_arbiter {
133         uint32_t   evclk;
134         uint32_t   ecclk;
135 };
136
137 struct phm_gfx_arbiter {
138         uint32_t sclk;
139         uint32_t sclk_hard_min;
140         uint32_t mclk;
141         uint32_t sclk_over_drive;
142         uint32_t mclk_over_drive;
143         uint32_t sclk_threshold;
144         uint32_t num_cus;
145         uint32_t gfxclk;
146         uint32_t fclk;
147 };
148
149 struct phm_clock_array {
150         uint32_t count;
151         uint32_t values[1];
152 };
153
154 struct phm_clock_voltage_dependency_record {
155         uint32_t clk;
156         uint32_t v;
157 };
158
159 struct phm_vceclock_voltage_dependency_record {
160         uint32_t ecclk;
161         uint32_t evclk;
162         uint32_t v;
163 };
164
165 struct phm_uvdclock_voltage_dependency_record {
166         uint32_t vclk;
167         uint32_t dclk;
168         uint32_t v;
169 };
170
171 struct phm_samuclock_voltage_dependency_record {
172         uint32_t samclk;
173         uint32_t v;
174 };
175
176 struct phm_acpclock_voltage_dependency_record {
177         uint32_t acpclk;
178         uint32_t v;
179 };
180
181 struct phm_clock_voltage_dependency_table {
182         uint32_t count;                                                                         /* Number of entries. */
183         struct phm_clock_voltage_dependency_record entries[1];          /* Dynamically allocate count entries. */
184 };
185
186 struct phm_phase_shedding_limits_record {
187         uint32_t  Voltage;
188         uint32_t    Sclk;
189         uint32_t    Mclk;
190 };
191
192 struct phm_uvd_clock_voltage_dependency_record {
193         uint32_t vclk;
194         uint32_t dclk;
195         uint32_t v;
196 };
197
198 struct phm_uvd_clock_voltage_dependency_table {
199         uint8_t count;
200         struct phm_uvd_clock_voltage_dependency_record entries[1];
201 };
202
203 struct phm_acp_clock_voltage_dependency_record {
204         uint32_t acpclk;
205         uint32_t v;
206 };
207
208 struct phm_acp_clock_voltage_dependency_table {
209         uint32_t count;
210         struct phm_acp_clock_voltage_dependency_record entries[1];
211 };
212
213 struct phm_vce_clock_voltage_dependency_record {
214         uint32_t ecclk;
215         uint32_t evclk;
216         uint32_t v;
217 };
218
219 struct phm_phase_shedding_limits_table {
220         uint32_t                           count;
221         struct phm_phase_shedding_limits_record  entries[1];
222 };
223
224 struct phm_vceclock_voltage_dependency_table {
225         uint8_t count;                                    /* Number of entries. */
226         struct phm_vceclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
227 };
228
229 struct phm_uvdclock_voltage_dependency_table {
230         uint8_t count;                                    /* Number of entries. */
231         struct phm_uvdclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
232 };
233
234 struct phm_samuclock_voltage_dependency_table {
235         uint8_t count;                                    /* Number of entries. */
236         struct phm_samuclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
237 };
238
239 struct phm_acpclock_voltage_dependency_table {
240         uint32_t count;                                    /* Number of entries. */
241         struct phm_acpclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
242 };
243
244 struct phm_vce_clock_voltage_dependency_table {
245         uint8_t count;
246         struct phm_vce_clock_voltage_dependency_record entries[1];
247 };
248
249 struct pp_hwmgr_func {
250         int (*backend_init)(struct pp_hwmgr *hw_mgr);
251         int (*backend_fini)(struct pp_hwmgr *hw_mgr);
252         int (*asic_setup)(struct pp_hwmgr *hw_mgr);
253         int (*get_power_state_size)(struct pp_hwmgr *hw_mgr);
254
255         int (*apply_state_adjust_rules)(struct pp_hwmgr *hwmgr,
256                                 struct pp_power_state  *prequest_ps,
257                         const struct pp_power_state *pcurrent_ps);
258
259         int (*force_dpm_level)(struct pp_hwmgr *hw_mgr,
260                                         enum amd_dpm_forced_level level);
261
262         int (*dynamic_state_management_enable)(
263                                                 struct pp_hwmgr *hw_mgr);
264         int (*dynamic_state_management_disable)(
265                                                 struct pp_hwmgr *hw_mgr);
266
267         int (*patch_boot_state)(struct pp_hwmgr *hwmgr,
268                                      struct pp_hw_power_state *hw_ps);
269
270         int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr,
271                             unsigned long, struct pp_power_state *);
272         int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr);
273         int (*powerdown_uvd)(struct pp_hwmgr *hwmgr);
274         void (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate);
275         void (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate);
276         uint32_t (*get_mclk)(struct pp_hwmgr *hwmgr, bool low);
277         uint32_t (*get_sclk)(struct pp_hwmgr *hwmgr, bool low);
278         int (*power_state_set)(struct pp_hwmgr *hwmgr,
279                                                 const void *state);
280         int (*enable_clock_power_gating)(struct pp_hwmgr *hwmgr);
281         int (*notify_smc_display_config_after_ps_adjustment)(struct pp_hwmgr *hwmgr);
282         int (*display_config_changed)(struct pp_hwmgr *hwmgr);
283         int (*disable_clock_power_gating)(struct pp_hwmgr *hwmgr);
284         int (*update_clock_gatings)(struct pp_hwmgr *hwmgr,
285                                                 const uint32_t *msg_id);
286         int (*set_max_fan_rpm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
287         int (*set_max_fan_pwm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
288         int (*get_temperature)(struct pp_hwmgr *hwmgr);
289         int (*stop_thermal_controller)(struct pp_hwmgr *hwmgr);
290         int (*get_fan_speed_info)(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
291         void (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode);
292         uint32_t (*get_fan_control_mode)(struct pp_hwmgr *hwmgr);
293         int (*set_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t percent);
294         int (*get_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t *speed);
295         int (*set_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t percent);
296         int (*get_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t *speed);
297         int (*reset_fan_speed_to_default)(struct pp_hwmgr *hwmgr);
298         int (*uninitialize_thermal_controller)(struct pp_hwmgr *hwmgr);
299         int (*register_internal_thermal_interrupt)(struct pp_hwmgr *hwmgr,
300                                         const void *thermal_interrupt_info);
301         bool (*check_smc_update_required_for_display_configuration)(struct pp_hwmgr *hwmgr);
302         int (*check_states_equal)(struct pp_hwmgr *hwmgr,
303                                         const struct pp_hw_power_state *pstate1,
304                                         const struct pp_hw_power_state *pstate2,
305                                         bool *equal);
306         int (*set_cpu_power_state)(struct pp_hwmgr *hwmgr);
307         int (*store_cc6_data)(struct pp_hwmgr *hwmgr, uint32_t separation_time,
308                                 bool cc6_disable, bool pstate_disable,
309                                 bool pstate_switch_disable);
310         int (*get_dal_power_level)(struct pp_hwmgr *hwmgr,
311                         struct amd_pp_simple_clock_info *info);
312         int (*get_performance_level)(struct pp_hwmgr *, const struct pp_hw_power_state *,
313                         PHM_PerformanceLevelDesignation, uint32_t, PHM_PerformanceLevel *);
314         int (*get_current_shallow_sleep_clocks)(struct pp_hwmgr *hwmgr,
315                                 const struct pp_hw_power_state *state, struct pp_clock_info *clock_info);
316         int (*get_clock_by_type)(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
317         int (*get_clock_by_type_with_latency)(struct pp_hwmgr *hwmgr,
318                         enum amd_pp_clock_type type,
319                         struct pp_clock_levels_with_latency *clocks);
320         int (*get_clock_by_type_with_voltage)(struct pp_hwmgr *hwmgr,
321                         enum amd_pp_clock_type type,
322                         struct pp_clock_levels_with_voltage *clocks);
323         int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr,
324                         struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
325         int (*display_clock_voltage_request)(struct pp_hwmgr *hwmgr,
326                         struct pp_display_clock_request *clock);
327         int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
328         int (*power_off_asic)(struct pp_hwmgr *hwmgr);
329         int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask);
330         int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf);
331         int (*enable_per_cu_power_gating)(struct pp_hwmgr *hwmgr, bool enable);
332         int (*get_sclk_od)(struct pp_hwmgr *hwmgr);
333         int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
334         int (*get_mclk_od)(struct pp_hwmgr *hwmgr);
335         int (*set_mclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
336         int (*read_sensor)(struct pp_hwmgr *hwmgr, int idx, void *value, int *size);
337         int (*set_power_profile_state)(struct pp_hwmgr *hwmgr,
338                         struct amd_pp_profile *request);
339         int (*avfs_control)(struct pp_hwmgr *hwmgr, bool enable);
340         int (*disable_smc_firmware_ctf)(struct pp_hwmgr *hwmgr);
341         int (*set_active_display_count)(struct pp_hwmgr *hwmgr, uint32_t count);
342         int (*set_deep_sleep_dcefclk)(struct pp_hwmgr *hwmgr, uint32_t clock);
343         int (*start_thermal_controller)(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *range);
344 };
345
346 struct pp_table_func {
347         int (*pptable_init)(struct pp_hwmgr *hw_mgr);
348         int (*pptable_fini)(struct pp_hwmgr *hw_mgr);
349         int (*pptable_get_number_of_vce_state_table_entries)(struct pp_hwmgr *hw_mgr);
350         int (*pptable_get_vce_state_table_entry)(
351                                                 struct pp_hwmgr *hwmgr,
352                                                 unsigned long i,
353                                                 struct amd_vce_state *vce_state,
354                                                 void **clock_info,
355                                                 unsigned long *flag);
356 };
357
358 union phm_cac_leakage_record {
359         struct {
360                 uint16_t Vddc;          /* in CI, we use it for StdVoltageHiSidd */
361                 uint32_t Leakage;       /* in CI, we use it for StdVoltageLoSidd */
362         };
363         struct {
364                 uint16_t Vddc1;
365                 uint16_t Vddc2;
366                 uint16_t Vddc3;
367         };
368 };
369
370 struct phm_cac_leakage_table {
371         uint32_t count;
372         union phm_cac_leakage_record entries[1];
373 };
374
375 struct phm_samu_clock_voltage_dependency_record {
376         uint32_t samclk;
377         uint32_t v;
378 };
379
380
381 struct phm_samu_clock_voltage_dependency_table {
382         uint8_t count;
383         struct phm_samu_clock_voltage_dependency_record entries[1];
384 };
385
386 struct phm_cac_tdp_table {
387         uint16_t usTDP;
388         uint16_t usConfigurableTDP;
389         uint16_t usTDC;
390         uint16_t usBatteryPowerLimit;
391         uint16_t usSmallPowerLimit;
392         uint16_t usLowCACLeakage;
393         uint16_t usHighCACLeakage;
394         uint16_t usMaximumPowerDeliveryLimit;
395         uint16_t usEDCLimit;
396         uint16_t usOperatingTempMinLimit;
397         uint16_t usOperatingTempMaxLimit;
398         uint16_t usOperatingTempStep;
399         uint16_t usOperatingTempHyst;
400         uint16_t usDefaultTargetOperatingTemp;
401         uint16_t usTargetOperatingTemp;
402         uint16_t usPowerTuneDataSetID;
403         uint16_t usSoftwareShutdownTemp;
404         uint16_t usClockStretchAmount;
405         uint16_t usTemperatureLimitHotspot;
406         uint16_t usTemperatureLimitLiquid1;
407         uint16_t usTemperatureLimitLiquid2;
408         uint16_t usTemperatureLimitVrVddc;
409         uint16_t usTemperatureLimitVrMvdd;
410         uint16_t usTemperatureLimitPlx;
411         uint8_t  ucLiquid1_I2C_address;
412         uint8_t  ucLiquid2_I2C_address;
413         uint8_t  ucLiquid_I2C_Line;
414         uint8_t  ucVr_I2C_address;
415         uint8_t  ucVr_I2C_Line;
416         uint8_t  ucPlx_I2C_address;
417         uint8_t  ucPlx_I2C_Line;
418         uint32_t usBoostPowerLimit;
419         uint8_t  ucCKS_LDO_REFSEL;
420 };
421
422 struct phm_tdp_table {
423         uint16_t usTDP;
424         uint16_t usConfigurableTDP;
425         uint16_t usTDC;
426         uint16_t usBatteryPowerLimit;
427         uint16_t usSmallPowerLimit;
428         uint16_t usLowCACLeakage;
429         uint16_t usHighCACLeakage;
430         uint16_t usMaximumPowerDeliveryLimit;
431         uint16_t usEDCLimit;
432         uint16_t usOperatingTempMinLimit;
433         uint16_t usOperatingTempMaxLimit;
434         uint16_t usOperatingTempStep;
435         uint16_t usOperatingTempHyst;
436         uint16_t usDefaultTargetOperatingTemp;
437         uint16_t usTargetOperatingTemp;
438         uint16_t usPowerTuneDataSetID;
439         uint16_t usSoftwareShutdownTemp;
440         uint16_t usClockStretchAmount;
441         uint16_t usTemperatureLimitTedge;
442         uint16_t usTemperatureLimitHotspot;
443         uint16_t usTemperatureLimitLiquid1;
444         uint16_t usTemperatureLimitLiquid2;
445         uint16_t usTemperatureLimitHBM;
446         uint16_t usTemperatureLimitVrVddc;
447         uint16_t usTemperatureLimitVrMvdd;
448         uint16_t usTemperatureLimitPlx;
449         uint8_t  ucLiquid1_I2C_address;
450         uint8_t  ucLiquid2_I2C_address;
451         uint8_t  ucLiquid_I2C_Line;
452         uint8_t  ucVr_I2C_address;
453         uint8_t  ucVr_I2C_Line;
454         uint8_t  ucPlx_I2C_address;
455         uint8_t  ucPlx_I2C_Line;
456         uint8_t  ucLiquid_I2C_LineSDA;
457         uint8_t  ucVr_I2C_LineSDA;
458         uint8_t  ucPlx_I2C_LineSDA;
459         uint32_t usBoostPowerLimit;
460         uint16_t usBoostStartTemperature;
461         uint16_t usBoostStopTemperature;
462         uint32_t  ulBoostClock;
463 };
464
465 struct phm_ppm_table {
466         uint8_t   ppm_design;
467         uint16_t  cpu_core_number;
468         uint32_t  platform_tdp;
469         uint32_t  small_ac_platform_tdp;
470         uint32_t  platform_tdc;
471         uint32_t  small_ac_platform_tdc;
472         uint32_t  apu_tdp;
473         uint32_t  dgpu_tdp;
474         uint32_t  dgpu_ulv_power;
475         uint32_t  tj_max;
476 };
477
478 struct phm_vq_budgeting_record {
479         uint32_t ulCUs;
480         uint32_t ulSustainableSOCPowerLimitLow;
481         uint32_t ulSustainableSOCPowerLimitHigh;
482         uint32_t ulMinSclkLow;
483         uint32_t ulMinSclkHigh;
484         uint8_t  ucDispConfig;
485         uint32_t ulDClk;
486         uint32_t ulEClk;
487         uint32_t ulSustainableSclk;
488         uint32_t ulSustainableCUs;
489 };
490
491 struct phm_vq_budgeting_table {
492         uint8_t numEntries;
493         struct phm_vq_budgeting_record entries[1];
494 };
495
496 struct phm_clock_and_voltage_limits {
497         uint32_t sclk;
498         uint32_t mclk;
499         uint32_t gfxclk;
500         uint16_t vddc;
501         uint16_t vddci;
502         uint16_t vddgfx;
503         uint16_t vddmem;
504 };
505
506 /* Structure to hold PPTable information */
507
508 struct phm_ppt_v1_information {
509         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
510         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
511         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
512         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
513         struct phm_clock_array *valid_sclk_values;
514         struct phm_clock_array *valid_mclk_values;
515         struct phm_clock_array *valid_socclk_values;
516         struct phm_clock_array *valid_dcefclk_values;
517         struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
518         struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
519         struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
520         struct phm_ppm_table *ppm_parameter_table;
521         struct phm_cac_tdp_table *cac_dtp_table;
522         struct phm_tdp_table *tdp_table;
523         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
524         struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
525         struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
526         struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
527         struct phm_ppt_v1_pcie_table *pcie_table;
528         struct phm_ppt_v1_gpio_table *gpio_table;
529         uint16_t us_ulv_voltage_offset;
530         uint16_t us_ulv_smnclk_did;
531         uint16_t us_ulv_mp1clk_did;
532         uint16_t us_ulv_gfxclk_bypass;
533         uint16_t us_gfxclk_slew_rate;
534         uint16_t us_min_gfxclk_freq_limit;
535 };
536
537 struct phm_ppt_v2_information {
538         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
539         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
540         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
541         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
542         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_pixclk;
543         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dispclk;
544         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_phyclk;
545         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
546
547         struct phm_clock_voltage_dependency_table *vddc_dep_on_dalpwrl;
548
549         struct phm_clock_array *valid_sclk_values;
550         struct phm_clock_array *valid_mclk_values;
551         struct phm_clock_array *valid_socclk_values;
552         struct phm_clock_array *valid_dcefclk_values;
553
554         struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
555         struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
556
557         struct phm_ppm_table *ppm_parameter_table;
558         struct phm_cac_tdp_table *cac_dtp_table;
559         struct phm_tdp_table *tdp_table;
560
561         struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
562         struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
563         struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
564         struct phm_ppt_v1_voltage_lookup_table *vddci_lookup_table;
565
566         struct phm_ppt_v1_pcie_table *pcie_table;
567
568         uint16_t us_ulv_voltage_offset;
569         uint16_t us_ulv_smnclk_did;
570         uint16_t us_ulv_mp1clk_did;
571         uint16_t us_ulv_gfxclk_bypass;
572         uint16_t us_gfxclk_slew_rate;
573         uint16_t us_min_gfxclk_freq_limit;
574
575         uint8_t  uc_gfx_dpm_voltage_mode;
576         uint8_t  uc_soc_dpm_voltage_mode;
577         uint8_t  uc_uclk_dpm_voltage_mode;
578         uint8_t  uc_uvd_dpm_voltage_mode;
579         uint8_t  uc_vce_dpm_voltage_mode;
580         uint8_t  uc_mp0_dpm_voltage_mode;
581         uint8_t  uc_dcef_dpm_voltage_mode;
582 };
583
584 struct phm_dynamic_state_info {
585         struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk;
586         struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk;
587         struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk;
588         struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk;
589         struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
590         struct phm_clock_array                    *valid_sclk_values;
591         struct phm_clock_array                    *valid_mclk_values;
592         struct phm_clock_and_voltage_limits       max_clock_voltage_on_dc;
593         struct phm_clock_and_voltage_limits       max_clock_voltage_on_ac;
594         uint32_t                                  mclk_sclk_ratio;
595         uint32_t                                  sclk_mclk_delta;
596         uint32_t                                  vddc_vddci_delta;
597         uint32_t                                  min_vddc_for_pcie_gen2;
598         struct phm_cac_leakage_table              *cac_leakage_table;
599         struct phm_phase_shedding_limits_table  *vddc_phase_shed_limits_table;
600
601         struct phm_vce_clock_voltage_dependency_table
602                                             *vce_clock_voltage_dependency_table;
603         struct phm_uvd_clock_voltage_dependency_table
604                                             *uvd_clock_voltage_dependency_table;
605         struct phm_acp_clock_voltage_dependency_table
606                                             *acp_clock_voltage_dependency_table;
607         struct phm_samu_clock_voltage_dependency_table
608                                            *samu_clock_voltage_dependency_table;
609
610         struct phm_ppm_table                          *ppm_parameter_table;
611         struct phm_cac_tdp_table                      *cac_dtp_table;
612         struct phm_clock_voltage_dependency_table       *vdd_gfx_dependency_on_sclk;
613         struct phm_vq_budgeting_table                           *vq_budgeting_table;
614 };
615
616 struct pp_fan_info {
617         bool bNoFan;
618         uint8_t   ucTachometerPulsesPerRevolution;
619         uint32_t   ulMinRPM;
620         uint32_t   ulMaxRPM;
621 };
622
623 struct pp_advance_fan_control_parameters {
624         uint16_t  usTMin;                          /* The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. */
625         uint16_t  usTMed;                          /* The middle temperature where we change slopes. */
626         uint16_t  usTHigh;                         /* The high temperature for setting the second slope. */
627         uint16_t  usPWMMin;                        /* The minimum PWM value in percent (0.01% increments). */
628         uint16_t  usPWMMed;                        /* The PWM value (in percent) at TMed. */
629         uint16_t  usPWMHigh;                       /* The PWM value at THigh. */
630         uint8_t   ucTHyst;                         /* Temperature hysteresis. Integer. */
631         uint32_t   ulCycleDelay;                   /* The time between two invocations of the fan control routine in microseconds. */
632         uint16_t  usTMax;                          /* The max temperature */
633         uint8_t   ucFanControlMode;
634         uint16_t  usFanPWMMinLimit;
635         uint16_t  usFanPWMMaxLimit;
636         uint16_t  usFanPWMStep;
637         uint16_t  usDefaultMaxFanPWM;
638         uint16_t  usFanOutputSensitivity;
639         uint16_t  usDefaultFanOutputSensitivity;
640         uint16_t  usMaxFanPWM;                     /* The max Fan PWM value for Fuzzy Fan Control feature */
641         uint16_t  usFanRPMMinLimit;                /* Minimum limit range in percentage, need to calculate based on minRPM/MaxRpm */
642         uint16_t  usFanRPMMaxLimit;                /* Maximum limit range in percentage, usually set to 100% by default */
643         uint16_t  usFanRPMStep;                    /* Step increments/decerements, in percent */
644         uint16_t  usDefaultMaxFanRPM;              /* The max Fan RPM value for Fuzzy Fan Control feature, default from PPTable */
645         uint16_t  usMaxFanRPM;                     /* The max Fan RPM value for Fuzzy Fan Control feature, user defined */
646         uint16_t  usFanCurrentLow;                 /* Low current */
647         uint16_t  usFanCurrentHigh;                /* High current */
648         uint16_t  usFanRPMLow;                     /* Low RPM */
649         uint16_t  usFanRPMHigh;                    /* High RPM */
650         uint32_t   ulMinFanSCLKAcousticLimit;      /* Minimum Fan Controller SCLK Frequency Acoustic Limit. */
651         uint8_t   ucTargetTemperature;             /* Advanced fan controller target temperature. */
652         uint8_t   ucMinimumPWMLimit;               /* The minimum PWM that the advanced fan controller can set.  This should be set to the highest PWM that will run the fan at its lowest RPM. */
653         uint16_t  usFanGainEdge;                   /* The following is added for Fiji */
654         uint16_t  usFanGainHotspot;
655         uint16_t  usFanGainLiquid;
656         uint16_t  usFanGainVrVddc;
657         uint16_t  usFanGainVrMvdd;
658         uint16_t  usFanGainPlx;
659         uint16_t  usFanGainHbm;
660         uint8_t   ucEnableZeroRPM;
661         uint8_t   ucFanStopTemperature;
662         uint8_t   ucFanStartTemperature;
663         uint32_t  ulMaxFanSCLKAcousticLimit;       /* Maximum Fan Controller SCLK Frequency Acoustic Limit. */
664         uint32_t  ulTargetGfxClk;
665         uint16_t  usZeroRPMStartTemperature;
666         uint16_t  usZeroRPMStopTemperature;
667 };
668
669 struct pp_thermal_controller_info {
670         uint8_t ucType;
671         uint8_t ucI2cLine;
672         uint8_t ucI2cAddress;
673         struct pp_fan_info fanInfo;
674         struct pp_advance_fan_control_parameters advanceFanControlParameters;
675 };
676
677 struct phm_microcode_version_info {
678         uint32_t SMC;
679         uint32_t DMCU;
680         uint32_t MC;
681         uint32_t NB;
682 };
683
684 enum PP_TABLE_VERSION {
685         PP_TABLE_V0 = 0,
686         PP_TABLE_V1,
687         PP_TABLE_V2,
688         PP_TABLE_MAX
689 };
690
691 /**
692  * The main hardware manager structure.
693  */
694 struct pp_hwmgr {
695         uint32_t chip_family;
696         uint32_t chip_id;
697
698         uint32_t pp_table_version;
699         void *device;
700         struct pp_smumgr *smumgr;
701         const void *soft_pp_table;
702         uint32_t soft_pp_table_size;
703         void *hardcode_pp_table;
704         bool need_pp_table_upload;
705
706         struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
707         uint32_t num_vce_state_tables;
708
709         enum amd_dpm_forced_level dpm_level;
710         enum amd_dpm_forced_level saved_dpm_level;
711         enum amd_dpm_forced_level request_dpm_level;
712         struct phm_gfx_arbiter gfx_arbiter;
713         struct phm_acp_arbiter acp_arbiter;
714         struct phm_uvd_arbiter uvd_arbiter;
715         struct phm_vce_arbiter vce_arbiter;
716         uint32_t usec_timeout;
717         void *pptable;
718         struct phm_platform_descriptor platform_descriptor;
719         void *backend;
720         enum PP_DAL_POWERLEVEL dal_power_level;
721         struct phm_dynamic_state_info dyn_state;
722         const struct pp_hwmgr_func *hwmgr_func;
723         const struct pp_table_func *pptable_func;
724         struct pp_power_state    *ps;
725         enum pp_power_source  power_source;
726         uint32_t num_ps;
727         struct pp_thermal_controller_info thermal_controller;
728         bool fan_ctrl_is_in_default_mode;
729         uint32_t fan_ctrl_default_mode;
730         bool fan_ctrl_enabled;
731         uint32_t tmin;
732         struct phm_microcode_version_info microcode_version_info;
733         uint32_t ps_size;
734         struct pp_power_state    *current_ps;
735         struct pp_power_state    *request_ps;
736         struct pp_power_state    *boot_ps;
737         struct pp_power_state    *uvd_ps;
738         struct amd_pp_display_configuration display_config;
739         uint32_t feature_mask;
740
741         /* UMD Pstate */
742         struct amd_pp_profile gfx_power_profile;
743         struct amd_pp_profile compute_power_profile;
744         struct amd_pp_profile default_gfx_power_profile;
745         struct amd_pp_profile default_compute_power_profile;
746         enum amd_pp_profile_type current_power_profile;
747         bool en_umd_pstate;
748 };
749
750 struct cgs_irq_src_funcs {
751         cgs_irq_source_set_func_t set;
752         cgs_irq_handler_func_t handler;
753 };
754
755 extern int hwmgr_early_init(struct pp_instance *handle);
756 extern int hwmgr_hw_init(struct pp_instance *handle);
757 extern int hwmgr_hw_fini(struct pp_instance *handle);
758 extern int hwmgr_hw_suspend(struct pp_instance *handle);
759 extern int hwmgr_hw_resume(struct pp_instance *handle);
760 extern int hwmgr_handle_task(struct pp_instance *handle,
761                                 enum amd_pp_task task_id,
762                                 void *input, void *output);
763 extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
764                                 uint32_t value, uint32_t mask);
765
766 extern void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
767                                 uint32_t indirect_port,
768                                 uint32_t index,
769                                 uint32_t value,
770                                 uint32_t mask);
771
772
773
774 extern bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr);
775 extern bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr);
776 extern bool phm_cf_want_microcode_fan_ctrl(struct pp_hwmgr *hwmgr);
777
778 extern int phm_trim_voltage_table(struct pp_atomctrl_voltage_table *vol_table);
779 extern int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
780 extern int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
781 extern int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_voltage_lookup_table *lookup_table);
782 extern void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table);
783 extern int phm_reset_single_dpm_table(void *table, uint32_t count, int max);
784 extern void phm_setup_pcie_table_entry(void *table, uint32_t index, uint32_t pcie_gen, uint32_t pcie_lanes);
785 extern int32_t phm_get_dpm_level_enable_mask_value(void *table);
786 extern uint8_t phm_get_voltage_id(struct pp_atomctrl_voltage_table *voltage_table,
787                 uint32_t voltage);
788 extern uint8_t phm_get_voltage_index(struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage);
789 extern uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, uint16_t vddci);
790 extern int phm_find_boot_level(void *table, uint32_t value, uint32_t *boot_level);
791 extern int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, phm_ppt_v1_voltage_lookup_table *lookup_table,
792                                                                 uint16_t virtual_voltage_id, int32_t *sclk);
793 extern int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr);
794 extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask);
795 extern void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr);
796
797 extern int smu7_init_function_pointers(struct pp_hwmgr *hwmgr);
798 extern int vega10_hwmgr_init(struct pp_hwmgr *hwmgr);
799 extern int rv_init_function_pointers(struct pp_hwmgr *hwmgr);
800
801 extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
802                                 uint32_t sclk, uint16_t id, uint16_t *voltage);
803
804 #define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU
805
806 #define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
807 #define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK
808
809 #define PHM_SET_FIELD(origval, reg, field, fieldval)    \
810         (((origval) & ~PHM_FIELD_MASK(reg, field)) |    \
811          (PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field))))
812
813 #define PHM_GET_FIELD(value, reg, field)        \
814         (((value) & PHM_FIELD_MASK(reg, field)) >>      \
815          PHM_FIELD_SHIFT(reg, field))
816
817
818 /* Operations on named fields. */
819
820 #define PHM_READ_FIELD(device, reg, field)      \
821         PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)
822
823 #define PHM_READ_INDIRECT_FIELD(device, port, reg, field)       \
824         PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
825                         reg, field)
826
827 #define PHM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field)  \
828         PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
829                         reg, field)
830
831 #define PHM_WRITE_FIELD(device, reg, field, fieldval)   \
832         cgs_write_register(device, mm##reg, PHM_SET_FIELD(      \
833                                 cgs_read_register(device, mm##reg), reg, field, fieldval))
834
835 #define PHM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval)    \
836         cgs_write_ind_register(device, port, ix##reg,   \
837                         PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
838                                 reg, field, fieldval))
839
840 #define PHM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval)       \
841         cgs_write_ind_register(device, port, ix##reg,   \
842                         PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
843                                 reg, field, fieldval))
844
845 #define PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask)        \
846        phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX, index, value, mask)
847
848
849 #define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask)      \
850        PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
851
852 #define PHM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval)      \
853         PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \
854                         << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
855
856
857 #endif /* _HWMGR_H_ */