Merge tag 'dw-hdmi-next-2016-09-19' of git://git.pengutronix.de/git/pza/linux into...
[muen/linux.git] / drivers / gpu / drm / bridge / dw-hdmi.c
1 /*
2  * DesignWare High-Definition Multimedia Interface (HDMI) driver
3  *
4  * Copyright (C) 2013-2015 Mentor Graphics Inc.
5  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
6  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  */
14 #include <linux/module.h>
15 #include <linux/irq.h>
16 #include <linux/delay.h>
17 #include <linux/err.h>
18 #include <linux/clk.h>
19 #include <linux/hdmi.h>
20 #include <linux/mutex.h>
21 #include <linux/of_device.h>
22 #include <linux/spinlock.h>
23
24 #include <drm/drm_of.h>
25 #include <drm/drmP.h>
26 #include <drm/drm_atomic_helper.h>
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/drm_edid.h>
29 #include <drm/drm_encoder_slave.h>
30 #include <drm/bridge/dw_hdmi.h>
31
32 #include "dw-hdmi.h"
33 #include "dw-hdmi-audio.h"
34
35 #define HDMI_EDID_LEN           512
36
37 #define RGB                     0
38 #define YCBCR444                1
39 #define YCBCR422_16BITS         2
40 #define YCBCR422_8BITS          3
41 #define XVYCC444                4
42
43 enum hdmi_datamap {
44         RGB444_8B = 0x01,
45         RGB444_10B = 0x03,
46         RGB444_12B = 0x05,
47         RGB444_16B = 0x07,
48         YCbCr444_8B = 0x09,
49         YCbCr444_10B = 0x0B,
50         YCbCr444_12B = 0x0D,
51         YCbCr444_16B = 0x0F,
52         YCbCr422_8B = 0x16,
53         YCbCr422_10B = 0x14,
54         YCbCr422_12B = 0x12,
55 };
56
57 static const u16 csc_coeff_default[3][4] = {
58         { 0x2000, 0x0000, 0x0000, 0x0000 },
59         { 0x0000, 0x2000, 0x0000, 0x0000 },
60         { 0x0000, 0x0000, 0x2000, 0x0000 }
61 };
62
63 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
64         { 0x2000, 0x6926, 0x74fd, 0x010e },
65         { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
66         { 0x2000, 0x0000, 0x38b4, 0x7e3b }
67 };
68
69 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
70         { 0x2000, 0x7106, 0x7a02, 0x00a7 },
71         { 0x2000, 0x3264, 0x0000, 0x7e6d },
72         { 0x2000, 0x0000, 0x3b61, 0x7e25 }
73 };
74
75 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
76         { 0x2591, 0x1322, 0x074b, 0x0000 },
77         { 0x6535, 0x2000, 0x7acc, 0x0200 },
78         { 0x6acd, 0x7534, 0x2000, 0x0200 }
79 };
80
81 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
82         { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
83         { 0x62f0, 0x2000, 0x7d11, 0x0200 },
84         { 0x6756, 0x78ab, 0x2000, 0x0200 }
85 };
86
87 struct hdmi_vmode {
88         bool mdataenablepolarity;
89
90         unsigned int mpixelclock;
91         unsigned int mpixelrepetitioninput;
92         unsigned int mpixelrepetitionoutput;
93 };
94
95 struct hdmi_data_info {
96         unsigned int enc_in_format;
97         unsigned int enc_out_format;
98         unsigned int enc_color_depth;
99         unsigned int colorimetry;
100         unsigned int pix_repet_factor;
101         unsigned int hdcp_enable;
102         struct hdmi_vmode video_mode;
103 };
104
105 struct dw_hdmi_i2c {
106         struct i2c_adapter      adap;
107
108         struct mutex            lock;   /* used to serialize data transfers */
109         struct completion       cmp;
110         u8                      stat;
111
112         u8                      slave_reg;
113         bool                    is_regaddr;
114 };
115
116 struct dw_hdmi {
117         struct drm_connector connector;
118         struct drm_encoder *encoder;
119         struct drm_bridge *bridge;
120
121         struct platform_device *audio;
122         enum dw_hdmi_devtype dev_type;
123         struct device *dev;
124         struct clk *isfr_clk;
125         struct clk *iahb_clk;
126         struct dw_hdmi_i2c *i2c;
127
128         struct hdmi_data_info hdmi_data;
129         const struct dw_hdmi_plat_data *plat_data;
130
131         int vic;
132
133         u8 edid[HDMI_EDID_LEN];
134         bool cable_plugin;
135
136         bool phy_enabled;
137         struct drm_display_mode previous_mode;
138
139         struct i2c_adapter *ddc;
140         void __iomem *regs;
141         bool sink_is_hdmi;
142         bool sink_has_audio;
143
144         struct mutex mutex;             /* for state below and previous_mode */
145         enum drm_connector_force force; /* mutex-protected force state */
146         bool disabled;                  /* DRM has disabled our bridge */
147         bool bridge_is_on;              /* indicates the bridge is on */
148         bool rxsense;                   /* rxsense state */
149         u8 phy_mask;                    /* desired phy int mask settings */
150
151         spinlock_t audio_lock;
152         struct mutex audio_mutex;
153         unsigned int sample_rate;
154         unsigned int audio_cts;
155         unsigned int audio_n;
156         bool audio_enable;
157
158         void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
159         u8 (*read)(struct dw_hdmi *hdmi, int offset);
160 };
161
162 #define HDMI_IH_PHY_STAT0_RX_SENSE \
163         (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
164          HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
165
166 #define HDMI_PHY_RX_SENSE \
167         (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
168          HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
169
170 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
171 {
172         writel(val, hdmi->regs + (offset << 2));
173 }
174
175 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset)
176 {
177         return readl(hdmi->regs + (offset << 2));
178 }
179
180 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
181 {
182         writeb(val, hdmi->regs + offset);
183 }
184
185 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset)
186 {
187         return readb(hdmi->regs + offset);
188 }
189
190 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
191 {
192         hdmi->write(hdmi, val, offset);
193 }
194
195 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
196 {
197         return hdmi->read(hdmi, offset);
198 }
199
200 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
201 {
202         u8 val = hdmi_readb(hdmi, reg) & ~mask;
203
204         val |= data & mask;
205         hdmi_writeb(hdmi, val, reg);
206 }
207
208 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
209                              u8 shift, u8 mask)
210 {
211         hdmi_modb(hdmi, data << shift, mask, reg);
212 }
213
214 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
215 {
216         /* Software reset */
217         hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
218
219         /* Set Standard Mode speed (determined to be 100KHz on iMX6) */
220         hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV);
221
222         /* Set done, not acknowledged and arbitration interrupt polarities */
223         hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
224         hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
225                     HDMI_I2CM_CTLINT);
226
227         /* Clear DONE and ERROR interrupts */
228         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
229                     HDMI_IH_I2CM_STAT0);
230
231         /* Mute DONE and ERROR interrupts */
232         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
233                     HDMI_IH_MUTE_I2CM_STAT0);
234 }
235
236 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
237                             unsigned char *buf, unsigned int length)
238 {
239         struct dw_hdmi_i2c *i2c = hdmi->i2c;
240         int stat;
241
242         if (!i2c->is_regaddr) {
243                 dev_dbg(hdmi->dev, "set read register address to 0\n");
244                 i2c->slave_reg = 0x00;
245                 i2c->is_regaddr = true;
246         }
247
248         while (length--) {
249                 reinit_completion(&i2c->cmp);
250
251                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
252                 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
253                             HDMI_I2CM_OPERATION);
254
255                 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
256                 if (!stat)
257                         return -EAGAIN;
258
259                 /* Check for error condition on the bus */
260                 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
261                         return -EIO;
262
263                 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
264         }
265
266         return 0;
267 }
268
269 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
270                              unsigned char *buf, unsigned int length)
271 {
272         struct dw_hdmi_i2c *i2c = hdmi->i2c;
273         int stat;
274
275         if (!i2c->is_regaddr) {
276                 /* Use the first write byte as register address */
277                 i2c->slave_reg = buf[0];
278                 length--;
279                 buf++;
280                 i2c->is_regaddr = true;
281         }
282
283         while (length--) {
284                 reinit_completion(&i2c->cmp);
285
286                 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
287                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
288                 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
289                             HDMI_I2CM_OPERATION);
290
291                 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
292                 if (!stat)
293                         return -EAGAIN;
294
295                 /* Check for error condition on the bus */
296                 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
297                         return -EIO;
298         }
299
300         return 0;
301 }
302
303 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
304                             struct i2c_msg *msgs, int num)
305 {
306         struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
307         struct dw_hdmi_i2c *i2c = hdmi->i2c;
308         u8 addr = msgs[0].addr;
309         int i, ret = 0;
310
311         dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
312
313         for (i = 0; i < num; i++) {
314                 if (msgs[i].addr != addr) {
315                         dev_warn(hdmi->dev,
316                                  "unsupported transfer, changed slave address\n");
317                         return -EOPNOTSUPP;
318                 }
319
320                 if (msgs[i].len == 0) {
321                         dev_dbg(hdmi->dev,
322                                 "unsupported transfer %d/%d, no data\n",
323                                 i + 1, num);
324                         return -EOPNOTSUPP;
325                 }
326         }
327
328         mutex_lock(&i2c->lock);
329
330         /* Unmute DONE and ERROR interrupts */
331         hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
332
333         /* Set slave device address taken from the first I2C message */
334         hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
335
336         /* Set slave device register address on transfer */
337         i2c->is_regaddr = false;
338
339         for (i = 0; i < num; i++) {
340                 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
341                         i + 1, num, msgs[i].len, msgs[i].flags);
342
343                 if (msgs[i].flags & I2C_M_RD)
344                         ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, msgs[i].len);
345                 else
346                         ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, msgs[i].len);
347
348                 if (ret < 0)
349                         break;
350         }
351
352         if (!ret)
353                 ret = num;
354
355         /* Mute DONE and ERROR interrupts */
356         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
357                     HDMI_IH_MUTE_I2CM_STAT0);
358
359         mutex_unlock(&i2c->lock);
360
361         return ret;
362 }
363
364 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
365 {
366         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
367 }
368
369 static const struct i2c_algorithm dw_hdmi_algorithm = {
370         .master_xfer    = dw_hdmi_i2c_xfer,
371         .functionality  = dw_hdmi_i2c_func,
372 };
373
374 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
375 {
376         struct i2c_adapter *adap;
377         struct dw_hdmi_i2c *i2c;
378         int ret;
379
380         i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
381         if (!i2c)
382                 return ERR_PTR(-ENOMEM);
383
384         mutex_init(&i2c->lock);
385         init_completion(&i2c->cmp);
386
387         adap = &i2c->adap;
388         adap->class = I2C_CLASS_DDC;
389         adap->owner = THIS_MODULE;
390         adap->dev.parent = hdmi->dev;
391         adap->algo = &dw_hdmi_algorithm;
392         strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
393         i2c_set_adapdata(adap, hdmi);
394
395         ret = i2c_add_adapter(adap);
396         if (ret) {
397                 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
398                 devm_kfree(hdmi->dev, i2c);
399                 return ERR_PTR(ret);
400         }
401
402         hdmi->i2c = i2c;
403
404         dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
405
406         return adap;
407 }
408
409 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
410                            unsigned int n)
411 {
412         /* Must be set/cleared first */
413         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
414
415         /* nshift factor = 0 */
416         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
417
418         hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
419                     HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
420         hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
421         hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
422
423         hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
424         hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
425         hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
426 }
427
428 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
429 {
430         unsigned int n = (128 * freq) / 1000;
431         unsigned int mult = 1;
432
433         while (freq > 48000) {
434                 mult *= 2;
435                 freq /= 2;
436         }
437
438         switch (freq) {
439         case 32000:
440                 if (pixel_clk == 25175000)
441                         n = 4576;
442                 else if (pixel_clk == 27027000)
443                         n = 4096;
444                 else if (pixel_clk == 74176000 || pixel_clk == 148352000)
445                         n = 11648;
446                 else
447                         n = 4096;
448                 n *= mult;
449                 break;
450
451         case 44100:
452                 if (pixel_clk == 25175000)
453                         n = 7007;
454                 else if (pixel_clk == 74176000)
455                         n = 17836;
456                 else if (pixel_clk == 148352000)
457                         n = 8918;
458                 else
459                         n = 6272;
460                 n *= mult;
461                 break;
462
463         case 48000:
464                 if (pixel_clk == 25175000)
465                         n = 6864;
466                 else if (pixel_clk == 27027000)
467                         n = 6144;
468                 else if (pixel_clk == 74176000)
469                         n = 11648;
470                 else if (pixel_clk == 148352000)
471                         n = 5824;
472                 else
473                         n = 6144;
474                 n *= mult;
475                 break;
476
477         default:
478                 break;
479         }
480
481         return n;
482 }
483
484 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
485         unsigned long pixel_clk, unsigned int sample_rate)
486 {
487         unsigned long ftdms = pixel_clk;
488         unsigned int n, cts;
489         u64 tmp;
490
491         n = hdmi_compute_n(sample_rate, pixel_clk);
492
493         /*
494          * Compute the CTS value from the N value.  Note that CTS and N
495          * can be up to 20 bits in total, so we need 64-bit math.  Also
496          * note that our TDMS clock is not fully accurate; it is accurate
497          * to kHz.  This can introduce an unnecessary remainder in the
498          * calculation below, so we don't try to warn about that.
499          */
500         tmp = (u64)ftdms * n;
501         do_div(tmp, 128 * sample_rate);
502         cts = tmp;
503
504         dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
505                 __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000,
506                 n, cts);
507
508         spin_lock_irq(&hdmi->audio_lock);
509         hdmi->audio_n = n;
510         hdmi->audio_cts = cts;
511         hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
512         spin_unlock_irq(&hdmi->audio_lock);
513 }
514
515 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
516 {
517         mutex_lock(&hdmi->audio_mutex);
518         hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
519         mutex_unlock(&hdmi->audio_mutex);
520 }
521
522 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
523 {
524         mutex_lock(&hdmi->audio_mutex);
525         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
526                                  hdmi->sample_rate);
527         mutex_unlock(&hdmi->audio_mutex);
528 }
529
530 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
531 {
532         mutex_lock(&hdmi->audio_mutex);
533         hdmi->sample_rate = rate;
534         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
535                                  hdmi->sample_rate);
536         mutex_unlock(&hdmi->audio_mutex);
537 }
538 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
539
540 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
541 {
542         unsigned long flags;
543
544         spin_lock_irqsave(&hdmi->audio_lock, flags);
545         hdmi->audio_enable = true;
546         hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
547         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
548 }
549 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
550
551 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
552 {
553         unsigned long flags;
554
555         spin_lock_irqsave(&hdmi->audio_lock, flags);
556         hdmi->audio_enable = false;
557         hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
558         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
559 }
560 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
561
562 /*
563  * this submodule is responsible for the video data synchronization.
564  * for example, for RGB 4:4:4 input, the data map is defined as
565  *                      pin{47~40} <==> R[7:0]
566  *                      pin{31~24} <==> G[7:0]
567  *                      pin{15~8}  <==> B[7:0]
568  */
569 static void hdmi_video_sample(struct dw_hdmi *hdmi)
570 {
571         int color_format = 0;
572         u8 val;
573
574         if (hdmi->hdmi_data.enc_in_format == RGB) {
575                 if (hdmi->hdmi_data.enc_color_depth == 8)
576                         color_format = 0x01;
577                 else if (hdmi->hdmi_data.enc_color_depth == 10)
578                         color_format = 0x03;
579                 else if (hdmi->hdmi_data.enc_color_depth == 12)
580                         color_format = 0x05;
581                 else if (hdmi->hdmi_data.enc_color_depth == 16)
582                         color_format = 0x07;
583                 else
584                         return;
585         } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
586                 if (hdmi->hdmi_data.enc_color_depth == 8)
587                         color_format = 0x09;
588                 else if (hdmi->hdmi_data.enc_color_depth == 10)
589                         color_format = 0x0B;
590                 else if (hdmi->hdmi_data.enc_color_depth == 12)
591                         color_format = 0x0D;
592                 else if (hdmi->hdmi_data.enc_color_depth == 16)
593                         color_format = 0x0F;
594                 else
595                         return;
596         } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
597                 if (hdmi->hdmi_data.enc_color_depth == 8)
598                         color_format = 0x16;
599                 else if (hdmi->hdmi_data.enc_color_depth == 10)
600                         color_format = 0x14;
601                 else if (hdmi->hdmi_data.enc_color_depth == 12)
602                         color_format = 0x12;
603                 else
604                         return;
605         }
606
607         val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
608                 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
609                 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
610         hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
611
612         /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
613         val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
614                 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
615                 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
616         hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
617         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
618         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
619         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
620         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
621         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
622         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
623 }
624
625 static int is_color_space_conversion(struct dw_hdmi *hdmi)
626 {
627         return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
628 }
629
630 static int is_color_space_decimation(struct dw_hdmi *hdmi)
631 {
632         if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
633                 return 0;
634         if (hdmi->hdmi_data.enc_in_format == RGB ||
635             hdmi->hdmi_data.enc_in_format == YCBCR444)
636                 return 1;
637         return 0;
638 }
639
640 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
641 {
642         if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
643                 return 0;
644         if (hdmi->hdmi_data.enc_out_format == RGB ||
645             hdmi->hdmi_data.enc_out_format == YCBCR444)
646                 return 1;
647         return 0;
648 }
649
650 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
651 {
652         const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
653         unsigned i;
654         u32 csc_scale = 1;
655
656         if (is_color_space_conversion(hdmi)) {
657                 if (hdmi->hdmi_data.enc_out_format == RGB) {
658                         if (hdmi->hdmi_data.colorimetry ==
659                                         HDMI_COLORIMETRY_ITU_601)
660                                 csc_coeff = &csc_coeff_rgb_out_eitu601;
661                         else
662                                 csc_coeff = &csc_coeff_rgb_out_eitu709;
663                 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
664                         if (hdmi->hdmi_data.colorimetry ==
665                                         HDMI_COLORIMETRY_ITU_601)
666                                 csc_coeff = &csc_coeff_rgb_in_eitu601;
667                         else
668                                 csc_coeff = &csc_coeff_rgb_in_eitu709;
669                         csc_scale = 0;
670                 }
671         }
672
673         /* The CSC registers are sequential, alternating MSB then LSB */
674         for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
675                 u16 coeff_a = (*csc_coeff)[0][i];
676                 u16 coeff_b = (*csc_coeff)[1][i];
677                 u16 coeff_c = (*csc_coeff)[2][i];
678
679                 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
680                 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
681                 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
682                 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
683                 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
684                 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
685         }
686
687         hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
688                   HDMI_CSC_SCALE);
689 }
690
691 static void hdmi_video_csc(struct dw_hdmi *hdmi)
692 {
693         int color_depth = 0;
694         int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
695         int decimation = 0;
696
697         /* YCC422 interpolation to 444 mode */
698         if (is_color_space_interpolation(hdmi))
699                 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
700         else if (is_color_space_decimation(hdmi))
701                 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
702
703         if (hdmi->hdmi_data.enc_color_depth == 8)
704                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
705         else if (hdmi->hdmi_data.enc_color_depth == 10)
706                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
707         else if (hdmi->hdmi_data.enc_color_depth == 12)
708                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
709         else if (hdmi->hdmi_data.enc_color_depth == 16)
710                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
711         else
712                 return;
713
714         /* Configure the CSC registers */
715         hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
716         hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
717                   HDMI_CSC_SCALE);
718
719         dw_hdmi_update_csc_coeffs(hdmi);
720 }
721
722 /*
723  * HDMI video packetizer is used to packetize the data.
724  * for example, if input is YCC422 mode or repeater is used,
725  * data should be repacked this module can be bypassed.
726  */
727 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
728 {
729         unsigned int color_depth = 0;
730         unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
731         unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
732         struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
733         u8 val, vp_conf;
734
735         if (hdmi_data->enc_out_format == RGB ||
736             hdmi_data->enc_out_format == YCBCR444) {
737                 if (!hdmi_data->enc_color_depth) {
738                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
739                 } else if (hdmi_data->enc_color_depth == 8) {
740                         color_depth = 4;
741                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
742                 } else if (hdmi_data->enc_color_depth == 10) {
743                         color_depth = 5;
744                 } else if (hdmi_data->enc_color_depth == 12) {
745                         color_depth = 6;
746                 } else if (hdmi_data->enc_color_depth == 16) {
747                         color_depth = 7;
748                 } else {
749                         return;
750                 }
751         } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
752                 if (!hdmi_data->enc_color_depth ||
753                     hdmi_data->enc_color_depth == 8)
754                         remap_size = HDMI_VP_REMAP_YCC422_16bit;
755                 else if (hdmi_data->enc_color_depth == 10)
756                         remap_size = HDMI_VP_REMAP_YCC422_20bit;
757                 else if (hdmi_data->enc_color_depth == 12)
758                         remap_size = HDMI_VP_REMAP_YCC422_24bit;
759                 else
760                         return;
761                 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
762         } else {
763                 return;
764         }
765
766         /* set the packetizer registers */
767         val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
768                 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
769                 ((hdmi_data->pix_repet_factor <<
770                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
771                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
772         hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
773
774         hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
775                   HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
776
777         /* Data from pixel repeater block */
778         if (hdmi_data->pix_repet_factor > 1) {
779                 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
780                           HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
781         } else { /* data from packetizer block */
782                 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
783                           HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
784         }
785
786         hdmi_modb(hdmi, vp_conf,
787                   HDMI_VP_CONF_PR_EN_MASK |
788                   HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
789
790         hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
791                   HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
792
793         hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
794
795         if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
796                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
797                           HDMI_VP_CONF_PP_EN_ENABLE |
798                           HDMI_VP_CONF_YCC422_EN_DISABLE;
799         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
800                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
801                           HDMI_VP_CONF_PP_EN_DISABLE |
802                           HDMI_VP_CONF_YCC422_EN_ENABLE;
803         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
804                 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
805                           HDMI_VP_CONF_PP_EN_DISABLE |
806                           HDMI_VP_CONF_YCC422_EN_DISABLE;
807         } else {
808                 return;
809         }
810
811         hdmi_modb(hdmi, vp_conf,
812                   HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
813                   HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
814
815         hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
816                         HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
817                   HDMI_VP_STUFF_PP_STUFFING_MASK |
818                   HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
819
820         hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
821                   HDMI_VP_CONF);
822 }
823
824 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
825                                        unsigned char bit)
826 {
827         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
828                   HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
829 }
830
831 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
832                                         unsigned char bit)
833 {
834         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
835                   HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
836 }
837
838 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
839                                        unsigned char bit)
840 {
841         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
842                   HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
843 }
844
845 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
846                                      unsigned char bit)
847 {
848         hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
849 }
850
851 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
852                                       unsigned char bit)
853 {
854         hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
855 }
856
857 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
858 {
859         u32 val;
860
861         while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
862                 if (msec-- == 0)
863                         return false;
864                 udelay(1000);
865         }
866         hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
867
868         return true;
869 }
870
871 static void __hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
872                                  unsigned char addr)
873 {
874         hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
875         hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
876         hdmi_writeb(hdmi, (unsigned char)(data >> 8),
877                     HDMI_PHY_I2CM_DATAO_1_ADDR);
878         hdmi_writeb(hdmi, (unsigned char)(data >> 0),
879                     HDMI_PHY_I2CM_DATAO_0_ADDR);
880         hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
881                     HDMI_PHY_I2CM_OPERATION_ADDR);
882         hdmi_phy_wait_i2c_done(hdmi, 1000);
883 }
884
885 static int hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
886                               unsigned char addr)
887 {
888         __hdmi_phy_i2c_write(hdmi, data, addr);
889         return 0;
890 }
891
892 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
893 {
894         hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
895                          HDMI_PHY_CONF0_PDZ_OFFSET,
896                          HDMI_PHY_CONF0_PDZ_MASK);
897 }
898
899 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
900 {
901         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
902                          HDMI_PHY_CONF0_ENTMDS_OFFSET,
903                          HDMI_PHY_CONF0_ENTMDS_MASK);
904 }
905
906 static void dw_hdmi_phy_enable_spare(struct dw_hdmi *hdmi, u8 enable)
907 {
908         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
909                          HDMI_PHY_CONF0_SPARECTRL_OFFSET,
910                          HDMI_PHY_CONF0_SPARECTRL_MASK);
911 }
912
913 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
914 {
915         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
916                          HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
917                          HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
918 }
919
920 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
921 {
922         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
923                          HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
924                          HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
925 }
926
927 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
928 {
929         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
930                          HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
931                          HDMI_PHY_CONF0_SELDATAENPOL_MASK);
932 }
933
934 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
935 {
936         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
937                          HDMI_PHY_CONF0_SELDIPIF_OFFSET,
938                          HDMI_PHY_CONF0_SELDIPIF_MASK);
939 }
940
941 static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
942                               unsigned char res, int cscon)
943 {
944         unsigned res_idx;
945         u8 val, msec;
946         const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
947         const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
948         const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
949         const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
950
951         if (prep)
952                 return -EINVAL;
953
954         switch (res) {
955         case 0: /* color resolution 0 is 8 bit colour depth */
956         case 8:
957                 res_idx = DW_HDMI_RES_8;
958                 break;
959         case 10:
960                 res_idx = DW_HDMI_RES_10;
961                 break;
962         case 12:
963                 res_idx = DW_HDMI_RES_12;
964                 break;
965         default:
966                 return -EINVAL;
967         }
968
969         /* PLL/MPLL Cfg - always match on final entry */
970         for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
971                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
972                     mpll_config->mpixelclock)
973                         break;
974
975         for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
976                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
977                     curr_ctrl->mpixelclock)
978                         break;
979
980         for (; phy_config->mpixelclock != ~0UL; phy_config++)
981                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
982                     phy_config->mpixelclock)
983                         break;
984
985         if (mpll_config->mpixelclock == ~0UL ||
986             curr_ctrl->mpixelclock == ~0UL ||
987             phy_config->mpixelclock == ~0UL) {
988                 dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
989                         hdmi->hdmi_data.video_mode.mpixelclock);
990                 return -EINVAL;
991         }
992
993         /* Enable csc path */
994         if (cscon)
995                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
996         else
997                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
998
999         hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
1000
1001         /* gen2 tx power off */
1002         dw_hdmi_phy_gen2_txpwron(hdmi, 0);
1003
1004         /* gen2 pddq */
1005         dw_hdmi_phy_gen2_pddq(hdmi, 1);
1006
1007         /* PHY reset */
1008         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
1009         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
1010
1011         hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1012
1013         hdmi_phy_test_clear(hdmi, 1);
1014         hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
1015                     HDMI_PHY_I2CM_SLAVE_ADDR);
1016         hdmi_phy_test_clear(hdmi, 0);
1017
1018         hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce, 0x06);
1019         hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].gmp, 0x15);
1020
1021         /* CURRCTRL */
1022         hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[res_idx], 0x10);
1023
1024         hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);  /* PLLPHBYCTRL */
1025         hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
1026
1027         hdmi_phy_i2c_write(hdmi, phy_config->term, 0x19);  /* TXTERM */
1028         hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 0x09); /* CKSYMTXCTRL */
1029         hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 0x0E); /* VLEVCTRL */
1030
1031         /* REMOVE CLK TERM */
1032         hdmi_phy_i2c_write(hdmi, 0x8000, 0x05);  /* CKCALCTRL */
1033
1034         dw_hdmi_phy_enable_powerdown(hdmi, false);
1035
1036         /* toggle TMDS enable */
1037         dw_hdmi_phy_enable_tmds(hdmi, 0);
1038         dw_hdmi_phy_enable_tmds(hdmi, 1);
1039
1040         /* gen2 tx power on */
1041         dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1042         dw_hdmi_phy_gen2_pddq(hdmi, 0);
1043
1044         if (hdmi->dev_type == RK3288_HDMI)
1045                 dw_hdmi_phy_enable_spare(hdmi, 1);
1046
1047         /*Wait for PHY PLL lock */
1048         msec = 5;
1049         do {
1050                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1051                 if (!val)
1052                         break;
1053
1054                 if (msec == 0) {
1055                         dev_err(hdmi->dev, "PHY PLL not locked\n");
1056                         return -ETIMEDOUT;
1057                 }
1058
1059                 udelay(1000);
1060                 msec--;
1061         } while (1);
1062
1063         return 0;
1064 }
1065
1066 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi)
1067 {
1068         int i, ret;
1069         bool cscon;
1070
1071         /*check csc whether needed activated in HDMI mode */
1072         cscon = hdmi->sink_is_hdmi && is_color_space_conversion(hdmi);
1073
1074         /* HDMI Phy spec says to do the phy initialization sequence twice */
1075         for (i = 0; i < 2; i++) {
1076                 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1077                 dw_hdmi_phy_sel_interface_control(hdmi, 0);
1078                 dw_hdmi_phy_enable_tmds(hdmi, 0);
1079                 dw_hdmi_phy_enable_powerdown(hdmi, true);
1080
1081                 /* Enable CSC */
1082                 ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
1083                 if (ret)
1084                         return ret;
1085         }
1086
1087         hdmi->phy_enabled = true;
1088         return 0;
1089 }
1090
1091 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
1092 {
1093         u8 de;
1094
1095         if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1096                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
1097         else
1098                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1099
1100         /* disable rx detect */
1101         hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1102                   HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
1103
1104         hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
1105
1106         hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1107                   HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
1108 }
1109
1110 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1111 {
1112         struct hdmi_avi_infoframe frame;
1113         u8 val;
1114
1115         /* Initialise info frame from DRM mode */
1116         drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1117
1118         if (hdmi->hdmi_data.enc_out_format == YCBCR444)
1119                 frame.colorspace = HDMI_COLORSPACE_YUV444;
1120         else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
1121                 frame.colorspace = HDMI_COLORSPACE_YUV422;
1122         else
1123                 frame.colorspace = HDMI_COLORSPACE_RGB;
1124
1125         /* Set up colorimetry */
1126         if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
1127                 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1128                 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
1129                         frame.extended_colorimetry =
1130                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1131                 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
1132                         frame.extended_colorimetry =
1133                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1134         } else if (hdmi->hdmi_data.enc_out_format != RGB) {
1135                 frame.colorimetry = hdmi->hdmi_data.colorimetry;
1136                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1137         } else { /* Carries no data */
1138                 frame.colorimetry = HDMI_COLORIMETRY_NONE;
1139                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1140         }
1141
1142         frame.scan_mode = HDMI_SCAN_MODE_NONE;
1143
1144         /*
1145          * The Designware IP uses a different byte format from standard
1146          * AVI info frames, though generally the bits are in the correct
1147          * bytes.
1148          */
1149
1150         /*
1151          * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6,
1152          * scan info in bits 4,5 rather than 0,1 and active aspect present in
1153          * bit 6 rather than 4.
1154          */
1155         val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3);
1156         if (frame.active_aspect & 15)
1157                 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1158         if (frame.top_bar || frame.bottom_bar)
1159                 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1160         if (frame.left_bar || frame.right_bar)
1161                 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1162         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1163
1164         /* AVI data byte 2 differences: none */
1165         val = ((frame.colorimetry & 0x3) << 6) |
1166               ((frame.picture_aspect & 0x3) << 4) |
1167               (frame.active_aspect & 0xf);
1168         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1169
1170         /* AVI data byte 3 differences: none */
1171         val = ((frame.extended_colorimetry & 0x7) << 4) |
1172               ((frame.quantization_range & 0x3) << 2) |
1173               (frame.nups & 0x3);
1174         if (frame.itc)
1175                 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1176         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1177
1178         /* AVI data byte 4 differences: none */
1179         val = frame.video_code & 0x7f;
1180         hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1181
1182         /* AVI Data Byte 5- set up input and output pixel repetition */
1183         val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1184                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1185                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1186                 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1187                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1188                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1189         hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1190
1191         /*
1192          * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1193          * ycc range in bits 2,3 rather than 6,7
1194          */
1195         val = ((frame.ycc_quantization_range & 0x3) << 2) |
1196               (frame.content_type & 0x3);
1197         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1198
1199         /* AVI Data Bytes 6-13 */
1200         hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1201         hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1202         hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1203         hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1204         hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1205         hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1206         hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1207         hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1208 }
1209
1210 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1211                              const struct drm_display_mode *mode)
1212 {
1213         u8 inv_val;
1214         struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1215         int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1216         unsigned int vdisplay;
1217
1218         vmode->mpixelclock = mode->clock * 1000;
1219
1220         dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1221
1222         /* Set up HDMI_FC_INVIDCONF */
1223         inv_val = (hdmi->hdmi_data.hdcp_enable ?
1224                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1225                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1226
1227         inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1228                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1229                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1230
1231         inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1232                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1233                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1234
1235         inv_val |= (vmode->mdataenablepolarity ?
1236                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1237                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1238
1239         if (hdmi->vic == 39)
1240                 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1241         else
1242                 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1243                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1244                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1245
1246         inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1247                 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1248                 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1249
1250         inv_val |= hdmi->sink_is_hdmi ?
1251                 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1252                 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1253
1254         hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1255
1256         vdisplay = mode->vdisplay;
1257         vblank = mode->vtotal - mode->vdisplay;
1258         v_de_vs = mode->vsync_start - mode->vdisplay;
1259         vsync_len = mode->vsync_end - mode->vsync_start;
1260
1261         /*
1262          * When we're setting an interlaced mode, we need
1263          * to adjust the vertical timing to suit.
1264          */
1265         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1266                 vdisplay /= 2;
1267                 vblank /= 2;
1268                 v_de_vs /= 2;
1269                 vsync_len /= 2;
1270         }
1271
1272         /* Set up horizontal active pixel width */
1273         hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
1274         hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
1275
1276         /* Set up vertical active lines */
1277         hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1278         hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
1279
1280         /* Set up horizontal blanking pixel region width */
1281         hblank = mode->htotal - mode->hdisplay;
1282         hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1283         hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1284
1285         /* Set up vertical blanking pixel region width */
1286         hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1287
1288         /* Set up HSYNC active edge delay width (in pixel clks) */
1289         h_de_hs = mode->hsync_start - mode->hdisplay;
1290         hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1291         hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1292
1293         /* Set up VSYNC active edge delay (in lines) */
1294         hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1295
1296         /* Set up HSYNC active pulse width (in pixel clks) */
1297         hsync_len = mode->hsync_end - mode->hsync_start;
1298         hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1299         hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1300
1301         /* Set up VSYNC active edge delay (in lines) */
1302         hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1303 }
1304
1305 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi)
1306 {
1307         if (!hdmi->phy_enabled)
1308                 return;
1309
1310         dw_hdmi_phy_enable_tmds(hdmi, 0);
1311         dw_hdmi_phy_enable_powerdown(hdmi, true);
1312
1313         hdmi->phy_enabled = false;
1314 }
1315
1316 /* HDMI Initialization Step B.4 */
1317 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1318 {
1319         u8 clkdis;
1320
1321         /* control period minimum duration */
1322         hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1323         hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1324         hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1325
1326         /* Set to fill TMDS data channels */
1327         hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1328         hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1329         hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1330
1331         /* Enable pixel clock and tmds data path */
1332         clkdis = 0x7F;
1333         clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1334         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1335
1336         clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1337         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1338
1339         /* Enable csc path */
1340         if (is_color_space_conversion(hdmi)) {
1341                 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1342                 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1343         }
1344 }
1345
1346 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
1347 {
1348         hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
1349 }
1350
1351 /* Workaround to clear the overflow condition */
1352 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1353 {
1354         int count;
1355         u8 val;
1356
1357         /* TMDS software reset */
1358         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1359
1360         val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1361         if (hdmi->dev_type == IMX6DL_HDMI) {
1362                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1363                 return;
1364         }
1365
1366         for (count = 0; count < 4; count++)
1367                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1368 }
1369
1370 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
1371 {
1372         hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1373         hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1374 }
1375
1376 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1377 {
1378         hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1379                     HDMI_IH_MUTE_FC_STAT2);
1380 }
1381
1382 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1383 {
1384         int ret;
1385
1386         hdmi_disable_overflow_interrupts(hdmi);
1387
1388         hdmi->vic = drm_match_cea_mode(mode);
1389
1390         if (!hdmi->vic) {
1391                 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1392         } else {
1393                 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1394         }
1395
1396         if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1397             (hdmi->vic == 21) || (hdmi->vic == 22) ||
1398             (hdmi->vic == 2) || (hdmi->vic == 3) ||
1399             (hdmi->vic == 17) || (hdmi->vic == 18))
1400                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
1401         else
1402                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
1403
1404         hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1405         hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1406
1407         /* TODO: Get input format from IPU (via FB driver interface) */
1408         hdmi->hdmi_data.enc_in_format = RGB;
1409
1410         hdmi->hdmi_data.enc_out_format = RGB;
1411
1412         hdmi->hdmi_data.enc_color_depth = 8;
1413         hdmi->hdmi_data.pix_repet_factor = 0;
1414         hdmi->hdmi_data.hdcp_enable = 0;
1415         hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1416
1417         /* HDMI Initialization Step B.1 */
1418         hdmi_av_composer(hdmi, mode);
1419
1420         /* HDMI Initializateion Step B.2 */
1421         ret = dw_hdmi_phy_init(hdmi);
1422         if (ret)
1423                 return ret;
1424
1425         /* HDMI Initialization Step B.3 */
1426         dw_hdmi_enable_video_path(hdmi);
1427
1428         if (hdmi->sink_has_audio) {
1429                 dev_dbg(hdmi->dev, "sink has audio support\n");
1430
1431                 /* HDMI Initialization Step E - Configure audio */
1432                 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1433                 hdmi_enable_audio_clk(hdmi);
1434         }
1435
1436         /* not for DVI mode */
1437         if (hdmi->sink_is_hdmi) {
1438                 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
1439
1440                 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1441                 hdmi_config_AVI(hdmi, mode);
1442         } else {
1443                 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1444         }
1445
1446         hdmi_video_packetize(hdmi);
1447         hdmi_video_csc(hdmi);
1448         hdmi_video_sample(hdmi);
1449         hdmi_tx_hdcp_config(hdmi);
1450
1451         dw_hdmi_clear_overflow(hdmi);
1452         if (hdmi->cable_plugin && hdmi->sink_is_hdmi)
1453                 hdmi_enable_overflow_interrupts(hdmi);
1454
1455         return 0;
1456 }
1457
1458 /* Wait until we are registered to enable interrupts */
1459 static int dw_hdmi_fb_registered(struct dw_hdmi *hdmi)
1460 {
1461         hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
1462                     HDMI_PHY_I2CM_INT_ADDR);
1463
1464         hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
1465                     HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
1466                     HDMI_PHY_I2CM_CTLINT_ADDR);
1467
1468         /* enable cable hot plug irq */
1469         hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1470
1471         /* Clear Hotplug interrupts */
1472         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1473                     HDMI_IH_PHY_STAT0);
1474
1475         return 0;
1476 }
1477
1478 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
1479 {
1480         u8 ih_mute;
1481
1482         /*
1483          * Boot up defaults are:
1484          * HDMI_IH_MUTE   = 0x03 (disabled)
1485          * HDMI_IH_MUTE_* = 0x00 (enabled)
1486          *
1487          * Disable top level interrupt bits in HDMI block
1488          */
1489         ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1490                   HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1491                   HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1492
1493         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1494
1495         /* by default mask all interrupts */
1496         hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1497         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1498         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1499         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1500         hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1501         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1502         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1503         hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1504         hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1505         hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1506         hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1507         hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1508         hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1509         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1510         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1511
1512         /* Disable interrupts in the IH_MUTE_* registers */
1513         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1514         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1515         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1516         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1517         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1518         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1519         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1520         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1521         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1522         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1523
1524         /* Enable top level interrupt bits in HDMI block */
1525         ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1526                     HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1527         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1528 }
1529
1530 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
1531 {
1532         hdmi->bridge_is_on = true;
1533         dw_hdmi_setup(hdmi, &hdmi->previous_mode);
1534 }
1535
1536 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
1537 {
1538         dw_hdmi_phy_disable(hdmi);
1539         hdmi->bridge_is_on = false;
1540 }
1541
1542 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
1543 {
1544         int force = hdmi->force;
1545
1546         if (hdmi->disabled) {
1547                 force = DRM_FORCE_OFF;
1548         } else if (force == DRM_FORCE_UNSPECIFIED) {
1549                 if (hdmi->rxsense)
1550                         force = DRM_FORCE_ON;
1551                 else
1552                         force = DRM_FORCE_OFF;
1553         }
1554
1555         if (force == DRM_FORCE_OFF) {
1556                 if (hdmi->bridge_is_on)
1557                         dw_hdmi_poweroff(hdmi);
1558         } else {
1559                 if (!hdmi->bridge_is_on)
1560                         dw_hdmi_poweron(hdmi);
1561         }
1562 }
1563
1564 /*
1565  * Adjust the detection of RXSENSE according to whether we have a forced
1566  * connection mode enabled, or whether we have been disabled.  There is
1567  * no point processing RXSENSE interrupts if we have a forced connection
1568  * state, or DRM has us disabled.
1569  *
1570  * We also disable rxsense interrupts when we think we're disconnected
1571  * to avoid floating TDMS signals giving false rxsense interrupts.
1572  *
1573  * Note: we still need to listen for HPD interrupts even when DRM has us
1574  * disabled so that we can detect a connect event.
1575  */
1576 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
1577 {
1578         u8 old_mask = hdmi->phy_mask;
1579
1580         if (hdmi->force || hdmi->disabled || !hdmi->rxsense)
1581                 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1582         else
1583                 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1584
1585         if (old_mask != hdmi->phy_mask)
1586                 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1587 }
1588
1589 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1590                                     struct drm_display_mode *orig_mode,
1591                                     struct drm_display_mode *mode)
1592 {
1593         struct dw_hdmi *hdmi = bridge->driver_private;
1594
1595         mutex_lock(&hdmi->mutex);
1596
1597         /* Store the display mode for plugin/DKMS poweron events */
1598         memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1599
1600         mutex_unlock(&hdmi->mutex);
1601 }
1602
1603 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
1604 {
1605         struct dw_hdmi *hdmi = bridge->driver_private;
1606
1607         mutex_lock(&hdmi->mutex);
1608         hdmi->disabled = true;
1609         dw_hdmi_update_power(hdmi);
1610         dw_hdmi_update_phy_mask(hdmi);
1611         mutex_unlock(&hdmi->mutex);
1612 }
1613
1614 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
1615 {
1616         struct dw_hdmi *hdmi = bridge->driver_private;
1617
1618         mutex_lock(&hdmi->mutex);
1619         hdmi->disabled = false;
1620         dw_hdmi_update_power(hdmi);
1621         dw_hdmi_update_phy_mask(hdmi);
1622         mutex_unlock(&hdmi->mutex);
1623 }
1624
1625 static enum drm_connector_status
1626 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
1627 {
1628         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1629                                              connector);
1630
1631         mutex_lock(&hdmi->mutex);
1632         hdmi->force = DRM_FORCE_UNSPECIFIED;
1633         dw_hdmi_update_power(hdmi);
1634         dw_hdmi_update_phy_mask(hdmi);
1635         mutex_unlock(&hdmi->mutex);
1636
1637         return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1638                 connector_status_connected : connector_status_disconnected;
1639 }
1640
1641 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
1642 {
1643         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1644                                              connector);
1645         struct edid *edid;
1646         int ret = 0;
1647
1648         if (!hdmi->ddc)
1649                 return 0;
1650
1651         edid = drm_get_edid(connector, hdmi->ddc);
1652         if (edid) {
1653                 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1654                         edid->width_cm, edid->height_cm);
1655
1656                 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
1657                 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
1658                 drm_mode_connector_update_edid_property(connector, edid);
1659                 ret = drm_add_edid_modes(connector, edid);
1660                 /* Store the ELD */
1661                 drm_edid_to_eld(connector, edid);
1662                 kfree(edid);
1663         } else {
1664                 dev_dbg(hdmi->dev, "failed to get edid\n");
1665         }
1666
1667         return ret;
1668 }
1669
1670 static enum drm_mode_status
1671 dw_hdmi_connector_mode_valid(struct drm_connector *connector,
1672                              struct drm_display_mode *mode)
1673 {
1674         struct dw_hdmi *hdmi = container_of(connector,
1675                                            struct dw_hdmi, connector);
1676         enum drm_mode_status mode_status = MODE_OK;
1677
1678         /* We don't support double-clocked modes */
1679         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1680                 return MODE_BAD;
1681
1682         if (hdmi->plat_data->mode_valid)
1683                 mode_status = hdmi->plat_data->mode_valid(connector, mode);
1684
1685         return mode_status;
1686 }
1687
1688 static void dw_hdmi_connector_force(struct drm_connector *connector)
1689 {
1690         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1691                                              connector);
1692
1693         mutex_lock(&hdmi->mutex);
1694         hdmi->force = connector->force;
1695         dw_hdmi_update_power(hdmi);
1696         dw_hdmi_update_phy_mask(hdmi);
1697         mutex_unlock(&hdmi->mutex);
1698 }
1699
1700 static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
1701         .dpms = drm_atomic_helper_connector_dpms,
1702         .fill_modes = drm_helper_probe_single_connector_modes,
1703         .detect = dw_hdmi_connector_detect,
1704         .destroy = drm_connector_cleanup,
1705         .force = dw_hdmi_connector_force,
1706         .reset = drm_atomic_helper_connector_reset,
1707         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1708         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1709 };
1710
1711 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1712         .get_modes = dw_hdmi_connector_get_modes,
1713         .mode_valid = dw_hdmi_connector_mode_valid,
1714         .best_encoder = drm_atomic_helper_best_encoder,
1715 };
1716
1717 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
1718         .enable = dw_hdmi_bridge_enable,
1719         .disable = dw_hdmi_bridge_disable,
1720         .mode_set = dw_hdmi_bridge_mode_set,
1721 };
1722
1723 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
1724 {
1725         struct dw_hdmi_i2c *i2c = hdmi->i2c;
1726         unsigned int stat;
1727
1728         stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
1729         if (!stat)
1730                 return IRQ_NONE;
1731
1732         hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
1733
1734         i2c->stat = stat;
1735
1736         complete(&i2c->cmp);
1737
1738         return IRQ_HANDLED;
1739 }
1740
1741 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
1742 {
1743         struct dw_hdmi *hdmi = dev_id;
1744         u8 intr_stat;
1745         irqreturn_t ret = IRQ_NONE;
1746
1747         if (hdmi->i2c)
1748                 ret = dw_hdmi_i2c_irq(hdmi);
1749
1750         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1751         if (intr_stat) {
1752                 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1753                 return IRQ_WAKE_THREAD;
1754         }
1755
1756         return ret;
1757 }
1758
1759 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
1760 {
1761         struct dw_hdmi *hdmi = dev_id;
1762         u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
1763
1764         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1765         phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
1766         phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1767
1768         phy_pol_mask = 0;
1769         if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
1770                 phy_pol_mask |= HDMI_PHY_HPD;
1771         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
1772                 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
1773         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
1774                 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
1775         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
1776                 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
1777         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
1778                 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
1779
1780         if (phy_pol_mask)
1781                 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
1782
1783         /*
1784          * RX sense tells us whether the TDMS transmitters are detecting
1785          * load - in other words, there's something listening on the
1786          * other end of the link.  Use this to decide whether we should
1787          * power on the phy as HPD may be toggled by the sink to merely
1788          * ask the source to re-read the EDID.
1789          */
1790         if (intr_stat &
1791             (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
1792                 mutex_lock(&hdmi->mutex);
1793                 if (!hdmi->disabled && !hdmi->force) {
1794                         /*
1795                          * If the RX sense status indicates we're disconnected,
1796                          * clear the software rxsense status.
1797                          */
1798                         if (!(phy_stat & HDMI_PHY_RX_SENSE))
1799                                 hdmi->rxsense = false;
1800
1801                         /*
1802                          * Only set the software rxsense status when both
1803                          * rxsense and hpd indicates we're connected.
1804                          * This avoids what seems to be bad behaviour in
1805                          * at least iMX6S versions of the phy.
1806                          */
1807                         if (phy_stat & HDMI_PHY_HPD)
1808                                 hdmi->rxsense = true;
1809
1810                         dw_hdmi_update_power(hdmi);
1811                         dw_hdmi_update_phy_mask(hdmi);
1812                 }
1813                 mutex_unlock(&hdmi->mutex);
1814         }
1815
1816         if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
1817                 dev_dbg(hdmi->dev, "EVENT=%s\n",
1818                         phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout");
1819                 drm_helper_hpd_irq_event(hdmi->bridge->dev);
1820         }
1821
1822         hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
1823         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1824                     HDMI_IH_MUTE_PHY_STAT0);
1825
1826         return IRQ_HANDLED;
1827 }
1828
1829 static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi)
1830 {
1831         struct drm_encoder *encoder = hdmi->encoder;
1832         struct drm_bridge *bridge;
1833         int ret;
1834
1835         bridge = devm_kzalloc(drm->dev, sizeof(*bridge), GFP_KERNEL);
1836         if (!bridge) {
1837                 DRM_ERROR("Failed to allocate drm bridge\n");
1838                 return -ENOMEM;
1839         }
1840
1841         hdmi->bridge = bridge;
1842         bridge->driver_private = hdmi;
1843         bridge->funcs = &dw_hdmi_bridge_funcs;
1844         ret = drm_bridge_attach(drm, bridge);
1845         if (ret) {
1846                 DRM_ERROR("Failed to initialize bridge with drm\n");
1847                 return -EINVAL;
1848         }
1849
1850         encoder->bridge = bridge;
1851         hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
1852
1853         drm_connector_helper_add(&hdmi->connector,
1854                                  &dw_hdmi_connector_helper_funcs);
1855
1856         drm_connector_init(drm, &hdmi->connector,
1857                            &dw_hdmi_connector_funcs,
1858                            DRM_MODE_CONNECTOR_HDMIA);
1859
1860         drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
1861
1862         return 0;
1863 }
1864
1865 int dw_hdmi_bind(struct device *dev, struct device *master,
1866                  void *data, struct drm_encoder *encoder,
1867                  struct resource *iores, int irq,
1868                  const struct dw_hdmi_plat_data *plat_data)
1869 {
1870         struct drm_device *drm = data;
1871         struct device_node *np = dev->of_node;
1872         struct platform_device_info pdevinfo;
1873         struct device_node *ddc_node;
1874         struct dw_hdmi_audio_data audio;
1875         struct dw_hdmi *hdmi;
1876         int ret;
1877         u32 val = 1;
1878
1879         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1880         if (!hdmi)
1881                 return -ENOMEM;
1882
1883         hdmi->connector.interlace_allowed = 1;
1884
1885         hdmi->plat_data = plat_data;
1886         hdmi->dev = dev;
1887         hdmi->dev_type = plat_data->dev_type;
1888         hdmi->sample_rate = 48000;
1889         hdmi->encoder = encoder;
1890         hdmi->disabled = true;
1891         hdmi->rxsense = true;
1892         hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
1893
1894         mutex_init(&hdmi->mutex);
1895         mutex_init(&hdmi->audio_mutex);
1896         spin_lock_init(&hdmi->audio_lock);
1897
1898         of_property_read_u32(np, "reg-io-width", &val);
1899
1900         switch (val) {
1901         case 4:
1902                 hdmi->write = dw_hdmi_writel;
1903                 hdmi->read = dw_hdmi_readl;
1904                 break;
1905         case 1:
1906                 hdmi->write = dw_hdmi_writeb;
1907                 hdmi->read = dw_hdmi_readb;
1908                 break;
1909         default:
1910                 dev_err(dev, "reg-io-width must be 1 or 4\n");
1911                 return -EINVAL;
1912         }
1913
1914         ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
1915         if (ddc_node) {
1916                 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node);
1917                 of_node_put(ddc_node);
1918                 if (!hdmi->ddc) {
1919                         dev_dbg(hdmi->dev, "failed to read ddc node\n");
1920                         return -EPROBE_DEFER;
1921                 }
1922
1923         } else {
1924                 dev_dbg(hdmi->dev, "no ddc property found\n");
1925         }
1926
1927         hdmi->regs = devm_ioremap_resource(dev, iores);
1928         if (IS_ERR(hdmi->regs)) {
1929                 ret = PTR_ERR(hdmi->regs);
1930                 goto err_res;
1931         }
1932
1933         hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
1934         if (IS_ERR(hdmi->isfr_clk)) {
1935                 ret = PTR_ERR(hdmi->isfr_clk);
1936                 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
1937                 goto err_res;
1938         }
1939
1940         ret = clk_prepare_enable(hdmi->isfr_clk);
1941         if (ret) {
1942                 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
1943                 goto err_res;
1944         }
1945
1946         hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
1947         if (IS_ERR(hdmi->iahb_clk)) {
1948                 ret = PTR_ERR(hdmi->iahb_clk);
1949                 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
1950                 goto err_isfr;
1951         }
1952
1953         ret = clk_prepare_enable(hdmi->iahb_clk);
1954         if (ret) {
1955                 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
1956                 goto err_isfr;
1957         }
1958
1959         /* Product and revision IDs */
1960         dev_info(dev,
1961                  "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
1962                  hdmi_readb(hdmi, HDMI_DESIGN_ID),
1963                  hdmi_readb(hdmi, HDMI_REVISION_ID),
1964                  hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
1965                  hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
1966
1967         initialize_hdmi_ih_mutes(hdmi);
1968
1969         ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
1970                                         dw_hdmi_irq, IRQF_SHARED,
1971                                         dev_name(dev), hdmi);
1972         if (ret)
1973                 goto err_iahb;
1974
1975         /*
1976          * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
1977          * N and cts values before enabling phy
1978          */
1979         hdmi_init_clk_regenerator(hdmi);
1980
1981         /* If DDC bus is not specified, try to register HDMI I2C bus */
1982         if (!hdmi->ddc) {
1983                 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
1984                 if (IS_ERR(hdmi->ddc))
1985                         hdmi->ddc = NULL;
1986         }
1987
1988         /*
1989          * Configure registers related to HDMI interrupt
1990          * generation before registering IRQ.
1991          */
1992         hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
1993
1994         /* Clear Hotplug interrupts */
1995         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1996                     HDMI_IH_PHY_STAT0);
1997
1998         ret = dw_hdmi_fb_registered(hdmi);
1999         if (ret)
2000                 goto err_iahb;
2001
2002         ret = dw_hdmi_register(drm, hdmi);
2003         if (ret)
2004                 goto err_iahb;
2005
2006         /* Unmute interrupts */
2007         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2008                     HDMI_IH_MUTE_PHY_STAT0);
2009
2010         memset(&pdevinfo, 0, sizeof(pdevinfo));
2011         pdevinfo.parent = dev;
2012         pdevinfo.id = PLATFORM_DEVID_AUTO;
2013
2014         if (hdmi_readb(hdmi, HDMI_CONFIG1_ID) & HDMI_CONFIG1_AHB) {
2015                 audio.phys = iores->start;
2016                 audio.base = hdmi->regs;
2017                 audio.irq = irq;
2018                 audio.hdmi = hdmi;
2019                 audio.eld = hdmi->connector.eld;
2020
2021                 pdevinfo.name = "dw-hdmi-ahb-audio";
2022                 pdevinfo.data = &audio;
2023                 pdevinfo.size_data = sizeof(audio);
2024                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2025                 hdmi->audio = platform_device_register_full(&pdevinfo);
2026         }
2027
2028         /* Reset HDMI DDC I2C master controller and mute I2CM interrupts */
2029         if (hdmi->i2c)
2030                 dw_hdmi_i2c_init(hdmi);
2031
2032         dev_set_drvdata(dev, hdmi);
2033
2034         return 0;
2035
2036 err_iahb:
2037         if (hdmi->i2c) {
2038                 i2c_del_adapter(&hdmi->i2c->adap);
2039                 hdmi->ddc = NULL;
2040         }
2041
2042         clk_disable_unprepare(hdmi->iahb_clk);
2043 err_isfr:
2044         clk_disable_unprepare(hdmi->isfr_clk);
2045 err_res:
2046         i2c_put_adapter(hdmi->ddc);
2047
2048         return ret;
2049 }
2050 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
2051
2052 void dw_hdmi_unbind(struct device *dev, struct device *master, void *data)
2053 {
2054         struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2055
2056         if (hdmi->audio && !IS_ERR(hdmi->audio))
2057                 platform_device_unregister(hdmi->audio);
2058
2059         /* Disable all interrupts */
2060         hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2061
2062         clk_disable_unprepare(hdmi->iahb_clk);
2063         clk_disable_unprepare(hdmi->isfr_clk);
2064
2065         if (hdmi->i2c)
2066                 i2c_del_adapter(&hdmi->i2c->adap);
2067         else
2068                 i2c_put_adapter(hdmi->ddc);
2069 }
2070 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
2071
2072 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
2073 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
2074 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
2075 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
2076 MODULE_DESCRIPTION("DW HDMI transmitter driver");
2077 MODULE_LICENSE("GPL");
2078 MODULE_ALIAS("platform:dw-hdmi");