drm/i915: Update DRIVER_DATE to 20180906
[muen/linux.git] / drivers / gpu / drm / i915 / gvt / cmd_parser.c
1 /*
2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21  * SOFTWARE.
22  *
23  * Authors:
24  *    Ke Yu
25  *    Kevin Tian <kevin.tian@intel.com>
26  *    Zhiyuan Lv <zhiyuan.lv@intel.com>
27  *
28  * Contributors:
29  *    Min He <min.he@intel.com>
30  *    Ping Gao <ping.a.gao@intel.com>
31  *    Tina Zhang <tina.zhang@intel.com>
32  *    Yulei Zhang <yulei.zhang@intel.com>
33  *    Zhi Wang <zhi.a.wang@intel.com>
34  *
35  */
36
37 #include <linux/slab.h>
38 #include "i915_drv.h"
39 #include "gvt.h"
40 #include "i915_pvinfo.h"
41 #include "trace.h"
42
43 #define INVALID_OP    (~0U)
44
45 #define OP_LEN_MI           9
46 #define OP_LEN_2D           10
47 #define OP_LEN_3D_MEDIA     16
48 #define OP_LEN_MFX_VC       16
49 #define OP_LEN_VEBOX        16
50
51 #define CMD_TYPE(cmd)   (((cmd) >> 29) & 7)
52
53 struct sub_op_bits {
54         int hi;
55         int low;
56 };
57 struct decode_info {
58         char *name;
59         int op_len;
60         int nr_sub_op;
61         struct sub_op_bits *sub_op;
62 };
63
64 #define   MAX_CMD_BUDGET                        0x7fffffff
65 #define   MI_WAIT_FOR_PLANE_C_FLIP_PENDING      (1<<15)
66 #define   MI_WAIT_FOR_PLANE_B_FLIP_PENDING      (1<<9)
67 #define   MI_WAIT_FOR_PLANE_A_FLIP_PENDING      (1<<1)
68
69 #define   MI_WAIT_FOR_SPRITE_C_FLIP_PENDING      (1<<20)
70 #define   MI_WAIT_FOR_SPRITE_B_FLIP_PENDING      (1<<10)
71 #define   MI_WAIT_FOR_SPRITE_A_FLIP_PENDING      (1<<2)
72
73 /* Render Command Map */
74
75 /* MI_* command Opcode (28:23) */
76 #define OP_MI_NOOP                          0x0
77 #define OP_MI_SET_PREDICATE                 0x1  /* HSW+ */
78 #define OP_MI_USER_INTERRUPT                0x2
79 #define OP_MI_WAIT_FOR_EVENT                0x3
80 #define OP_MI_FLUSH                         0x4
81 #define OP_MI_ARB_CHECK                     0x5
82 #define OP_MI_RS_CONTROL                    0x6  /* HSW+ */
83 #define OP_MI_REPORT_HEAD                   0x7
84 #define OP_MI_ARB_ON_OFF                    0x8
85 #define OP_MI_URB_ATOMIC_ALLOC              0x9  /* HSW+ */
86 #define OP_MI_BATCH_BUFFER_END              0xA
87 #define OP_MI_SUSPEND_FLUSH                 0xB
88 #define OP_MI_PREDICATE                     0xC  /* IVB+ */
89 #define OP_MI_TOPOLOGY_FILTER               0xD  /* IVB+ */
90 #define OP_MI_SET_APPID                     0xE  /* IVB+ */
91 #define OP_MI_RS_CONTEXT                    0xF  /* HSW+ */
92 #define OP_MI_LOAD_SCAN_LINES_INCL          0x12 /* HSW+ */
93 #define OP_MI_DISPLAY_FLIP                  0x14
94 #define OP_MI_SEMAPHORE_MBOX                0x16
95 #define OP_MI_SET_CONTEXT                   0x18
96 #define OP_MI_MATH                          0x1A
97 #define OP_MI_URB_CLEAR                     0x19
98 #define OP_MI_SEMAPHORE_SIGNAL              0x1B  /* BDW+ */
99 #define OP_MI_SEMAPHORE_WAIT                0x1C  /* BDW+ */
100
101 #define OP_MI_STORE_DATA_IMM                0x20
102 #define OP_MI_STORE_DATA_INDEX              0x21
103 #define OP_MI_LOAD_REGISTER_IMM             0x22
104 #define OP_MI_UPDATE_GTT                    0x23
105 #define OP_MI_STORE_REGISTER_MEM            0x24
106 #define OP_MI_FLUSH_DW                      0x26
107 #define OP_MI_CLFLUSH                       0x27
108 #define OP_MI_REPORT_PERF_COUNT             0x28
109 #define OP_MI_LOAD_REGISTER_MEM             0x29  /* HSW+ */
110 #define OP_MI_LOAD_REGISTER_REG             0x2A  /* HSW+ */
111 #define OP_MI_RS_STORE_DATA_IMM             0x2B  /* HSW+ */
112 #define OP_MI_LOAD_URB_MEM                  0x2C  /* HSW+ */
113 #define OP_MI_STORE_URM_MEM                 0x2D  /* HSW+ */
114 #define OP_MI_2E                            0x2E  /* BDW+ */
115 #define OP_MI_2F                            0x2F  /* BDW+ */
116 #define OP_MI_BATCH_BUFFER_START            0x31
117
118 /* Bit definition for dword 0 */
119 #define _CMDBIT_BB_START_IN_PPGTT       (1UL << 8)
120
121 #define OP_MI_CONDITIONAL_BATCH_BUFFER_END  0x36
122
123 #define BATCH_BUFFER_ADDR_MASK ((1UL << 32) - (1U << 2))
124 #define BATCH_BUFFER_ADDR_HIGH_MASK ((1UL << 16) - (1U))
125 #define BATCH_BUFFER_ADR_SPACE_BIT(x)   (((x) >> 8) & 1U)
126 #define BATCH_BUFFER_2ND_LEVEL_BIT(x)   ((x) >> 22 & 1U)
127
128 /* 2D command: Opcode (28:22) */
129 #define OP_2D(x)    ((2<<7) | x)
130
131 #define OP_XY_SETUP_BLT                             OP_2D(0x1)
132 #define OP_XY_SETUP_CLIP_BLT                        OP_2D(0x3)
133 #define OP_XY_SETUP_MONO_PATTERN_SL_BLT             OP_2D(0x11)
134 #define OP_XY_PIXEL_BLT                             OP_2D(0x24)
135 #define OP_XY_SCANLINES_BLT                         OP_2D(0x25)
136 #define OP_XY_TEXT_BLT                              OP_2D(0x26)
137 #define OP_XY_TEXT_IMMEDIATE_BLT                    OP_2D(0x31)
138 #define OP_XY_COLOR_BLT                             OP_2D(0x50)
139 #define OP_XY_PAT_BLT                               OP_2D(0x51)
140 #define OP_XY_MONO_PAT_BLT                          OP_2D(0x52)
141 #define OP_XY_SRC_COPY_BLT                          OP_2D(0x53)
142 #define OP_XY_MONO_SRC_COPY_BLT                     OP_2D(0x54)
143 #define OP_XY_FULL_BLT                              OP_2D(0x55)
144 #define OP_XY_FULL_MONO_SRC_BLT                     OP_2D(0x56)
145 #define OP_XY_FULL_MONO_PATTERN_BLT                 OP_2D(0x57)
146 #define OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT        OP_2D(0x58)
147 #define OP_XY_MONO_PAT_FIXED_BLT                    OP_2D(0x59)
148 #define OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT           OP_2D(0x71)
149 #define OP_XY_PAT_BLT_IMMEDIATE                     OP_2D(0x72)
150 #define OP_XY_SRC_COPY_CHROMA_BLT                   OP_2D(0x73)
151 #define OP_XY_FULL_IMMEDIATE_PATTERN_BLT            OP_2D(0x74)
152 #define OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT   OP_2D(0x75)
153 #define OP_XY_PAT_CHROMA_BLT                        OP_2D(0x76)
154 #define OP_XY_PAT_CHROMA_BLT_IMMEDIATE              OP_2D(0x77)
155
156 /* 3D/Media Command: Pipeline Type(28:27) Opcode(26:24) Sub Opcode(23:16) */
157 #define OP_3D_MEDIA(sub_type, opcode, sub_opcode) \
158         ((3 << 13) | ((sub_type) << 11) | ((opcode) << 8) | (sub_opcode))
159
160 #define OP_STATE_PREFETCH                       OP_3D_MEDIA(0x0, 0x0, 0x03)
161
162 #define OP_STATE_BASE_ADDRESS                   OP_3D_MEDIA(0x0, 0x1, 0x01)
163 #define OP_STATE_SIP                            OP_3D_MEDIA(0x0, 0x1, 0x02)
164 #define OP_3D_MEDIA_0_1_4                       OP_3D_MEDIA(0x0, 0x1, 0x04)
165
166 #define OP_3DSTATE_VF_STATISTICS_GM45           OP_3D_MEDIA(0x1, 0x0, 0x0B)
167
168 #define OP_PIPELINE_SELECT                      OP_3D_MEDIA(0x1, 0x1, 0x04)
169
170 #define OP_MEDIA_VFE_STATE                      OP_3D_MEDIA(0x2, 0x0, 0x0)
171 #define OP_MEDIA_CURBE_LOAD                     OP_3D_MEDIA(0x2, 0x0, 0x1)
172 #define OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD      OP_3D_MEDIA(0x2, 0x0, 0x2)
173 #define OP_MEDIA_GATEWAY_STATE                  OP_3D_MEDIA(0x2, 0x0, 0x3)
174 #define OP_MEDIA_STATE_FLUSH                    OP_3D_MEDIA(0x2, 0x0, 0x4)
175 #define OP_MEDIA_POOL_STATE                     OP_3D_MEDIA(0x2, 0x0, 0x5)
176
177 #define OP_MEDIA_OBJECT                         OP_3D_MEDIA(0x2, 0x1, 0x0)
178 #define OP_MEDIA_OBJECT_PRT                     OP_3D_MEDIA(0x2, 0x1, 0x2)
179 #define OP_MEDIA_OBJECT_WALKER                  OP_3D_MEDIA(0x2, 0x1, 0x3)
180 #define OP_GPGPU_WALKER                         OP_3D_MEDIA(0x2, 0x1, 0x5)
181
182 #define OP_3DSTATE_CLEAR_PARAMS                 OP_3D_MEDIA(0x3, 0x0, 0x04) /* IVB+ */
183 #define OP_3DSTATE_DEPTH_BUFFER                 OP_3D_MEDIA(0x3, 0x0, 0x05) /* IVB+ */
184 #define OP_3DSTATE_STENCIL_BUFFER               OP_3D_MEDIA(0x3, 0x0, 0x06) /* IVB+ */
185 #define OP_3DSTATE_HIER_DEPTH_BUFFER            OP_3D_MEDIA(0x3, 0x0, 0x07) /* IVB+ */
186 #define OP_3DSTATE_VERTEX_BUFFERS               OP_3D_MEDIA(0x3, 0x0, 0x08)
187 #define OP_3DSTATE_VERTEX_ELEMENTS              OP_3D_MEDIA(0x3, 0x0, 0x09)
188 #define OP_3DSTATE_INDEX_BUFFER                 OP_3D_MEDIA(0x3, 0x0, 0x0A)
189 #define OP_3DSTATE_VF_STATISTICS                OP_3D_MEDIA(0x3, 0x0, 0x0B)
190 #define OP_3DSTATE_VF                           OP_3D_MEDIA(0x3, 0x0, 0x0C)  /* HSW+ */
191 #define OP_3DSTATE_CC_STATE_POINTERS            OP_3D_MEDIA(0x3, 0x0, 0x0E)
192 #define OP_3DSTATE_SCISSOR_STATE_POINTERS       OP_3D_MEDIA(0x3, 0x0, 0x0F)
193 #define OP_3DSTATE_VS                           OP_3D_MEDIA(0x3, 0x0, 0x10)
194 #define OP_3DSTATE_GS                           OP_3D_MEDIA(0x3, 0x0, 0x11)
195 #define OP_3DSTATE_CLIP                         OP_3D_MEDIA(0x3, 0x0, 0x12)
196 #define OP_3DSTATE_SF                           OP_3D_MEDIA(0x3, 0x0, 0x13)
197 #define OP_3DSTATE_WM                           OP_3D_MEDIA(0x3, 0x0, 0x14)
198 #define OP_3DSTATE_CONSTANT_VS                  OP_3D_MEDIA(0x3, 0x0, 0x15)
199 #define OP_3DSTATE_CONSTANT_GS                  OP_3D_MEDIA(0x3, 0x0, 0x16)
200 #define OP_3DSTATE_CONSTANT_PS                  OP_3D_MEDIA(0x3, 0x0, 0x17)
201 #define OP_3DSTATE_SAMPLE_MASK                  OP_3D_MEDIA(0x3, 0x0, 0x18)
202 #define OP_3DSTATE_CONSTANT_HS                  OP_3D_MEDIA(0x3, 0x0, 0x19) /* IVB+ */
203 #define OP_3DSTATE_CONSTANT_DS                  OP_3D_MEDIA(0x3, 0x0, 0x1A) /* IVB+ */
204 #define OP_3DSTATE_HS                           OP_3D_MEDIA(0x3, 0x0, 0x1B) /* IVB+ */
205 #define OP_3DSTATE_TE                           OP_3D_MEDIA(0x3, 0x0, 0x1C) /* IVB+ */
206 #define OP_3DSTATE_DS                           OP_3D_MEDIA(0x3, 0x0, 0x1D) /* IVB+ */
207 #define OP_3DSTATE_STREAMOUT                    OP_3D_MEDIA(0x3, 0x0, 0x1E) /* IVB+ */
208 #define OP_3DSTATE_SBE                          OP_3D_MEDIA(0x3, 0x0, 0x1F) /* IVB+ */
209 #define OP_3DSTATE_PS                           OP_3D_MEDIA(0x3, 0x0, 0x20) /* IVB+ */
210 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP OP_3D_MEDIA(0x3, 0x0, 0x21) /* IVB+ */
211 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC   OP_3D_MEDIA(0x3, 0x0, 0x23) /* IVB+ */
212 #define OP_3DSTATE_BLEND_STATE_POINTERS         OP_3D_MEDIA(0x3, 0x0, 0x24) /* IVB+ */
213 #define OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x25) /* IVB+ */
214 #define OP_3DSTATE_BINDING_TABLE_POINTERS_VS    OP_3D_MEDIA(0x3, 0x0, 0x26) /* IVB+ */
215 #define OP_3DSTATE_BINDING_TABLE_POINTERS_HS    OP_3D_MEDIA(0x3, 0x0, 0x27) /* IVB+ */
216 #define OP_3DSTATE_BINDING_TABLE_POINTERS_DS    OP_3D_MEDIA(0x3, 0x0, 0x28) /* IVB+ */
217 #define OP_3DSTATE_BINDING_TABLE_POINTERS_GS    OP_3D_MEDIA(0x3, 0x0, 0x29) /* IVB+ */
218 #define OP_3DSTATE_BINDING_TABLE_POINTERS_PS    OP_3D_MEDIA(0x3, 0x0, 0x2A) /* IVB+ */
219 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_VS    OP_3D_MEDIA(0x3, 0x0, 0x2B) /* IVB+ */
220 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_HS    OP_3D_MEDIA(0x3, 0x0, 0x2C) /* IVB+ */
221 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_DS    OP_3D_MEDIA(0x3, 0x0, 0x2D) /* IVB+ */
222 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_GS    OP_3D_MEDIA(0x3, 0x0, 0x2E) /* IVB+ */
223 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_PS    OP_3D_MEDIA(0x3, 0x0, 0x2F) /* IVB+ */
224 #define OP_3DSTATE_URB_VS                       OP_3D_MEDIA(0x3, 0x0, 0x30) /* IVB+ */
225 #define OP_3DSTATE_URB_HS                       OP_3D_MEDIA(0x3, 0x0, 0x31) /* IVB+ */
226 #define OP_3DSTATE_URB_DS                       OP_3D_MEDIA(0x3, 0x0, 0x32) /* IVB+ */
227 #define OP_3DSTATE_URB_GS                       OP_3D_MEDIA(0x3, 0x0, 0x33) /* IVB+ */
228 #define OP_3DSTATE_GATHER_CONSTANT_VS           OP_3D_MEDIA(0x3, 0x0, 0x34) /* HSW+ */
229 #define OP_3DSTATE_GATHER_CONSTANT_GS           OP_3D_MEDIA(0x3, 0x0, 0x35) /* HSW+ */
230 #define OP_3DSTATE_GATHER_CONSTANT_HS           OP_3D_MEDIA(0x3, 0x0, 0x36) /* HSW+ */
231 #define OP_3DSTATE_GATHER_CONSTANT_DS           OP_3D_MEDIA(0x3, 0x0, 0x37) /* HSW+ */
232 #define OP_3DSTATE_GATHER_CONSTANT_PS           OP_3D_MEDIA(0x3, 0x0, 0x38) /* HSW+ */
233 #define OP_3DSTATE_DX9_CONSTANTF_VS             OP_3D_MEDIA(0x3, 0x0, 0x39) /* HSW+ */
234 #define OP_3DSTATE_DX9_CONSTANTF_PS             OP_3D_MEDIA(0x3, 0x0, 0x3A) /* HSW+ */
235 #define OP_3DSTATE_DX9_CONSTANTI_VS             OP_3D_MEDIA(0x3, 0x0, 0x3B) /* HSW+ */
236 #define OP_3DSTATE_DX9_CONSTANTI_PS             OP_3D_MEDIA(0x3, 0x0, 0x3C) /* HSW+ */
237 #define OP_3DSTATE_DX9_CONSTANTB_VS             OP_3D_MEDIA(0x3, 0x0, 0x3D) /* HSW+ */
238 #define OP_3DSTATE_DX9_CONSTANTB_PS             OP_3D_MEDIA(0x3, 0x0, 0x3E) /* HSW+ */
239 #define OP_3DSTATE_DX9_LOCAL_VALID_VS           OP_3D_MEDIA(0x3, 0x0, 0x3F) /* HSW+ */
240 #define OP_3DSTATE_DX9_LOCAL_VALID_PS           OP_3D_MEDIA(0x3, 0x0, 0x40) /* HSW+ */
241 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_VS       OP_3D_MEDIA(0x3, 0x0, 0x41) /* HSW+ */
242 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_PS       OP_3D_MEDIA(0x3, 0x0, 0x42) /* HSW+ */
243 #define OP_3DSTATE_BINDING_TABLE_EDIT_VS        OP_3D_MEDIA(0x3, 0x0, 0x43) /* HSW+ */
244 #define OP_3DSTATE_BINDING_TABLE_EDIT_GS        OP_3D_MEDIA(0x3, 0x0, 0x44) /* HSW+ */
245 #define OP_3DSTATE_BINDING_TABLE_EDIT_HS        OP_3D_MEDIA(0x3, 0x0, 0x45) /* HSW+ */
246 #define OP_3DSTATE_BINDING_TABLE_EDIT_DS        OP_3D_MEDIA(0x3, 0x0, 0x46) /* HSW+ */
247 #define OP_3DSTATE_BINDING_TABLE_EDIT_PS        OP_3D_MEDIA(0x3, 0x0, 0x47) /* HSW+ */
248
249 #define OP_3DSTATE_VF_INSTANCING                OP_3D_MEDIA(0x3, 0x0, 0x49) /* BDW+ */
250 #define OP_3DSTATE_VF_SGVS                      OP_3D_MEDIA(0x3, 0x0, 0x4A) /* BDW+ */
251 #define OP_3DSTATE_VF_TOPOLOGY                  OP_3D_MEDIA(0x3, 0x0, 0x4B) /* BDW+ */
252 #define OP_3DSTATE_WM_CHROMAKEY                 OP_3D_MEDIA(0x3, 0x0, 0x4C) /* BDW+ */
253 #define OP_3DSTATE_PS_BLEND                     OP_3D_MEDIA(0x3, 0x0, 0x4D) /* BDW+ */
254 #define OP_3DSTATE_WM_DEPTH_STENCIL             OP_3D_MEDIA(0x3, 0x0, 0x4E) /* BDW+ */
255 #define OP_3DSTATE_PS_EXTRA                     OP_3D_MEDIA(0x3, 0x0, 0x4F) /* BDW+ */
256 #define OP_3DSTATE_RASTER                       OP_3D_MEDIA(0x3, 0x0, 0x50) /* BDW+ */
257 #define OP_3DSTATE_SBE_SWIZ                     OP_3D_MEDIA(0x3, 0x0, 0x51) /* BDW+ */
258 #define OP_3DSTATE_WM_HZ_OP                     OP_3D_MEDIA(0x3, 0x0, 0x52) /* BDW+ */
259 #define OP_3DSTATE_COMPONENT_PACKING            OP_3D_MEDIA(0x3, 0x0, 0x55) /* SKL+ */
260
261 #define OP_3DSTATE_DRAWING_RECTANGLE            OP_3D_MEDIA(0x3, 0x1, 0x00)
262 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD0        OP_3D_MEDIA(0x3, 0x1, 0x02)
263 #define OP_3DSTATE_CHROMA_KEY                   OP_3D_MEDIA(0x3, 0x1, 0x04)
264 #define OP_SNB_3DSTATE_DEPTH_BUFFER             OP_3D_MEDIA(0x3, 0x1, 0x05)
265 #define OP_3DSTATE_POLY_STIPPLE_OFFSET          OP_3D_MEDIA(0x3, 0x1, 0x06)
266 #define OP_3DSTATE_POLY_STIPPLE_PATTERN         OP_3D_MEDIA(0x3, 0x1, 0x07)
267 #define OP_3DSTATE_LINE_STIPPLE                 OP_3D_MEDIA(0x3, 0x1, 0x08)
268 #define OP_3DSTATE_AA_LINE_PARAMS               OP_3D_MEDIA(0x3, 0x1, 0x0A)
269 #define OP_3DSTATE_GS_SVB_INDEX                 OP_3D_MEDIA(0x3, 0x1, 0x0B)
270 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD1        OP_3D_MEDIA(0x3, 0x1, 0x0C)
271 #define OP_3DSTATE_MULTISAMPLE_BDW              OP_3D_MEDIA(0x3, 0x0, 0x0D)
272 #define OP_SNB_3DSTATE_STENCIL_BUFFER           OP_3D_MEDIA(0x3, 0x1, 0x0E)
273 #define OP_SNB_3DSTATE_HIER_DEPTH_BUFFER        OP_3D_MEDIA(0x3, 0x1, 0x0F)
274 #define OP_SNB_3DSTATE_CLEAR_PARAMS             OP_3D_MEDIA(0x3, 0x1, 0x10)
275 #define OP_3DSTATE_MONOFILTER_SIZE              OP_3D_MEDIA(0x3, 0x1, 0x11)
276 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS       OP_3D_MEDIA(0x3, 0x1, 0x12) /* IVB+ */
277 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS       OP_3D_MEDIA(0x3, 0x1, 0x13) /* IVB+ */
278 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS       OP_3D_MEDIA(0x3, 0x1, 0x14) /* IVB+ */
279 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS       OP_3D_MEDIA(0x3, 0x1, 0x15) /* IVB+ */
280 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS       OP_3D_MEDIA(0x3, 0x1, 0x16) /* IVB+ */
281 #define OP_3DSTATE_SO_DECL_LIST                 OP_3D_MEDIA(0x3, 0x1, 0x17)
282 #define OP_3DSTATE_SO_BUFFER                    OP_3D_MEDIA(0x3, 0x1, 0x18)
283 #define OP_3DSTATE_BINDING_TABLE_POOL_ALLOC     OP_3D_MEDIA(0x3, 0x1, 0x19) /* HSW+ */
284 #define OP_3DSTATE_GATHER_POOL_ALLOC            OP_3D_MEDIA(0x3, 0x1, 0x1A) /* HSW+ */
285 #define OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1B) /* HSW+ */
286 #define OP_3DSTATE_SAMPLE_PATTERN               OP_3D_MEDIA(0x3, 0x1, 0x1C)
287 #define OP_PIPE_CONTROL                         OP_3D_MEDIA(0x3, 0x2, 0x00)
288 #define OP_3DPRIMITIVE                          OP_3D_MEDIA(0x3, 0x3, 0x00)
289
290 /* VCCP Command Parser */
291
292 /*
293  * Below MFX and VBE cmd definition is from vaapi intel driver project (BSD License)
294  * git://anongit.freedesktop.org/vaapi/intel-driver
295  * src/i965_defines.h
296  *
297  */
298
299 #define OP_MFX(pipeline, op, sub_opa, sub_opb)     \
300         (3 << 13 | \
301          (pipeline) << 11 | \
302          (op) << 8 | \
303          (sub_opa) << 5 | \
304          (sub_opb))
305
306 #define OP_MFX_PIPE_MODE_SELECT                    OP_MFX(2, 0, 0, 0)  /* ALL */
307 #define OP_MFX_SURFACE_STATE                       OP_MFX(2, 0, 0, 1)  /* ALL */
308 #define OP_MFX_PIPE_BUF_ADDR_STATE                 OP_MFX(2, 0, 0, 2)  /* ALL */
309 #define OP_MFX_IND_OBJ_BASE_ADDR_STATE             OP_MFX(2, 0, 0, 3)  /* ALL */
310 #define OP_MFX_BSP_BUF_BASE_ADDR_STATE             OP_MFX(2, 0, 0, 4)  /* ALL */
311 #define OP_2_0_0_5                                 OP_MFX(2, 0, 0, 5)  /* ALL */
312 #define OP_MFX_STATE_POINTER                       OP_MFX(2, 0, 0, 6)  /* ALL */
313 #define OP_MFX_QM_STATE                            OP_MFX(2, 0, 0, 7)  /* IVB+ */
314 #define OP_MFX_FQM_STATE                           OP_MFX(2, 0, 0, 8)  /* IVB+ */
315 #define OP_MFX_PAK_INSERT_OBJECT                   OP_MFX(2, 0, 2, 8)  /* IVB+ */
316 #define OP_MFX_STITCH_OBJECT                       OP_MFX(2, 0, 2, 0xA)  /* IVB+ */
317
318 #define OP_MFD_IT_OBJECT                           OP_MFX(2, 0, 1, 9) /* ALL */
319
320 #define OP_MFX_WAIT                                OP_MFX(1, 0, 0, 0) /* IVB+ */
321 #define OP_MFX_AVC_IMG_STATE                       OP_MFX(2, 1, 0, 0) /* ALL */
322 #define OP_MFX_AVC_QM_STATE                        OP_MFX(2, 1, 0, 1) /* ALL */
323 #define OP_MFX_AVC_DIRECTMODE_STATE                OP_MFX(2, 1, 0, 2) /* ALL */
324 #define OP_MFX_AVC_SLICE_STATE                     OP_MFX(2, 1, 0, 3) /* ALL */
325 #define OP_MFX_AVC_REF_IDX_STATE                   OP_MFX(2, 1, 0, 4) /* ALL */
326 #define OP_MFX_AVC_WEIGHTOFFSET_STATE              OP_MFX(2, 1, 0, 5) /* ALL */
327 #define OP_MFD_AVC_PICID_STATE                     OP_MFX(2, 1, 1, 5) /* HSW+ */
328 #define OP_MFD_AVC_DPB_STATE                       OP_MFX(2, 1, 1, 6) /* IVB+ */
329 #define OP_MFD_AVC_SLICEADDR                       OP_MFX(2, 1, 1, 7) /* IVB+ */
330 #define OP_MFD_AVC_BSD_OBJECT                      OP_MFX(2, 1, 1, 8) /* ALL */
331 #define OP_MFC_AVC_PAK_OBJECT                      OP_MFX(2, 1, 2, 9) /* ALL */
332
333 #define OP_MFX_VC1_PRED_PIPE_STATE                 OP_MFX(2, 2, 0, 1) /* ALL */
334 #define OP_MFX_VC1_DIRECTMODE_STATE                OP_MFX(2, 2, 0, 2) /* ALL */
335 #define OP_MFD_VC1_SHORT_PIC_STATE                 OP_MFX(2, 2, 1, 0) /* IVB+ */
336 #define OP_MFD_VC1_LONG_PIC_STATE                  OP_MFX(2, 2, 1, 1) /* IVB+ */
337 #define OP_MFD_VC1_BSD_OBJECT                      OP_MFX(2, 2, 1, 8) /* ALL */
338
339 #define OP_MFX_MPEG2_PIC_STATE                     OP_MFX(2, 3, 0, 0) /* ALL */
340 #define OP_MFX_MPEG2_QM_STATE                      OP_MFX(2, 3, 0, 1) /* ALL */
341 #define OP_MFD_MPEG2_BSD_OBJECT                    OP_MFX(2, 3, 1, 8) /* ALL */
342 #define OP_MFC_MPEG2_SLICEGROUP_STATE              OP_MFX(2, 3, 2, 3) /* ALL */
343 #define OP_MFC_MPEG2_PAK_OBJECT                    OP_MFX(2, 3, 2, 9) /* ALL */
344
345 #define OP_MFX_2_6_0_0                             OP_MFX(2, 6, 0, 0) /* IVB+ */
346 #define OP_MFX_2_6_0_8                             OP_MFX(2, 6, 0, 8) /* IVB+ */
347 #define OP_MFX_2_6_0_9                             OP_MFX(2, 6, 0, 9) /* IVB+ */
348
349 #define OP_MFX_JPEG_PIC_STATE                      OP_MFX(2, 7, 0, 0)
350 #define OP_MFX_JPEG_HUFF_TABLE_STATE               OP_MFX(2, 7, 0, 2)
351 #define OP_MFD_JPEG_BSD_OBJECT                     OP_MFX(2, 7, 1, 8)
352
353 #define OP_VEB(pipeline, op, sub_opa, sub_opb) \
354         (3 << 13 | \
355          (pipeline) << 11 | \
356          (op) << 8 | \
357          (sub_opa) << 5 | \
358          (sub_opb))
359
360 #define OP_VEB_SURFACE_STATE                       OP_VEB(2, 4, 0, 0)
361 #define OP_VEB_STATE                               OP_VEB(2, 4, 0, 2)
362 #define OP_VEB_DNDI_IECP_STATE                     OP_VEB(2, 4, 0, 3)
363
364 struct parser_exec_state;
365
366 typedef int (*parser_cmd_handler)(struct parser_exec_state *s);
367
368 #define GVT_CMD_HASH_BITS   7
369
370 /* which DWords need address fix */
371 #define ADDR_FIX_1(x1)                  (1 << (x1))
372 #define ADDR_FIX_2(x1, x2)              (ADDR_FIX_1(x1) | ADDR_FIX_1(x2))
373 #define ADDR_FIX_3(x1, x2, x3)          (ADDR_FIX_1(x1) | ADDR_FIX_2(x2, x3))
374 #define ADDR_FIX_4(x1, x2, x3, x4)      (ADDR_FIX_1(x1) | ADDR_FIX_3(x2, x3, x4))
375 #define ADDR_FIX_5(x1, x2, x3, x4, x5)  (ADDR_FIX_1(x1) | ADDR_FIX_4(x2, x3, x4, x5))
376
377 struct cmd_info {
378         char *name;
379         u32 opcode;
380
381 #define F_LEN_MASK      (1U<<0)
382 #define F_LEN_CONST  1U
383 #define F_LEN_VAR    0U
384
385 /*
386  * command has its own ip advance logic
387  * e.g. MI_BATCH_START, MI_BATCH_END
388  */
389 #define F_IP_ADVANCE_CUSTOM (1<<1)
390
391 #define F_POST_HANDLE   (1<<2)
392         u32 flag;
393
394 #define R_RCS   (1 << RCS)
395 #define R_VCS1  (1 << VCS)
396 #define R_VCS2  (1 << VCS2)
397 #define R_VCS   (R_VCS1 | R_VCS2)
398 #define R_BCS   (1 << BCS)
399 #define R_VECS  (1 << VECS)
400 #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
401         /* rings that support this cmd: BLT/RCS/VCS/VECS */
402         uint16_t rings;
403
404         /* devices that support this cmd: SNB/IVB/HSW/... */
405         uint16_t devices;
406
407         /* which DWords are address that need fix up.
408          * bit 0 means a 32-bit non address operand in command
409          * bit 1 means address operand, which could be 32-bit
410          * or 64-bit depending on different architectures.(
411          * defined by "gmadr_bytes_in_cmd" in intel_gvt.
412          * No matter the address length, each address only takes
413          * one bit in the bitmap.
414          */
415         uint16_t addr_bitmap;
416
417         /* flag == F_LEN_CONST : command length
418          * flag == F_LEN_VAR : length bias bits
419          * Note: length is in DWord
420          */
421         uint8_t len;
422
423         parser_cmd_handler handler;
424 };
425
426 struct cmd_entry {
427         struct hlist_node hlist;
428         struct cmd_info *info;
429 };
430
431 enum {
432         RING_BUFFER_INSTRUCTION,
433         BATCH_BUFFER_INSTRUCTION,
434         BATCH_BUFFER_2ND_LEVEL,
435 };
436
437 enum {
438         GTT_BUFFER,
439         PPGTT_BUFFER
440 };
441
442 struct parser_exec_state {
443         struct intel_vgpu *vgpu;
444         int ring_id;
445
446         int buf_type;
447
448         /* batch buffer address type */
449         int buf_addr_type;
450
451         /* graphics memory address of ring buffer start */
452         unsigned long ring_start;
453         unsigned long ring_size;
454         unsigned long ring_head;
455         unsigned long ring_tail;
456
457         /* instruction graphics memory address */
458         unsigned long ip_gma;
459
460         /* mapped va of the instr_gma */
461         void *ip_va;
462         void *rb_va;
463
464         void *ret_bb_va;
465         /* next instruction when return from  batch buffer to ring buffer */
466         unsigned long ret_ip_gma_ring;
467
468         /* next instruction when return from 2nd batch buffer to batch buffer */
469         unsigned long ret_ip_gma_bb;
470
471         /* batch buffer address type (GTT or PPGTT)
472          * used when ret from 2nd level batch buffer
473          */
474         int saved_buf_addr_type;
475         bool is_ctx_wa;
476
477         struct cmd_info *info;
478
479         struct intel_vgpu_workload *workload;
480 };
481
482 #define gmadr_dw_number(s)      \
483         (s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2)
484
485 static unsigned long bypass_scan_mask = 0;
486
487 /* ring ALL, type = 0 */
488 static struct sub_op_bits sub_op_mi[] = {
489         {31, 29},
490         {28, 23},
491 };
492
493 static struct decode_info decode_info_mi = {
494         "MI",
495         OP_LEN_MI,
496         ARRAY_SIZE(sub_op_mi),
497         sub_op_mi,
498 };
499
500 /* ring RCS, command type 2 */
501 static struct sub_op_bits sub_op_2d[] = {
502         {31, 29},
503         {28, 22},
504 };
505
506 static struct decode_info decode_info_2d = {
507         "2D",
508         OP_LEN_2D,
509         ARRAY_SIZE(sub_op_2d),
510         sub_op_2d,
511 };
512
513 /* ring RCS, command type 3 */
514 static struct sub_op_bits sub_op_3d_media[] = {
515         {31, 29},
516         {28, 27},
517         {26, 24},
518         {23, 16},
519 };
520
521 static struct decode_info decode_info_3d_media = {
522         "3D_Media",
523         OP_LEN_3D_MEDIA,
524         ARRAY_SIZE(sub_op_3d_media),
525         sub_op_3d_media,
526 };
527
528 /* ring VCS, command type 3 */
529 static struct sub_op_bits sub_op_mfx_vc[] = {
530         {31, 29},
531         {28, 27},
532         {26, 24},
533         {23, 21},
534         {20, 16},
535 };
536
537 static struct decode_info decode_info_mfx_vc = {
538         "MFX_VC",
539         OP_LEN_MFX_VC,
540         ARRAY_SIZE(sub_op_mfx_vc),
541         sub_op_mfx_vc,
542 };
543
544 /* ring VECS, command type 3 */
545 static struct sub_op_bits sub_op_vebox[] = {
546         {31, 29},
547         {28, 27},
548         {26, 24},
549         {23, 21},
550         {20, 16},
551 };
552
553 static struct decode_info decode_info_vebox = {
554         "VEBOX",
555         OP_LEN_VEBOX,
556         ARRAY_SIZE(sub_op_vebox),
557         sub_op_vebox,
558 };
559
560 static struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
561         [RCS] = {
562                 &decode_info_mi,
563                 NULL,
564                 NULL,
565                 &decode_info_3d_media,
566                 NULL,
567                 NULL,
568                 NULL,
569                 NULL,
570         },
571
572         [VCS] = {
573                 &decode_info_mi,
574                 NULL,
575                 NULL,
576                 &decode_info_mfx_vc,
577                 NULL,
578                 NULL,
579                 NULL,
580                 NULL,
581         },
582
583         [BCS] = {
584                 &decode_info_mi,
585                 NULL,
586                 &decode_info_2d,
587                 NULL,
588                 NULL,
589                 NULL,
590                 NULL,
591                 NULL,
592         },
593
594         [VECS] = {
595                 &decode_info_mi,
596                 NULL,
597                 NULL,
598                 &decode_info_vebox,
599                 NULL,
600                 NULL,
601                 NULL,
602                 NULL,
603         },
604
605         [VCS2] = {
606                 &decode_info_mi,
607                 NULL,
608                 NULL,
609                 &decode_info_mfx_vc,
610                 NULL,
611                 NULL,
612                 NULL,
613                 NULL,
614         },
615 };
616
617 static inline u32 get_opcode(u32 cmd, int ring_id)
618 {
619         struct decode_info *d_info;
620
621         d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)];
622         if (d_info == NULL)
623                 return INVALID_OP;
624
625         return cmd >> (32 - d_info->op_len);
626 }
627
628 static inline struct cmd_info *find_cmd_entry(struct intel_gvt *gvt,
629                 unsigned int opcode, int ring_id)
630 {
631         struct cmd_entry *e;
632
633         hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) {
634                 if ((opcode == e->info->opcode) &&
635                                 (e->info->rings & (1 << ring_id)))
636                         return e->info;
637         }
638         return NULL;
639 }
640
641 static inline struct cmd_info *get_cmd_info(struct intel_gvt *gvt,
642                 u32 cmd, int ring_id)
643 {
644         u32 opcode;
645
646         opcode = get_opcode(cmd, ring_id);
647         if (opcode == INVALID_OP)
648                 return NULL;
649
650         return find_cmd_entry(gvt, opcode, ring_id);
651 }
652
653 static inline u32 sub_op_val(u32 cmd, u32 hi, u32 low)
654 {
655         return (cmd >> low) & ((1U << (hi - low + 1)) - 1);
656 }
657
658 static inline void print_opcode(u32 cmd, int ring_id)
659 {
660         struct decode_info *d_info;
661         int i;
662
663         d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)];
664         if (d_info == NULL)
665                 return;
666
667         gvt_dbg_cmd("opcode=0x%x %s sub_ops:",
668                         cmd >> (32 - d_info->op_len), d_info->name);
669
670         for (i = 0; i < d_info->nr_sub_op; i++)
671                 pr_err("0x%x ", sub_op_val(cmd, d_info->sub_op[i].hi,
672                                         d_info->sub_op[i].low));
673
674         pr_err("\n");
675 }
676
677 static inline u32 *cmd_ptr(struct parser_exec_state *s, int index)
678 {
679         return s->ip_va + (index << 2);
680 }
681
682 static inline u32 cmd_val(struct parser_exec_state *s, int index)
683 {
684         return *cmd_ptr(s, index);
685 }
686
687 static void parser_exec_state_dump(struct parser_exec_state *s)
688 {
689         int cnt = 0;
690         int i;
691
692         gvt_dbg_cmd("  vgpu%d RING%d: ring_start(%08lx) ring_end(%08lx)"
693                         " ring_head(%08lx) ring_tail(%08lx)\n", s->vgpu->id,
694                         s->ring_id, s->ring_start, s->ring_start + s->ring_size,
695                         s->ring_head, s->ring_tail);
696
697         gvt_dbg_cmd("  %s %s ip_gma(%08lx) ",
698                         s->buf_type == RING_BUFFER_INSTRUCTION ?
699                         "RING_BUFFER" : "BATCH_BUFFER",
700                         s->buf_addr_type == GTT_BUFFER ?
701                         "GTT" : "PPGTT", s->ip_gma);
702
703         if (s->ip_va == NULL) {
704                 gvt_dbg_cmd(" ip_va(NULL)");
705                 return;
706         }
707
708         gvt_dbg_cmd("  ip_va=%p: %08x %08x %08x %08x\n",
709                         s->ip_va, cmd_val(s, 0), cmd_val(s, 1),
710                         cmd_val(s, 2), cmd_val(s, 3));
711
712         print_opcode(cmd_val(s, 0), s->ring_id);
713
714         s->ip_va = (u32 *)((((u64)s->ip_va) >> 12) << 12);
715
716         while (cnt < 1024) {
717                 gvt_dbg_cmd("ip_va=%p: ", s->ip_va);
718                 for (i = 0; i < 8; i++)
719                         gvt_dbg_cmd("%08x ", cmd_val(s, i));
720                 gvt_dbg_cmd("\n");
721
722                 s->ip_va += 8 * sizeof(u32);
723                 cnt += 8;
724         }
725 }
726
727 static inline void update_ip_va(struct parser_exec_state *s)
728 {
729         unsigned long len = 0;
730
731         if (WARN_ON(s->ring_head == s->ring_tail))
732                 return;
733
734         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
735                 unsigned long ring_top = s->ring_start + s->ring_size;
736
737                 if (s->ring_head > s->ring_tail) {
738                         if (s->ip_gma >= s->ring_head && s->ip_gma < ring_top)
739                                 len = (s->ip_gma - s->ring_head);
740                         else if (s->ip_gma >= s->ring_start &&
741                                         s->ip_gma <= s->ring_tail)
742                                 len = (ring_top - s->ring_head) +
743                                         (s->ip_gma - s->ring_start);
744                 } else
745                         len = (s->ip_gma - s->ring_head);
746
747                 s->ip_va = s->rb_va + len;
748         } else {/* shadow batch buffer */
749                 s->ip_va = s->ret_bb_va;
750         }
751 }
752
753 static inline int ip_gma_set(struct parser_exec_state *s,
754                 unsigned long ip_gma)
755 {
756         WARN_ON(!IS_ALIGNED(ip_gma, 4));
757
758         s->ip_gma = ip_gma;
759         update_ip_va(s);
760         return 0;
761 }
762
763 static inline int ip_gma_advance(struct parser_exec_state *s,
764                 unsigned int dw_len)
765 {
766         s->ip_gma += (dw_len << 2);
767
768         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
769                 if (s->ip_gma >= s->ring_start + s->ring_size)
770                         s->ip_gma -= s->ring_size;
771                 update_ip_va(s);
772         } else {
773                 s->ip_va += (dw_len << 2);
774         }
775
776         return 0;
777 }
778
779 static inline int get_cmd_length(struct cmd_info *info, u32 cmd)
780 {
781         if ((info->flag & F_LEN_MASK) == F_LEN_CONST)
782                 return info->len;
783         else
784                 return (cmd & ((1U << info->len) - 1)) + 2;
785         return 0;
786 }
787
788 static inline int cmd_length(struct parser_exec_state *s)
789 {
790         return get_cmd_length(s->info, cmd_val(s, 0));
791 }
792
793 /* do not remove this, some platform may need clflush here */
794 #define patch_value(s, addr, val) do { \
795         *addr = val; \
796 } while (0)
797
798 static bool is_shadowed_mmio(unsigned int offset)
799 {
800         bool ret = false;
801
802         if ((offset == 0x2168) || /*BB current head register UDW */
803             (offset == 0x2140) || /*BB current header register */
804             (offset == 0x211c) || /*second BB header register UDW */
805             (offset == 0x2114)) { /*second BB header register UDW */
806                 ret = true;
807         }
808         return ret;
809 }
810
811 static inline bool is_force_nonpriv_mmio(unsigned int offset)
812 {
813         return (offset >= 0x24d0 && offset < 0x2500);
814 }
815
816 static int force_nonpriv_reg_handler(struct parser_exec_state *s,
817                 unsigned int offset, unsigned int index, char *cmd)
818 {
819         struct intel_gvt *gvt = s->vgpu->gvt;
820         unsigned int data;
821         u32 ring_base;
822         u32 nopid;
823         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
824
825         if (!strcmp(cmd, "lri"))
826                 data = cmd_val(s, index + 1);
827         else {
828                 gvt_err("Unexpected forcenonpriv 0x%x write from cmd %s\n",
829                         offset, cmd);
830                 return -EINVAL;
831         }
832
833         ring_base = dev_priv->engine[s->ring_id]->mmio_base;
834         nopid = i915_mmio_reg_offset(RING_NOPID(ring_base));
835
836         if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data) &&
837                         data != nopid) {
838                 gvt_err("Unexpected forcenonpriv 0x%x LRI write, value=0x%x\n",
839                         offset, data);
840                 patch_value(s, cmd_ptr(s, index), nopid);
841                 return 0;
842         }
843         return 0;
844 }
845
846 static inline bool is_mocs_mmio(unsigned int offset)
847 {
848         return ((offset >= 0xc800) && (offset <= 0xcff8)) ||
849                 ((offset >= 0xb020) && (offset <= 0xb0a0));
850 }
851
852 static int mocs_cmd_reg_handler(struct parser_exec_state *s,
853                                 unsigned int offset, unsigned int index)
854 {
855         if (!is_mocs_mmio(offset))
856                 return -EINVAL;
857         vgpu_vreg(s->vgpu, offset) = cmd_val(s, index + 1);
858         return 0;
859 }
860
861 static int cmd_reg_handler(struct parser_exec_state *s,
862         unsigned int offset, unsigned int index, char *cmd)
863 {
864         struct intel_vgpu *vgpu = s->vgpu;
865         struct intel_gvt *gvt = vgpu->gvt;
866
867         if (offset + 4 > gvt->device_info.mmio_size) {
868                 gvt_vgpu_err("%s access to (%x) outside of MMIO range\n",
869                                 cmd, offset);
870                 return -EFAULT;
871         }
872
873         if (!intel_gvt_mmio_is_cmd_access(gvt, offset)) {
874                 gvt_vgpu_err("%s access to non-render register (%x)\n",
875                                 cmd, offset);
876                 return 0;
877         }
878
879         if (is_shadowed_mmio(offset)) {
880                 gvt_vgpu_err("found access of shadowed MMIO %x\n", offset);
881                 return 0;
882         }
883
884         if (is_mocs_mmio(offset) &&
885             mocs_cmd_reg_handler(s, offset, index))
886                 return -EINVAL;
887
888         if (is_force_nonpriv_mmio(offset) &&
889                 force_nonpriv_reg_handler(s, offset, index, cmd))
890                 return -EPERM;
891
892         if (offset == i915_mmio_reg_offset(DERRMR) ||
893                 offset == i915_mmio_reg_offset(FORCEWAKE_MT)) {
894                 /* Writing to HW VGT_PVINFO_PAGE offset will be discarded */
895                 patch_value(s, cmd_ptr(s, index), VGT_PVINFO_PAGE);
896         }
897
898         /* TODO: Update the global mask if this MMIO is a masked-MMIO */
899         intel_gvt_mmio_set_cmd_accessed(gvt, offset);
900         return 0;
901 }
902
903 #define cmd_reg(s, i) \
904         (cmd_val(s, i) & GENMASK(22, 2))
905
906 #define cmd_reg_inhibit(s, i) \
907         (cmd_val(s, i) & GENMASK(22, 18))
908
909 #define cmd_gma(s, i) \
910         (cmd_val(s, i) & GENMASK(31, 2))
911
912 #define cmd_gma_hi(s, i) \
913         (cmd_val(s, i) & GENMASK(15, 0))
914
915 static int cmd_handler_lri(struct parser_exec_state *s)
916 {
917         int i, ret = 0;
918         int cmd_len = cmd_length(s);
919         struct intel_gvt *gvt = s->vgpu->gvt;
920
921         for (i = 1; i < cmd_len; i += 2) {
922                 if (IS_BROADWELL(gvt->dev_priv) &&
923                                 (s->ring_id != RCS)) {
924                         if (s->ring_id == BCS &&
925                                         cmd_reg(s, i) ==
926                                         i915_mmio_reg_offset(DERRMR))
927                                 ret |= 0;
928                         else
929                                 ret |= (cmd_reg_inhibit(s, i)) ?
930                                         -EBADRQC : 0;
931                 }
932                 if (ret)
933                         break;
934                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lri");
935                 if (ret)
936                         break;
937         }
938         return ret;
939 }
940
941 static int cmd_handler_lrr(struct parser_exec_state *s)
942 {
943         int i, ret = 0;
944         int cmd_len = cmd_length(s);
945
946         for (i = 1; i < cmd_len; i += 2) {
947                 if (IS_BROADWELL(s->vgpu->gvt->dev_priv))
948                         ret |= ((cmd_reg_inhibit(s, i) ||
949                                         (cmd_reg_inhibit(s, i + 1)))) ?
950                                 -EBADRQC : 0;
951                 if (ret)
952                         break;
953                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrr-src");
954                 if (ret)
955                         break;
956                 ret |= cmd_reg_handler(s, cmd_reg(s, i + 1), i, "lrr-dst");
957                 if (ret)
958                         break;
959         }
960         return ret;
961 }
962
963 static inline int cmd_address_audit(struct parser_exec_state *s,
964                 unsigned long guest_gma, int op_size, bool index_mode);
965
966 static int cmd_handler_lrm(struct parser_exec_state *s)
967 {
968         struct intel_gvt *gvt = s->vgpu->gvt;
969         int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
970         unsigned long gma;
971         int i, ret = 0;
972         int cmd_len = cmd_length(s);
973
974         for (i = 1; i < cmd_len;) {
975                 if (IS_BROADWELL(gvt->dev_priv))
976                         ret |= (cmd_reg_inhibit(s, i)) ? -EBADRQC : 0;
977                 if (ret)
978                         break;
979                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrm");
980                 if (ret)
981                         break;
982                 if (cmd_val(s, 0) & (1 << 22)) {
983                         gma = cmd_gma(s, i + 1);
984                         if (gmadr_bytes == 8)
985                                 gma |= (cmd_gma_hi(s, i + 2)) << 32;
986                         ret |= cmd_address_audit(s, gma, sizeof(u32), false);
987                         if (ret)
988                                 break;
989                 }
990                 i += gmadr_dw_number(s) + 1;
991         }
992         return ret;
993 }
994
995 static int cmd_handler_srm(struct parser_exec_state *s)
996 {
997         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
998         unsigned long gma;
999         int i, ret = 0;
1000         int cmd_len = cmd_length(s);
1001
1002         for (i = 1; i < cmd_len;) {
1003                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "srm");
1004                 if (ret)
1005                         break;
1006                 if (cmd_val(s, 0) & (1 << 22)) {
1007                         gma = cmd_gma(s, i + 1);
1008                         if (gmadr_bytes == 8)
1009                                 gma |= (cmd_gma_hi(s, i + 2)) << 32;
1010                         ret |= cmd_address_audit(s, gma, sizeof(u32), false);
1011                         if (ret)
1012                                 break;
1013                 }
1014                 i += gmadr_dw_number(s) + 1;
1015         }
1016         return ret;
1017 }
1018
1019 struct cmd_interrupt_event {
1020         int pipe_control_notify;
1021         int mi_flush_dw;
1022         int mi_user_interrupt;
1023 };
1024
1025 static struct cmd_interrupt_event cmd_interrupt_events[] = {
1026         [RCS] = {
1027                 .pipe_control_notify = RCS_PIPE_CONTROL,
1028                 .mi_flush_dw = INTEL_GVT_EVENT_RESERVED,
1029                 .mi_user_interrupt = RCS_MI_USER_INTERRUPT,
1030         },
1031         [BCS] = {
1032                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1033                 .mi_flush_dw = BCS_MI_FLUSH_DW,
1034                 .mi_user_interrupt = BCS_MI_USER_INTERRUPT,
1035         },
1036         [VCS] = {
1037                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1038                 .mi_flush_dw = VCS_MI_FLUSH_DW,
1039                 .mi_user_interrupt = VCS_MI_USER_INTERRUPT,
1040         },
1041         [VCS2] = {
1042                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1043                 .mi_flush_dw = VCS2_MI_FLUSH_DW,
1044                 .mi_user_interrupt = VCS2_MI_USER_INTERRUPT,
1045         },
1046         [VECS] = {
1047                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1048                 .mi_flush_dw = VECS_MI_FLUSH_DW,
1049                 .mi_user_interrupt = VECS_MI_USER_INTERRUPT,
1050         },
1051 };
1052
1053 static int cmd_handler_pipe_control(struct parser_exec_state *s)
1054 {
1055         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1056         unsigned long gma;
1057         bool index_mode = false;
1058         unsigned int post_sync;
1059         int ret = 0;
1060
1061         post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14;
1062
1063         /* LRI post sync */
1064         if (cmd_val(s, 1) & PIPE_CONTROL_MMIO_WRITE)
1065                 ret = cmd_reg_handler(s, cmd_reg(s, 2), 1, "pipe_ctrl");
1066         /* post sync */
1067         else if (post_sync) {
1068                 if (post_sync == 2)
1069                         ret = cmd_reg_handler(s, 0x2350, 1, "pipe_ctrl");
1070                 else if (post_sync == 3)
1071                         ret = cmd_reg_handler(s, 0x2358, 1, "pipe_ctrl");
1072                 else if (post_sync == 1) {
1073                         /* check ggtt*/
1074                         if ((cmd_val(s, 1) & PIPE_CONTROL_GLOBAL_GTT_IVB)) {
1075                                 gma = cmd_val(s, 2) & GENMASK(31, 3);
1076                                 if (gmadr_bytes == 8)
1077                                         gma |= (cmd_gma_hi(s, 3)) << 32;
1078                                 /* Store Data Index */
1079                                 if (cmd_val(s, 1) & (1 << 21))
1080                                         index_mode = true;
1081                                 ret |= cmd_address_audit(s, gma, sizeof(u64),
1082                                                 index_mode);
1083                         }
1084                 }
1085         }
1086
1087         if (ret)
1088                 return ret;
1089
1090         if (cmd_val(s, 1) & PIPE_CONTROL_NOTIFY)
1091                 set_bit(cmd_interrupt_events[s->ring_id].pipe_control_notify,
1092                                 s->workload->pending_events);
1093         return 0;
1094 }
1095
1096 static int cmd_handler_mi_user_interrupt(struct parser_exec_state *s)
1097 {
1098         set_bit(cmd_interrupt_events[s->ring_id].mi_user_interrupt,
1099                         s->workload->pending_events);
1100         patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1101         return 0;
1102 }
1103
1104 static int cmd_advance_default(struct parser_exec_state *s)
1105 {
1106         return ip_gma_advance(s, cmd_length(s));
1107 }
1108
1109 static int cmd_handler_mi_batch_buffer_end(struct parser_exec_state *s)
1110 {
1111         int ret;
1112
1113         if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1114                 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1115                 ret = ip_gma_set(s, s->ret_ip_gma_bb);
1116                 s->buf_addr_type = s->saved_buf_addr_type;
1117         } else {
1118                 s->buf_type = RING_BUFFER_INSTRUCTION;
1119                 s->buf_addr_type = GTT_BUFFER;
1120                 if (s->ret_ip_gma_ring >= s->ring_start + s->ring_size)
1121                         s->ret_ip_gma_ring -= s->ring_size;
1122                 ret = ip_gma_set(s, s->ret_ip_gma_ring);
1123         }
1124         return ret;
1125 }
1126
1127 struct mi_display_flip_command_info {
1128         int pipe;
1129         int plane;
1130         int event;
1131         i915_reg_t stride_reg;
1132         i915_reg_t ctrl_reg;
1133         i915_reg_t surf_reg;
1134         u64 stride_val;
1135         u64 tile_val;
1136         u64 surf_val;
1137         bool async_flip;
1138 };
1139
1140 struct plane_code_mapping {
1141         int pipe;
1142         int plane;
1143         int event;
1144 };
1145
1146 static int gen8_decode_mi_display_flip(struct parser_exec_state *s,
1147                 struct mi_display_flip_command_info *info)
1148 {
1149         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1150         struct plane_code_mapping gen8_plane_code[] = {
1151                 [0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE},
1152                 [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE},
1153                 [2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE},
1154                 [3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE},
1155                 [4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE},
1156                 [5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE},
1157         };
1158         u32 dword0, dword1, dword2;
1159         u32 v;
1160
1161         dword0 = cmd_val(s, 0);
1162         dword1 = cmd_val(s, 1);
1163         dword2 = cmd_val(s, 2);
1164
1165         v = (dword0 & GENMASK(21, 19)) >> 19;
1166         if (WARN_ON(v >= ARRAY_SIZE(gen8_plane_code)))
1167                 return -EBADRQC;
1168
1169         info->pipe = gen8_plane_code[v].pipe;
1170         info->plane = gen8_plane_code[v].plane;
1171         info->event = gen8_plane_code[v].event;
1172         info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1173         info->tile_val = (dword1 & 0x1);
1174         info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1175         info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1176
1177         if (info->plane == PLANE_A) {
1178                 info->ctrl_reg = DSPCNTR(info->pipe);
1179                 info->stride_reg = DSPSTRIDE(info->pipe);
1180                 info->surf_reg = DSPSURF(info->pipe);
1181         } else if (info->plane == PLANE_B) {
1182                 info->ctrl_reg = SPRCTL(info->pipe);
1183                 info->stride_reg = SPRSTRIDE(info->pipe);
1184                 info->surf_reg = SPRSURF(info->pipe);
1185         } else {
1186                 WARN_ON(1);
1187                 return -EBADRQC;
1188         }
1189         return 0;
1190 }
1191
1192 static int skl_decode_mi_display_flip(struct parser_exec_state *s,
1193                 struct mi_display_flip_command_info *info)
1194 {
1195         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1196         struct intel_vgpu *vgpu = s->vgpu;
1197         u32 dword0 = cmd_val(s, 0);
1198         u32 dword1 = cmd_val(s, 1);
1199         u32 dword2 = cmd_val(s, 2);
1200         u32 plane = (dword0 & GENMASK(12, 8)) >> 8;
1201
1202         info->plane = PRIMARY_PLANE;
1203
1204         switch (plane) {
1205         case MI_DISPLAY_FLIP_SKL_PLANE_1_A:
1206                 info->pipe = PIPE_A;
1207                 info->event = PRIMARY_A_FLIP_DONE;
1208                 break;
1209         case MI_DISPLAY_FLIP_SKL_PLANE_1_B:
1210                 info->pipe = PIPE_B;
1211                 info->event = PRIMARY_B_FLIP_DONE;
1212                 break;
1213         case MI_DISPLAY_FLIP_SKL_PLANE_1_C:
1214                 info->pipe = PIPE_C;
1215                 info->event = PRIMARY_C_FLIP_DONE;
1216                 break;
1217
1218         case MI_DISPLAY_FLIP_SKL_PLANE_2_A:
1219                 info->pipe = PIPE_A;
1220                 info->event = SPRITE_A_FLIP_DONE;
1221                 info->plane = SPRITE_PLANE;
1222                 break;
1223         case MI_DISPLAY_FLIP_SKL_PLANE_2_B:
1224                 info->pipe = PIPE_B;
1225                 info->event = SPRITE_B_FLIP_DONE;
1226                 info->plane = SPRITE_PLANE;
1227                 break;
1228         case MI_DISPLAY_FLIP_SKL_PLANE_2_C:
1229                 info->pipe = PIPE_C;
1230                 info->event = SPRITE_C_FLIP_DONE;
1231                 info->plane = SPRITE_PLANE;
1232                 break;
1233
1234         default:
1235                 gvt_vgpu_err("unknown plane code %d\n", plane);
1236                 return -EBADRQC;
1237         }
1238
1239         info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1240         info->tile_val = (dword1 & GENMASK(2, 0));
1241         info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1242         info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1243
1244         info->ctrl_reg = DSPCNTR(info->pipe);
1245         info->stride_reg = DSPSTRIDE(info->pipe);
1246         info->surf_reg = DSPSURF(info->pipe);
1247
1248         return 0;
1249 }
1250
1251 static int gen8_check_mi_display_flip(struct parser_exec_state *s,
1252                 struct mi_display_flip_command_info *info)
1253 {
1254         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1255         u32 stride, tile;
1256
1257         if (!info->async_flip)
1258                 return 0;
1259
1260         if (IS_SKYLAKE(dev_priv)
1261                 || IS_KABYLAKE(dev_priv)
1262                 || IS_BROXTON(dev_priv)) {
1263                 stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);
1264                 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &
1265                                 GENMASK(12, 10)) >> 10;
1266         } else {
1267                 stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) &
1268                                 GENMASK(15, 6)) >> 6;
1269                 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;
1270         }
1271
1272         if (stride != info->stride_val)
1273                 gvt_dbg_cmd("cannot change stride during async flip\n");
1274
1275         if (tile != info->tile_val)
1276                 gvt_dbg_cmd("cannot change tile during async flip\n");
1277
1278         return 0;
1279 }
1280
1281 static int gen8_update_plane_mmio_from_mi_display_flip(
1282                 struct parser_exec_state *s,
1283                 struct mi_display_flip_command_info *info)
1284 {
1285         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1286         struct intel_vgpu *vgpu = s->vgpu;
1287
1288         set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),
1289                       info->surf_val << 12);
1290         if (IS_SKYLAKE(dev_priv)
1291                 || IS_KABYLAKE(dev_priv)
1292                 || IS_BROXTON(dev_priv)) {
1293                 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),
1294                               info->stride_val);
1295                 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),
1296                               info->tile_val << 10);
1297         } else {
1298                 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6),
1299                               info->stride_val << 6);
1300                 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),
1301                               info->tile_val << 10);
1302         }
1303
1304         vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(info->pipe))++;
1305         intel_vgpu_trigger_virtual_event(vgpu, info->event);
1306         return 0;
1307 }
1308
1309 static int decode_mi_display_flip(struct parser_exec_state *s,
1310                 struct mi_display_flip_command_info *info)
1311 {
1312         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1313
1314         if (IS_BROADWELL(dev_priv))
1315                 return gen8_decode_mi_display_flip(s, info);
1316         if (IS_SKYLAKE(dev_priv)
1317                 || IS_KABYLAKE(dev_priv)
1318                 || IS_BROXTON(dev_priv))
1319                 return skl_decode_mi_display_flip(s, info);
1320
1321         return -ENODEV;
1322 }
1323
1324 static int check_mi_display_flip(struct parser_exec_state *s,
1325                 struct mi_display_flip_command_info *info)
1326 {
1327         return gen8_check_mi_display_flip(s, info);
1328 }
1329
1330 static int update_plane_mmio_from_mi_display_flip(
1331                 struct parser_exec_state *s,
1332                 struct mi_display_flip_command_info *info)
1333 {
1334         return gen8_update_plane_mmio_from_mi_display_flip(s, info);
1335 }
1336
1337 static int cmd_handler_mi_display_flip(struct parser_exec_state *s)
1338 {
1339         struct mi_display_flip_command_info info;
1340         struct intel_vgpu *vgpu = s->vgpu;
1341         int ret;
1342         int i;
1343         int len = cmd_length(s);
1344
1345         ret = decode_mi_display_flip(s, &info);
1346         if (ret) {
1347                 gvt_vgpu_err("fail to decode MI display flip command\n");
1348                 return ret;
1349         }
1350
1351         ret = check_mi_display_flip(s, &info);
1352         if (ret) {
1353                 gvt_vgpu_err("invalid MI display flip command\n");
1354                 return ret;
1355         }
1356
1357         ret = update_plane_mmio_from_mi_display_flip(s, &info);
1358         if (ret) {
1359                 gvt_vgpu_err("fail to update plane mmio\n");
1360                 return ret;
1361         }
1362
1363         for (i = 0; i < len; i++)
1364                 patch_value(s, cmd_ptr(s, i), MI_NOOP);
1365         return 0;
1366 }
1367
1368 static bool is_wait_for_flip_pending(u32 cmd)
1369 {
1370         return cmd & (MI_WAIT_FOR_PLANE_A_FLIP_PENDING |
1371                         MI_WAIT_FOR_PLANE_B_FLIP_PENDING |
1372                         MI_WAIT_FOR_PLANE_C_FLIP_PENDING |
1373                         MI_WAIT_FOR_SPRITE_A_FLIP_PENDING |
1374                         MI_WAIT_FOR_SPRITE_B_FLIP_PENDING |
1375                         MI_WAIT_FOR_SPRITE_C_FLIP_PENDING);
1376 }
1377
1378 static int cmd_handler_mi_wait_for_event(struct parser_exec_state *s)
1379 {
1380         u32 cmd = cmd_val(s, 0);
1381
1382         if (!is_wait_for_flip_pending(cmd))
1383                 return 0;
1384
1385         patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1386         return 0;
1387 }
1388
1389 static unsigned long get_gma_bb_from_cmd(struct parser_exec_state *s, int index)
1390 {
1391         unsigned long addr;
1392         unsigned long gma_high, gma_low;
1393         struct intel_vgpu *vgpu = s->vgpu;
1394         int gmadr_bytes = vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1395
1396         if (WARN_ON(gmadr_bytes != 4 && gmadr_bytes != 8)) {
1397                 gvt_vgpu_err("invalid gma bytes %d\n", gmadr_bytes);
1398                 return INTEL_GVT_INVALID_ADDR;
1399         }
1400
1401         gma_low = cmd_val(s, index) & BATCH_BUFFER_ADDR_MASK;
1402         if (gmadr_bytes == 4) {
1403                 addr = gma_low;
1404         } else {
1405                 gma_high = cmd_val(s, index + 1) & BATCH_BUFFER_ADDR_HIGH_MASK;
1406                 addr = (((unsigned long)gma_high) << 32) | gma_low;
1407         }
1408         return addr;
1409 }
1410
1411 static inline int cmd_address_audit(struct parser_exec_state *s,
1412                 unsigned long guest_gma, int op_size, bool index_mode)
1413 {
1414         struct intel_vgpu *vgpu = s->vgpu;
1415         u32 max_surface_size = vgpu->gvt->device_info.max_surface_size;
1416         int i;
1417         int ret;
1418
1419         if (op_size > max_surface_size) {
1420                 gvt_vgpu_err("command address audit fail name %s\n",
1421                         s->info->name);
1422                 return -EFAULT;
1423         }
1424
1425         if (index_mode) {
1426                 if (guest_gma >= I915_GTT_PAGE_SIZE / sizeof(u64)) {
1427                         ret = -EFAULT;
1428                         goto err;
1429                 }
1430         } else if (!intel_gvt_ggtt_validate_range(vgpu, guest_gma, op_size)) {
1431                 ret = -EFAULT;
1432                 goto err;
1433         }
1434
1435         return 0;
1436
1437 err:
1438         gvt_vgpu_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n",
1439                         s->info->name, guest_gma, op_size);
1440
1441         pr_err("cmd dump: ");
1442         for (i = 0; i < cmd_length(s); i++) {
1443                 if (!(i % 4))
1444                         pr_err("\n%08x ", cmd_val(s, i));
1445                 else
1446                         pr_err("%08x ", cmd_val(s, i));
1447         }
1448         pr_err("\nvgpu%d: aperture 0x%llx - 0x%llx, hidden 0x%llx - 0x%llx\n",
1449                         vgpu->id,
1450                         vgpu_aperture_gmadr_base(vgpu),
1451                         vgpu_aperture_gmadr_end(vgpu),
1452                         vgpu_hidden_gmadr_base(vgpu),
1453                         vgpu_hidden_gmadr_end(vgpu));
1454         return ret;
1455 }
1456
1457 static int cmd_handler_mi_store_data_imm(struct parser_exec_state *s)
1458 {
1459         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1460         int op_size = (cmd_length(s) - 3) * sizeof(u32);
1461         int core_id = (cmd_val(s, 2) & (1 << 0)) ? 1 : 0;
1462         unsigned long gma, gma_low, gma_high;
1463         int ret = 0;
1464
1465         /* check ppggt */
1466         if (!(cmd_val(s, 0) & (1 << 22)))
1467                 return 0;
1468
1469         gma = cmd_val(s, 2) & GENMASK(31, 2);
1470
1471         if (gmadr_bytes == 8) {
1472                 gma_low = cmd_val(s, 1) & GENMASK(31, 2);
1473                 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1474                 gma = (gma_high << 32) | gma_low;
1475                 core_id = (cmd_val(s, 1) & (1 << 0)) ? 1 : 0;
1476         }
1477         ret = cmd_address_audit(s, gma + op_size * core_id, op_size, false);
1478         return ret;
1479 }
1480
1481 static inline int unexpected_cmd(struct parser_exec_state *s)
1482 {
1483         struct intel_vgpu *vgpu = s->vgpu;
1484
1485         gvt_vgpu_err("Unexpected %s in command buffer!\n", s->info->name);
1486
1487         return -EBADRQC;
1488 }
1489
1490 static int cmd_handler_mi_semaphore_wait(struct parser_exec_state *s)
1491 {
1492         return unexpected_cmd(s);
1493 }
1494
1495 static int cmd_handler_mi_report_perf_count(struct parser_exec_state *s)
1496 {
1497         return unexpected_cmd(s);
1498 }
1499
1500 static int cmd_handler_mi_op_2e(struct parser_exec_state *s)
1501 {
1502         return unexpected_cmd(s);
1503 }
1504
1505 static int cmd_handler_mi_op_2f(struct parser_exec_state *s)
1506 {
1507         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1508         int op_size = (1 << ((cmd_val(s, 0) & GENMASK(20, 19)) >> 19)) *
1509                         sizeof(u32);
1510         unsigned long gma, gma_high;
1511         int ret = 0;
1512
1513         if (!(cmd_val(s, 0) & (1 << 22)))
1514                 return ret;
1515
1516         gma = cmd_val(s, 1) & GENMASK(31, 2);
1517         if (gmadr_bytes == 8) {
1518                 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1519                 gma = (gma_high << 32) | gma;
1520         }
1521         ret = cmd_address_audit(s, gma, op_size, false);
1522         return ret;
1523 }
1524
1525 static int cmd_handler_mi_store_data_index(struct parser_exec_state *s)
1526 {
1527         return unexpected_cmd(s);
1528 }
1529
1530 static int cmd_handler_mi_clflush(struct parser_exec_state *s)
1531 {
1532         return unexpected_cmd(s);
1533 }
1534
1535 static int cmd_handler_mi_conditional_batch_buffer_end(
1536                 struct parser_exec_state *s)
1537 {
1538         return unexpected_cmd(s);
1539 }
1540
1541 static int cmd_handler_mi_update_gtt(struct parser_exec_state *s)
1542 {
1543         return unexpected_cmd(s);
1544 }
1545
1546 static int cmd_handler_mi_flush_dw(struct parser_exec_state *s)
1547 {
1548         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1549         unsigned long gma;
1550         bool index_mode = false;
1551         int ret = 0;
1552
1553         /* Check post-sync and ppgtt bit */
1554         if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) {
1555                 gma = cmd_val(s, 1) & GENMASK(31, 3);
1556                 if (gmadr_bytes == 8)
1557                         gma |= (cmd_val(s, 2) & GENMASK(15, 0)) << 32;
1558                 /* Store Data Index */
1559                 if (cmd_val(s, 0) & (1 << 21))
1560                         index_mode = true;
1561                 ret = cmd_address_audit(s, gma, sizeof(u64), index_mode);
1562         }
1563         /* Check notify bit */
1564         if ((cmd_val(s, 0) & (1 << 8)))
1565                 set_bit(cmd_interrupt_events[s->ring_id].mi_flush_dw,
1566                                 s->workload->pending_events);
1567         return ret;
1568 }
1569
1570 static void addr_type_update_snb(struct parser_exec_state *s)
1571 {
1572         if ((s->buf_type == RING_BUFFER_INSTRUCTION) &&
1573                         (BATCH_BUFFER_ADR_SPACE_BIT(cmd_val(s, 0)) == 1)) {
1574                 s->buf_addr_type = PPGTT_BUFFER;
1575         }
1576 }
1577
1578
1579 static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm,
1580                 unsigned long gma, unsigned long end_gma, void *va)
1581 {
1582         unsigned long copy_len, offset;
1583         unsigned long len = 0;
1584         unsigned long gpa;
1585
1586         while (gma != end_gma) {
1587                 gpa = intel_vgpu_gma_to_gpa(mm, gma);
1588                 if (gpa == INTEL_GVT_INVALID_ADDR) {
1589                         gvt_vgpu_err("invalid gma address: %lx\n", gma);
1590                         return -EFAULT;
1591                 }
1592
1593                 offset = gma & (I915_GTT_PAGE_SIZE - 1);
1594
1595                 copy_len = (end_gma - gma) >= (I915_GTT_PAGE_SIZE - offset) ?
1596                         I915_GTT_PAGE_SIZE - offset : end_gma - gma;
1597
1598                 intel_gvt_hypervisor_read_gpa(vgpu, gpa, va + len, copy_len);
1599
1600                 len += copy_len;
1601                 gma += copy_len;
1602         }
1603         return len;
1604 }
1605
1606
1607 /*
1608  * Check whether a batch buffer needs to be scanned. Currently
1609  * the only criteria is based on privilege.
1610  */
1611 static int batch_buffer_needs_scan(struct parser_exec_state *s)
1612 {
1613         /* Decide privilege based on address space */
1614         if (cmd_val(s, 0) & (1 << 8) &&
1615                         !(s->vgpu->scan_nonprivbb & (1 << s->ring_id)))
1616                 return 0;
1617         return 1;
1618 }
1619
1620 static int find_bb_size(struct parser_exec_state *s, unsigned long *bb_size)
1621 {
1622         unsigned long gma = 0;
1623         struct cmd_info *info;
1624         uint32_t cmd_len = 0;
1625         bool bb_end = false;
1626         struct intel_vgpu *vgpu = s->vgpu;
1627         u32 cmd;
1628         struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1629                 s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1630
1631         *bb_size = 0;
1632
1633         /* get the start gm address of the batch buffer */
1634         gma = get_gma_bb_from_cmd(s, 1);
1635         if (gma == INTEL_GVT_INVALID_ADDR)
1636                 return -EFAULT;
1637
1638         cmd = cmd_val(s, 0);
1639         info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
1640         if (info == NULL) {
1641                 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",
1642                                 cmd, get_opcode(cmd, s->ring_id),
1643                                 (s->buf_addr_type == PPGTT_BUFFER) ?
1644                                 "ppgtt" : "ggtt", s->ring_id, s->workload);
1645                 return -EBADRQC;
1646         }
1647         do {
1648                 if (copy_gma_to_hva(s->vgpu, mm,
1649                                 gma, gma + 4, &cmd) < 0)
1650                         return -EFAULT;
1651                 info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
1652                 if (info == NULL) {
1653                         gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",
1654                                 cmd, get_opcode(cmd, s->ring_id),
1655                                 (s->buf_addr_type == PPGTT_BUFFER) ?
1656                                 "ppgtt" : "ggtt", s->ring_id, s->workload);
1657                         return -EBADRQC;
1658                 }
1659
1660                 if (info->opcode == OP_MI_BATCH_BUFFER_END) {
1661                         bb_end = true;
1662                 } else if (info->opcode == OP_MI_BATCH_BUFFER_START) {
1663                         if (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0)
1664                                 /* chained batch buffer */
1665                                 bb_end = true;
1666                 }
1667                 cmd_len = get_cmd_length(info, cmd) << 2;
1668                 *bb_size += cmd_len;
1669                 gma += cmd_len;
1670         } while (!bb_end);
1671
1672         return 0;
1673 }
1674
1675 static int perform_bb_shadow(struct parser_exec_state *s)
1676 {
1677         struct intel_vgpu *vgpu = s->vgpu;
1678         struct intel_vgpu_shadow_bb *bb;
1679         unsigned long gma = 0;
1680         unsigned long bb_size;
1681         int ret = 0;
1682         struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1683                 s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1684         unsigned long gma_start_offset = 0;
1685
1686         /* get the start gm address of the batch buffer */
1687         gma = get_gma_bb_from_cmd(s, 1);
1688         if (gma == INTEL_GVT_INVALID_ADDR)
1689                 return -EFAULT;
1690
1691         ret = find_bb_size(s, &bb_size);
1692         if (ret)
1693                 return ret;
1694
1695         bb = kzalloc(sizeof(*bb), GFP_KERNEL);
1696         if (!bb)
1697                 return -ENOMEM;
1698
1699         bb->ppgtt = (s->buf_addr_type == GTT_BUFFER) ? false : true;
1700
1701         /* the gma_start_offset stores the batch buffer's start gma's
1702          * offset relative to page boundary. so for non-privileged batch
1703          * buffer, the shadowed gem object holds exactly the same page
1704          * layout as original gem object. This is for the convience of
1705          * replacing the whole non-privilged batch buffer page to this
1706          * shadowed one in PPGTT at the same gma address. (this replacing
1707          * action is not implemented yet now, but may be necessary in
1708          * future).
1709          * for prileged batch buffer, we just change start gma address to
1710          * that of shadowed page.
1711          */
1712         if (bb->ppgtt)
1713                 gma_start_offset = gma & ~I915_GTT_PAGE_MASK;
1714
1715         bb->obj = i915_gem_object_create(s->vgpu->gvt->dev_priv,
1716                          roundup(bb_size + gma_start_offset, PAGE_SIZE));
1717         if (IS_ERR(bb->obj)) {
1718                 ret = PTR_ERR(bb->obj);
1719                 goto err_free_bb;
1720         }
1721
1722         ret = i915_gem_obj_prepare_shmem_write(bb->obj, &bb->clflush);
1723         if (ret)
1724                 goto err_free_obj;
1725
1726         bb->va = i915_gem_object_pin_map(bb->obj, I915_MAP_WB);
1727         if (IS_ERR(bb->va)) {
1728                 ret = PTR_ERR(bb->va);
1729                 goto err_finish_shmem_access;
1730         }
1731
1732         if (bb->clflush & CLFLUSH_BEFORE) {
1733                 drm_clflush_virt_range(bb->va, bb->obj->base.size);
1734                 bb->clflush &= ~CLFLUSH_BEFORE;
1735         }
1736
1737         ret = copy_gma_to_hva(s->vgpu, mm,
1738                               gma, gma + bb_size,
1739                               bb->va + gma_start_offset);
1740         if (ret < 0) {
1741                 gvt_vgpu_err("fail to copy guest ring buffer\n");
1742                 ret = -EFAULT;
1743                 goto err_unmap;
1744         }
1745
1746         INIT_LIST_HEAD(&bb->list);
1747         list_add(&bb->list, &s->workload->shadow_bb);
1748
1749         bb->accessing = true;
1750         bb->bb_start_cmd_va = s->ip_va;
1751
1752         if ((s->buf_type == BATCH_BUFFER_INSTRUCTION) && (!s->is_ctx_wa))
1753                 bb->bb_offset = s->ip_va - s->rb_va;
1754         else
1755                 bb->bb_offset = 0;
1756
1757         /*
1758          * ip_va saves the virtual address of the shadow batch buffer, while
1759          * ip_gma saves the graphics address of the original batch buffer.
1760          * As the shadow batch buffer is just a copy from the originial one,
1761          * it should be right to use shadow batch buffer'va and original batch
1762          * buffer's gma in pair. After all, we don't want to pin the shadow
1763          * buffer here (too early).
1764          */
1765         s->ip_va = bb->va + gma_start_offset;
1766         s->ip_gma = gma;
1767         return 0;
1768 err_unmap:
1769         i915_gem_object_unpin_map(bb->obj);
1770 err_finish_shmem_access:
1771         i915_gem_obj_finish_shmem_access(bb->obj);
1772 err_free_obj:
1773         i915_gem_object_put(bb->obj);
1774 err_free_bb:
1775         kfree(bb);
1776         return ret;
1777 }
1778
1779 static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s)
1780 {
1781         bool second_level;
1782         int ret = 0;
1783         struct intel_vgpu *vgpu = s->vgpu;
1784
1785         if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1786                 gvt_vgpu_err("Found MI_BATCH_BUFFER_START in 2nd level BB\n");
1787                 return -EFAULT;
1788         }
1789
1790         second_level = BATCH_BUFFER_2ND_LEVEL_BIT(cmd_val(s, 0)) == 1;
1791         if (second_level && (s->buf_type != BATCH_BUFFER_INSTRUCTION)) {
1792                 gvt_vgpu_err("Jumping to 2nd level BB from RB is not allowed\n");
1793                 return -EFAULT;
1794         }
1795
1796         s->saved_buf_addr_type = s->buf_addr_type;
1797         addr_type_update_snb(s);
1798         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
1799                 s->ret_ip_gma_ring = s->ip_gma + cmd_length(s) * sizeof(u32);
1800                 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1801         } else if (second_level) {
1802                 s->buf_type = BATCH_BUFFER_2ND_LEVEL;
1803                 s->ret_ip_gma_bb = s->ip_gma + cmd_length(s) * sizeof(u32);
1804                 s->ret_bb_va = s->ip_va + cmd_length(s) * sizeof(u32);
1805         }
1806
1807         if (batch_buffer_needs_scan(s)) {
1808                 ret = perform_bb_shadow(s);
1809                 if (ret < 0)
1810                         gvt_vgpu_err("invalid shadow batch buffer\n");
1811         } else {
1812                 /* emulate a batch buffer end to do return right */
1813                 ret = cmd_handler_mi_batch_buffer_end(s);
1814                 if (ret < 0)
1815                         return ret;
1816         }
1817         return ret;
1818 }
1819
1820 static struct cmd_info cmd_info[] = {
1821         {"MI_NOOP", OP_MI_NOOP, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
1822
1823         {"MI_SET_PREDICATE", OP_MI_SET_PREDICATE, F_LEN_CONST, R_ALL, D_ALL,
1824                 0, 1, NULL},
1825
1826         {"MI_USER_INTERRUPT", OP_MI_USER_INTERRUPT, F_LEN_CONST, R_ALL, D_ALL,
1827                 0, 1, cmd_handler_mi_user_interrupt},
1828
1829         {"MI_WAIT_FOR_EVENT", OP_MI_WAIT_FOR_EVENT, F_LEN_CONST, R_RCS | R_BCS,
1830                 D_ALL, 0, 1, cmd_handler_mi_wait_for_event},
1831
1832         {"MI_FLUSH", OP_MI_FLUSH, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
1833
1834         {"MI_ARB_CHECK", OP_MI_ARB_CHECK, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1835                 NULL},
1836
1837         {"MI_RS_CONTROL", OP_MI_RS_CONTROL, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1838                 NULL},
1839
1840         {"MI_REPORT_HEAD", OP_MI_REPORT_HEAD, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1841                 NULL},
1842
1843         {"MI_ARB_ON_OFF", OP_MI_ARB_ON_OFF, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1844                 NULL},
1845
1846         {"MI_URB_ATOMIC_ALLOC", OP_MI_URB_ATOMIC_ALLOC, F_LEN_CONST, R_RCS,
1847                 D_ALL, 0, 1, NULL},
1848
1849         {"MI_BATCH_BUFFER_END", OP_MI_BATCH_BUFFER_END,
1850                 F_IP_ADVANCE_CUSTOM | F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1851                 cmd_handler_mi_batch_buffer_end},
1852
1853         {"MI_SUSPEND_FLUSH", OP_MI_SUSPEND_FLUSH, F_LEN_CONST, R_ALL, D_ALL,
1854                 0, 1, NULL},
1855
1856         {"MI_PREDICATE", OP_MI_PREDICATE, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1857                 NULL},
1858
1859         {"MI_TOPOLOGY_FILTER", OP_MI_TOPOLOGY_FILTER, F_LEN_CONST, R_ALL,
1860                 D_ALL, 0, 1, NULL},
1861
1862         {"MI_SET_APPID", OP_MI_SET_APPID, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1863                 NULL},
1864
1865         {"MI_RS_CONTEXT", OP_MI_RS_CONTEXT, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1866                 NULL},
1867
1868         {"MI_DISPLAY_FLIP", OP_MI_DISPLAY_FLIP, F_LEN_VAR | F_POST_HANDLE,
1869                 R_RCS | R_BCS, D_ALL, 0, 8, cmd_handler_mi_display_flip},
1870
1871         {"MI_SEMAPHORE_MBOX", OP_MI_SEMAPHORE_MBOX, F_LEN_VAR, R_ALL, D_ALL,
1872                 0, 8, NULL},
1873
1874         {"MI_MATH", OP_MI_MATH, F_LEN_VAR, R_ALL, D_ALL, 0, 8, NULL},
1875
1876         {"MI_URB_CLEAR", OP_MI_URB_CLEAR, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1877
1878         {"ME_SEMAPHORE_SIGNAL", OP_MI_SEMAPHORE_SIGNAL, F_LEN_VAR, R_ALL,
1879                 D_BDW_PLUS, 0, 8, NULL},
1880
1881         {"ME_SEMAPHORE_WAIT", OP_MI_SEMAPHORE_WAIT, F_LEN_VAR, R_ALL, D_BDW_PLUS,
1882                 ADDR_FIX_1(2), 8, cmd_handler_mi_semaphore_wait},
1883
1884         {"MI_STORE_DATA_IMM", OP_MI_STORE_DATA_IMM, F_LEN_VAR, R_ALL, D_BDW_PLUS,
1885                 ADDR_FIX_1(1), 10, cmd_handler_mi_store_data_imm},
1886
1887         {"MI_STORE_DATA_INDEX", OP_MI_STORE_DATA_INDEX, F_LEN_VAR, R_ALL, D_ALL,
1888                 0, 8, cmd_handler_mi_store_data_index},
1889
1890         {"MI_LOAD_REGISTER_IMM", OP_MI_LOAD_REGISTER_IMM, F_LEN_VAR, R_ALL,
1891                 D_ALL, 0, 8, cmd_handler_lri},
1892
1893         {"MI_UPDATE_GTT", OP_MI_UPDATE_GTT, F_LEN_VAR, R_ALL, D_BDW_PLUS, 0, 10,
1894                 cmd_handler_mi_update_gtt},
1895
1896         {"MI_STORE_REGISTER_MEM", OP_MI_STORE_REGISTER_MEM, F_LEN_VAR, R_ALL,
1897                 D_ALL, ADDR_FIX_1(2), 8, cmd_handler_srm},
1898
1899         {"MI_FLUSH_DW", OP_MI_FLUSH_DW, F_LEN_VAR, R_ALL, D_ALL, 0, 6,
1900                 cmd_handler_mi_flush_dw},
1901
1902         {"MI_CLFLUSH", OP_MI_CLFLUSH, F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(1),
1903                 10, cmd_handler_mi_clflush},
1904
1905         {"MI_REPORT_PERF_COUNT", OP_MI_REPORT_PERF_COUNT, F_LEN_VAR, R_ALL,
1906                 D_ALL, ADDR_FIX_1(1), 6, cmd_handler_mi_report_perf_count},
1907
1908         {"MI_LOAD_REGISTER_MEM", OP_MI_LOAD_REGISTER_MEM, F_LEN_VAR, R_ALL,
1909                 D_ALL, ADDR_FIX_1(2), 8, cmd_handler_lrm},
1910
1911         {"MI_LOAD_REGISTER_REG", OP_MI_LOAD_REGISTER_REG, F_LEN_VAR, R_ALL,
1912                 D_ALL, 0, 8, cmd_handler_lrr},
1913
1914         {"MI_RS_STORE_DATA_IMM", OP_MI_RS_STORE_DATA_IMM, F_LEN_VAR, R_RCS,
1915                 D_ALL, 0, 8, NULL},
1916
1917         {"MI_LOAD_URB_MEM", OP_MI_LOAD_URB_MEM, F_LEN_VAR, R_RCS, D_ALL,
1918                 ADDR_FIX_1(2), 8, NULL},
1919
1920         {"MI_STORE_URM_MEM", OP_MI_STORE_URM_MEM, F_LEN_VAR, R_RCS, D_ALL,
1921                 ADDR_FIX_1(2), 8, NULL},
1922
1923         {"MI_OP_2E", OP_MI_2E, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_2(1, 2),
1924                 8, cmd_handler_mi_op_2e},
1925
1926         {"MI_OP_2F", OP_MI_2F, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_1(1),
1927                 8, cmd_handler_mi_op_2f},
1928
1929         {"MI_BATCH_BUFFER_START", OP_MI_BATCH_BUFFER_START,
1930                 F_IP_ADVANCE_CUSTOM, R_ALL, D_ALL, 0, 8,
1931                 cmd_handler_mi_batch_buffer_start},
1932
1933         {"MI_CONDITIONAL_BATCH_BUFFER_END", OP_MI_CONDITIONAL_BATCH_BUFFER_END,
1934                 F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
1935                 cmd_handler_mi_conditional_batch_buffer_end},
1936
1937         {"MI_LOAD_SCAN_LINES_INCL", OP_MI_LOAD_SCAN_LINES_INCL, F_LEN_CONST,
1938                 R_RCS | R_BCS, D_ALL, 0, 2, NULL},
1939
1940         {"XY_SETUP_BLT", OP_XY_SETUP_BLT, F_LEN_VAR, R_BCS, D_ALL,
1941                 ADDR_FIX_2(4, 7), 8, NULL},
1942
1943         {"XY_SETUP_CLIP_BLT", OP_XY_SETUP_CLIP_BLT, F_LEN_VAR, R_BCS, D_ALL,
1944                 0, 8, NULL},
1945
1946         {"XY_SETUP_MONO_PATTERN_SL_BLT", OP_XY_SETUP_MONO_PATTERN_SL_BLT,
1947                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
1948
1949         {"XY_PIXEL_BLT", OP_XY_PIXEL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
1950
1951         {"XY_SCANLINES_BLT", OP_XY_SCANLINES_BLT, F_LEN_VAR, R_BCS, D_ALL,
1952                 0, 8, NULL},
1953
1954         {"XY_TEXT_BLT", OP_XY_TEXT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1955                 ADDR_FIX_1(3), 8, NULL},
1956
1957         {"XY_TEXT_IMMEDIATE_BLT", OP_XY_TEXT_IMMEDIATE_BLT, F_LEN_VAR, R_BCS,
1958                 D_ALL, 0, 8, NULL},
1959
1960         {"XY_COLOR_BLT", OP_XY_COLOR_BLT, F_LEN_VAR, R_BCS, D_ALL,
1961                 ADDR_FIX_1(4), 8, NULL},
1962
1963         {"XY_PAT_BLT", OP_XY_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1964                 ADDR_FIX_2(4, 5), 8, NULL},
1965
1966         {"XY_MONO_PAT_BLT", OP_XY_MONO_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1967                 ADDR_FIX_1(4), 8, NULL},
1968
1969         {"XY_SRC_COPY_BLT", OP_XY_SRC_COPY_BLT, F_LEN_VAR, R_BCS, D_ALL,
1970                 ADDR_FIX_2(4, 7), 8, NULL},
1971
1972         {"XY_MONO_SRC_COPY_BLT", OP_XY_MONO_SRC_COPY_BLT, F_LEN_VAR, R_BCS,
1973                 D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
1974
1975         {"XY_FULL_BLT", OP_XY_FULL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
1976
1977         {"XY_FULL_MONO_SRC_BLT", OP_XY_FULL_MONO_SRC_BLT, F_LEN_VAR, R_BCS,
1978                 D_ALL, ADDR_FIX_3(4, 5, 8), 8, NULL},
1979
1980         {"XY_FULL_MONO_PATTERN_BLT", OP_XY_FULL_MONO_PATTERN_BLT, F_LEN_VAR,
1981                 R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
1982
1983         {"XY_FULL_MONO_PATTERN_MONO_SRC_BLT",
1984                 OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT,
1985                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
1986
1987         {"XY_MONO_PAT_FIXED_BLT", OP_XY_MONO_PAT_FIXED_BLT, F_LEN_VAR, R_BCS,
1988                 D_ALL, ADDR_FIX_1(4), 8, NULL},
1989
1990         {"XY_MONO_SRC_COPY_IMMEDIATE_BLT", OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT,
1991                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
1992
1993         {"XY_PAT_BLT_IMMEDIATE", OP_XY_PAT_BLT_IMMEDIATE, F_LEN_VAR, R_BCS,
1994                 D_ALL, ADDR_FIX_1(4), 8, NULL},
1995
1996         {"XY_SRC_COPY_CHROMA_BLT", OP_XY_SRC_COPY_CHROMA_BLT, F_LEN_VAR, R_BCS,
1997                 D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
1998
1999         {"XY_FULL_IMMEDIATE_PATTERN_BLT", OP_XY_FULL_IMMEDIATE_PATTERN_BLT,
2000                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2001
2002         {"XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT",
2003                 OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT,
2004                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2005
2006         {"XY_PAT_CHROMA_BLT", OP_XY_PAT_CHROMA_BLT, F_LEN_VAR, R_BCS, D_ALL,
2007                 ADDR_FIX_2(4, 5), 8, NULL},
2008
2009         {"XY_PAT_CHROMA_BLT_IMMEDIATE", OP_XY_PAT_CHROMA_BLT_IMMEDIATE,
2010                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2011
2012         {"3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP",
2013                 OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP,
2014                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2015
2016         {"3DSTATE_VIEWPORT_STATE_POINTERS_CC",
2017                 OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
2018                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2019
2020         {"3DSTATE_BLEND_STATE_POINTERS",
2021                 OP_3DSTATE_BLEND_STATE_POINTERS,
2022                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2023
2024         {"3DSTATE_DEPTH_STENCIL_STATE_POINTERS",
2025                 OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
2026                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2027
2028         {"3DSTATE_BINDING_TABLE_POINTERS_VS",
2029                 OP_3DSTATE_BINDING_TABLE_POINTERS_VS,
2030                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2031
2032         {"3DSTATE_BINDING_TABLE_POINTERS_HS",
2033                 OP_3DSTATE_BINDING_TABLE_POINTERS_HS,
2034                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2035
2036         {"3DSTATE_BINDING_TABLE_POINTERS_DS",
2037                 OP_3DSTATE_BINDING_TABLE_POINTERS_DS,
2038                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2039
2040         {"3DSTATE_BINDING_TABLE_POINTERS_GS",
2041                 OP_3DSTATE_BINDING_TABLE_POINTERS_GS,
2042                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2043
2044         {"3DSTATE_BINDING_TABLE_POINTERS_PS",
2045                 OP_3DSTATE_BINDING_TABLE_POINTERS_PS,
2046                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2047
2048         {"3DSTATE_SAMPLER_STATE_POINTERS_VS",
2049                 OP_3DSTATE_SAMPLER_STATE_POINTERS_VS,
2050                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2051
2052         {"3DSTATE_SAMPLER_STATE_POINTERS_HS",
2053                 OP_3DSTATE_SAMPLER_STATE_POINTERS_HS,
2054                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2055
2056         {"3DSTATE_SAMPLER_STATE_POINTERS_DS",
2057                 OP_3DSTATE_SAMPLER_STATE_POINTERS_DS,
2058                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2059
2060         {"3DSTATE_SAMPLER_STATE_POINTERS_GS",
2061                 OP_3DSTATE_SAMPLER_STATE_POINTERS_GS,
2062                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2063
2064         {"3DSTATE_SAMPLER_STATE_POINTERS_PS",
2065                 OP_3DSTATE_SAMPLER_STATE_POINTERS_PS,
2066                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2067
2068         {"3DSTATE_URB_VS", OP_3DSTATE_URB_VS, F_LEN_VAR, R_RCS, D_ALL,
2069                 0, 8, NULL},
2070
2071         {"3DSTATE_URB_HS", OP_3DSTATE_URB_HS, F_LEN_VAR, R_RCS, D_ALL,
2072                 0, 8, NULL},
2073
2074         {"3DSTATE_URB_DS", OP_3DSTATE_URB_DS, F_LEN_VAR, R_RCS, D_ALL,
2075                 0, 8, NULL},
2076
2077         {"3DSTATE_URB_GS", OP_3DSTATE_URB_GS, F_LEN_VAR, R_RCS, D_ALL,
2078                 0, 8, NULL},
2079
2080         {"3DSTATE_GATHER_CONSTANT_VS", OP_3DSTATE_GATHER_CONSTANT_VS,
2081                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2082
2083         {"3DSTATE_GATHER_CONSTANT_GS", OP_3DSTATE_GATHER_CONSTANT_GS,
2084                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2085
2086         {"3DSTATE_GATHER_CONSTANT_HS", OP_3DSTATE_GATHER_CONSTANT_HS,
2087                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2088
2089         {"3DSTATE_GATHER_CONSTANT_DS", OP_3DSTATE_GATHER_CONSTANT_DS,
2090                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2091
2092         {"3DSTATE_GATHER_CONSTANT_PS", OP_3DSTATE_GATHER_CONSTANT_PS,
2093                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2094
2095         {"3DSTATE_DX9_CONSTANTF_VS", OP_3DSTATE_DX9_CONSTANTF_VS,
2096                 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2097
2098         {"3DSTATE_DX9_CONSTANTF_PS", OP_3DSTATE_DX9_CONSTANTF_PS,
2099                 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2100
2101         {"3DSTATE_DX9_CONSTANTI_VS", OP_3DSTATE_DX9_CONSTANTI_VS,
2102                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2103
2104         {"3DSTATE_DX9_CONSTANTI_PS", OP_3DSTATE_DX9_CONSTANTI_PS,
2105                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2106
2107         {"3DSTATE_DX9_CONSTANTB_VS", OP_3DSTATE_DX9_CONSTANTB_VS,
2108                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2109
2110         {"3DSTATE_DX9_CONSTANTB_PS", OP_3DSTATE_DX9_CONSTANTB_PS,
2111                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2112
2113         {"3DSTATE_DX9_LOCAL_VALID_VS", OP_3DSTATE_DX9_LOCAL_VALID_VS,
2114                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2115
2116         {"3DSTATE_DX9_LOCAL_VALID_PS", OP_3DSTATE_DX9_LOCAL_VALID_PS,
2117                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2118
2119         {"3DSTATE_DX9_GENERATE_ACTIVE_VS", OP_3DSTATE_DX9_GENERATE_ACTIVE_VS,
2120                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2121
2122         {"3DSTATE_DX9_GENERATE_ACTIVE_PS", OP_3DSTATE_DX9_GENERATE_ACTIVE_PS,
2123                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2124
2125         {"3DSTATE_BINDING_TABLE_EDIT_VS", OP_3DSTATE_BINDING_TABLE_EDIT_VS,
2126                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2127
2128         {"3DSTATE_BINDING_TABLE_EDIT_GS", OP_3DSTATE_BINDING_TABLE_EDIT_GS,
2129                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2130
2131         {"3DSTATE_BINDING_TABLE_EDIT_HS", OP_3DSTATE_BINDING_TABLE_EDIT_HS,
2132                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2133
2134         {"3DSTATE_BINDING_TABLE_EDIT_DS", OP_3DSTATE_BINDING_TABLE_EDIT_DS,
2135                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2136
2137         {"3DSTATE_BINDING_TABLE_EDIT_PS", OP_3DSTATE_BINDING_TABLE_EDIT_PS,
2138                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2139
2140         {"3DSTATE_VF_INSTANCING", OP_3DSTATE_VF_INSTANCING, F_LEN_VAR, R_RCS,
2141                 D_BDW_PLUS, 0, 8, NULL},
2142
2143         {"3DSTATE_VF_SGVS", OP_3DSTATE_VF_SGVS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2144                 NULL},
2145
2146         {"3DSTATE_VF_TOPOLOGY", OP_3DSTATE_VF_TOPOLOGY, F_LEN_VAR, R_RCS,
2147                 D_BDW_PLUS, 0, 8, NULL},
2148
2149         {"3DSTATE_WM_CHROMAKEY", OP_3DSTATE_WM_CHROMAKEY, F_LEN_VAR, R_RCS,
2150                 D_BDW_PLUS, 0, 8, NULL},
2151
2152         {"3DSTATE_PS_BLEND", OP_3DSTATE_PS_BLEND, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2153                 8, NULL},
2154
2155         {"3DSTATE_WM_DEPTH_STENCIL", OP_3DSTATE_WM_DEPTH_STENCIL, F_LEN_VAR,
2156                 R_RCS, D_BDW_PLUS, 0, 8, NULL},
2157
2158         {"3DSTATE_PS_EXTRA", OP_3DSTATE_PS_EXTRA, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2159                 8, NULL},
2160
2161         {"3DSTATE_RASTER", OP_3DSTATE_RASTER, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2162                 NULL},
2163
2164         {"3DSTATE_SBE_SWIZ", OP_3DSTATE_SBE_SWIZ, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2165                 NULL},
2166
2167         {"3DSTATE_WM_HZ_OP", OP_3DSTATE_WM_HZ_OP, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2168                 NULL},
2169
2170         {"3DSTATE_VERTEX_BUFFERS", OP_3DSTATE_VERTEX_BUFFERS, F_LEN_VAR, R_RCS,
2171                 D_BDW_PLUS, 0, 8, NULL},
2172
2173         {"3DSTATE_VERTEX_ELEMENTS", OP_3DSTATE_VERTEX_ELEMENTS, F_LEN_VAR,
2174                 R_RCS, D_ALL, 0, 8, NULL},
2175
2176         {"3DSTATE_INDEX_BUFFER", OP_3DSTATE_INDEX_BUFFER, F_LEN_VAR, R_RCS,
2177                 D_BDW_PLUS, ADDR_FIX_1(2), 8, NULL},
2178
2179         {"3DSTATE_VF_STATISTICS", OP_3DSTATE_VF_STATISTICS, F_LEN_CONST,
2180                 R_RCS, D_ALL, 0, 1, NULL},
2181
2182         {"3DSTATE_VF", OP_3DSTATE_VF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2183
2184         {"3DSTATE_CC_STATE_POINTERS", OP_3DSTATE_CC_STATE_POINTERS, F_LEN_VAR,
2185                 R_RCS, D_ALL, 0, 8, NULL},
2186
2187         {"3DSTATE_SCISSOR_STATE_POINTERS", OP_3DSTATE_SCISSOR_STATE_POINTERS,
2188                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2189
2190         {"3DSTATE_GS", OP_3DSTATE_GS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2191
2192         {"3DSTATE_CLIP", OP_3DSTATE_CLIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2193
2194         {"3DSTATE_WM", OP_3DSTATE_WM, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2195
2196         {"3DSTATE_CONSTANT_GS", OP_3DSTATE_CONSTANT_GS, F_LEN_VAR, R_RCS,
2197                 D_BDW_PLUS, 0, 8, NULL},
2198
2199         {"3DSTATE_CONSTANT_PS", OP_3DSTATE_CONSTANT_PS, F_LEN_VAR, R_RCS,
2200                 D_BDW_PLUS, 0, 8, NULL},
2201
2202         {"3DSTATE_SAMPLE_MASK", OP_3DSTATE_SAMPLE_MASK, F_LEN_VAR, R_RCS,
2203                 D_ALL, 0, 8, NULL},
2204
2205         {"3DSTATE_CONSTANT_HS", OP_3DSTATE_CONSTANT_HS, F_LEN_VAR, R_RCS,
2206                 D_BDW_PLUS, 0, 8, NULL},
2207
2208         {"3DSTATE_CONSTANT_DS", OP_3DSTATE_CONSTANT_DS, F_LEN_VAR, R_RCS,
2209                 D_BDW_PLUS, 0, 8, NULL},
2210
2211         {"3DSTATE_HS", OP_3DSTATE_HS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2212
2213         {"3DSTATE_TE", OP_3DSTATE_TE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2214
2215         {"3DSTATE_DS", OP_3DSTATE_DS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2216
2217         {"3DSTATE_STREAMOUT", OP_3DSTATE_STREAMOUT, F_LEN_VAR, R_RCS,
2218                 D_ALL, 0, 8, NULL},
2219
2220         {"3DSTATE_SBE", OP_3DSTATE_SBE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2221
2222         {"3DSTATE_PS", OP_3DSTATE_PS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2223
2224         {"3DSTATE_DRAWING_RECTANGLE", OP_3DSTATE_DRAWING_RECTANGLE, F_LEN_VAR,
2225                 R_RCS, D_ALL, 0, 8, NULL},
2226
2227         {"3DSTATE_SAMPLER_PALETTE_LOAD0", OP_3DSTATE_SAMPLER_PALETTE_LOAD0,
2228                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2229
2230         {"3DSTATE_CHROMA_KEY", OP_3DSTATE_CHROMA_KEY, F_LEN_VAR, R_RCS, D_ALL,
2231                 0, 8, NULL},
2232
2233         {"3DSTATE_DEPTH_BUFFER", OP_3DSTATE_DEPTH_BUFFER, F_LEN_VAR, R_RCS,
2234                 D_ALL, ADDR_FIX_1(2), 8, NULL},
2235
2236         {"3DSTATE_POLY_STIPPLE_OFFSET", OP_3DSTATE_POLY_STIPPLE_OFFSET,
2237                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2238
2239         {"3DSTATE_POLY_STIPPLE_PATTERN", OP_3DSTATE_POLY_STIPPLE_PATTERN,
2240                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2241
2242         {"3DSTATE_LINE_STIPPLE", OP_3DSTATE_LINE_STIPPLE, F_LEN_VAR, R_RCS,
2243                 D_ALL, 0, 8, NULL},
2244
2245         {"3DSTATE_AA_LINE_PARAMS", OP_3DSTATE_AA_LINE_PARAMS, F_LEN_VAR, R_RCS,
2246                 D_ALL, 0, 8, NULL},
2247
2248         {"3DSTATE_GS_SVB_INDEX", OP_3DSTATE_GS_SVB_INDEX, F_LEN_VAR, R_RCS,
2249                 D_ALL, 0, 8, NULL},
2250
2251         {"3DSTATE_SAMPLER_PALETTE_LOAD1", OP_3DSTATE_SAMPLER_PALETTE_LOAD1,
2252                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2253
2254         {"3DSTATE_MULTISAMPLE", OP_3DSTATE_MULTISAMPLE_BDW, F_LEN_VAR, R_RCS,
2255                 D_BDW_PLUS, 0, 8, NULL},
2256
2257         {"3DSTATE_STENCIL_BUFFER", OP_3DSTATE_STENCIL_BUFFER, F_LEN_VAR, R_RCS,
2258                 D_ALL, ADDR_FIX_1(2), 8, NULL},
2259
2260         {"3DSTATE_HIER_DEPTH_BUFFER", OP_3DSTATE_HIER_DEPTH_BUFFER, F_LEN_VAR,
2261                 R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL},
2262
2263         {"3DSTATE_CLEAR_PARAMS", OP_3DSTATE_CLEAR_PARAMS, F_LEN_VAR,
2264                 R_RCS, D_ALL, 0, 8, NULL},
2265
2266         {"3DSTATE_PUSH_CONSTANT_ALLOC_VS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
2267                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2268
2269         {"3DSTATE_PUSH_CONSTANT_ALLOC_HS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS,
2270                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2271
2272         {"3DSTATE_PUSH_CONSTANT_ALLOC_DS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS,
2273                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2274
2275         {"3DSTATE_PUSH_CONSTANT_ALLOC_GS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS,
2276                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2277
2278         {"3DSTATE_PUSH_CONSTANT_ALLOC_PS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS,
2279                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2280
2281         {"3DSTATE_MONOFILTER_SIZE", OP_3DSTATE_MONOFILTER_SIZE, F_LEN_VAR,
2282                 R_RCS, D_ALL, 0, 8, NULL},
2283
2284         {"3DSTATE_SO_DECL_LIST", OP_3DSTATE_SO_DECL_LIST, F_LEN_VAR, R_RCS,
2285                 D_ALL, 0, 9, NULL},
2286
2287         {"3DSTATE_SO_BUFFER", OP_3DSTATE_SO_BUFFER, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2288                 ADDR_FIX_2(2, 4), 8, NULL},
2289
2290         {"3DSTATE_BINDING_TABLE_POOL_ALLOC",
2291                 OP_3DSTATE_BINDING_TABLE_POOL_ALLOC,
2292                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2293
2294         {"3DSTATE_GATHER_POOL_ALLOC", OP_3DSTATE_GATHER_POOL_ALLOC,
2295                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2296
2297         {"3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC",
2298                 OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC,
2299                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2300
2301         {"3DSTATE_SAMPLE_PATTERN", OP_3DSTATE_SAMPLE_PATTERN, F_LEN_VAR, R_RCS,
2302                 D_BDW_PLUS, 0, 8, NULL},
2303
2304         {"PIPE_CONTROL", OP_PIPE_CONTROL, F_LEN_VAR, R_RCS, D_ALL,
2305                 ADDR_FIX_1(2), 8, cmd_handler_pipe_control},
2306
2307         {"3DPRIMITIVE", OP_3DPRIMITIVE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2308
2309         {"PIPELINE_SELECT", OP_PIPELINE_SELECT, F_LEN_CONST, R_RCS, D_ALL, 0,
2310                 1, NULL},
2311
2312         {"STATE_PREFETCH", OP_STATE_PREFETCH, F_LEN_VAR, R_RCS, D_ALL,
2313                 ADDR_FIX_1(1), 8, NULL},
2314
2315         {"STATE_SIP", OP_STATE_SIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2316
2317         {"STATE_BASE_ADDRESS", OP_STATE_BASE_ADDRESS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2318                 ADDR_FIX_5(1, 3, 4, 5, 6), 8, NULL},
2319
2320         {"OP_3D_MEDIA_0_1_4", OP_3D_MEDIA_0_1_4, F_LEN_VAR, R_RCS, D_ALL,
2321                 ADDR_FIX_1(1), 8, NULL},
2322
2323         {"3DSTATE_VS", OP_3DSTATE_VS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2324
2325         {"3DSTATE_SF", OP_3DSTATE_SF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2326
2327         {"3DSTATE_CONSTANT_VS", OP_3DSTATE_CONSTANT_VS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2328                 0, 8, NULL},
2329
2330         {"3DSTATE_COMPONENT_PACKING", OP_3DSTATE_COMPONENT_PACKING, F_LEN_VAR, R_RCS,
2331                 D_SKL_PLUS, 0, 8, NULL},
2332
2333         {"MEDIA_INTERFACE_DESCRIPTOR_LOAD", OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD,
2334                 F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2335
2336         {"MEDIA_GATEWAY_STATE", OP_MEDIA_GATEWAY_STATE, F_LEN_VAR, R_RCS, D_ALL,
2337                 0, 16, NULL},
2338
2339         {"MEDIA_STATE_FLUSH", OP_MEDIA_STATE_FLUSH, F_LEN_VAR, R_RCS, D_ALL,
2340                 0, 16, NULL},
2341
2342         {"MEDIA_POOL_STATE", OP_MEDIA_POOL_STATE, F_LEN_VAR, R_RCS, D_ALL,
2343                 0, 16, NULL},
2344
2345         {"MEDIA_OBJECT", OP_MEDIA_OBJECT, F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2346
2347         {"MEDIA_CURBE_LOAD", OP_MEDIA_CURBE_LOAD, F_LEN_VAR, R_RCS, D_ALL,
2348                 0, 16, NULL},
2349
2350         {"MEDIA_OBJECT_PRT", OP_MEDIA_OBJECT_PRT, F_LEN_VAR, R_RCS, D_ALL,
2351                 0, 16, NULL},
2352
2353         {"MEDIA_OBJECT_WALKER", OP_MEDIA_OBJECT_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2354                 0, 16, NULL},
2355
2356         {"GPGPU_WALKER", OP_GPGPU_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2357                 0, 8, NULL},
2358
2359         {"MEDIA_VFE_STATE", OP_MEDIA_VFE_STATE, F_LEN_VAR, R_RCS, D_ALL, 0, 16,
2360                 NULL},
2361
2362         {"3DSTATE_VF_STATISTICS_GM45", OP_3DSTATE_VF_STATISTICS_GM45,
2363                 F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2364
2365         {"MFX_PIPE_MODE_SELECT", OP_MFX_PIPE_MODE_SELECT, F_LEN_VAR,
2366                 R_VCS, D_ALL, 0, 12, NULL},
2367
2368         {"MFX_SURFACE_STATE", OP_MFX_SURFACE_STATE, F_LEN_VAR,
2369                 R_VCS, D_ALL, 0, 12, NULL},
2370
2371         {"MFX_PIPE_BUF_ADDR_STATE", OP_MFX_PIPE_BUF_ADDR_STATE, F_LEN_VAR,
2372                 R_VCS, D_BDW_PLUS, 0, 12, NULL},
2373
2374         {"MFX_IND_OBJ_BASE_ADDR_STATE", OP_MFX_IND_OBJ_BASE_ADDR_STATE,
2375                 F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2376
2377         {"MFX_BSP_BUF_BASE_ADDR_STATE", OP_MFX_BSP_BUF_BASE_ADDR_STATE,
2378                 F_LEN_VAR, R_VCS, D_BDW_PLUS, ADDR_FIX_3(1, 3, 5), 12, NULL},
2379
2380         {"OP_2_0_0_5", OP_2_0_0_5, F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2381
2382         {"MFX_STATE_POINTER", OP_MFX_STATE_POINTER, F_LEN_VAR,
2383                 R_VCS, D_ALL, 0, 12, NULL},
2384
2385         {"MFX_QM_STATE", OP_MFX_QM_STATE, F_LEN_VAR,
2386                 R_VCS, D_ALL, 0, 12, NULL},
2387
2388         {"MFX_FQM_STATE", OP_MFX_FQM_STATE, F_LEN_VAR,
2389                 R_VCS, D_ALL, 0, 12, NULL},
2390
2391         {"MFX_PAK_INSERT_OBJECT", OP_MFX_PAK_INSERT_OBJECT, F_LEN_VAR,
2392                 R_VCS, D_ALL, 0, 12, NULL},
2393
2394         {"MFX_STITCH_OBJECT", OP_MFX_STITCH_OBJECT, F_LEN_VAR,
2395                 R_VCS, D_ALL, 0, 12, NULL},
2396
2397         {"MFD_IT_OBJECT", OP_MFD_IT_OBJECT, F_LEN_VAR,
2398                 R_VCS, D_ALL, 0, 12, NULL},
2399
2400         {"MFX_WAIT", OP_MFX_WAIT, F_LEN_VAR,
2401                 R_VCS, D_ALL, 0, 6, NULL},
2402
2403         {"MFX_AVC_IMG_STATE", OP_MFX_AVC_IMG_STATE, F_LEN_VAR,
2404                 R_VCS, D_ALL, 0, 12, NULL},
2405
2406         {"MFX_AVC_QM_STATE", OP_MFX_AVC_QM_STATE, F_LEN_VAR,
2407                 R_VCS, D_ALL, 0, 12, NULL},
2408
2409         {"MFX_AVC_DIRECTMODE_STATE", OP_MFX_AVC_DIRECTMODE_STATE, F_LEN_VAR,
2410                 R_VCS, D_ALL, 0, 12, NULL},
2411
2412         {"MFX_AVC_SLICE_STATE", OP_MFX_AVC_SLICE_STATE, F_LEN_VAR,
2413                 R_VCS, D_ALL, 0, 12, NULL},
2414
2415         {"MFX_AVC_REF_IDX_STATE", OP_MFX_AVC_REF_IDX_STATE, F_LEN_VAR,
2416                 R_VCS, D_ALL, 0, 12, NULL},
2417
2418         {"MFX_AVC_WEIGHTOFFSET_STATE", OP_MFX_AVC_WEIGHTOFFSET_STATE, F_LEN_VAR,
2419                 R_VCS, D_ALL, 0, 12, NULL},
2420
2421         {"MFD_AVC_PICID_STATE", OP_MFD_AVC_PICID_STATE, F_LEN_VAR,
2422                 R_VCS, D_ALL, 0, 12, NULL},
2423         {"MFD_AVC_DPB_STATE", OP_MFD_AVC_DPB_STATE, F_LEN_VAR,
2424                 R_VCS, D_ALL, 0, 12, NULL},
2425
2426         {"MFD_AVC_BSD_OBJECT", OP_MFD_AVC_BSD_OBJECT, F_LEN_VAR,
2427                 R_VCS, D_ALL, 0, 12, NULL},
2428
2429         {"MFD_AVC_SLICEADDR", OP_MFD_AVC_SLICEADDR, F_LEN_VAR,
2430                 R_VCS, D_ALL, ADDR_FIX_1(2), 12, NULL},
2431
2432         {"MFC_AVC_PAK_OBJECT", OP_MFC_AVC_PAK_OBJECT, F_LEN_VAR,
2433                 R_VCS, D_ALL, 0, 12, NULL},
2434
2435         {"MFX_VC1_PRED_PIPE_STATE", OP_MFX_VC1_PRED_PIPE_STATE, F_LEN_VAR,
2436                 R_VCS, D_ALL, 0, 12, NULL},
2437
2438         {"MFX_VC1_DIRECTMODE_STATE", OP_MFX_VC1_DIRECTMODE_STATE, F_LEN_VAR,
2439                 R_VCS, D_ALL, 0, 12, NULL},
2440
2441         {"MFD_VC1_SHORT_PIC_STATE", OP_MFD_VC1_SHORT_PIC_STATE, F_LEN_VAR,
2442                 R_VCS, D_ALL, 0, 12, NULL},
2443
2444         {"MFD_VC1_LONG_PIC_STATE", OP_MFD_VC1_LONG_PIC_STATE, F_LEN_VAR,
2445                 R_VCS, D_ALL, 0, 12, NULL},
2446
2447         {"MFD_VC1_BSD_OBJECT", OP_MFD_VC1_BSD_OBJECT, F_LEN_VAR,
2448                 R_VCS, D_ALL, 0, 12, NULL},
2449
2450         {"MFC_MPEG2_SLICEGROUP_STATE", OP_MFC_MPEG2_SLICEGROUP_STATE, F_LEN_VAR,
2451                 R_VCS, D_ALL, 0, 12, NULL},
2452
2453         {"MFC_MPEG2_PAK_OBJECT", OP_MFC_MPEG2_PAK_OBJECT, F_LEN_VAR,
2454                 R_VCS, D_ALL, 0, 12, NULL},
2455
2456         {"MFX_MPEG2_PIC_STATE", OP_MFX_MPEG2_PIC_STATE, F_LEN_VAR,
2457                 R_VCS, D_ALL, 0, 12, NULL},
2458
2459         {"MFX_MPEG2_QM_STATE", OP_MFX_MPEG2_QM_STATE, F_LEN_VAR,
2460                 R_VCS, D_ALL, 0, 12, NULL},
2461
2462         {"MFD_MPEG2_BSD_OBJECT", OP_MFD_MPEG2_BSD_OBJECT, F_LEN_VAR,
2463                 R_VCS, D_ALL, 0, 12, NULL},
2464
2465         {"MFX_2_6_0_0", OP_MFX_2_6_0_0, F_LEN_VAR, R_VCS, D_ALL,
2466                 0, 16, NULL},
2467
2468         {"MFX_2_6_0_9", OP_MFX_2_6_0_9, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2469
2470         {"MFX_2_6_0_8", OP_MFX_2_6_0_8, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2471
2472         {"MFX_JPEG_PIC_STATE", OP_MFX_JPEG_PIC_STATE, F_LEN_VAR,
2473                 R_VCS, D_ALL, 0, 12, NULL},
2474
2475         {"MFX_JPEG_HUFF_TABLE_STATE", OP_MFX_JPEG_HUFF_TABLE_STATE, F_LEN_VAR,
2476                 R_VCS, D_ALL, 0, 12, NULL},
2477
2478         {"MFD_JPEG_BSD_OBJECT", OP_MFD_JPEG_BSD_OBJECT, F_LEN_VAR,
2479                 R_VCS, D_ALL, 0, 12, NULL},
2480
2481         {"VEBOX_STATE", OP_VEB_STATE, F_LEN_VAR, R_VECS, D_ALL, 0, 12, NULL},
2482
2483         {"VEBOX_SURFACE_STATE", OP_VEB_SURFACE_STATE, F_LEN_VAR, R_VECS, D_ALL,
2484                 0, 12, NULL},
2485
2486         {"VEB_DI_IECP", OP_VEB_DNDI_IECP_STATE, F_LEN_VAR, R_VECS, D_BDW_PLUS,
2487                 0, 20, NULL},
2488 };
2489
2490 static void add_cmd_entry(struct intel_gvt *gvt, struct cmd_entry *e)
2491 {
2492         hash_add(gvt->cmd_table, &e->hlist, e->info->opcode);
2493 }
2494
2495 /* call the cmd handler, and advance ip */
2496 static int cmd_parser_exec(struct parser_exec_state *s)
2497 {
2498         struct intel_vgpu *vgpu = s->vgpu;
2499         struct cmd_info *info;
2500         u32 cmd;
2501         int ret = 0;
2502
2503         cmd = cmd_val(s, 0);
2504
2505         info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
2506         if (info == NULL) {
2507                 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",
2508                                 cmd, get_opcode(cmd, s->ring_id),
2509                                 (s->buf_addr_type == PPGTT_BUFFER) ?
2510                                 "ppgtt" : "ggtt", s->ring_id, s->workload);
2511                 return -EBADRQC;
2512         }
2513
2514         s->info = info;
2515
2516         trace_gvt_command(vgpu->id, s->ring_id, s->ip_gma, s->ip_va,
2517                           cmd_length(s), s->buf_type, s->buf_addr_type,
2518                           s->workload, info->name);
2519
2520         if (info->handler) {
2521                 ret = info->handler(s);
2522                 if (ret < 0) {
2523                         gvt_vgpu_err("%s handler error\n", info->name);
2524                         return ret;
2525                 }
2526         }
2527
2528         if (!(info->flag & F_IP_ADVANCE_CUSTOM)) {
2529                 ret = cmd_advance_default(s);
2530                 if (ret) {
2531                         gvt_vgpu_err("%s IP advance error\n", info->name);
2532                         return ret;
2533                 }
2534         }
2535         return 0;
2536 }
2537
2538 static inline bool gma_out_of_range(unsigned long gma,
2539                 unsigned long gma_head, unsigned int gma_tail)
2540 {
2541         if (gma_tail >= gma_head)
2542                 return (gma < gma_head) || (gma > gma_tail);
2543         else
2544                 return (gma > gma_tail) && (gma < gma_head);
2545 }
2546
2547 /* Keep the consistent return type, e.g EBADRQC for unknown
2548  * cmd, EFAULT for invalid address, EPERM for nonpriv. later
2549  * works as the input of VM healthy status.
2550  */
2551 static int command_scan(struct parser_exec_state *s,
2552                 unsigned long rb_head, unsigned long rb_tail,
2553                 unsigned long rb_start, unsigned long rb_len)
2554 {
2555
2556         unsigned long gma_head, gma_tail, gma_bottom;
2557         int ret = 0;
2558         struct intel_vgpu *vgpu = s->vgpu;
2559
2560         gma_head = rb_start + rb_head;
2561         gma_tail = rb_start + rb_tail;
2562         gma_bottom = rb_start +  rb_len;
2563
2564         while (s->ip_gma != gma_tail) {
2565                 if (s->buf_type == RING_BUFFER_INSTRUCTION) {
2566                         if (!(s->ip_gma >= rb_start) ||
2567                                 !(s->ip_gma < gma_bottom)) {
2568                                 gvt_vgpu_err("ip_gma %lx out of ring scope."
2569                                         "(base:0x%lx, bottom: 0x%lx)\n",
2570                                         s->ip_gma, rb_start,
2571                                         gma_bottom);
2572                                 parser_exec_state_dump(s);
2573                                 return -EFAULT;
2574                         }
2575                         if (gma_out_of_range(s->ip_gma, gma_head, gma_tail)) {
2576                                 gvt_vgpu_err("ip_gma %lx out of range."
2577                                         "base 0x%lx head 0x%lx tail 0x%lx\n",
2578                                         s->ip_gma, rb_start,
2579                                         rb_head, rb_tail);
2580                                 parser_exec_state_dump(s);
2581                                 break;
2582                         }
2583                 }
2584                 ret = cmd_parser_exec(s);
2585                 if (ret) {
2586                         gvt_vgpu_err("cmd parser error\n");
2587                         parser_exec_state_dump(s);
2588                         break;
2589                 }
2590         }
2591
2592         return ret;
2593 }
2594
2595 static int scan_workload(struct intel_vgpu_workload *workload)
2596 {
2597         unsigned long gma_head, gma_tail, gma_bottom;
2598         struct parser_exec_state s;
2599         int ret = 0;
2600
2601         /* ring base is page aligned */
2602         if (WARN_ON(!IS_ALIGNED(workload->rb_start, I915_GTT_PAGE_SIZE)))
2603                 return -EINVAL;
2604
2605         gma_head = workload->rb_start + workload->rb_head;
2606         gma_tail = workload->rb_start + workload->rb_tail;
2607         gma_bottom = workload->rb_start +  _RING_CTL_BUF_SIZE(workload->rb_ctl);
2608
2609         s.buf_type = RING_BUFFER_INSTRUCTION;
2610         s.buf_addr_type = GTT_BUFFER;
2611         s.vgpu = workload->vgpu;
2612         s.ring_id = workload->ring_id;
2613         s.ring_start = workload->rb_start;
2614         s.ring_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2615         s.ring_head = gma_head;
2616         s.ring_tail = gma_tail;
2617         s.rb_va = workload->shadow_ring_buffer_va;
2618         s.workload = workload;
2619         s.is_ctx_wa = false;
2620
2621         if ((bypass_scan_mask & (1 << workload->ring_id)) ||
2622                 gma_head == gma_tail)
2623                 return 0;
2624
2625         if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) {
2626                 ret = -EINVAL;
2627                 goto out;
2628         }
2629
2630         ret = ip_gma_set(&s, gma_head);
2631         if (ret)
2632                 goto out;
2633
2634         ret = command_scan(&s, workload->rb_head, workload->rb_tail,
2635                 workload->rb_start, _RING_CTL_BUF_SIZE(workload->rb_ctl));
2636
2637 out:
2638         return ret;
2639 }
2640
2641 static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2642 {
2643
2644         unsigned long gma_head, gma_tail, gma_bottom, ring_size, ring_tail;
2645         struct parser_exec_state s;
2646         int ret = 0;
2647         struct intel_vgpu_workload *workload = container_of(wa_ctx,
2648                                 struct intel_vgpu_workload,
2649                                 wa_ctx);
2650
2651         /* ring base is page aligned */
2652         if (WARN_ON(!IS_ALIGNED(wa_ctx->indirect_ctx.guest_gma,
2653                                         I915_GTT_PAGE_SIZE)))
2654                 return -EINVAL;
2655
2656         ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(uint32_t);
2657         ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES,
2658                         PAGE_SIZE);
2659         gma_head = wa_ctx->indirect_ctx.guest_gma;
2660         gma_tail = wa_ctx->indirect_ctx.guest_gma + ring_tail;
2661         gma_bottom = wa_ctx->indirect_ctx.guest_gma + ring_size;
2662
2663         s.buf_type = RING_BUFFER_INSTRUCTION;
2664         s.buf_addr_type = GTT_BUFFER;
2665         s.vgpu = workload->vgpu;
2666         s.ring_id = workload->ring_id;
2667         s.ring_start = wa_ctx->indirect_ctx.guest_gma;
2668         s.ring_size = ring_size;
2669         s.ring_head = gma_head;
2670         s.ring_tail = gma_tail;
2671         s.rb_va = wa_ctx->indirect_ctx.shadow_va;
2672         s.workload = workload;
2673         s.is_ctx_wa = true;
2674
2675         if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) {
2676                 ret = -EINVAL;
2677                 goto out;
2678         }
2679
2680         ret = ip_gma_set(&s, gma_head);
2681         if (ret)
2682                 goto out;
2683
2684         ret = command_scan(&s, 0, ring_tail,
2685                 wa_ctx->indirect_ctx.guest_gma, ring_size);
2686 out:
2687         return ret;
2688 }
2689
2690 static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload)
2691 {
2692         struct intel_vgpu *vgpu = workload->vgpu;
2693         struct intel_vgpu_submission *s = &vgpu->submission;
2694         unsigned long gma_head, gma_tail, gma_top, guest_rb_size;
2695         void *shadow_ring_buffer_va;
2696         int ring_id = workload->ring_id;
2697         int ret;
2698
2699         guest_rb_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2700
2701         /* calculate workload ring buffer size */
2702         workload->rb_len = (workload->rb_tail + guest_rb_size -
2703                         workload->rb_head) % guest_rb_size;
2704
2705         gma_head = workload->rb_start + workload->rb_head;
2706         gma_tail = workload->rb_start + workload->rb_tail;
2707         gma_top = workload->rb_start + guest_rb_size;
2708
2709         if (workload->rb_len > s->ring_scan_buffer_size[ring_id]) {
2710                 void *p;
2711
2712                 /* realloc the new ring buffer if needed */
2713                 p = krealloc(s->ring_scan_buffer[ring_id], workload->rb_len,
2714                                 GFP_KERNEL);
2715                 if (!p) {
2716                         gvt_vgpu_err("fail to re-alloc ring scan buffer\n");
2717                         return -ENOMEM;
2718                 }
2719                 s->ring_scan_buffer[ring_id] = p;
2720                 s->ring_scan_buffer_size[ring_id] = workload->rb_len;
2721         }
2722
2723         shadow_ring_buffer_va = s->ring_scan_buffer[ring_id];
2724
2725         /* get shadow ring buffer va */
2726         workload->shadow_ring_buffer_va = shadow_ring_buffer_va;
2727
2728         /* head > tail --> copy head <-> top */
2729         if (gma_head > gma_tail) {
2730                 ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm,
2731                                       gma_head, gma_top, shadow_ring_buffer_va);
2732                 if (ret < 0) {
2733                         gvt_vgpu_err("fail to copy guest ring buffer\n");
2734                         return ret;
2735                 }
2736                 shadow_ring_buffer_va += ret;
2737                 gma_head = workload->rb_start;
2738         }
2739
2740         /* copy head or start <-> tail */
2741         ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, gma_head, gma_tail,
2742                                 shadow_ring_buffer_va);
2743         if (ret < 0) {
2744                 gvt_vgpu_err("fail to copy guest ring buffer\n");
2745                 return ret;
2746         }
2747         return 0;
2748 }
2749
2750 int intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload *workload)
2751 {
2752         int ret;
2753         struct intel_vgpu *vgpu = workload->vgpu;
2754
2755         ret = shadow_workload_ring_buffer(workload);
2756         if (ret) {
2757                 gvt_vgpu_err("fail to shadow workload ring_buffer\n");
2758                 return ret;
2759         }
2760
2761         ret = scan_workload(workload);
2762         if (ret) {
2763                 gvt_vgpu_err("scan workload error\n");
2764                 return ret;
2765         }
2766         return 0;
2767 }
2768
2769 static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2770 {
2771         int ctx_size = wa_ctx->indirect_ctx.size;
2772         unsigned long guest_gma = wa_ctx->indirect_ctx.guest_gma;
2773         struct intel_vgpu_workload *workload = container_of(wa_ctx,
2774                                         struct intel_vgpu_workload,
2775                                         wa_ctx);
2776         struct intel_vgpu *vgpu = workload->vgpu;
2777         struct drm_i915_gem_object *obj;
2778         int ret = 0;
2779         void *map;
2780
2781         obj = i915_gem_object_create(workload->vgpu->gvt->dev_priv,
2782                                      roundup(ctx_size + CACHELINE_BYTES,
2783                                              PAGE_SIZE));
2784         if (IS_ERR(obj))
2785                 return PTR_ERR(obj);
2786
2787         /* get the va of the shadow batch buffer */
2788         map = i915_gem_object_pin_map(obj, I915_MAP_WB);
2789         if (IS_ERR(map)) {
2790                 gvt_vgpu_err("failed to vmap shadow indirect ctx\n");
2791                 ret = PTR_ERR(map);
2792                 goto put_obj;
2793         }
2794
2795         ret = i915_gem_object_set_to_cpu_domain(obj, false);
2796         if (ret) {
2797                 gvt_vgpu_err("failed to set shadow indirect ctx to CPU\n");
2798                 goto unmap_src;
2799         }
2800
2801         ret = copy_gma_to_hva(workload->vgpu,
2802                                 workload->vgpu->gtt.ggtt_mm,
2803                                 guest_gma, guest_gma + ctx_size,
2804                                 map);
2805         if (ret < 0) {
2806                 gvt_vgpu_err("fail to copy guest indirect ctx\n");
2807                 goto unmap_src;
2808         }
2809
2810         wa_ctx->indirect_ctx.obj = obj;
2811         wa_ctx->indirect_ctx.shadow_va = map;
2812         return 0;
2813
2814 unmap_src:
2815         i915_gem_object_unpin_map(obj);
2816 put_obj:
2817         i915_gem_object_put(obj);
2818         return ret;
2819 }
2820
2821 static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2822 {
2823         uint32_t per_ctx_start[CACHELINE_DWORDS] = {0};
2824         unsigned char *bb_start_sva;
2825
2826         if (!wa_ctx->per_ctx.valid)
2827                 return 0;
2828
2829         per_ctx_start[0] = 0x18800001;
2830         per_ctx_start[1] = wa_ctx->per_ctx.guest_gma;
2831
2832         bb_start_sva = (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
2833                                 wa_ctx->indirect_ctx.size;
2834
2835         memcpy(bb_start_sva, per_ctx_start, CACHELINE_BYTES);
2836
2837         return 0;
2838 }
2839
2840 int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2841 {
2842         int ret;
2843         struct intel_vgpu_workload *workload = container_of(wa_ctx,
2844                                         struct intel_vgpu_workload,
2845                                         wa_ctx);
2846         struct intel_vgpu *vgpu = workload->vgpu;
2847
2848         if (wa_ctx->indirect_ctx.size == 0)
2849                 return 0;
2850
2851         ret = shadow_indirect_ctx(wa_ctx);
2852         if (ret) {
2853                 gvt_vgpu_err("fail to shadow indirect ctx\n");
2854                 return ret;
2855         }
2856
2857         combine_wa_ctx(wa_ctx);
2858
2859         ret = scan_wa_ctx(wa_ctx);
2860         if (ret) {
2861                 gvt_vgpu_err("scan wa ctx error\n");
2862                 return ret;
2863         }
2864
2865         return 0;
2866 }
2867
2868 static struct cmd_info *find_cmd_entry_any_ring(struct intel_gvt *gvt,
2869                 unsigned int opcode, unsigned long rings)
2870 {
2871         struct cmd_info *info = NULL;
2872         unsigned int ring;
2873
2874         for_each_set_bit(ring, &rings, I915_NUM_ENGINES) {
2875                 info = find_cmd_entry(gvt, opcode, ring);
2876                 if (info)
2877                         break;
2878         }
2879         return info;
2880 }
2881
2882 static int init_cmd_table(struct intel_gvt *gvt)
2883 {
2884         int i;
2885         struct cmd_entry *e;
2886         struct cmd_info *info;
2887         unsigned int gen_type;
2888
2889         gen_type = intel_gvt_get_device_type(gvt);
2890
2891         for (i = 0; i < ARRAY_SIZE(cmd_info); i++) {
2892                 if (!(cmd_info[i].devices & gen_type))
2893                         continue;
2894
2895                 e = kzalloc(sizeof(*e), GFP_KERNEL);
2896                 if (!e)
2897                         return -ENOMEM;
2898
2899                 e->info = &cmd_info[i];
2900                 info = find_cmd_entry_any_ring(gvt,
2901                                 e->info->opcode, e->info->rings);
2902                 if (info) {
2903                         gvt_err("%s %s duplicated\n", e->info->name,
2904                                         info->name);
2905                         kfree(e);
2906                         return -EEXIST;
2907                 }
2908
2909                 INIT_HLIST_NODE(&e->hlist);
2910                 add_cmd_entry(gvt, e);
2911                 gvt_dbg_cmd("add %-30s op %04x flag %x devs %02x rings %02x\n",
2912                                 e->info->name, e->info->opcode, e->info->flag,
2913                                 e->info->devices, e->info->rings);
2914         }
2915         return 0;
2916 }
2917
2918 static void clean_cmd_table(struct intel_gvt *gvt)
2919 {
2920         struct hlist_node *tmp;
2921         struct cmd_entry *e;
2922         int i;
2923
2924         hash_for_each_safe(gvt->cmd_table, i, tmp, e, hlist)
2925                 kfree(e);
2926
2927         hash_init(gvt->cmd_table);
2928 }
2929
2930 void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt)
2931 {
2932         clean_cmd_table(gvt);
2933 }
2934
2935 int intel_gvt_init_cmd_parser(struct intel_gvt *gvt)
2936 {
2937         int ret;
2938
2939         ret = init_cmd_table(gvt);
2940         if (ret) {
2941                 intel_gvt_clean_cmd_parser(gvt);
2942                 return ret;
2943         }
2944         return 0;
2945 }