36c6180e57693d79c0edb39fa1a243d13d9e8912
[muen/linux.git] / drivers / gpu / drm / i915 / gvt / cmd_parser.c
1 /*
2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21  * SOFTWARE.
22  *
23  * Authors:
24  *    Ke Yu
25  *    Kevin Tian <kevin.tian@intel.com>
26  *    Zhiyuan Lv <zhiyuan.lv@intel.com>
27  *
28  * Contributors:
29  *    Min He <min.he@intel.com>
30  *    Ping Gao <ping.a.gao@intel.com>
31  *    Tina Zhang <tina.zhang@intel.com>
32  *    Yulei Zhang <yulei.zhang@intel.com>
33  *    Zhi Wang <zhi.a.wang@intel.com>
34  *
35  */
36
37 #include <linux/slab.h>
38 #include "i915_drv.h"
39 #include "gvt.h"
40 #include "i915_pvinfo.h"
41 #include "trace.h"
42
43 #define INVALID_OP    (~0U)
44
45 #define OP_LEN_MI           9
46 #define OP_LEN_2D           10
47 #define OP_LEN_3D_MEDIA     16
48 #define OP_LEN_MFX_VC       16
49 #define OP_LEN_VEBOX        16
50
51 #define CMD_TYPE(cmd)   (((cmd) >> 29) & 7)
52
53 struct sub_op_bits {
54         int hi;
55         int low;
56 };
57 struct decode_info {
58         char *name;
59         int op_len;
60         int nr_sub_op;
61         struct sub_op_bits *sub_op;
62 };
63
64 #define   MAX_CMD_BUDGET                        0x7fffffff
65 #define   MI_WAIT_FOR_PLANE_C_FLIP_PENDING      (1<<15)
66 #define   MI_WAIT_FOR_PLANE_B_FLIP_PENDING      (1<<9)
67 #define   MI_WAIT_FOR_PLANE_A_FLIP_PENDING      (1<<1)
68
69 #define   MI_WAIT_FOR_SPRITE_C_FLIP_PENDING      (1<<20)
70 #define   MI_WAIT_FOR_SPRITE_B_FLIP_PENDING      (1<<10)
71 #define   MI_WAIT_FOR_SPRITE_A_FLIP_PENDING      (1<<2)
72
73 /* Render Command Map */
74
75 /* MI_* command Opcode (28:23) */
76 #define OP_MI_NOOP                          0x0
77 #define OP_MI_SET_PREDICATE                 0x1  /* HSW+ */
78 #define OP_MI_USER_INTERRUPT                0x2
79 #define OP_MI_WAIT_FOR_EVENT                0x3
80 #define OP_MI_FLUSH                         0x4
81 #define OP_MI_ARB_CHECK                     0x5
82 #define OP_MI_RS_CONTROL                    0x6  /* HSW+ */
83 #define OP_MI_REPORT_HEAD                   0x7
84 #define OP_MI_ARB_ON_OFF                    0x8
85 #define OP_MI_URB_ATOMIC_ALLOC              0x9  /* HSW+ */
86 #define OP_MI_BATCH_BUFFER_END              0xA
87 #define OP_MI_SUSPEND_FLUSH                 0xB
88 #define OP_MI_PREDICATE                     0xC  /* IVB+ */
89 #define OP_MI_TOPOLOGY_FILTER               0xD  /* IVB+ */
90 #define OP_MI_SET_APPID                     0xE  /* IVB+ */
91 #define OP_MI_RS_CONTEXT                    0xF  /* HSW+ */
92 #define OP_MI_LOAD_SCAN_LINES_INCL          0x12 /* HSW+ */
93 #define OP_MI_DISPLAY_FLIP                  0x14
94 #define OP_MI_SEMAPHORE_MBOX                0x16
95 #define OP_MI_SET_CONTEXT                   0x18
96 #define OP_MI_MATH                          0x1A
97 #define OP_MI_URB_CLEAR                     0x19
98 #define OP_MI_SEMAPHORE_SIGNAL              0x1B  /* BDW+ */
99 #define OP_MI_SEMAPHORE_WAIT                0x1C  /* BDW+ */
100
101 #define OP_MI_STORE_DATA_IMM                0x20
102 #define OP_MI_STORE_DATA_INDEX              0x21
103 #define OP_MI_LOAD_REGISTER_IMM             0x22
104 #define OP_MI_UPDATE_GTT                    0x23
105 #define OP_MI_STORE_REGISTER_MEM            0x24
106 #define OP_MI_FLUSH_DW                      0x26
107 #define OP_MI_CLFLUSH                       0x27
108 #define OP_MI_REPORT_PERF_COUNT             0x28
109 #define OP_MI_LOAD_REGISTER_MEM             0x29  /* HSW+ */
110 #define OP_MI_LOAD_REGISTER_REG             0x2A  /* HSW+ */
111 #define OP_MI_RS_STORE_DATA_IMM             0x2B  /* HSW+ */
112 #define OP_MI_LOAD_URB_MEM                  0x2C  /* HSW+ */
113 #define OP_MI_STORE_URM_MEM                 0x2D  /* HSW+ */
114 #define OP_MI_2E                            0x2E  /* BDW+ */
115 #define OP_MI_2F                            0x2F  /* BDW+ */
116 #define OP_MI_BATCH_BUFFER_START            0x31
117
118 /* Bit definition for dword 0 */
119 #define _CMDBIT_BB_START_IN_PPGTT       (1UL << 8)
120
121 #define OP_MI_CONDITIONAL_BATCH_BUFFER_END  0x36
122
123 #define BATCH_BUFFER_ADDR_MASK ((1UL << 32) - (1U << 2))
124 #define BATCH_BUFFER_ADDR_HIGH_MASK ((1UL << 16) - (1U))
125 #define BATCH_BUFFER_ADR_SPACE_BIT(x)   (((x) >> 8) & 1U)
126 #define BATCH_BUFFER_2ND_LEVEL_BIT(x)   ((x) >> 22 & 1U)
127
128 /* 2D command: Opcode (28:22) */
129 #define OP_2D(x)    ((2<<7) | x)
130
131 #define OP_XY_SETUP_BLT                             OP_2D(0x1)
132 #define OP_XY_SETUP_CLIP_BLT                        OP_2D(0x3)
133 #define OP_XY_SETUP_MONO_PATTERN_SL_BLT             OP_2D(0x11)
134 #define OP_XY_PIXEL_BLT                             OP_2D(0x24)
135 #define OP_XY_SCANLINES_BLT                         OP_2D(0x25)
136 #define OP_XY_TEXT_BLT                              OP_2D(0x26)
137 #define OP_XY_TEXT_IMMEDIATE_BLT                    OP_2D(0x31)
138 #define OP_XY_COLOR_BLT                             OP_2D(0x50)
139 #define OP_XY_PAT_BLT                               OP_2D(0x51)
140 #define OP_XY_MONO_PAT_BLT                          OP_2D(0x52)
141 #define OP_XY_SRC_COPY_BLT                          OP_2D(0x53)
142 #define OP_XY_MONO_SRC_COPY_BLT                     OP_2D(0x54)
143 #define OP_XY_FULL_BLT                              OP_2D(0x55)
144 #define OP_XY_FULL_MONO_SRC_BLT                     OP_2D(0x56)
145 #define OP_XY_FULL_MONO_PATTERN_BLT                 OP_2D(0x57)
146 #define OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT        OP_2D(0x58)
147 #define OP_XY_MONO_PAT_FIXED_BLT                    OP_2D(0x59)
148 #define OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT           OP_2D(0x71)
149 #define OP_XY_PAT_BLT_IMMEDIATE                     OP_2D(0x72)
150 #define OP_XY_SRC_COPY_CHROMA_BLT                   OP_2D(0x73)
151 #define OP_XY_FULL_IMMEDIATE_PATTERN_BLT            OP_2D(0x74)
152 #define OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT   OP_2D(0x75)
153 #define OP_XY_PAT_CHROMA_BLT                        OP_2D(0x76)
154 #define OP_XY_PAT_CHROMA_BLT_IMMEDIATE              OP_2D(0x77)
155
156 /* 3D/Media Command: Pipeline Type(28:27) Opcode(26:24) Sub Opcode(23:16) */
157 #define OP_3D_MEDIA(sub_type, opcode, sub_opcode) \
158         ((3 << 13) | ((sub_type) << 11) | ((opcode) << 8) | (sub_opcode))
159
160 #define OP_STATE_PREFETCH                       OP_3D_MEDIA(0x0, 0x0, 0x03)
161
162 #define OP_STATE_BASE_ADDRESS                   OP_3D_MEDIA(0x0, 0x1, 0x01)
163 #define OP_STATE_SIP                            OP_3D_MEDIA(0x0, 0x1, 0x02)
164 #define OP_3D_MEDIA_0_1_4                       OP_3D_MEDIA(0x0, 0x1, 0x04)
165
166 #define OP_3DSTATE_VF_STATISTICS_GM45           OP_3D_MEDIA(0x1, 0x0, 0x0B)
167
168 #define OP_PIPELINE_SELECT                      OP_3D_MEDIA(0x1, 0x1, 0x04)
169
170 #define OP_MEDIA_VFE_STATE                      OP_3D_MEDIA(0x2, 0x0, 0x0)
171 #define OP_MEDIA_CURBE_LOAD                     OP_3D_MEDIA(0x2, 0x0, 0x1)
172 #define OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD      OP_3D_MEDIA(0x2, 0x0, 0x2)
173 #define OP_MEDIA_GATEWAY_STATE                  OP_3D_MEDIA(0x2, 0x0, 0x3)
174 #define OP_MEDIA_STATE_FLUSH                    OP_3D_MEDIA(0x2, 0x0, 0x4)
175
176 #define OP_MEDIA_OBJECT                         OP_3D_MEDIA(0x2, 0x1, 0x0)
177 #define OP_MEDIA_OBJECT_PRT                     OP_3D_MEDIA(0x2, 0x1, 0x2)
178 #define OP_MEDIA_OBJECT_WALKER                  OP_3D_MEDIA(0x2, 0x1, 0x3)
179 #define OP_GPGPU_WALKER                         OP_3D_MEDIA(0x2, 0x1, 0x5)
180
181 #define OP_3DSTATE_CLEAR_PARAMS                 OP_3D_MEDIA(0x3, 0x0, 0x04) /* IVB+ */
182 #define OP_3DSTATE_DEPTH_BUFFER                 OP_3D_MEDIA(0x3, 0x0, 0x05) /* IVB+ */
183 #define OP_3DSTATE_STENCIL_BUFFER               OP_3D_MEDIA(0x3, 0x0, 0x06) /* IVB+ */
184 #define OP_3DSTATE_HIER_DEPTH_BUFFER            OP_3D_MEDIA(0x3, 0x0, 0x07) /* IVB+ */
185 #define OP_3DSTATE_VERTEX_BUFFERS               OP_3D_MEDIA(0x3, 0x0, 0x08)
186 #define OP_3DSTATE_VERTEX_ELEMENTS              OP_3D_MEDIA(0x3, 0x0, 0x09)
187 #define OP_3DSTATE_INDEX_BUFFER                 OP_3D_MEDIA(0x3, 0x0, 0x0A)
188 #define OP_3DSTATE_VF_STATISTICS                OP_3D_MEDIA(0x3, 0x0, 0x0B)
189 #define OP_3DSTATE_VF                           OP_3D_MEDIA(0x3, 0x0, 0x0C)  /* HSW+ */
190 #define OP_3DSTATE_CC_STATE_POINTERS            OP_3D_MEDIA(0x3, 0x0, 0x0E)
191 #define OP_3DSTATE_SCISSOR_STATE_POINTERS       OP_3D_MEDIA(0x3, 0x0, 0x0F)
192 #define OP_3DSTATE_VS                           OP_3D_MEDIA(0x3, 0x0, 0x10)
193 #define OP_3DSTATE_GS                           OP_3D_MEDIA(0x3, 0x0, 0x11)
194 #define OP_3DSTATE_CLIP                         OP_3D_MEDIA(0x3, 0x0, 0x12)
195 #define OP_3DSTATE_SF                           OP_3D_MEDIA(0x3, 0x0, 0x13)
196 #define OP_3DSTATE_WM                           OP_3D_MEDIA(0x3, 0x0, 0x14)
197 #define OP_3DSTATE_CONSTANT_VS                  OP_3D_MEDIA(0x3, 0x0, 0x15)
198 #define OP_3DSTATE_CONSTANT_GS                  OP_3D_MEDIA(0x3, 0x0, 0x16)
199 #define OP_3DSTATE_CONSTANT_PS                  OP_3D_MEDIA(0x3, 0x0, 0x17)
200 #define OP_3DSTATE_SAMPLE_MASK                  OP_3D_MEDIA(0x3, 0x0, 0x18)
201 #define OP_3DSTATE_CONSTANT_HS                  OP_3D_MEDIA(0x3, 0x0, 0x19) /* IVB+ */
202 #define OP_3DSTATE_CONSTANT_DS                  OP_3D_MEDIA(0x3, 0x0, 0x1A) /* IVB+ */
203 #define OP_3DSTATE_HS                           OP_3D_MEDIA(0x3, 0x0, 0x1B) /* IVB+ */
204 #define OP_3DSTATE_TE                           OP_3D_MEDIA(0x3, 0x0, 0x1C) /* IVB+ */
205 #define OP_3DSTATE_DS                           OP_3D_MEDIA(0x3, 0x0, 0x1D) /* IVB+ */
206 #define OP_3DSTATE_STREAMOUT                    OP_3D_MEDIA(0x3, 0x0, 0x1E) /* IVB+ */
207 #define OP_3DSTATE_SBE                          OP_3D_MEDIA(0x3, 0x0, 0x1F) /* IVB+ */
208 #define OP_3DSTATE_PS                           OP_3D_MEDIA(0x3, 0x0, 0x20) /* IVB+ */
209 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP OP_3D_MEDIA(0x3, 0x0, 0x21) /* IVB+ */
210 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC   OP_3D_MEDIA(0x3, 0x0, 0x23) /* IVB+ */
211 #define OP_3DSTATE_BLEND_STATE_POINTERS         OP_3D_MEDIA(0x3, 0x0, 0x24) /* IVB+ */
212 #define OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x25) /* IVB+ */
213 #define OP_3DSTATE_BINDING_TABLE_POINTERS_VS    OP_3D_MEDIA(0x3, 0x0, 0x26) /* IVB+ */
214 #define OP_3DSTATE_BINDING_TABLE_POINTERS_HS    OP_3D_MEDIA(0x3, 0x0, 0x27) /* IVB+ */
215 #define OP_3DSTATE_BINDING_TABLE_POINTERS_DS    OP_3D_MEDIA(0x3, 0x0, 0x28) /* IVB+ */
216 #define OP_3DSTATE_BINDING_TABLE_POINTERS_GS    OP_3D_MEDIA(0x3, 0x0, 0x29) /* IVB+ */
217 #define OP_3DSTATE_BINDING_TABLE_POINTERS_PS    OP_3D_MEDIA(0x3, 0x0, 0x2A) /* IVB+ */
218 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_VS    OP_3D_MEDIA(0x3, 0x0, 0x2B) /* IVB+ */
219 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_HS    OP_3D_MEDIA(0x3, 0x0, 0x2C) /* IVB+ */
220 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_DS    OP_3D_MEDIA(0x3, 0x0, 0x2D) /* IVB+ */
221 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_GS    OP_3D_MEDIA(0x3, 0x0, 0x2E) /* IVB+ */
222 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_PS    OP_3D_MEDIA(0x3, 0x0, 0x2F) /* IVB+ */
223 #define OP_3DSTATE_URB_VS                       OP_3D_MEDIA(0x3, 0x0, 0x30) /* IVB+ */
224 #define OP_3DSTATE_URB_HS                       OP_3D_MEDIA(0x3, 0x0, 0x31) /* IVB+ */
225 #define OP_3DSTATE_URB_DS                       OP_3D_MEDIA(0x3, 0x0, 0x32) /* IVB+ */
226 #define OP_3DSTATE_URB_GS                       OP_3D_MEDIA(0x3, 0x0, 0x33) /* IVB+ */
227 #define OP_3DSTATE_GATHER_CONSTANT_VS           OP_3D_MEDIA(0x3, 0x0, 0x34) /* HSW+ */
228 #define OP_3DSTATE_GATHER_CONSTANT_GS           OP_3D_MEDIA(0x3, 0x0, 0x35) /* HSW+ */
229 #define OP_3DSTATE_GATHER_CONSTANT_HS           OP_3D_MEDIA(0x3, 0x0, 0x36) /* HSW+ */
230 #define OP_3DSTATE_GATHER_CONSTANT_DS           OP_3D_MEDIA(0x3, 0x0, 0x37) /* HSW+ */
231 #define OP_3DSTATE_GATHER_CONSTANT_PS           OP_3D_MEDIA(0x3, 0x0, 0x38) /* HSW+ */
232 #define OP_3DSTATE_DX9_CONSTANTF_VS             OP_3D_MEDIA(0x3, 0x0, 0x39) /* HSW+ */
233 #define OP_3DSTATE_DX9_CONSTANTF_PS             OP_3D_MEDIA(0x3, 0x0, 0x3A) /* HSW+ */
234 #define OP_3DSTATE_DX9_CONSTANTI_VS             OP_3D_MEDIA(0x3, 0x0, 0x3B) /* HSW+ */
235 #define OP_3DSTATE_DX9_CONSTANTI_PS             OP_3D_MEDIA(0x3, 0x0, 0x3C) /* HSW+ */
236 #define OP_3DSTATE_DX9_CONSTANTB_VS             OP_3D_MEDIA(0x3, 0x0, 0x3D) /* HSW+ */
237 #define OP_3DSTATE_DX9_CONSTANTB_PS             OP_3D_MEDIA(0x3, 0x0, 0x3E) /* HSW+ */
238 #define OP_3DSTATE_DX9_LOCAL_VALID_VS           OP_3D_MEDIA(0x3, 0x0, 0x3F) /* HSW+ */
239 #define OP_3DSTATE_DX9_LOCAL_VALID_PS           OP_3D_MEDIA(0x3, 0x0, 0x40) /* HSW+ */
240 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_VS       OP_3D_MEDIA(0x3, 0x0, 0x41) /* HSW+ */
241 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_PS       OP_3D_MEDIA(0x3, 0x0, 0x42) /* HSW+ */
242 #define OP_3DSTATE_BINDING_TABLE_EDIT_VS        OP_3D_MEDIA(0x3, 0x0, 0x43) /* HSW+ */
243 #define OP_3DSTATE_BINDING_TABLE_EDIT_GS        OP_3D_MEDIA(0x3, 0x0, 0x44) /* HSW+ */
244 #define OP_3DSTATE_BINDING_TABLE_EDIT_HS        OP_3D_MEDIA(0x3, 0x0, 0x45) /* HSW+ */
245 #define OP_3DSTATE_BINDING_TABLE_EDIT_DS        OP_3D_MEDIA(0x3, 0x0, 0x46) /* HSW+ */
246 #define OP_3DSTATE_BINDING_TABLE_EDIT_PS        OP_3D_MEDIA(0x3, 0x0, 0x47) /* HSW+ */
247
248 #define OP_3DSTATE_VF_INSTANCING                OP_3D_MEDIA(0x3, 0x0, 0x49) /* BDW+ */
249 #define OP_3DSTATE_VF_SGVS                      OP_3D_MEDIA(0x3, 0x0, 0x4A) /* BDW+ */
250 #define OP_3DSTATE_VF_TOPOLOGY                  OP_3D_MEDIA(0x3, 0x0, 0x4B) /* BDW+ */
251 #define OP_3DSTATE_WM_CHROMAKEY                 OP_3D_MEDIA(0x3, 0x0, 0x4C) /* BDW+ */
252 #define OP_3DSTATE_PS_BLEND                     OP_3D_MEDIA(0x3, 0x0, 0x4D) /* BDW+ */
253 #define OP_3DSTATE_WM_DEPTH_STENCIL             OP_3D_MEDIA(0x3, 0x0, 0x4E) /* BDW+ */
254 #define OP_3DSTATE_PS_EXTRA                     OP_3D_MEDIA(0x3, 0x0, 0x4F) /* BDW+ */
255 #define OP_3DSTATE_RASTER                       OP_3D_MEDIA(0x3, 0x0, 0x50) /* BDW+ */
256 #define OP_3DSTATE_SBE_SWIZ                     OP_3D_MEDIA(0x3, 0x0, 0x51) /* BDW+ */
257 #define OP_3DSTATE_WM_HZ_OP                     OP_3D_MEDIA(0x3, 0x0, 0x52) /* BDW+ */
258 #define OP_3DSTATE_COMPONENT_PACKING            OP_3D_MEDIA(0x3, 0x0, 0x55) /* SKL+ */
259
260 #define OP_3DSTATE_DRAWING_RECTANGLE            OP_3D_MEDIA(0x3, 0x1, 0x00)
261 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD0        OP_3D_MEDIA(0x3, 0x1, 0x02)
262 #define OP_3DSTATE_CHROMA_KEY                   OP_3D_MEDIA(0x3, 0x1, 0x04)
263 #define OP_SNB_3DSTATE_DEPTH_BUFFER             OP_3D_MEDIA(0x3, 0x1, 0x05)
264 #define OP_3DSTATE_POLY_STIPPLE_OFFSET          OP_3D_MEDIA(0x3, 0x1, 0x06)
265 #define OP_3DSTATE_POLY_STIPPLE_PATTERN         OP_3D_MEDIA(0x3, 0x1, 0x07)
266 #define OP_3DSTATE_LINE_STIPPLE                 OP_3D_MEDIA(0x3, 0x1, 0x08)
267 #define OP_3DSTATE_AA_LINE_PARAMS               OP_3D_MEDIA(0x3, 0x1, 0x0A)
268 #define OP_3DSTATE_GS_SVB_INDEX                 OP_3D_MEDIA(0x3, 0x1, 0x0B)
269 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD1        OP_3D_MEDIA(0x3, 0x1, 0x0C)
270 #define OP_3DSTATE_MULTISAMPLE_BDW              OP_3D_MEDIA(0x3, 0x0, 0x0D)
271 #define OP_SNB_3DSTATE_STENCIL_BUFFER           OP_3D_MEDIA(0x3, 0x1, 0x0E)
272 #define OP_SNB_3DSTATE_HIER_DEPTH_BUFFER        OP_3D_MEDIA(0x3, 0x1, 0x0F)
273 #define OP_SNB_3DSTATE_CLEAR_PARAMS             OP_3D_MEDIA(0x3, 0x1, 0x10)
274 #define OP_3DSTATE_MONOFILTER_SIZE              OP_3D_MEDIA(0x3, 0x1, 0x11)
275 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS       OP_3D_MEDIA(0x3, 0x1, 0x12) /* IVB+ */
276 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS       OP_3D_MEDIA(0x3, 0x1, 0x13) /* IVB+ */
277 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS       OP_3D_MEDIA(0x3, 0x1, 0x14) /* IVB+ */
278 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS       OP_3D_MEDIA(0x3, 0x1, 0x15) /* IVB+ */
279 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS       OP_3D_MEDIA(0x3, 0x1, 0x16) /* IVB+ */
280 #define OP_3DSTATE_SO_DECL_LIST                 OP_3D_MEDIA(0x3, 0x1, 0x17)
281 #define OP_3DSTATE_SO_BUFFER                    OP_3D_MEDIA(0x3, 0x1, 0x18)
282 #define OP_3DSTATE_BINDING_TABLE_POOL_ALLOC     OP_3D_MEDIA(0x3, 0x1, 0x19) /* HSW+ */
283 #define OP_3DSTATE_GATHER_POOL_ALLOC            OP_3D_MEDIA(0x3, 0x1, 0x1A) /* HSW+ */
284 #define OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1B) /* HSW+ */
285 #define OP_3DSTATE_SAMPLE_PATTERN               OP_3D_MEDIA(0x3, 0x1, 0x1C)
286 #define OP_PIPE_CONTROL                         OP_3D_MEDIA(0x3, 0x2, 0x00)
287 #define OP_3DPRIMITIVE                          OP_3D_MEDIA(0x3, 0x3, 0x00)
288
289 /* VCCP Command Parser */
290
291 /*
292  * Below MFX and VBE cmd definition is from vaapi intel driver project (BSD License)
293  * git://anongit.freedesktop.org/vaapi/intel-driver
294  * src/i965_defines.h
295  *
296  */
297
298 #define OP_MFX(pipeline, op, sub_opa, sub_opb)     \
299         (3 << 13 | \
300          (pipeline) << 11 | \
301          (op) << 8 | \
302          (sub_opa) << 5 | \
303          (sub_opb))
304
305 #define OP_MFX_PIPE_MODE_SELECT                    OP_MFX(2, 0, 0, 0)  /* ALL */
306 #define OP_MFX_SURFACE_STATE                       OP_MFX(2, 0, 0, 1)  /* ALL */
307 #define OP_MFX_PIPE_BUF_ADDR_STATE                 OP_MFX(2, 0, 0, 2)  /* ALL */
308 #define OP_MFX_IND_OBJ_BASE_ADDR_STATE             OP_MFX(2, 0, 0, 3)  /* ALL */
309 #define OP_MFX_BSP_BUF_BASE_ADDR_STATE             OP_MFX(2, 0, 0, 4)  /* ALL */
310 #define OP_2_0_0_5                                 OP_MFX(2, 0, 0, 5)  /* ALL */
311 #define OP_MFX_STATE_POINTER                       OP_MFX(2, 0, 0, 6)  /* ALL */
312 #define OP_MFX_QM_STATE                            OP_MFX(2, 0, 0, 7)  /* IVB+ */
313 #define OP_MFX_FQM_STATE                           OP_MFX(2, 0, 0, 8)  /* IVB+ */
314 #define OP_MFX_PAK_INSERT_OBJECT                   OP_MFX(2, 0, 2, 8)  /* IVB+ */
315 #define OP_MFX_STITCH_OBJECT                       OP_MFX(2, 0, 2, 0xA)  /* IVB+ */
316
317 #define OP_MFD_IT_OBJECT                           OP_MFX(2, 0, 1, 9) /* ALL */
318
319 #define OP_MFX_WAIT                                OP_MFX(1, 0, 0, 0) /* IVB+ */
320 #define OP_MFX_AVC_IMG_STATE                       OP_MFX(2, 1, 0, 0) /* ALL */
321 #define OP_MFX_AVC_QM_STATE                        OP_MFX(2, 1, 0, 1) /* ALL */
322 #define OP_MFX_AVC_DIRECTMODE_STATE                OP_MFX(2, 1, 0, 2) /* ALL */
323 #define OP_MFX_AVC_SLICE_STATE                     OP_MFX(2, 1, 0, 3) /* ALL */
324 #define OP_MFX_AVC_REF_IDX_STATE                   OP_MFX(2, 1, 0, 4) /* ALL */
325 #define OP_MFX_AVC_WEIGHTOFFSET_STATE              OP_MFX(2, 1, 0, 5) /* ALL */
326 #define OP_MFD_AVC_PICID_STATE                     OP_MFX(2, 1, 1, 5) /* HSW+ */
327 #define OP_MFD_AVC_DPB_STATE                       OP_MFX(2, 1, 1, 6) /* IVB+ */
328 #define OP_MFD_AVC_SLICEADDR                       OP_MFX(2, 1, 1, 7) /* IVB+ */
329 #define OP_MFD_AVC_BSD_OBJECT                      OP_MFX(2, 1, 1, 8) /* ALL */
330 #define OP_MFC_AVC_PAK_OBJECT                      OP_MFX(2, 1, 2, 9) /* ALL */
331
332 #define OP_MFX_VC1_PRED_PIPE_STATE                 OP_MFX(2, 2, 0, 1) /* ALL */
333 #define OP_MFX_VC1_DIRECTMODE_STATE                OP_MFX(2, 2, 0, 2) /* ALL */
334 #define OP_MFD_VC1_SHORT_PIC_STATE                 OP_MFX(2, 2, 1, 0) /* IVB+ */
335 #define OP_MFD_VC1_LONG_PIC_STATE                  OP_MFX(2, 2, 1, 1) /* IVB+ */
336 #define OP_MFD_VC1_BSD_OBJECT                      OP_MFX(2, 2, 1, 8) /* ALL */
337
338 #define OP_MFX_MPEG2_PIC_STATE                     OP_MFX(2, 3, 0, 0) /* ALL */
339 #define OP_MFX_MPEG2_QM_STATE                      OP_MFX(2, 3, 0, 1) /* ALL */
340 #define OP_MFD_MPEG2_BSD_OBJECT                    OP_MFX(2, 3, 1, 8) /* ALL */
341 #define OP_MFC_MPEG2_SLICEGROUP_STATE              OP_MFX(2, 3, 2, 3) /* ALL */
342 #define OP_MFC_MPEG2_PAK_OBJECT                    OP_MFX(2, 3, 2, 9) /* ALL */
343
344 #define OP_MFX_2_6_0_0                             OP_MFX(2, 6, 0, 0) /* IVB+ */
345 #define OP_MFX_2_6_0_8                             OP_MFX(2, 6, 0, 8) /* IVB+ */
346 #define OP_MFX_2_6_0_9                             OP_MFX(2, 6, 0, 9) /* IVB+ */
347
348 #define OP_MFX_JPEG_PIC_STATE                      OP_MFX(2, 7, 0, 0)
349 #define OP_MFX_JPEG_HUFF_TABLE_STATE               OP_MFX(2, 7, 0, 2)
350 #define OP_MFD_JPEG_BSD_OBJECT                     OP_MFX(2, 7, 1, 8)
351
352 #define OP_VEB(pipeline, op, sub_opa, sub_opb) \
353         (3 << 13 | \
354          (pipeline) << 11 | \
355          (op) << 8 | \
356          (sub_opa) << 5 | \
357          (sub_opb))
358
359 #define OP_VEB_SURFACE_STATE                       OP_VEB(2, 4, 0, 0)
360 #define OP_VEB_STATE                               OP_VEB(2, 4, 0, 2)
361 #define OP_VEB_DNDI_IECP_STATE                     OP_VEB(2, 4, 0, 3)
362
363 struct parser_exec_state;
364
365 typedef int (*parser_cmd_handler)(struct parser_exec_state *s);
366
367 #define GVT_CMD_HASH_BITS   7
368
369 /* which DWords need address fix */
370 #define ADDR_FIX_1(x1)                  (1 << (x1))
371 #define ADDR_FIX_2(x1, x2)              (ADDR_FIX_1(x1) | ADDR_FIX_1(x2))
372 #define ADDR_FIX_3(x1, x2, x3)          (ADDR_FIX_1(x1) | ADDR_FIX_2(x2, x3))
373 #define ADDR_FIX_4(x1, x2, x3, x4)      (ADDR_FIX_1(x1) | ADDR_FIX_3(x2, x3, x4))
374 #define ADDR_FIX_5(x1, x2, x3, x4, x5)  (ADDR_FIX_1(x1) | ADDR_FIX_4(x2, x3, x4, x5))
375
376 struct cmd_info {
377         char *name;
378         u32 opcode;
379
380 #define F_LEN_MASK      (1U<<0)
381 #define F_LEN_CONST  1U
382 #define F_LEN_VAR    0U
383
384 /*
385  * command has its own ip advance logic
386  * e.g. MI_BATCH_START, MI_BATCH_END
387  */
388 #define F_IP_ADVANCE_CUSTOM (1<<1)
389
390 #define F_POST_HANDLE   (1<<2)
391         u32 flag;
392
393 #define R_RCS   (1 << RCS)
394 #define R_VCS1  (1 << VCS)
395 #define R_VCS2  (1 << VCS2)
396 #define R_VCS   (R_VCS1 | R_VCS2)
397 #define R_BCS   (1 << BCS)
398 #define R_VECS  (1 << VECS)
399 #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
400         /* rings that support this cmd: BLT/RCS/VCS/VECS */
401         uint16_t rings;
402
403         /* devices that support this cmd: SNB/IVB/HSW/... */
404         uint16_t devices;
405
406         /* which DWords are address that need fix up.
407          * bit 0 means a 32-bit non address operand in command
408          * bit 1 means address operand, which could be 32-bit
409          * or 64-bit depending on different architectures.(
410          * defined by "gmadr_bytes_in_cmd" in intel_gvt.
411          * No matter the address length, each address only takes
412          * one bit in the bitmap.
413          */
414         uint16_t addr_bitmap;
415
416         /* flag == F_LEN_CONST : command length
417          * flag == F_LEN_VAR : length bias bits
418          * Note: length is in DWord
419          */
420         uint8_t len;
421
422         parser_cmd_handler handler;
423 };
424
425 struct cmd_entry {
426         struct hlist_node hlist;
427         struct cmd_info *info;
428 };
429
430 enum {
431         RING_BUFFER_INSTRUCTION,
432         BATCH_BUFFER_INSTRUCTION,
433         BATCH_BUFFER_2ND_LEVEL,
434 };
435
436 enum {
437         GTT_BUFFER,
438         PPGTT_BUFFER
439 };
440
441 struct parser_exec_state {
442         struct intel_vgpu *vgpu;
443         int ring_id;
444
445         int buf_type;
446
447         /* batch buffer address type */
448         int buf_addr_type;
449
450         /* graphics memory address of ring buffer start */
451         unsigned long ring_start;
452         unsigned long ring_size;
453         unsigned long ring_head;
454         unsigned long ring_tail;
455
456         /* instruction graphics memory address */
457         unsigned long ip_gma;
458
459         /* mapped va of the instr_gma */
460         void *ip_va;
461         void *rb_va;
462
463         void *ret_bb_va;
464         /* next instruction when return from  batch buffer to ring buffer */
465         unsigned long ret_ip_gma_ring;
466
467         /* next instruction when return from 2nd batch buffer to batch buffer */
468         unsigned long ret_ip_gma_bb;
469
470         /* batch buffer address type (GTT or PPGTT)
471          * used when ret from 2nd level batch buffer
472          */
473         int saved_buf_addr_type;
474         bool is_ctx_wa;
475
476         struct cmd_info *info;
477
478         struct intel_vgpu_workload *workload;
479 };
480
481 #define gmadr_dw_number(s)      \
482         (s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2)
483
484 static unsigned long bypass_scan_mask = 0;
485
486 /* ring ALL, type = 0 */
487 static struct sub_op_bits sub_op_mi[] = {
488         {31, 29},
489         {28, 23},
490 };
491
492 static struct decode_info decode_info_mi = {
493         "MI",
494         OP_LEN_MI,
495         ARRAY_SIZE(sub_op_mi),
496         sub_op_mi,
497 };
498
499 /* ring RCS, command type 2 */
500 static struct sub_op_bits sub_op_2d[] = {
501         {31, 29},
502         {28, 22},
503 };
504
505 static struct decode_info decode_info_2d = {
506         "2D",
507         OP_LEN_2D,
508         ARRAY_SIZE(sub_op_2d),
509         sub_op_2d,
510 };
511
512 /* ring RCS, command type 3 */
513 static struct sub_op_bits sub_op_3d_media[] = {
514         {31, 29},
515         {28, 27},
516         {26, 24},
517         {23, 16},
518 };
519
520 static struct decode_info decode_info_3d_media = {
521         "3D_Media",
522         OP_LEN_3D_MEDIA,
523         ARRAY_SIZE(sub_op_3d_media),
524         sub_op_3d_media,
525 };
526
527 /* ring VCS, command type 3 */
528 static struct sub_op_bits sub_op_mfx_vc[] = {
529         {31, 29},
530         {28, 27},
531         {26, 24},
532         {23, 21},
533         {20, 16},
534 };
535
536 static struct decode_info decode_info_mfx_vc = {
537         "MFX_VC",
538         OP_LEN_MFX_VC,
539         ARRAY_SIZE(sub_op_mfx_vc),
540         sub_op_mfx_vc,
541 };
542
543 /* ring VECS, command type 3 */
544 static struct sub_op_bits sub_op_vebox[] = {
545         {31, 29},
546         {28, 27},
547         {26, 24},
548         {23, 21},
549         {20, 16},
550 };
551
552 static struct decode_info decode_info_vebox = {
553         "VEBOX",
554         OP_LEN_VEBOX,
555         ARRAY_SIZE(sub_op_vebox),
556         sub_op_vebox,
557 };
558
559 static struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
560         [RCS] = {
561                 &decode_info_mi,
562                 NULL,
563                 NULL,
564                 &decode_info_3d_media,
565                 NULL,
566                 NULL,
567                 NULL,
568                 NULL,
569         },
570
571         [VCS] = {
572                 &decode_info_mi,
573                 NULL,
574                 NULL,
575                 &decode_info_mfx_vc,
576                 NULL,
577                 NULL,
578                 NULL,
579                 NULL,
580         },
581
582         [BCS] = {
583                 &decode_info_mi,
584                 NULL,
585                 &decode_info_2d,
586                 NULL,
587                 NULL,
588                 NULL,
589                 NULL,
590                 NULL,
591         },
592
593         [VECS] = {
594                 &decode_info_mi,
595                 NULL,
596                 NULL,
597                 &decode_info_vebox,
598                 NULL,
599                 NULL,
600                 NULL,
601                 NULL,
602         },
603
604         [VCS2] = {
605                 &decode_info_mi,
606                 NULL,
607                 NULL,
608                 &decode_info_mfx_vc,
609                 NULL,
610                 NULL,
611                 NULL,
612                 NULL,
613         },
614 };
615
616 static inline u32 get_opcode(u32 cmd, int ring_id)
617 {
618         struct decode_info *d_info;
619
620         d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)];
621         if (d_info == NULL)
622                 return INVALID_OP;
623
624         return cmd >> (32 - d_info->op_len);
625 }
626
627 static inline struct cmd_info *find_cmd_entry(struct intel_gvt *gvt,
628                 unsigned int opcode, int ring_id)
629 {
630         struct cmd_entry *e;
631
632         hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) {
633                 if ((opcode == e->info->opcode) &&
634                                 (e->info->rings & (1 << ring_id)))
635                         return e->info;
636         }
637         return NULL;
638 }
639
640 static inline struct cmd_info *get_cmd_info(struct intel_gvt *gvt,
641                 u32 cmd, int ring_id)
642 {
643         u32 opcode;
644
645         opcode = get_opcode(cmd, ring_id);
646         if (opcode == INVALID_OP)
647                 return NULL;
648
649         return find_cmd_entry(gvt, opcode, ring_id);
650 }
651
652 static inline u32 sub_op_val(u32 cmd, u32 hi, u32 low)
653 {
654         return (cmd >> low) & ((1U << (hi - low + 1)) - 1);
655 }
656
657 static inline void print_opcode(u32 cmd, int ring_id)
658 {
659         struct decode_info *d_info;
660         int i;
661
662         d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)];
663         if (d_info == NULL)
664                 return;
665
666         gvt_dbg_cmd("opcode=0x%x %s sub_ops:",
667                         cmd >> (32 - d_info->op_len), d_info->name);
668
669         for (i = 0; i < d_info->nr_sub_op; i++)
670                 pr_err("0x%x ", sub_op_val(cmd, d_info->sub_op[i].hi,
671                                         d_info->sub_op[i].low));
672
673         pr_err("\n");
674 }
675
676 static inline u32 *cmd_ptr(struct parser_exec_state *s, int index)
677 {
678         return s->ip_va + (index << 2);
679 }
680
681 static inline u32 cmd_val(struct parser_exec_state *s, int index)
682 {
683         return *cmd_ptr(s, index);
684 }
685
686 static void parser_exec_state_dump(struct parser_exec_state *s)
687 {
688         int cnt = 0;
689         int i;
690
691         gvt_dbg_cmd("  vgpu%d RING%d: ring_start(%08lx) ring_end(%08lx)"
692                         " ring_head(%08lx) ring_tail(%08lx)\n", s->vgpu->id,
693                         s->ring_id, s->ring_start, s->ring_start + s->ring_size,
694                         s->ring_head, s->ring_tail);
695
696         gvt_dbg_cmd("  %s %s ip_gma(%08lx) ",
697                         s->buf_type == RING_BUFFER_INSTRUCTION ?
698                         "RING_BUFFER" : "BATCH_BUFFER",
699                         s->buf_addr_type == GTT_BUFFER ?
700                         "GTT" : "PPGTT", s->ip_gma);
701
702         if (s->ip_va == NULL) {
703                 gvt_dbg_cmd(" ip_va(NULL)");
704                 return;
705         }
706
707         gvt_dbg_cmd("  ip_va=%p: %08x %08x %08x %08x\n",
708                         s->ip_va, cmd_val(s, 0), cmd_val(s, 1),
709                         cmd_val(s, 2), cmd_val(s, 3));
710
711         print_opcode(cmd_val(s, 0), s->ring_id);
712
713         s->ip_va = (u32 *)((((u64)s->ip_va) >> 12) << 12);
714
715         while (cnt < 1024) {
716                 gvt_dbg_cmd("ip_va=%p: ", s->ip_va);
717                 for (i = 0; i < 8; i++)
718                         gvt_dbg_cmd("%08x ", cmd_val(s, i));
719                 gvt_dbg_cmd("\n");
720
721                 s->ip_va += 8 * sizeof(u32);
722                 cnt += 8;
723         }
724 }
725
726 static inline void update_ip_va(struct parser_exec_state *s)
727 {
728         unsigned long len = 0;
729
730         if (WARN_ON(s->ring_head == s->ring_tail))
731                 return;
732
733         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
734                 unsigned long ring_top = s->ring_start + s->ring_size;
735
736                 if (s->ring_head > s->ring_tail) {
737                         if (s->ip_gma >= s->ring_head && s->ip_gma < ring_top)
738                                 len = (s->ip_gma - s->ring_head);
739                         else if (s->ip_gma >= s->ring_start &&
740                                         s->ip_gma <= s->ring_tail)
741                                 len = (ring_top - s->ring_head) +
742                                         (s->ip_gma - s->ring_start);
743                 } else
744                         len = (s->ip_gma - s->ring_head);
745
746                 s->ip_va = s->rb_va + len;
747         } else {/* shadow batch buffer */
748                 s->ip_va = s->ret_bb_va;
749         }
750 }
751
752 static inline int ip_gma_set(struct parser_exec_state *s,
753                 unsigned long ip_gma)
754 {
755         WARN_ON(!IS_ALIGNED(ip_gma, 4));
756
757         s->ip_gma = ip_gma;
758         update_ip_va(s);
759         return 0;
760 }
761
762 static inline int ip_gma_advance(struct parser_exec_state *s,
763                 unsigned int dw_len)
764 {
765         s->ip_gma += (dw_len << 2);
766
767         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
768                 if (s->ip_gma >= s->ring_start + s->ring_size)
769                         s->ip_gma -= s->ring_size;
770                 update_ip_va(s);
771         } else {
772                 s->ip_va += (dw_len << 2);
773         }
774
775         return 0;
776 }
777
778 static inline int get_cmd_length(struct cmd_info *info, u32 cmd)
779 {
780         if ((info->flag & F_LEN_MASK) == F_LEN_CONST)
781                 return info->len;
782         else
783                 return (cmd & ((1U << info->len) - 1)) + 2;
784         return 0;
785 }
786
787 static inline int cmd_length(struct parser_exec_state *s)
788 {
789         return get_cmd_length(s->info, cmd_val(s, 0));
790 }
791
792 /* do not remove this, some platform may need clflush here */
793 #define patch_value(s, addr, val) do { \
794         *addr = val; \
795 } while (0)
796
797 static bool is_shadowed_mmio(unsigned int offset)
798 {
799         bool ret = false;
800
801         if ((offset == 0x2168) || /*BB current head register UDW */
802             (offset == 0x2140) || /*BB current header register */
803             (offset == 0x211c) || /*second BB header register UDW */
804             (offset == 0x2114)) { /*second BB header register UDW */
805                 ret = true;
806         }
807         return ret;
808 }
809
810 static inline bool is_force_nonpriv_mmio(unsigned int offset)
811 {
812         return (offset >= 0x24d0 && offset < 0x2500);
813 }
814
815 static int force_nonpriv_reg_handler(struct parser_exec_state *s,
816                 unsigned int offset, unsigned int index, char *cmd)
817 {
818         struct intel_gvt *gvt = s->vgpu->gvt;
819         unsigned int data;
820         u32 ring_base;
821         u32 nopid;
822         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
823
824         if (!strcmp(cmd, "lri"))
825                 data = cmd_val(s, index + 1);
826         else {
827                 gvt_err("Unexpected forcenonpriv 0x%x write from cmd %s\n",
828                         offset, cmd);
829                 return -EINVAL;
830         }
831
832         ring_base = dev_priv->engine[s->ring_id]->mmio_base;
833         nopid = i915_mmio_reg_offset(RING_NOPID(ring_base));
834
835         if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data) &&
836                         data != nopid) {
837                 gvt_err("Unexpected forcenonpriv 0x%x LRI write, value=0x%x\n",
838                         offset, data);
839                 patch_value(s, cmd_ptr(s, index), nopid);
840                 return 0;
841         }
842         return 0;
843 }
844
845 static inline bool is_mocs_mmio(unsigned int offset)
846 {
847         return ((offset >= 0xc800) && (offset <= 0xcff8)) ||
848                 ((offset >= 0xb020) && (offset <= 0xb0a0));
849 }
850
851 static int mocs_cmd_reg_handler(struct parser_exec_state *s,
852                                 unsigned int offset, unsigned int index)
853 {
854         if (!is_mocs_mmio(offset))
855                 return -EINVAL;
856         vgpu_vreg(s->vgpu, offset) = cmd_val(s, index + 1);
857         return 0;
858 }
859
860 static int cmd_reg_handler(struct parser_exec_state *s,
861         unsigned int offset, unsigned int index, char *cmd)
862 {
863         struct intel_vgpu *vgpu = s->vgpu;
864         struct intel_gvt *gvt = vgpu->gvt;
865
866         if (offset + 4 > gvt->device_info.mmio_size) {
867                 gvt_vgpu_err("%s access to (%x) outside of MMIO range\n",
868                                 cmd, offset);
869                 return -EFAULT;
870         }
871
872         if (!intel_gvt_mmio_is_cmd_access(gvt, offset)) {
873                 gvt_vgpu_err("%s access to non-render register (%x)\n",
874                                 cmd, offset);
875                 return 0;
876         }
877
878         if (is_shadowed_mmio(offset)) {
879                 gvt_vgpu_err("found access of shadowed MMIO %x\n", offset);
880                 return 0;
881         }
882
883         if (is_mocs_mmio(offset) &&
884             mocs_cmd_reg_handler(s, offset, index))
885                 return -EINVAL;
886
887         if (is_force_nonpriv_mmio(offset) &&
888                 force_nonpriv_reg_handler(s, offset, index, cmd))
889                 return -EPERM;
890
891         if (offset == i915_mmio_reg_offset(DERRMR) ||
892                 offset == i915_mmio_reg_offset(FORCEWAKE_MT)) {
893                 /* Writing to HW VGT_PVINFO_PAGE offset will be discarded */
894                 patch_value(s, cmd_ptr(s, index), VGT_PVINFO_PAGE);
895         }
896
897         /* TODO: Update the global mask if this MMIO is a masked-MMIO */
898         intel_gvt_mmio_set_cmd_accessed(gvt, offset);
899         return 0;
900 }
901
902 #define cmd_reg(s, i) \
903         (cmd_val(s, i) & GENMASK(22, 2))
904
905 #define cmd_reg_inhibit(s, i) \
906         (cmd_val(s, i) & GENMASK(22, 18))
907
908 #define cmd_gma(s, i) \
909         (cmd_val(s, i) & GENMASK(31, 2))
910
911 #define cmd_gma_hi(s, i) \
912         (cmd_val(s, i) & GENMASK(15, 0))
913
914 static int cmd_handler_lri(struct parser_exec_state *s)
915 {
916         int i, ret = 0;
917         int cmd_len = cmd_length(s);
918         struct intel_gvt *gvt = s->vgpu->gvt;
919
920         for (i = 1; i < cmd_len; i += 2) {
921                 if (IS_BROADWELL(gvt->dev_priv) &&
922                                 (s->ring_id != RCS)) {
923                         if (s->ring_id == BCS &&
924                                         cmd_reg(s, i) ==
925                                         i915_mmio_reg_offset(DERRMR))
926                                 ret |= 0;
927                         else
928                                 ret |= (cmd_reg_inhibit(s, i)) ?
929                                         -EBADRQC : 0;
930                 }
931                 if (ret)
932                         break;
933                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lri");
934                 if (ret)
935                         break;
936         }
937         return ret;
938 }
939
940 static int cmd_handler_lrr(struct parser_exec_state *s)
941 {
942         int i, ret = 0;
943         int cmd_len = cmd_length(s);
944
945         for (i = 1; i < cmd_len; i += 2) {
946                 if (IS_BROADWELL(s->vgpu->gvt->dev_priv))
947                         ret |= ((cmd_reg_inhibit(s, i) ||
948                                         (cmd_reg_inhibit(s, i + 1)))) ?
949                                 -EBADRQC : 0;
950                 if (ret)
951                         break;
952                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrr-src");
953                 if (ret)
954                         break;
955                 ret |= cmd_reg_handler(s, cmd_reg(s, i + 1), i, "lrr-dst");
956                 if (ret)
957                         break;
958         }
959         return ret;
960 }
961
962 static inline int cmd_address_audit(struct parser_exec_state *s,
963                 unsigned long guest_gma, int op_size, bool index_mode);
964
965 static int cmd_handler_lrm(struct parser_exec_state *s)
966 {
967         struct intel_gvt *gvt = s->vgpu->gvt;
968         int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
969         unsigned long gma;
970         int i, ret = 0;
971         int cmd_len = cmd_length(s);
972
973         for (i = 1; i < cmd_len;) {
974                 if (IS_BROADWELL(gvt->dev_priv))
975                         ret |= (cmd_reg_inhibit(s, i)) ? -EBADRQC : 0;
976                 if (ret)
977                         break;
978                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrm");
979                 if (ret)
980                         break;
981                 if (cmd_val(s, 0) & (1 << 22)) {
982                         gma = cmd_gma(s, i + 1);
983                         if (gmadr_bytes == 8)
984                                 gma |= (cmd_gma_hi(s, i + 2)) << 32;
985                         ret |= cmd_address_audit(s, gma, sizeof(u32), false);
986                         if (ret)
987                                 break;
988                 }
989                 i += gmadr_dw_number(s) + 1;
990         }
991         return ret;
992 }
993
994 static int cmd_handler_srm(struct parser_exec_state *s)
995 {
996         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
997         unsigned long gma;
998         int i, ret = 0;
999         int cmd_len = cmd_length(s);
1000
1001         for (i = 1; i < cmd_len;) {
1002                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "srm");
1003                 if (ret)
1004                         break;
1005                 if (cmd_val(s, 0) & (1 << 22)) {
1006                         gma = cmd_gma(s, i + 1);
1007                         if (gmadr_bytes == 8)
1008                                 gma |= (cmd_gma_hi(s, i + 2)) << 32;
1009                         ret |= cmd_address_audit(s, gma, sizeof(u32), false);
1010                         if (ret)
1011                                 break;
1012                 }
1013                 i += gmadr_dw_number(s) + 1;
1014         }
1015         return ret;
1016 }
1017
1018 struct cmd_interrupt_event {
1019         int pipe_control_notify;
1020         int mi_flush_dw;
1021         int mi_user_interrupt;
1022 };
1023
1024 static struct cmd_interrupt_event cmd_interrupt_events[] = {
1025         [RCS] = {
1026                 .pipe_control_notify = RCS_PIPE_CONTROL,
1027                 .mi_flush_dw = INTEL_GVT_EVENT_RESERVED,
1028                 .mi_user_interrupt = RCS_MI_USER_INTERRUPT,
1029         },
1030         [BCS] = {
1031                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1032                 .mi_flush_dw = BCS_MI_FLUSH_DW,
1033                 .mi_user_interrupt = BCS_MI_USER_INTERRUPT,
1034         },
1035         [VCS] = {
1036                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1037                 .mi_flush_dw = VCS_MI_FLUSH_DW,
1038                 .mi_user_interrupt = VCS_MI_USER_INTERRUPT,
1039         },
1040         [VCS2] = {
1041                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1042                 .mi_flush_dw = VCS2_MI_FLUSH_DW,
1043                 .mi_user_interrupt = VCS2_MI_USER_INTERRUPT,
1044         },
1045         [VECS] = {
1046                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1047                 .mi_flush_dw = VECS_MI_FLUSH_DW,
1048                 .mi_user_interrupt = VECS_MI_USER_INTERRUPT,
1049         },
1050 };
1051
1052 static int cmd_handler_pipe_control(struct parser_exec_state *s)
1053 {
1054         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1055         unsigned long gma;
1056         bool index_mode = false;
1057         unsigned int post_sync;
1058         int ret = 0;
1059
1060         post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14;
1061
1062         /* LRI post sync */
1063         if (cmd_val(s, 1) & PIPE_CONTROL_MMIO_WRITE)
1064                 ret = cmd_reg_handler(s, cmd_reg(s, 2), 1, "pipe_ctrl");
1065         /* post sync */
1066         else if (post_sync) {
1067                 if (post_sync == 2)
1068                         ret = cmd_reg_handler(s, 0x2350, 1, "pipe_ctrl");
1069                 else if (post_sync == 3)
1070                         ret = cmd_reg_handler(s, 0x2358, 1, "pipe_ctrl");
1071                 else if (post_sync == 1) {
1072                         /* check ggtt*/
1073                         if ((cmd_val(s, 1) & PIPE_CONTROL_GLOBAL_GTT_IVB)) {
1074                                 gma = cmd_val(s, 2) & GENMASK(31, 3);
1075                                 if (gmadr_bytes == 8)
1076                                         gma |= (cmd_gma_hi(s, 3)) << 32;
1077                                 /* Store Data Index */
1078                                 if (cmd_val(s, 1) & (1 << 21))
1079                                         index_mode = true;
1080                                 ret |= cmd_address_audit(s, gma, sizeof(u64),
1081                                                 index_mode);
1082                         }
1083                 }
1084         }
1085
1086         if (ret)
1087                 return ret;
1088
1089         if (cmd_val(s, 1) & PIPE_CONTROL_NOTIFY)
1090                 set_bit(cmd_interrupt_events[s->ring_id].pipe_control_notify,
1091                                 s->workload->pending_events);
1092         return 0;
1093 }
1094
1095 static int cmd_handler_mi_user_interrupt(struct parser_exec_state *s)
1096 {
1097         set_bit(cmd_interrupt_events[s->ring_id].mi_user_interrupt,
1098                         s->workload->pending_events);
1099         return 0;
1100 }
1101
1102 static int cmd_advance_default(struct parser_exec_state *s)
1103 {
1104         return ip_gma_advance(s, cmd_length(s));
1105 }
1106
1107 static int cmd_handler_mi_batch_buffer_end(struct parser_exec_state *s)
1108 {
1109         int ret;
1110
1111         if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1112                 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1113                 ret = ip_gma_set(s, s->ret_ip_gma_bb);
1114                 s->buf_addr_type = s->saved_buf_addr_type;
1115         } else {
1116                 s->buf_type = RING_BUFFER_INSTRUCTION;
1117                 s->buf_addr_type = GTT_BUFFER;
1118                 if (s->ret_ip_gma_ring >= s->ring_start + s->ring_size)
1119                         s->ret_ip_gma_ring -= s->ring_size;
1120                 ret = ip_gma_set(s, s->ret_ip_gma_ring);
1121         }
1122         return ret;
1123 }
1124
1125 struct mi_display_flip_command_info {
1126         int pipe;
1127         int plane;
1128         int event;
1129         i915_reg_t stride_reg;
1130         i915_reg_t ctrl_reg;
1131         i915_reg_t surf_reg;
1132         u64 stride_val;
1133         u64 tile_val;
1134         u64 surf_val;
1135         bool async_flip;
1136 };
1137
1138 struct plane_code_mapping {
1139         int pipe;
1140         int plane;
1141         int event;
1142 };
1143
1144 static int gen8_decode_mi_display_flip(struct parser_exec_state *s,
1145                 struct mi_display_flip_command_info *info)
1146 {
1147         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1148         struct plane_code_mapping gen8_plane_code[] = {
1149                 [0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE},
1150                 [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE},
1151                 [2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE},
1152                 [3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE},
1153                 [4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE},
1154                 [5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE},
1155         };
1156         u32 dword0, dword1, dword2;
1157         u32 v;
1158
1159         dword0 = cmd_val(s, 0);
1160         dword1 = cmd_val(s, 1);
1161         dword2 = cmd_val(s, 2);
1162
1163         v = (dword0 & GENMASK(21, 19)) >> 19;
1164         if (WARN_ON(v >= ARRAY_SIZE(gen8_plane_code)))
1165                 return -EBADRQC;
1166
1167         info->pipe = gen8_plane_code[v].pipe;
1168         info->plane = gen8_plane_code[v].plane;
1169         info->event = gen8_plane_code[v].event;
1170         info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1171         info->tile_val = (dword1 & 0x1);
1172         info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1173         info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1174
1175         if (info->plane == PLANE_A) {
1176                 info->ctrl_reg = DSPCNTR(info->pipe);
1177                 info->stride_reg = DSPSTRIDE(info->pipe);
1178                 info->surf_reg = DSPSURF(info->pipe);
1179         } else if (info->plane == PLANE_B) {
1180                 info->ctrl_reg = SPRCTL(info->pipe);
1181                 info->stride_reg = SPRSTRIDE(info->pipe);
1182                 info->surf_reg = SPRSURF(info->pipe);
1183         } else {
1184                 WARN_ON(1);
1185                 return -EBADRQC;
1186         }
1187         return 0;
1188 }
1189
1190 static int skl_decode_mi_display_flip(struct parser_exec_state *s,
1191                 struct mi_display_flip_command_info *info)
1192 {
1193         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1194         struct intel_vgpu *vgpu = s->vgpu;
1195         u32 dword0 = cmd_val(s, 0);
1196         u32 dword1 = cmd_val(s, 1);
1197         u32 dword2 = cmd_val(s, 2);
1198         u32 plane = (dword0 & GENMASK(12, 8)) >> 8;
1199
1200         info->plane = PRIMARY_PLANE;
1201
1202         switch (plane) {
1203         case MI_DISPLAY_FLIP_SKL_PLANE_1_A:
1204                 info->pipe = PIPE_A;
1205                 info->event = PRIMARY_A_FLIP_DONE;
1206                 break;
1207         case MI_DISPLAY_FLIP_SKL_PLANE_1_B:
1208                 info->pipe = PIPE_B;
1209                 info->event = PRIMARY_B_FLIP_DONE;
1210                 break;
1211         case MI_DISPLAY_FLIP_SKL_PLANE_1_C:
1212                 info->pipe = PIPE_C;
1213                 info->event = PRIMARY_C_FLIP_DONE;
1214                 break;
1215
1216         case MI_DISPLAY_FLIP_SKL_PLANE_2_A:
1217                 info->pipe = PIPE_A;
1218                 info->event = SPRITE_A_FLIP_DONE;
1219                 info->plane = SPRITE_PLANE;
1220                 break;
1221         case MI_DISPLAY_FLIP_SKL_PLANE_2_B:
1222                 info->pipe = PIPE_B;
1223                 info->event = SPRITE_B_FLIP_DONE;
1224                 info->plane = SPRITE_PLANE;
1225                 break;
1226         case MI_DISPLAY_FLIP_SKL_PLANE_2_C:
1227                 info->pipe = PIPE_C;
1228                 info->event = SPRITE_C_FLIP_DONE;
1229                 info->plane = SPRITE_PLANE;
1230                 break;
1231
1232         default:
1233                 gvt_vgpu_err("unknown plane code %d\n", plane);
1234                 return -EBADRQC;
1235         }
1236
1237         info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1238         info->tile_val = (dword1 & GENMASK(2, 0));
1239         info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1240         info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1241
1242         info->ctrl_reg = DSPCNTR(info->pipe);
1243         info->stride_reg = DSPSTRIDE(info->pipe);
1244         info->surf_reg = DSPSURF(info->pipe);
1245
1246         return 0;
1247 }
1248
1249 static int gen8_check_mi_display_flip(struct parser_exec_state *s,
1250                 struct mi_display_flip_command_info *info)
1251 {
1252         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1253         u32 stride, tile;
1254
1255         if (!info->async_flip)
1256                 return 0;
1257
1258         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1259                 stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);
1260                 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &
1261                                 GENMASK(12, 10)) >> 10;
1262         } else {
1263                 stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) &
1264                                 GENMASK(15, 6)) >> 6;
1265                 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;
1266         }
1267
1268         if (stride != info->stride_val)
1269                 gvt_dbg_cmd("cannot change stride during async flip\n");
1270
1271         if (tile != info->tile_val)
1272                 gvt_dbg_cmd("cannot change tile during async flip\n");
1273
1274         return 0;
1275 }
1276
1277 static int gen8_update_plane_mmio_from_mi_display_flip(
1278                 struct parser_exec_state *s,
1279                 struct mi_display_flip_command_info *info)
1280 {
1281         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1282         struct intel_vgpu *vgpu = s->vgpu;
1283
1284         set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),
1285                       info->surf_val << 12);
1286         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1287                 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),
1288                               info->stride_val);
1289                 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),
1290                               info->tile_val << 10);
1291         } else {
1292                 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6),
1293                               info->stride_val << 6);
1294                 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),
1295                               info->tile_val << 10);
1296         }
1297
1298         vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(info->pipe))++;
1299         intel_vgpu_trigger_virtual_event(vgpu, info->event);
1300         return 0;
1301 }
1302
1303 static int decode_mi_display_flip(struct parser_exec_state *s,
1304                 struct mi_display_flip_command_info *info)
1305 {
1306         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1307
1308         if (IS_BROADWELL(dev_priv))
1309                 return gen8_decode_mi_display_flip(s, info);
1310         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
1311                 return skl_decode_mi_display_flip(s, info);
1312
1313         return -ENODEV;
1314 }
1315
1316 static int check_mi_display_flip(struct parser_exec_state *s,
1317                 struct mi_display_flip_command_info *info)
1318 {
1319         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1320
1321         if (IS_BROADWELL(dev_priv)
1322                 || IS_SKYLAKE(dev_priv)
1323                 || IS_KABYLAKE(dev_priv))
1324                 return gen8_check_mi_display_flip(s, info);
1325         return -ENODEV;
1326 }
1327
1328 static int update_plane_mmio_from_mi_display_flip(
1329                 struct parser_exec_state *s,
1330                 struct mi_display_flip_command_info *info)
1331 {
1332         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1333
1334         if (IS_BROADWELL(dev_priv)
1335                 || IS_SKYLAKE(dev_priv)
1336                 || IS_KABYLAKE(dev_priv))
1337                 return gen8_update_plane_mmio_from_mi_display_flip(s, info);
1338         return -ENODEV;
1339 }
1340
1341 static int cmd_handler_mi_display_flip(struct parser_exec_state *s)
1342 {
1343         struct mi_display_flip_command_info info;
1344         struct intel_vgpu *vgpu = s->vgpu;
1345         int ret;
1346         int i;
1347         int len = cmd_length(s);
1348
1349         ret = decode_mi_display_flip(s, &info);
1350         if (ret) {
1351                 gvt_vgpu_err("fail to decode MI display flip command\n");
1352                 return ret;
1353         }
1354
1355         ret = check_mi_display_flip(s, &info);
1356         if (ret) {
1357                 gvt_vgpu_err("invalid MI display flip command\n");
1358                 return ret;
1359         }
1360
1361         ret = update_plane_mmio_from_mi_display_flip(s, &info);
1362         if (ret) {
1363                 gvt_vgpu_err("fail to update plane mmio\n");
1364                 return ret;
1365         }
1366
1367         for (i = 0; i < len; i++)
1368                 patch_value(s, cmd_ptr(s, i), MI_NOOP);
1369         return 0;
1370 }
1371
1372 static bool is_wait_for_flip_pending(u32 cmd)
1373 {
1374         return cmd & (MI_WAIT_FOR_PLANE_A_FLIP_PENDING |
1375                         MI_WAIT_FOR_PLANE_B_FLIP_PENDING |
1376                         MI_WAIT_FOR_PLANE_C_FLIP_PENDING |
1377                         MI_WAIT_FOR_SPRITE_A_FLIP_PENDING |
1378                         MI_WAIT_FOR_SPRITE_B_FLIP_PENDING |
1379                         MI_WAIT_FOR_SPRITE_C_FLIP_PENDING);
1380 }
1381
1382 static int cmd_handler_mi_wait_for_event(struct parser_exec_state *s)
1383 {
1384         u32 cmd = cmd_val(s, 0);
1385
1386         if (!is_wait_for_flip_pending(cmd))
1387                 return 0;
1388
1389         patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1390         return 0;
1391 }
1392
1393 static unsigned long get_gma_bb_from_cmd(struct parser_exec_state *s, int index)
1394 {
1395         unsigned long addr;
1396         unsigned long gma_high, gma_low;
1397         struct intel_vgpu *vgpu = s->vgpu;
1398         int gmadr_bytes = vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1399
1400         if (WARN_ON(gmadr_bytes != 4 && gmadr_bytes != 8)) {
1401                 gvt_vgpu_err("invalid gma bytes %d\n", gmadr_bytes);
1402                 return INTEL_GVT_INVALID_ADDR;
1403         }
1404
1405         gma_low = cmd_val(s, index) & BATCH_BUFFER_ADDR_MASK;
1406         if (gmadr_bytes == 4) {
1407                 addr = gma_low;
1408         } else {
1409                 gma_high = cmd_val(s, index + 1) & BATCH_BUFFER_ADDR_HIGH_MASK;
1410                 addr = (((unsigned long)gma_high) << 32) | gma_low;
1411         }
1412         return addr;
1413 }
1414
1415 static inline int cmd_address_audit(struct parser_exec_state *s,
1416                 unsigned long guest_gma, int op_size, bool index_mode)
1417 {
1418         struct intel_vgpu *vgpu = s->vgpu;
1419         u32 max_surface_size = vgpu->gvt->device_info.max_surface_size;
1420         int i;
1421         int ret;
1422
1423         if (op_size > max_surface_size) {
1424                 gvt_vgpu_err("command address audit fail name %s\n",
1425                         s->info->name);
1426                 return -EFAULT;
1427         }
1428
1429         if (index_mode) {
1430                 if (guest_gma >= I915_GTT_PAGE_SIZE / sizeof(u64)) {
1431                         ret = -EFAULT;
1432                         goto err;
1433                 }
1434         } else if (!intel_gvt_ggtt_validate_range(vgpu, guest_gma, op_size)) {
1435                 ret = -EFAULT;
1436                 goto err;
1437         }
1438
1439         return 0;
1440
1441 err:
1442         gvt_vgpu_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n",
1443                         s->info->name, guest_gma, op_size);
1444
1445         pr_err("cmd dump: ");
1446         for (i = 0; i < cmd_length(s); i++) {
1447                 if (!(i % 4))
1448                         pr_err("\n%08x ", cmd_val(s, i));
1449                 else
1450                         pr_err("%08x ", cmd_val(s, i));
1451         }
1452         pr_err("\nvgpu%d: aperture 0x%llx - 0x%llx, hidden 0x%llx - 0x%llx\n",
1453                         vgpu->id,
1454                         vgpu_aperture_gmadr_base(vgpu),
1455                         vgpu_aperture_gmadr_end(vgpu),
1456                         vgpu_hidden_gmadr_base(vgpu),
1457                         vgpu_hidden_gmadr_end(vgpu));
1458         return ret;
1459 }
1460
1461 static int cmd_handler_mi_store_data_imm(struct parser_exec_state *s)
1462 {
1463         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1464         int op_size = (cmd_length(s) - 3) * sizeof(u32);
1465         int core_id = (cmd_val(s, 2) & (1 << 0)) ? 1 : 0;
1466         unsigned long gma, gma_low, gma_high;
1467         int ret = 0;
1468
1469         /* check ppggt */
1470         if (!(cmd_val(s, 0) & (1 << 22)))
1471                 return 0;
1472
1473         gma = cmd_val(s, 2) & GENMASK(31, 2);
1474
1475         if (gmadr_bytes == 8) {
1476                 gma_low = cmd_val(s, 1) & GENMASK(31, 2);
1477                 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1478                 gma = (gma_high << 32) | gma_low;
1479                 core_id = (cmd_val(s, 1) & (1 << 0)) ? 1 : 0;
1480         }
1481         ret = cmd_address_audit(s, gma + op_size * core_id, op_size, false);
1482         return ret;
1483 }
1484
1485 static inline int unexpected_cmd(struct parser_exec_state *s)
1486 {
1487         struct intel_vgpu *vgpu = s->vgpu;
1488
1489         gvt_vgpu_err("Unexpected %s in command buffer!\n", s->info->name);
1490
1491         return -EBADRQC;
1492 }
1493
1494 static int cmd_handler_mi_semaphore_wait(struct parser_exec_state *s)
1495 {
1496         return unexpected_cmd(s);
1497 }
1498
1499 static int cmd_handler_mi_report_perf_count(struct parser_exec_state *s)
1500 {
1501         return unexpected_cmd(s);
1502 }
1503
1504 static int cmd_handler_mi_op_2e(struct parser_exec_state *s)
1505 {
1506         return unexpected_cmd(s);
1507 }
1508
1509 static int cmd_handler_mi_op_2f(struct parser_exec_state *s)
1510 {
1511         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1512         int op_size = (1 << ((cmd_val(s, 0) & GENMASK(20, 19)) >> 19)) *
1513                         sizeof(u32);
1514         unsigned long gma, gma_high;
1515         int ret = 0;
1516
1517         if (!(cmd_val(s, 0) & (1 << 22)))
1518                 return ret;
1519
1520         gma = cmd_val(s, 1) & GENMASK(31, 2);
1521         if (gmadr_bytes == 8) {
1522                 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1523                 gma = (gma_high << 32) | gma;
1524         }
1525         ret = cmd_address_audit(s, gma, op_size, false);
1526         return ret;
1527 }
1528
1529 static int cmd_handler_mi_store_data_index(struct parser_exec_state *s)
1530 {
1531         return unexpected_cmd(s);
1532 }
1533
1534 static int cmd_handler_mi_clflush(struct parser_exec_state *s)
1535 {
1536         return unexpected_cmd(s);
1537 }
1538
1539 static int cmd_handler_mi_conditional_batch_buffer_end(
1540                 struct parser_exec_state *s)
1541 {
1542         return unexpected_cmd(s);
1543 }
1544
1545 static int cmd_handler_mi_update_gtt(struct parser_exec_state *s)
1546 {
1547         return unexpected_cmd(s);
1548 }
1549
1550 static int cmd_handler_mi_flush_dw(struct parser_exec_state *s)
1551 {
1552         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1553         unsigned long gma;
1554         bool index_mode = false;
1555         int ret = 0;
1556
1557         /* Check post-sync and ppgtt bit */
1558         if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) {
1559                 gma = cmd_val(s, 1) & GENMASK(31, 3);
1560                 if (gmadr_bytes == 8)
1561                         gma |= (cmd_val(s, 2) & GENMASK(15, 0)) << 32;
1562                 /* Store Data Index */
1563                 if (cmd_val(s, 0) & (1 << 21))
1564                         index_mode = true;
1565                 ret = cmd_address_audit(s, gma, sizeof(u64), index_mode);
1566         }
1567         /* Check notify bit */
1568         if ((cmd_val(s, 0) & (1 << 8)))
1569                 set_bit(cmd_interrupt_events[s->ring_id].mi_flush_dw,
1570                                 s->workload->pending_events);
1571         return ret;
1572 }
1573
1574 static void addr_type_update_snb(struct parser_exec_state *s)
1575 {
1576         if ((s->buf_type == RING_BUFFER_INSTRUCTION) &&
1577                         (BATCH_BUFFER_ADR_SPACE_BIT(cmd_val(s, 0)) == 1)) {
1578                 s->buf_addr_type = PPGTT_BUFFER;
1579         }
1580 }
1581
1582
1583 static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm,
1584                 unsigned long gma, unsigned long end_gma, void *va)
1585 {
1586         unsigned long copy_len, offset;
1587         unsigned long len = 0;
1588         unsigned long gpa;
1589
1590         while (gma != end_gma) {
1591                 gpa = intel_vgpu_gma_to_gpa(mm, gma);
1592                 if (gpa == INTEL_GVT_INVALID_ADDR) {
1593                         gvt_vgpu_err("invalid gma address: %lx\n", gma);
1594                         return -EFAULT;
1595                 }
1596
1597                 offset = gma & (I915_GTT_PAGE_SIZE - 1);
1598
1599                 copy_len = (end_gma - gma) >= (I915_GTT_PAGE_SIZE - offset) ?
1600                         I915_GTT_PAGE_SIZE - offset : end_gma - gma;
1601
1602                 intel_gvt_hypervisor_read_gpa(vgpu, gpa, va + len, copy_len);
1603
1604                 len += copy_len;
1605                 gma += copy_len;
1606         }
1607         return len;
1608 }
1609
1610
1611 /*
1612  * Check whether a batch buffer needs to be scanned. Currently
1613  * the only criteria is based on privilege.
1614  */
1615 static int batch_buffer_needs_scan(struct parser_exec_state *s)
1616 {
1617         struct intel_gvt *gvt = s->vgpu->gvt;
1618
1619         if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)
1620                 || IS_KABYLAKE(gvt->dev_priv)) {
1621                 /* BDW decides privilege based on address space */
1622                 if (cmd_val(s, 0) & (1 << 8) &&
1623                         !(s->vgpu->scan_nonprivbb & (1 << s->ring_id)))
1624                         return 0;
1625         }
1626         return 1;
1627 }
1628
1629 static int find_bb_size(struct parser_exec_state *s, unsigned long *bb_size)
1630 {
1631         unsigned long gma = 0;
1632         struct cmd_info *info;
1633         uint32_t cmd_len = 0;
1634         bool bb_end = false;
1635         struct intel_vgpu *vgpu = s->vgpu;
1636         u32 cmd;
1637         struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1638                 s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1639
1640         *bb_size = 0;
1641
1642         /* get the start gm address of the batch buffer */
1643         gma = get_gma_bb_from_cmd(s, 1);
1644         if (gma == INTEL_GVT_INVALID_ADDR)
1645                 return -EFAULT;
1646
1647         cmd = cmd_val(s, 0);
1648         info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
1649         if (info == NULL) {
1650                 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",
1651                                 cmd, get_opcode(cmd, s->ring_id),
1652                                 (s->buf_addr_type == PPGTT_BUFFER) ?
1653                                 "ppgtt" : "ggtt", s->ring_id, s->workload);
1654                 return -EBADRQC;
1655         }
1656         do {
1657                 if (copy_gma_to_hva(s->vgpu, mm,
1658                                 gma, gma + 4, &cmd) < 0)
1659                         return -EFAULT;
1660                 info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
1661                 if (info == NULL) {
1662                         gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",
1663                                 cmd, get_opcode(cmd, s->ring_id),
1664                                 (s->buf_addr_type == PPGTT_BUFFER) ?
1665                                 "ppgtt" : "ggtt", s->ring_id, s->workload);
1666                         return -EBADRQC;
1667                 }
1668
1669                 if (info->opcode == OP_MI_BATCH_BUFFER_END) {
1670                         bb_end = true;
1671                 } else if (info->opcode == OP_MI_BATCH_BUFFER_START) {
1672                         if (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0)
1673                                 /* chained batch buffer */
1674                                 bb_end = true;
1675                 }
1676                 cmd_len = get_cmd_length(info, cmd) << 2;
1677                 *bb_size += cmd_len;
1678                 gma += cmd_len;
1679         } while (!bb_end);
1680
1681         return 0;
1682 }
1683
1684 static int perform_bb_shadow(struct parser_exec_state *s)
1685 {
1686         struct intel_vgpu *vgpu = s->vgpu;
1687         struct intel_vgpu_shadow_bb *bb;
1688         unsigned long gma = 0;
1689         unsigned long bb_size;
1690         int ret = 0;
1691         struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1692                 s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1693         unsigned long gma_start_offset = 0;
1694
1695         /* get the start gm address of the batch buffer */
1696         gma = get_gma_bb_from_cmd(s, 1);
1697         if (gma == INTEL_GVT_INVALID_ADDR)
1698                 return -EFAULT;
1699
1700         ret = find_bb_size(s, &bb_size);
1701         if (ret)
1702                 return ret;
1703
1704         bb = kzalloc(sizeof(*bb), GFP_KERNEL);
1705         if (!bb)
1706                 return -ENOMEM;
1707
1708         bb->ppgtt = (s->buf_addr_type == GTT_BUFFER) ? false : true;
1709
1710         /* the gma_start_offset stores the batch buffer's start gma's
1711          * offset relative to page boundary. so for non-privileged batch
1712          * buffer, the shadowed gem object holds exactly the same page
1713          * layout as original gem object. This is for the convience of
1714          * replacing the whole non-privilged batch buffer page to this
1715          * shadowed one in PPGTT at the same gma address. (this replacing
1716          * action is not implemented yet now, but may be necessary in
1717          * future).
1718          * for prileged batch buffer, we just change start gma address to
1719          * that of shadowed page.
1720          */
1721         if (bb->ppgtt)
1722                 gma_start_offset = gma & ~I915_GTT_PAGE_MASK;
1723
1724         bb->obj = i915_gem_object_create(s->vgpu->gvt->dev_priv,
1725                          roundup(bb_size + gma_start_offset, PAGE_SIZE));
1726         if (IS_ERR(bb->obj)) {
1727                 ret = PTR_ERR(bb->obj);
1728                 goto err_free_bb;
1729         }
1730
1731         ret = i915_gem_obj_prepare_shmem_write(bb->obj, &bb->clflush);
1732         if (ret)
1733                 goto err_free_obj;
1734
1735         bb->va = i915_gem_object_pin_map(bb->obj, I915_MAP_WB);
1736         if (IS_ERR(bb->va)) {
1737                 ret = PTR_ERR(bb->va);
1738                 goto err_finish_shmem_access;
1739         }
1740
1741         if (bb->clflush & CLFLUSH_BEFORE) {
1742                 drm_clflush_virt_range(bb->va, bb->obj->base.size);
1743                 bb->clflush &= ~CLFLUSH_BEFORE;
1744         }
1745
1746         ret = copy_gma_to_hva(s->vgpu, mm,
1747                               gma, gma + bb_size,
1748                               bb->va + gma_start_offset);
1749         if (ret < 0) {
1750                 gvt_vgpu_err("fail to copy guest ring buffer\n");
1751                 ret = -EFAULT;
1752                 goto err_unmap;
1753         }
1754
1755         INIT_LIST_HEAD(&bb->list);
1756         list_add(&bb->list, &s->workload->shadow_bb);
1757
1758         bb->accessing = true;
1759         bb->bb_start_cmd_va = s->ip_va;
1760
1761         if ((s->buf_type == BATCH_BUFFER_INSTRUCTION) && (!s->is_ctx_wa))
1762                 bb->bb_offset = s->ip_va - s->rb_va;
1763         else
1764                 bb->bb_offset = 0;
1765
1766         /*
1767          * ip_va saves the virtual address of the shadow batch buffer, while
1768          * ip_gma saves the graphics address of the original batch buffer.
1769          * As the shadow batch buffer is just a copy from the originial one,
1770          * it should be right to use shadow batch buffer'va and original batch
1771          * buffer's gma in pair. After all, we don't want to pin the shadow
1772          * buffer here (too early).
1773          */
1774         s->ip_va = bb->va + gma_start_offset;
1775         s->ip_gma = gma;
1776         return 0;
1777 err_unmap:
1778         i915_gem_object_unpin_map(bb->obj);
1779 err_finish_shmem_access:
1780         i915_gem_obj_finish_shmem_access(bb->obj);
1781 err_free_obj:
1782         i915_gem_object_put(bb->obj);
1783 err_free_bb:
1784         kfree(bb);
1785         return ret;
1786 }
1787
1788 static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s)
1789 {
1790         bool second_level;
1791         int ret = 0;
1792         struct intel_vgpu *vgpu = s->vgpu;
1793
1794         if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1795                 gvt_vgpu_err("Found MI_BATCH_BUFFER_START in 2nd level BB\n");
1796                 return -EFAULT;
1797         }
1798
1799         second_level = BATCH_BUFFER_2ND_LEVEL_BIT(cmd_val(s, 0)) == 1;
1800         if (second_level && (s->buf_type != BATCH_BUFFER_INSTRUCTION)) {
1801                 gvt_vgpu_err("Jumping to 2nd level BB from RB is not allowed\n");
1802                 return -EFAULT;
1803         }
1804
1805         s->saved_buf_addr_type = s->buf_addr_type;
1806         addr_type_update_snb(s);
1807         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
1808                 s->ret_ip_gma_ring = s->ip_gma + cmd_length(s) * sizeof(u32);
1809                 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1810         } else if (second_level) {
1811                 s->buf_type = BATCH_BUFFER_2ND_LEVEL;
1812                 s->ret_ip_gma_bb = s->ip_gma + cmd_length(s) * sizeof(u32);
1813                 s->ret_bb_va = s->ip_va + cmd_length(s) * sizeof(u32);
1814         }
1815
1816         if (batch_buffer_needs_scan(s)) {
1817                 ret = perform_bb_shadow(s);
1818                 if (ret < 0)
1819                         gvt_vgpu_err("invalid shadow batch buffer\n");
1820         } else {
1821                 /* emulate a batch buffer end to do return right */
1822                 ret = cmd_handler_mi_batch_buffer_end(s);
1823                 if (ret < 0)
1824                         return ret;
1825         }
1826         return ret;
1827 }
1828
1829 static struct cmd_info cmd_info[] = {
1830         {"MI_NOOP", OP_MI_NOOP, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
1831
1832         {"MI_SET_PREDICATE", OP_MI_SET_PREDICATE, F_LEN_CONST, R_ALL, D_ALL,
1833                 0, 1, NULL},
1834
1835         {"MI_USER_INTERRUPT", OP_MI_USER_INTERRUPT, F_LEN_CONST, R_ALL, D_ALL,
1836                 0, 1, cmd_handler_mi_user_interrupt},
1837
1838         {"MI_WAIT_FOR_EVENT", OP_MI_WAIT_FOR_EVENT, F_LEN_CONST, R_RCS | R_BCS,
1839                 D_ALL, 0, 1, cmd_handler_mi_wait_for_event},
1840
1841         {"MI_FLUSH", OP_MI_FLUSH, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
1842
1843         {"MI_ARB_CHECK", OP_MI_ARB_CHECK, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1844                 NULL},
1845
1846         {"MI_RS_CONTROL", OP_MI_RS_CONTROL, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1847                 NULL},
1848
1849         {"MI_REPORT_HEAD", OP_MI_REPORT_HEAD, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1850                 NULL},
1851
1852         {"MI_ARB_ON_OFF", OP_MI_ARB_ON_OFF, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1853                 NULL},
1854
1855         {"MI_URB_ATOMIC_ALLOC", OP_MI_URB_ATOMIC_ALLOC, F_LEN_CONST, R_RCS,
1856                 D_ALL, 0, 1, NULL},
1857
1858         {"MI_BATCH_BUFFER_END", OP_MI_BATCH_BUFFER_END,
1859                 F_IP_ADVANCE_CUSTOM | F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1860                 cmd_handler_mi_batch_buffer_end},
1861
1862         {"MI_SUSPEND_FLUSH", OP_MI_SUSPEND_FLUSH, F_LEN_CONST, R_ALL, D_ALL,
1863                 0, 1, NULL},
1864
1865         {"MI_PREDICATE", OP_MI_PREDICATE, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1866                 NULL},
1867
1868         {"MI_TOPOLOGY_FILTER", OP_MI_TOPOLOGY_FILTER, F_LEN_CONST, R_ALL,
1869                 D_ALL, 0, 1, NULL},
1870
1871         {"MI_SET_APPID", OP_MI_SET_APPID, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1872                 NULL},
1873
1874         {"MI_RS_CONTEXT", OP_MI_RS_CONTEXT, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1875                 NULL},
1876
1877         {"MI_DISPLAY_FLIP", OP_MI_DISPLAY_FLIP, F_LEN_VAR | F_POST_HANDLE,
1878                 R_RCS | R_BCS, D_ALL, 0, 8, cmd_handler_mi_display_flip},
1879
1880         {"MI_SEMAPHORE_MBOX", OP_MI_SEMAPHORE_MBOX, F_LEN_VAR, R_ALL, D_ALL,
1881                 0, 8, NULL},
1882
1883         {"MI_MATH", OP_MI_MATH, F_LEN_VAR, R_ALL, D_ALL, 0, 8, NULL},
1884
1885         {"MI_URB_CLEAR", OP_MI_URB_CLEAR, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1886
1887         {"ME_SEMAPHORE_SIGNAL", OP_MI_SEMAPHORE_SIGNAL, F_LEN_VAR, R_ALL,
1888                 D_BDW_PLUS, 0, 8, NULL},
1889
1890         {"ME_SEMAPHORE_WAIT", OP_MI_SEMAPHORE_WAIT, F_LEN_VAR, R_ALL, D_BDW_PLUS,
1891                 ADDR_FIX_1(2), 8, cmd_handler_mi_semaphore_wait},
1892
1893         {"MI_STORE_DATA_IMM", OP_MI_STORE_DATA_IMM, F_LEN_VAR, R_ALL, D_BDW_PLUS,
1894                 ADDR_FIX_1(1), 10, cmd_handler_mi_store_data_imm},
1895
1896         {"MI_STORE_DATA_INDEX", OP_MI_STORE_DATA_INDEX, F_LEN_VAR, R_ALL, D_ALL,
1897                 0, 8, cmd_handler_mi_store_data_index},
1898
1899         {"MI_LOAD_REGISTER_IMM", OP_MI_LOAD_REGISTER_IMM, F_LEN_VAR, R_ALL,
1900                 D_ALL, 0, 8, cmd_handler_lri},
1901
1902         {"MI_UPDATE_GTT", OP_MI_UPDATE_GTT, F_LEN_VAR, R_ALL, D_BDW_PLUS, 0, 10,
1903                 cmd_handler_mi_update_gtt},
1904
1905         {"MI_STORE_REGISTER_MEM", OP_MI_STORE_REGISTER_MEM, F_LEN_VAR, R_ALL,
1906                 D_ALL, ADDR_FIX_1(2), 8, cmd_handler_srm},
1907
1908         {"MI_FLUSH_DW", OP_MI_FLUSH_DW, F_LEN_VAR, R_ALL, D_ALL, 0, 6,
1909                 cmd_handler_mi_flush_dw},
1910
1911         {"MI_CLFLUSH", OP_MI_CLFLUSH, F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(1),
1912                 10, cmd_handler_mi_clflush},
1913
1914         {"MI_REPORT_PERF_COUNT", OP_MI_REPORT_PERF_COUNT, F_LEN_VAR, R_ALL,
1915                 D_ALL, ADDR_FIX_1(1), 6, cmd_handler_mi_report_perf_count},
1916
1917         {"MI_LOAD_REGISTER_MEM", OP_MI_LOAD_REGISTER_MEM, F_LEN_VAR, R_ALL,
1918                 D_ALL, ADDR_FIX_1(2), 8, cmd_handler_lrm},
1919
1920         {"MI_LOAD_REGISTER_REG", OP_MI_LOAD_REGISTER_REG, F_LEN_VAR, R_ALL,
1921                 D_ALL, 0, 8, cmd_handler_lrr},
1922
1923         {"MI_RS_STORE_DATA_IMM", OP_MI_RS_STORE_DATA_IMM, F_LEN_VAR, R_RCS,
1924                 D_ALL, 0, 8, NULL},
1925
1926         {"MI_LOAD_URB_MEM", OP_MI_LOAD_URB_MEM, F_LEN_VAR, R_RCS, D_ALL,
1927                 ADDR_FIX_1(2), 8, NULL},
1928
1929         {"MI_STORE_URM_MEM", OP_MI_STORE_URM_MEM, F_LEN_VAR, R_RCS, D_ALL,
1930                 ADDR_FIX_1(2), 8, NULL},
1931
1932         {"MI_OP_2E", OP_MI_2E, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_2(1, 2),
1933                 8, cmd_handler_mi_op_2e},
1934
1935         {"MI_OP_2F", OP_MI_2F, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_1(1),
1936                 8, cmd_handler_mi_op_2f},
1937
1938         {"MI_BATCH_BUFFER_START", OP_MI_BATCH_BUFFER_START,
1939                 F_IP_ADVANCE_CUSTOM, R_ALL, D_ALL, 0, 8,
1940                 cmd_handler_mi_batch_buffer_start},
1941
1942         {"MI_CONDITIONAL_BATCH_BUFFER_END", OP_MI_CONDITIONAL_BATCH_BUFFER_END,
1943                 F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
1944                 cmd_handler_mi_conditional_batch_buffer_end},
1945
1946         {"MI_LOAD_SCAN_LINES_INCL", OP_MI_LOAD_SCAN_LINES_INCL, F_LEN_CONST,
1947                 R_RCS | R_BCS, D_ALL, 0, 2, NULL},
1948
1949         {"XY_SETUP_BLT", OP_XY_SETUP_BLT, F_LEN_VAR, R_BCS, D_ALL,
1950                 ADDR_FIX_2(4, 7), 8, NULL},
1951
1952         {"XY_SETUP_CLIP_BLT", OP_XY_SETUP_CLIP_BLT, F_LEN_VAR, R_BCS, D_ALL,
1953                 0, 8, NULL},
1954
1955         {"XY_SETUP_MONO_PATTERN_SL_BLT", OP_XY_SETUP_MONO_PATTERN_SL_BLT,
1956                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
1957
1958         {"XY_PIXEL_BLT", OP_XY_PIXEL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
1959
1960         {"XY_SCANLINES_BLT", OP_XY_SCANLINES_BLT, F_LEN_VAR, R_BCS, D_ALL,
1961                 0, 8, NULL},
1962
1963         {"XY_TEXT_BLT", OP_XY_TEXT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1964                 ADDR_FIX_1(3), 8, NULL},
1965
1966         {"XY_TEXT_IMMEDIATE_BLT", OP_XY_TEXT_IMMEDIATE_BLT, F_LEN_VAR, R_BCS,
1967                 D_ALL, 0, 8, NULL},
1968
1969         {"XY_COLOR_BLT", OP_XY_COLOR_BLT, F_LEN_VAR, R_BCS, D_ALL,
1970                 ADDR_FIX_1(4), 8, NULL},
1971
1972         {"XY_PAT_BLT", OP_XY_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1973                 ADDR_FIX_2(4, 5), 8, NULL},
1974
1975         {"XY_MONO_PAT_BLT", OP_XY_MONO_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1976                 ADDR_FIX_1(4), 8, NULL},
1977
1978         {"XY_SRC_COPY_BLT", OP_XY_SRC_COPY_BLT, F_LEN_VAR, R_BCS, D_ALL,
1979                 ADDR_FIX_2(4, 7), 8, NULL},
1980
1981         {"XY_MONO_SRC_COPY_BLT", OP_XY_MONO_SRC_COPY_BLT, F_LEN_VAR, R_BCS,
1982                 D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
1983
1984         {"XY_FULL_BLT", OP_XY_FULL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
1985
1986         {"XY_FULL_MONO_SRC_BLT", OP_XY_FULL_MONO_SRC_BLT, F_LEN_VAR, R_BCS,
1987                 D_ALL, ADDR_FIX_3(4, 5, 8), 8, NULL},
1988
1989         {"XY_FULL_MONO_PATTERN_BLT", OP_XY_FULL_MONO_PATTERN_BLT, F_LEN_VAR,
1990                 R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
1991
1992         {"XY_FULL_MONO_PATTERN_MONO_SRC_BLT",
1993                 OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT,
1994                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
1995
1996         {"XY_MONO_PAT_FIXED_BLT", OP_XY_MONO_PAT_FIXED_BLT, F_LEN_VAR, R_BCS,
1997                 D_ALL, ADDR_FIX_1(4), 8, NULL},
1998
1999         {"XY_MONO_SRC_COPY_IMMEDIATE_BLT", OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT,
2000                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2001
2002         {"XY_PAT_BLT_IMMEDIATE", OP_XY_PAT_BLT_IMMEDIATE, F_LEN_VAR, R_BCS,
2003                 D_ALL, ADDR_FIX_1(4), 8, NULL},
2004
2005         {"XY_SRC_COPY_CHROMA_BLT", OP_XY_SRC_COPY_CHROMA_BLT, F_LEN_VAR, R_BCS,
2006                 D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2007
2008         {"XY_FULL_IMMEDIATE_PATTERN_BLT", OP_XY_FULL_IMMEDIATE_PATTERN_BLT,
2009                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2010
2011         {"XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT",
2012                 OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT,
2013                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2014
2015         {"XY_PAT_CHROMA_BLT", OP_XY_PAT_CHROMA_BLT, F_LEN_VAR, R_BCS, D_ALL,
2016                 ADDR_FIX_2(4, 5), 8, NULL},
2017
2018         {"XY_PAT_CHROMA_BLT_IMMEDIATE", OP_XY_PAT_CHROMA_BLT_IMMEDIATE,
2019                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2020
2021         {"3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP",
2022                 OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP,
2023                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2024
2025         {"3DSTATE_VIEWPORT_STATE_POINTERS_CC",
2026                 OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
2027                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2028
2029         {"3DSTATE_BLEND_STATE_POINTERS",
2030                 OP_3DSTATE_BLEND_STATE_POINTERS,
2031                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2032
2033         {"3DSTATE_DEPTH_STENCIL_STATE_POINTERS",
2034                 OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
2035                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2036
2037         {"3DSTATE_BINDING_TABLE_POINTERS_VS",
2038                 OP_3DSTATE_BINDING_TABLE_POINTERS_VS,
2039                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2040
2041         {"3DSTATE_BINDING_TABLE_POINTERS_HS",
2042                 OP_3DSTATE_BINDING_TABLE_POINTERS_HS,
2043                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2044
2045         {"3DSTATE_BINDING_TABLE_POINTERS_DS",
2046                 OP_3DSTATE_BINDING_TABLE_POINTERS_DS,
2047                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2048
2049         {"3DSTATE_BINDING_TABLE_POINTERS_GS",
2050                 OP_3DSTATE_BINDING_TABLE_POINTERS_GS,
2051                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2052
2053         {"3DSTATE_BINDING_TABLE_POINTERS_PS",
2054                 OP_3DSTATE_BINDING_TABLE_POINTERS_PS,
2055                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2056
2057         {"3DSTATE_SAMPLER_STATE_POINTERS_VS",
2058                 OP_3DSTATE_SAMPLER_STATE_POINTERS_VS,
2059                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2060
2061         {"3DSTATE_SAMPLER_STATE_POINTERS_HS",
2062                 OP_3DSTATE_SAMPLER_STATE_POINTERS_HS,
2063                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2064
2065         {"3DSTATE_SAMPLER_STATE_POINTERS_DS",
2066                 OP_3DSTATE_SAMPLER_STATE_POINTERS_DS,
2067                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2068
2069         {"3DSTATE_SAMPLER_STATE_POINTERS_GS",
2070                 OP_3DSTATE_SAMPLER_STATE_POINTERS_GS,
2071                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2072
2073         {"3DSTATE_SAMPLER_STATE_POINTERS_PS",
2074                 OP_3DSTATE_SAMPLER_STATE_POINTERS_PS,
2075                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2076
2077         {"3DSTATE_URB_VS", OP_3DSTATE_URB_VS, F_LEN_VAR, R_RCS, D_ALL,
2078                 0, 8, NULL},
2079
2080         {"3DSTATE_URB_HS", OP_3DSTATE_URB_HS, F_LEN_VAR, R_RCS, D_ALL,
2081                 0, 8, NULL},
2082
2083         {"3DSTATE_URB_DS", OP_3DSTATE_URB_DS, F_LEN_VAR, R_RCS, D_ALL,
2084                 0, 8, NULL},
2085
2086         {"3DSTATE_URB_GS", OP_3DSTATE_URB_GS, F_LEN_VAR, R_RCS, D_ALL,
2087                 0, 8, NULL},
2088
2089         {"3DSTATE_GATHER_CONSTANT_VS", OP_3DSTATE_GATHER_CONSTANT_VS,
2090                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2091
2092         {"3DSTATE_GATHER_CONSTANT_GS", OP_3DSTATE_GATHER_CONSTANT_GS,
2093                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2094
2095         {"3DSTATE_GATHER_CONSTANT_HS", OP_3DSTATE_GATHER_CONSTANT_HS,
2096                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2097
2098         {"3DSTATE_GATHER_CONSTANT_DS", OP_3DSTATE_GATHER_CONSTANT_DS,
2099                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2100
2101         {"3DSTATE_GATHER_CONSTANT_PS", OP_3DSTATE_GATHER_CONSTANT_PS,
2102                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2103
2104         {"3DSTATE_DX9_CONSTANTF_VS", OP_3DSTATE_DX9_CONSTANTF_VS,
2105                 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2106
2107         {"3DSTATE_DX9_CONSTANTF_PS", OP_3DSTATE_DX9_CONSTANTF_PS,
2108                 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2109
2110         {"3DSTATE_DX9_CONSTANTI_VS", OP_3DSTATE_DX9_CONSTANTI_VS,
2111                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2112
2113         {"3DSTATE_DX9_CONSTANTI_PS", OP_3DSTATE_DX9_CONSTANTI_PS,
2114                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2115
2116         {"3DSTATE_DX9_CONSTANTB_VS", OP_3DSTATE_DX9_CONSTANTB_VS,
2117                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2118
2119         {"3DSTATE_DX9_CONSTANTB_PS", OP_3DSTATE_DX9_CONSTANTB_PS,
2120                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2121
2122         {"3DSTATE_DX9_LOCAL_VALID_VS", OP_3DSTATE_DX9_LOCAL_VALID_VS,
2123                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2124
2125         {"3DSTATE_DX9_LOCAL_VALID_PS", OP_3DSTATE_DX9_LOCAL_VALID_PS,
2126                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2127
2128         {"3DSTATE_DX9_GENERATE_ACTIVE_VS", OP_3DSTATE_DX9_GENERATE_ACTIVE_VS,
2129                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2130
2131         {"3DSTATE_DX9_GENERATE_ACTIVE_PS", OP_3DSTATE_DX9_GENERATE_ACTIVE_PS,
2132                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2133
2134         {"3DSTATE_BINDING_TABLE_EDIT_VS", OP_3DSTATE_BINDING_TABLE_EDIT_VS,
2135                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2136
2137         {"3DSTATE_BINDING_TABLE_EDIT_GS", OP_3DSTATE_BINDING_TABLE_EDIT_GS,
2138                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2139
2140         {"3DSTATE_BINDING_TABLE_EDIT_HS", OP_3DSTATE_BINDING_TABLE_EDIT_HS,
2141                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2142
2143         {"3DSTATE_BINDING_TABLE_EDIT_DS", OP_3DSTATE_BINDING_TABLE_EDIT_DS,
2144                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2145
2146         {"3DSTATE_BINDING_TABLE_EDIT_PS", OP_3DSTATE_BINDING_TABLE_EDIT_PS,
2147                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2148
2149         {"3DSTATE_VF_INSTANCING", OP_3DSTATE_VF_INSTANCING, F_LEN_VAR, R_RCS,
2150                 D_BDW_PLUS, 0, 8, NULL},
2151
2152         {"3DSTATE_VF_SGVS", OP_3DSTATE_VF_SGVS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2153                 NULL},
2154
2155         {"3DSTATE_VF_TOPOLOGY", OP_3DSTATE_VF_TOPOLOGY, F_LEN_VAR, R_RCS,
2156                 D_BDW_PLUS, 0, 8, NULL},
2157
2158         {"3DSTATE_WM_CHROMAKEY", OP_3DSTATE_WM_CHROMAKEY, F_LEN_VAR, R_RCS,
2159                 D_BDW_PLUS, 0, 8, NULL},
2160
2161         {"3DSTATE_PS_BLEND", OP_3DSTATE_PS_BLEND, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2162                 8, NULL},
2163
2164         {"3DSTATE_WM_DEPTH_STENCIL", OP_3DSTATE_WM_DEPTH_STENCIL, F_LEN_VAR,
2165                 R_RCS, D_BDW_PLUS, 0, 8, NULL},
2166
2167         {"3DSTATE_PS_EXTRA", OP_3DSTATE_PS_EXTRA, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2168                 8, NULL},
2169
2170         {"3DSTATE_RASTER", OP_3DSTATE_RASTER, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2171                 NULL},
2172
2173         {"3DSTATE_SBE_SWIZ", OP_3DSTATE_SBE_SWIZ, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2174                 NULL},
2175
2176         {"3DSTATE_WM_HZ_OP", OP_3DSTATE_WM_HZ_OP, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2177                 NULL},
2178
2179         {"3DSTATE_VERTEX_BUFFERS", OP_3DSTATE_VERTEX_BUFFERS, F_LEN_VAR, R_RCS,
2180                 D_BDW_PLUS, 0, 8, NULL},
2181
2182         {"3DSTATE_VERTEX_ELEMENTS", OP_3DSTATE_VERTEX_ELEMENTS, F_LEN_VAR,
2183                 R_RCS, D_ALL, 0, 8, NULL},
2184
2185         {"3DSTATE_INDEX_BUFFER", OP_3DSTATE_INDEX_BUFFER, F_LEN_VAR, R_RCS,
2186                 D_BDW_PLUS, ADDR_FIX_1(2), 8, NULL},
2187
2188         {"3DSTATE_VF_STATISTICS", OP_3DSTATE_VF_STATISTICS, F_LEN_CONST,
2189                 R_RCS, D_ALL, 0, 1, NULL},
2190
2191         {"3DSTATE_VF", OP_3DSTATE_VF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2192
2193         {"3DSTATE_CC_STATE_POINTERS", OP_3DSTATE_CC_STATE_POINTERS, F_LEN_VAR,
2194                 R_RCS, D_ALL, 0, 8, NULL},
2195
2196         {"3DSTATE_SCISSOR_STATE_POINTERS", OP_3DSTATE_SCISSOR_STATE_POINTERS,
2197                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2198
2199         {"3DSTATE_GS", OP_3DSTATE_GS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2200
2201         {"3DSTATE_CLIP", OP_3DSTATE_CLIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2202
2203         {"3DSTATE_WM", OP_3DSTATE_WM, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2204
2205         {"3DSTATE_CONSTANT_GS", OP_3DSTATE_CONSTANT_GS, F_LEN_VAR, R_RCS,
2206                 D_BDW_PLUS, 0, 8, NULL},
2207
2208         {"3DSTATE_CONSTANT_PS", OP_3DSTATE_CONSTANT_PS, F_LEN_VAR, R_RCS,
2209                 D_BDW_PLUS, 0, 8, NULL},
2210
2211         {"3DSTATE_SAMPLE_MASK", OP_3DSTATE_SAMPLE_MASK, F_LEN_VAR, R_RCS,
2212                 D_ALL, 0, 8, NULL},
2213
2214         {"3DSTATE_CONSTANT_HS", OP_3DSTATE_CONSTANT_HS, F_LEN_VAR, R_RCS,
2215                 D_BDW_PLUS, 0, 8, NULL},
2216
2217         {"3DSTATE_CONSTANT_DS", OP_3DSTATE_CONSTANT_DS, F_LEN_VAR, R_RCS,
2218                 D_BDW_PLUS, 0, 8, NULL},
2219
2220         {"3DSTATE_HS", OP_3DSTATE_HS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2221
2222         {"3DSTATE_TE", OP_3DSTATE_TE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2223
2224         {"3DSTATE_DS", OP_3DSTATE_DS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2225
2226         {"3DSTATE_STREAMOUT", OP_3DSTATE_STREAMOUT, F_LEN_VAR, R_RCS,
2227                 D_ALL, 0, 8, NULL},
2228
2229         {"3DSTATE_SBE", OP_3DSTATE_SBE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2230
2231         {"3DSTATE_PS", OP_3DSTATE_PS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2232
2233         {"3DSTATE_DRAWING_RECTANGLE", OP_3DSTATE_DRAWING_RECTANGLE, F_LEN_VAR,
2234                 R_RCS, D_ALL, 0, 8, NULL},
2235
2236         {"3DSTATE_SAMPLER_PALETTE_LOAD0", OP_3DSTATE_SAMPLER_PALETTE_LOAD0,
2237                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2238
2239         {"3DSTATE_CHROMA_KEY", OP_3DSTATE_CHROMA_KEY, F_LEN_VAR, R_RCS, D_ALL,
2240                 0, 8, NULL},
2241
2242         {"3DSTATE_DEPTH_BUFFER", OP_3DSTATE_DEPTH_BUFFER, F_LEN_VAR, R_RCS,
2243                 D_ALL, ADDR_FIX_1(2), 8, NULL},
2244
2245         {"3DSTATE_POLY_STIPPLE_OFFSET", OP_3DSTATE_POLY_STIPPLE_OFFSET,
2246                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2247
2248         {"3DSTATE_POLY_STIPPLE_PATTERN", OP_3DSTATE_POLY_STIPPLE_PATTERN,
2249                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2250
2251         {"3DSTATE_LINE_STIPPLE", OP_3DSTATE_LINE_STIPPLE, F_LEN_VAR, R_RCS,
2252                 D_ALL, 0, 8, NULL},
2253
2254         {"3DSTATE_AA_LINE_PARAMS", OP_3DSTATE_AA_LINE_PARAMS, F_LEN_VAR, R_RCS,
2255                 D_ALL, 0, 8, NULL},
2256
2257         {"3DSTATE_GS_SVB_INDEX", OP_3DSTATE_GS_SVB_INDEX, F_LEN_VAR, R_RCS,
2258                 D_ALL, 0, 8, NULL},
2259
2260         {"3DSTATE_SAMPLER_PALETTE_LOAD1", OP_3DSTATE_SAMPLER_PALETTE_LOAD1,
2261                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2262
2263         {"3DSTATE_MULTISAMPLE", OP_3DSTATE_MULTISAMPLE_BDW, F_LEN_VAR, R_RCS,
2264                 D_BDW_PLUS, 0, 8, NULL},
2265
2266         {"3DSTATE_STENCIL_BUFFER", OP_3DSTATE_STENCIL_BUFFER, F_LEN_VAR, R_RCS,
2267                 D_ALL, ADDR_FIX_1(2), 8, NULL},
2268
2269         {"3DSTATE_HIER_DEPTH_BUFFER", OP_3DSTATE_HIER_DEPTH_BUFFER, F_LEN_VAR,
2270                 R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL},
2271
2272         {"3DSTATE_CLEAR_PARAMS", OP_3DSTATE_CLEAR_PARAMS, F_LEN_VAR,
2273                 R_RCS, D_ALL, 0, 8, NULL},
2274
2275         {"3DSTATE_PUSH_CONSTANT_ALLOC_VS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
2276                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2277
2278         {"3DSTATE_PUSH_CONSTANT_ALLOC_HS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS,
2279                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2280
2281         {"3DSTATE_PUSH_CONSTANT_ALLOC_DS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS,
2282                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2283
2284         {"3DSTATE_PUSH_CONSTANT_ALLOC_GS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS,
2285                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2286
2287         {"3DSTATE_PUSH_CONSTANT_ALLOC_PS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS,
2288                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2289
2290         {"3DSTATE_MONOFILTER_SIZE", OP_3DSTATE_MONOFILTER_SIZE, F_LEN_VAR,
2291                 R_RCS, D_ALL, 0, 8, NULL},
2292
2293         {"3DSTATE_SO_DECL_LIST", OP_3DSTATE_SO_DECL_LIST, F_LEN_VAR, R_RCS,
2294                 D_ALL, 0, 9, NULL},
2295
2296         {"3DSTATE_SO_BUFFER", OP_3DSTATE_SO_BUFFER, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2297                 ADDR_FIX_2(2, 4), 8, NULL},
2298
2299         {"3DSTATE_BINDING_TABLE_POOL_ALLOC",
2300                 OP_3DSTATE_BINDING_TABLE_POOL_ALLOC,
2301                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2302
2303         {"3DSTATE_GATHER_POOL_ALLOC", OP_3DSTATE_GATHER_POOL_ALLOC,
2304                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2305
2306         {"3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC",
2307                 OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC,
2308                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2309
2310         {"3DSTATE_SAMPLE_PATTERN", OP_3DSTATE_SAMPLE_PATTERN, F_LEN_VAR, R_RCS,
2311                 D_BDW_PLUS, 0, 8, NULL},
2312
2313         {"PIPE_CONTROL", OP_PIPE_CONTROL, F_LEN_VAR, R_RCS, D_ALL,
2314                 ADDR_FIX_1(2), 8, cmd_handler_pipe_control},
2315
2316         {"3DPRIMITIVE", OP_3DPRIMITIVE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2317
2318         {"PIPELINE_SELECT", OP_PIPELINE_SELECT, F_LEN_CONST, R_RCS, D_ALL, 0,
2319                 1, NULL},
2320
2321         {"STATE_PREFETCH", OP_STATE_PREFETCH, F_LEN_VAR, R_RCS, D_ALL,
2322                 ADDR_FIX_1(1), 8, NULL},
2323
2324         {"STATE_SIP", OP_STATE_SIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2325
2326         {"STATE_BASE_ADDRESS", OP_STATE_BASE_ADDRESS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2327                 ADDR_FIX_5(1, 3, 4, 5, 6), 8, NULL},
2328
2329         {"OP_3D_MEDIA_0_1_4", OP_3D_MEDIA_0_1_4, F_LEN_VAR, R_RCS, D_ALL,
2330                 ADDR_FIX_1(1), 8, NULL},
2331
2332         {"3DSTATE_VS", OP_3DSTATE_VS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2333
2334         {"3DSTATE_SF", OP_3DSTATE_SF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2335
2336         {"3DSTATE_CONSTANT_VS", OP_3DSTATE_CONSTANT_VS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2337                 0, 8, NULL},
2338
2339         {"3DSTATE_COMPONENT_PACKING", OP_3DSTATE_COMPONENT_PACKING, F_LEN_VAR, R_RCS,
2340                 D_SKL_PLUS, 0, 8, NULL},
2341
2342         {"MEDIA_INTERFACE_DESCRIPTOR_LOAD", OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD,
2343                 F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2344
2345         {"MEDIA_GATEWAY_STATE", OP_MEDIA_GATEWAY_STATE, F_LEN_VAR, R_RCS, D_ALL,
2346                 0, 16, NULL},
2347
2348         {"MEDIA_STATE_FLUSH", OP_MEDIA_STATE_FLUSH, F_LEN_VAR, R_RCS, D_ALL,
2349                 0, 16, NULL},
2350
2351         {"MEDIA_OBJECT", OP_MEDIA_OBJECT, F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2352
2353         {"MEDIA_CURBE_LOAD", OP_MEDIA_CURBE_LOAD, F_LEN_VAR, R_RCS, D_ALL,
2354                 0, 16, NULL},
2355
2356         {"MEDIA_OBJECT_PRT", OP_MEDIA_OBJECT_PRT, F_LEN_VAR, R_RCS, D_ALL,
2357                 0, 16, NULL},
2358
2359         {"MEDIA_OBJECT_WALKER", OP_MEDIA_OBJECT_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2360                 0, 16, NULL},
2361
2362         {"GPGPU_WALKER", OP_GPGPU_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2363                 0, 8, NULL},
2364
2365         {"MEDIA_VFE_STATE", OP_MEDIA_VFE_STATE, F_LEN_VAR, R_RCS, D_ALL, 0, 16,
2366                 NULL},
2367
2368         {"3DSTATE_VF_STATISTICS_GM45", OP_3DSTATE_VF_STATISTICS_GM45,
2369                 F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2370
2371         {"MFX_PIPE_MODE_SELECT", OP_MFX_PIPE_MODE_SELECT, F_LEN_VAR,
2372                 R_VCS, D_ALL, 0, 12, NULL},
2373
2374         {"MFX_SURFACE_STATE", OP_MFX_SURFACE_STATE, F_LEN_VAR,
2375                 R_VCS, D_ALL, 0, 12, NULL},
2376
2377         {"MFX_PIPE_BUF_ADDR_STATE", OP_MFX_PIPE_BUF_ADDR_STATE, F_LEN_VAR,
2378                 R_VCS, D_BDW_PLUS, 0, 12, NULL},
2379
2380         {"MFX_IND_OBJ_BASE_ADDR_STATE", OP_MFX_IND_OBJ_BASE_ADDR_STATE,
2381                 F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2382
2383         {"MFX_BSP_BUF_BASE_ADDR_STATE", OP_MFX_BSP_BUF_BASE_ADDR_STATE,
2384                 F_LEN_VAR, R_VCS, D_BDW_PLUS, ADDR_FIX_3(1, 3, 5), 12, NULL},
2385
2386         {"OP_2_0_0_5", OP_2_0_0_5, F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2387
2388         {"MFX_STATE_POINTER", OP_MFX_STATE_POINTER, F_LEN_VAR,
2389                 R_VCS, D_ALL, 0, 12, NULL},
2390
2391         {"MFX_QM_STATE", OP_MFX_QM_STATE, F_LEN_VAR,
2392                 R_VCS, D_ALL, 0, 12, NULL},
2393
2394         {"MFX_FQM_STATE", OP_MFX_FQM_STATE, F_LEN_VAR,
2395                 R_VCS, D_ALL, 0, 12, NULL},
2396
2397         {"MFX_PAK_INSERT_OBJECT", OP_MFX_PAK_INSERT_OBJECT, F_LEN_VAR,
2398                 R_VCS, D_ALL, 0, 12, NULL},
2399
2400         {"MFX_STITCH_OBJECT", OP_MFX_STITCH_OBJECT, F_LEN_VAR,
2401                 R_VCS, D_ALL, 0, 12, NULL},
2402
2403         {"MFD_IT_OBJECT", OP_MFD_IT_OBJECT, F_LEN_VAR,
2404                 R_VCS, D_ALL, 0, 12, NULL},
2405
2406         {"MFX_WAIT", OP_MFX_WAIT, F_LEN_VAR,
2407                 R_VCS, D_ALL, 0, 6, NULL},
2408
2409         {"MFX_AVC_IMG_STATE", OP_MFX_AVC_IMG_STATE, F_LEN_VAR,
2410                 R_VCS, D_ALL, 0, 12, NULL},
2411
2412         {"MFX_AVC_QM_STATE", OP_MFX_AVC_QM_STATE, F_LEN_VAR,
2413                 R_VCS, D_ALL, 0, 12, NULL},
2414
2415         {"MFX_AVC_DIRECTMODE_STATE", OP_MFX_AVC_DIRECTMODE_STATE, F_LEN_VAR,
2416                 R_VCS, D_ALL, 0, 12, NULL},
2417
2418         {"MFX_AVC_SLICE_STATE", OP_MFX_AVC_SLICE_STATE, F_LEN_VAR,
2419                 R_VCS, D_ALL, 0, 12, NULL},
2420
2421         {"MFX_AVC_REF_IDX_STATE", OP_MFX_AVC_REF_IDX_STATE, F_LEN_VAR,
2422                 R_VCS, D_ALL, 0, 12, NULL},
2423
2424         {"MFX_AVC_WEIGHTOFFSET_STATE", OP_MFX_AVC_WEIGHTOFFSET_STATE, F_LEN_VAR,
2425                 R_VCS, D_ALL, 0, 12, NULL},
2426
2427         {"MFD_AVC_PICID_STATE", OP_MFD_AVC_PICID_STATE, F_LEN_VAR,
2428                 R_VCS, D_ALL, 0, 12, NULL},
2429         {"MFD_AVC_DPB_STATE", OP_MFD_AVC_DPB_STATE, F_LEN_VAR,
2430                 R_VCS, D_ALL, 0, 12, NULL},
2431
2432         {"MFD_AVC_BSD_OBJECT", OP_MFD_AVC_BSD_OBJECT, F_LEN_VAR,
2433                 R_VCS, D_ALL, 0, 12, NULL},
2434
2435         {"MFD_AVC_SLICEADDR", OP_MFD_AVC_SLICEADDR, F_LEN_VAR,
2436                 R_VCS, D_ALL, ADDR_FIX_1(2), 12, NULL},
2437
2438         {"MFC_AVC_PAK_OBJECT", OP_MFC_AVC_PAK_OBJECT, F_LEN_VAR,
2439                 R_VCS, D_ALL, 0, 12, NULL},
2440
2441         {"MFX_VC1_PRED_PIPE_STATE", OP_MFX_VC1_PRED_PIPE_STATE, F_LEN_VAR,
2442                 R_VCS, D_ALL, 0, 12, NULL},
2443
2444         {"MFX_VC1_DIRECTMODE_STATE", OP_MFX_VC1_DIRECTMODE_STATE, F_LEN_VAR,
2445                 R_VCS, D_ALL, 0, 12, NULL},
2446
2447         {"MFD_VC1_SHORT_PIC_STATE", OP_MFD_VC1_SHORT_PIC_STATE, F_LEN_VAR,
2448                 R_VCS, D_ALL, 0, 12, NULL},
2449
2450         {"MFD_VC1_LONG_PIC_STATE", OP_MFD_VC1_LONG_PIC_STATE, F_LEN_VAR,
2451                 R_VCS, D_ALL, 0, 12, NULL},
2452
2453         {"MFD_VC1_BSD_OBJECT", OP_MFD_VC1_BSD_OBJECT, F_LEN_VAR,
2454                 R_VCS, D_ALL, 0, 12, NULL},
2455
2456         {"MFC_MPEG2_SLICEGROUP_STATE", OP_MFC_MPEG2_SLICEGROUP_STATE, F_LEN_VAR,
2457                 R_VCS, D_ALL, 0, 12, NULL},
2458
2459         {"MFC_MPEG2_PAK_OBJECT", OP_MFC_MPEG2_PAK_OBJECT, F_LEN_VAR,
2460                 R_VCS, D_ALL, 0, 12, NULL},
2461
2462         {"MFX_MPEG2_PIC_STATE", OP_MFX_MPEG2_PIC_STATE, F_LEN_VAR,
2463                 R_VCS, D_ALL, 0, 12, NULL},
2464
2465         {"MFX_MPEG2_QM_STATE", OP_MFX_MPEG2_QM_STATE, F_LEN_VAR,
2466                 R_VCS, D_ALL, 0, 12, NULL},
2467
2468         {"MFD_MPEG2_BSD_OBJECT", OP_MFD_MPEG2_BSD_OBJECT, F_LEN_VAR,
2469                 R_VCS, D_ALL, 0, 12, NULL},
2470
2471         {"MFX_2_6_0_0", OP_MFX_2_6_0_0, F_LEN_VAR, R_VCS, D_ALL,
2472                 0, 16, NULL},
2473
2474         {"MFX_2_6_0_9", OP_MFX_2_6_0_9, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2475
2476         {"MFX_2_6_0_8", OP_MFX_2_6_0_8, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2477
2478         {"MFX_JPEG_PIC_STATE", OP_MFX_JPEG_PIC_STATE, F_LEN_VAR,
2479                 R_VCS, D_ALL, 0, 12, NULL},
2480
2481         {"MFX_JPEG_HUFF_TABLE_STATE", OP_MFX_JPEG_HUFF_TABLE_STATE, F_LEN_VAR,
2482                 R_VCS, D_ALL, 0, 12, NULL},
2483
2484         {"MFD_JPEG_BSD_OBJECT", OP_MFD_JPEG_BSD_OBJECT, F_LEN_VAR,
2485                 R_VCS, D_ALL, 0, 12, NULL},
2486
2487         {"VEBOX_STATE", OP_VEB_STATE, F_LEN_VAR, R_VECS, D_ALL, 0, 12, NULL},
2488
2489         {"VEBOX_SURFACE_STATE", OP_VEB_SURFACE_STATE, F_LEN_VAR, R_VECS, D_ALL,
2490                 0, 12, NULL},
2491
2492         {"VEB_DI_IECP", OP_VEB_DNDI_IECP_STATE, F_LEN_VAR, R_VECS, D_BDW_PLUS,
2493                 0, 20, NULL},
2494 };
2495
2496 static void add_cmd_entry(struct intel_gvt *gvt, struct cmd_entry *e)
2497 {
2498         hash_add(gvt->cmd_table, &e->hlist, e->info->opcode);
2499 }
2500
2501 /* call the cmd handler, and advance ip */
2502 static int cmd_parser_exec(struct parser_exec_state *s)
2503 {
2504         struct intel_vgpu *vgpu = s->vgpu;
2505         struct cmd_info *info;
2506         u32 cmd;
2507         int ret = 0;
2508
2509         cmd = cmd_val(s, 0);
2510
2511         info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
2512         if (info == NULL) {
2513                 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",
2514                                 cmd, get_opcode(cmd, s->ring_id),
2515                                 (s->buf_addr_type == PPGTT_BUFFER) ?
2516                                 "ppgtt" : "ggtt", s->ring_id, s->workload);
2517                 return -EBADRQC;
2518         }
2519
2520         s->info = info;
2521
2522         trace_gvt_command(vgpu->id, s->ring_id, s->ip_gma, s->ip_va,
2523                           cmd_length(s), s->buf_type, s->buf_addr_type,
2524                           s->workload, info->name);
2525
2526         if (info->handler) {
2527                 ret = info->handler(s);
2528                 if (ret < 0) {
2529                         gvt_vgpu_err("%s handler error\n", info->name);
2530                         return ret;
2531                 }
2532         }
2533
2534         if (!(info->flag & F_IP_ADVANCE_CUSTOM)) {
2535                 ret = cmd_advance_default(s);
2536                 if (ret) {
2537                         gvt_vgpu_err("%s IP advance error\n", info->name);
2538                         return ret;
2539                 }
2540         }
2541         return 0;
2542 }
2543
2544 static inline bool gma_out_of_range(unsigned long gma,
2545                 unsigned long gma_head, unsigned int gma_tail)
2546 {
2547         if (gma_tail >= gma_head)
2548                 return (gma < gma_head) || (gma > gma_tail);
2549         else
2550                 return (gma > gma_tail) && (gma < gma_head);
2551 }
2552
2553 /* Keep the consistent return type, e.g EBADRQC for unknown
2554  * cmd, EFAULT for invalid address, EPERM for nonpriv. later
2555  * works as the input of VM healthy status.
2556  */
2557 static int command_scan(struct parser_exec_state *s,
2558                 unsigned long rb_head, unsigned long rb_tail,
2559                 unsigned long rb_start, unsigned long rb_len)
2560 {
2561
2562         unsigned long gma_head, gma_tail, gma_bottom;
2563         int ret = 0;
2564         struct intel_vgpu *vgpu = s->vgpu;
2565
2566         gma_head = rb_start + rb_head;
2567         gma_tail = rb_start + rb_tail;
2568         gma_bottom = rb_start +  rb_len;
2569
2570         while (s->ip_gma != gma_tail) {
2571                 if (s->buf_type == RING_BUFFER_INSTRUCTION) {
2572                         if (!(s->ip_gma >= rb_start) ||
2573                                 !(s->ip_gma < gma_bottom)) {
2574                                 gvt_vgpu_err("ip_gma %lx out of ring scope."
2575                                         "(base:0x%lx, bottom: 0x%lx)\n",
2576                                         s->ip_gma, rb_start,
2577                                         gma_bottom);
2578                                 parser_exec_state_dump(s);
2579                                 return -EFAULT;
2580                         }
2581                         if (gma_out_of_range(s->ip_gma, gma_head, gma_tail)) {
2582                                 gvt_vgpu_err("ip_gma %lx out of range."
2583                                         "base 0x%lx head 0x%lx tail 0x%lx\n",
2584                                         s->ip_gma, rb_start,
2585                                         rb_head, rb_tail);
2586                                 parser_exec_state_dump(s);
2587                                 break;
2588                         }
2589                 }
2590                 ret = cmd_parser_exec(s);
2591                 if (ret) {
2592                         gvt_vgpu_err("cmd parser error\n");
2593                         parser_exec_state_dump(s);
2594                         break;
2595                 }
2596         }
2597
2598         return ret;
2599 }
2600
2601 static int scan_workload(struct intel_vgpu_workload *workload)
2602 {
2603         unsigned long gma_head, gma_tail, gma_bottom;
2604         struct parser_exec_state s;
2605         int ret = 0;
2606
2607         /* ring base is page aligned */
2608         if (WARN_ON(!IS_ALIGNED(workload->rb_start, I915_GTT_PAGE_SIZE)))
2609                 return -EINVAL;
2610
2611         gma_head = workload->rb_start + workload->rb_head;
2612         gma_tail = workload->rb_start + workload->rb_tail;
2613         gma_bottom = workload->rb_start +  _RING_CTL_BUF_SIZE(workload->rb_ctl);
2614
2615         s.buf_type = RING_BUFFER_INSTRUCTION;
2616         s.buf_addr_type = GTT_BUFFER;
2617         s.vgpu = workload->vgpu;
2618         s.ring_id = workload->ring_id;
2619         s.ring_start = workload->rb_start;
2620         s.ring_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2621         s.ring_head = gma_head;
2622         s.ring_tail = gma_tail;
2623         s.rb_va = workload->shadow_ring_buffer_va;
2624         s.workload = workload;
2625         s.is_ctx_wa = false;
2626
2627         if ((bypass_scan_mask & (1 << workload->ring_id)) ||
2628                 gma_head == gma_tail)
2629                 return 0;
2630
2631         if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) {
2632                 ret = -EINVAL;
2633                 goto out;
2634         }
2635
2636         ret = ip_gma_set(&s, gma_head);
2637         if (ret)
2638                 goto out;
2639
2640         ret = command_scan(&s, workload->rb_head, workload->rb_tail,
2641                 workload->rb_start, _RING_CTL_BUF_SIZE(workload->rb_ctl));
2642
2643 out:
2644         return ret;
2645 }
2646
2647 static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2648 {
2649
2650         unsigned long gma_head, gma_tail, gma_bottom, ring_size, ring_tail;
2651         struct parser_exec_state s;
2652         int ret = 0;
2653         struct intel_vgpu_workload *workload = container_of(wa_ctx,
2654                                 struct intel_vgpu_workload,
2655                                 wa_ctx);
2656
2657         /* ring base is page aligned */
2658         if (WARN_ON(!IS_ALIGNED(wa_ctx->indirect_ctx.guest_gma,
2659                                         I915_GTT_PAGE_SIZE)))
2660                 return -EINVAL;
2661
2662         ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(uint32_t);
2663         ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES,
2664                         PAGE_SIZE);
2665         gma_head = wa_ctx->indirect_ctx.guest_gma;
2666         gma_tail = wa_ctx->indirect_ctx.guest_gma + ring_tail;
2667         gma_bottom = wa_ctx->indirect_ctx.guest_gma + ring_size;
2668
2669         s.buf_type = RING_BUFFER_INSTRUCTION;
2670         s.buf_addr_type = GTT_BUFFER;
2671         s.vgpu = workload->vgpu;
2672         s.ring_id = workload->ring_id;
2673         s.ring_start = wa_ctx->indirect_ctx.guest_gma;
2674         s.ring_size = ring_size;
2675         s.ring_head = gma_head;
2676         s.ring_tail = gma_tail;
2677         s.rb_va = wa_ctx->indirect_ctx.shadow_va;
2678         s.workload = workload;
2679         s.is_ctx_wa = true;
2680
2681         if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) {
2682                 ret = -EINVAL;
2683                 goto out;
2684         }
2685
2686         ret = ip_gma_set(&s, gma_head);
2687         if (ret)
2688                 goto out;
2689
2690         ret = command_scan(&s, 0, ring_tail,
2691                 wa_ctx->indirect_ctx.guest_gma, ring_size);
2692 out:
2693         return ret;
2694 }
2695
2696 static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload)
2697 {
2698         struct intel_vgpu *vgpu = workload->vgpu;
2699         struct intel_vgpu_submission *s = &vgpu->submission;
2700         unsigned long gma_head, gma_tail, gma_top, guest_rb_size;
2701         void *shadow_ring_buffer_va;
2702         int ring_id = workload->ring_id;
2703         int ret;
2704
2705         guest_rb_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2706
2707         /* calculate workload ring buffer size */
2708         workload->rb_len = (workload->rb_tail + guest_rb_size -
2709                         workload->rb_head) % guest_rb_size;
2710
2711         gma_head = workload->rb_start + workload->rb_head;
2712         gma_tail = workload->rb_start + workload->rb_tail;
2713         gma_top = workload->rb_start + guest_rb_size;
2714
2715         if (workload->rb_len > s->ring_scan_buffer_size[ring_id]) {
2716                 void *p;
2717
2718                 /* realloc the new ring buffer if needed */
2719                 p = krealloc(s->ring_scan_buffer[ring_id], workload->rb_len,
2720                                 GFP_KERNEL);
2721                 if (!p) {
2722                         gvt_vgpu_err("fail to re-alloc ring scan buffer\n");
2723                         return -ENOMEM;
2724                 }
2725                 s->ring_scan_buffer[ring_id] = p;
2726                 s->ring_scan_buffer_size[ring_id] = workload->rb_len;
2727         }
2728
2729         shadow_ring_buffer_va = s->ring_scan_buffer[ring_id];
2730
2731         /* get shadow ring buffer va */
2732         workload->shadow_ring_buffer_va = shadow_ring_buffer_va;
2733
2734         /* head > tail --> copy head <-> top */
2735         if (gma_head > gma_tail) {
2736                 ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm,
2737                                       gma_head, gma_top, shadow_ring_buffer_va);
2738                 if (ret < 0) {
2739                         gvt_vgpu_err("fail to copy guest ring buffer\n");
2740                         return ret;
2741                 }
2742                 shadow_ring_buffer_va += ret;
2743                 gma_head = workload->rb_start;
2744         }
2745
2746         /* copy head or start <-> tail */
2747         ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, gma_head, gma_tail,
2748                                 shadow_ring_buffer_va);
2749         if (ret < 0) {
2750                 gvt_vgpu_err("fail to copy guest ring buffer\n");
2751                 return ret;
2752         }
2753         return 0;
2754 }
2755
2756 int intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload *workload)
2757 {
2758         int ret;
2759         struct intel_vgpu *vgpu = workload->vgpu;
2760
2761         ret = shadow_workload_ring_buffer(workload);
2762         if (ret) {
2763                 gvt_vgpu_err("fail to shadow workload ring_buffer\n");
2764                 return ret;
2765         }
2766
2767         ret = scan_workload(workload);
2768         if (ret) {
2769                 gvt_vgpu_err("scan workload error\n");
2770                 return ret;
2771         }
2772         return 0;
2773 }
2774
2775 static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2776 {
2777         int ctx_size = wa_ctx->indirect_ctx.size;
2778         unsigned long guest_gma = wa_ctx->indirect_ctx.guest_gma;
2779         struct intel_vgpu_workload *workload = container_of(wa_ctx,
2780                                         struct intel_vgpu_workload,
2781                                         wa_ctx);
2782         struct intel_vgpu *vgpu = workload->vgpu;
2783         struct drm_i915_gem_object *obj;
2784         int ret = 0;
2785         void *map;
2786
2787         obj = i915_gem_object_create(workload->vgpu->gvt->dev_priv,
2788                                      roundup(ctx_size + CACHELINE_BYTES,
2789                                              PAGE_SIZE));
2790         if (IS_ERR(obj))
2791                 return PTR_ERR(obj);
2792
2793         /* get the va of the shadow batch buffer */
2794         map = i915_gem_object_pin_map(obj, I915_MAP_WB);
2795         if (IS_ERR(map)) {
2796                 gvt_vgpu_err("failed to vmap shadow indirect ctx\n");
2797                 ret = PTR_ERR(map);
2798                 goto put_obj;
2799         }
2800
2801         ret = i915_gem_object_set_to_cpu_domain(obj, false);
2802         if (ret) {
2803                 gvt_vgpu_err("failed to set shadow indirect ctx to CPU\n");
2804                 goto unmap_src;
2805         }
2806
2807         ret = copy_gma_to_hva(workload->vgpu,
2808                                 workload->vgpu->gtt.ggtt_mm,
2809                                 guest_gma, guest_gma + ctx_size,
2810                                 map);
2811         if (ret < 0) {
2812                 gvt_vgpu_err("fail to copy guest indirect ctx\n");
2813                 goto unmap_src;
2814         }
2815
2816         wa_ctx->indirect_ctx.obj = obj;
2817         wa_ctx->indirect_ctx.shadow_va = map;
2818         return 0;
2819
2820 unmap_src:
2821         i915_gem_object_unpin_map(obj);
2822 put_obj:
2823         i915_gem_object_put(obj);
2824         return ret;
2825 }
2826
2827 static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2828 {
2829         uint32_t per_ctx_start[CACHELINE_DWORDS] = {0};
2830         unsigned char *bb_start_sva;
2831
2832         if (!wa_ctx->per_ctx.valid)
2833                 return 0;
2834
2835         per_ctx_start[0] = 0x18800001;
2836         per_ctx_start[1] = wa_ctx->per_ctx.guest_gma;
2837
2838         bb_start_sva = (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
2839                                 wa_ctx->indirect_ctx.size;
2840
2841         memcpy(bb_start_sva, per_ctx_start, CACHELINE_BYTES);
2842
2843         return 0;
2844 }
2845
2846 int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2847 {
2848         int ret;
2849         struct intel_vgpu_workload *workload = container_of(wa_ctx,
2850                                         struct intel_vgpu_workload,
2851                                         wa_ctx);
2852         struct intel_vgpu *vgpu = workload->vgpu;
2853
2854         if (wa_ctx->indirect_ctx.size == 0)
2855                 return 0;
2856
2857         ret = shadow_indirect_ctx(wa_ctx);
2858         if (ret) {
2859                 gvt_vgpu_err("fail to shadow indirect ctx\n");
2860                 return ret;
2861         }
2862
2863         combine_wa_ctx(wa_ctx);
2864
2865         ret = scan_wa_ctx(wa_ctx);
2866         if (ret) {
2867                 gvt_vgpu_err("scan wa ctx error\n");
2868                 return ret;
2869         }
2870
2871         return 0;
2872 }
2873
2874 static struct cmd_info *find_cmd_entry_any_ring(struct intel_gvt *gvt,
2875                 unsigned int opcode, unsigned long rings)
2876 {
2877         struct cmd_info *info = NULL;
2878         unsigned int ring;
2879
2880         for_each_set_bit(ring, &rings, I915_NUM_ENGINES) {
2881                 info = find_cmd_entry(gvt, opcode, ring);
2882                 if (info)
2883                         break;
2884         }
2885         return info;
2886 }
2887
2888 static int init_cmd_table(struct intel_gvt *gvt)
2889 {
2890         int i;
2891         struct cmd_entry *e;
2892         struct cmd_info *info;
2893         unsigned int gen_type;
2894
2895         gen_type = intel_gvt_get_device_type(gvt);
2896
2897         for (i = 0; i < ARRAY_SIZE(cmd_info); i++) {
2898                 if (!(cmd_info[i].devices & gen_type))
2899                         continue;
2900
2901                 e = kzalloc(sizeof(*e), GFP_KERNEL);
2902                 if (!e)
2903                         return -ENOMEM;
2904
2905                 e->info = &cmd_info[i];
2906                 info = find_cmd_entry_any_ring(gvt,
2907                                 e->info->opcode, e->info->rings);
2908                 if (info) {
2909                         gvt_err("%s %s duplicated\n", e->info->name,
2910                                         info->name);
2911                         return -EEXIST;
2912                 }
2913
2914                 INIT_HLIST_NODE(&e->hlist);
2915                 add_cmd_entry(gvt, e);
2916                 gvt_dbg_cmd("add %-30s op %04x flag %x devs %02x rings %02x\n",
2917                                 e->info->name, e->info->opcode, e->info->flag,
2918                                 e->info->devices, e->info->rings);
2919         }
2920         return 0;
2921 }
2922
2923 static void clean_cmd_table(struct intel_gvt *gvt)
2924 {
2925         struct hlist_node *tmp;
2926         struct cmd_entry *e;
2927         int i;
2928
2929         hash_for_each_safe(gvt->cmd_table, i, tmp, e, hlist)
2930                 kfree(e);
2931
2932         hash_init(gvt->cmd_table);
2933 }
2934
2935 void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt)
2936 {
2937         clean_cmd_table(gvt);
2938 }
2939
2940 int intel_gvt_init_cmd_parser(struct intel_gvt *gvt)
2941 {
2942         int ret;
2943
2944         ret = init_cmd_table(gvt);
2945         if (ret) {
2946                 intel_gvt_clean_cmd_parser(gvt);
2947                 return ret;
2948         }
2949         return 0;
2950 }