drm/i915/gvt: do not return error on handling force_to_nonpriv registers
[muen/linux.git] / drivers / gpu / drm / i915 / gvt / cmd_parser.c
1 /*
2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21  * SOFTWARE.
22  *
23  * Authors:
24  *    Ke Yu
25  *    Kevin Tian <kevin.tian@intel.com>
26  *    Zhiyuan Lv <zhiyuan.lv@intel.com>
27  *
28  * Contributors:
29  *    Min He <min.he@intel.com>
30  *    Ping Gao <ping.a.gao@intel.com>
31  *    Tina Zhang <tina.zhang@intel.com>
32  *    Yulei Zhang <yulei.zhang@intel.com>
33  *    Zhi Wang <zhi.a.wang@intel.com>
34  *
35  */
36
37 #include <linux/slab.h>
38 #include "i915_drv.h"
39 #include "gvt.h"
40 #include "i915_pvinfo.h"
41 #include "trace.h"
42
43 #define INVALID_OP    (~0U)
44
45 #define OP_LEN_MI           9
46 #define OP_LEN_2D           10
47 #define OP_LEN_3D_MEDIA     16
48 #define OP_LEN_MFX_VC       16
49 #define OP_LEN_VEBOX        16
50
51 #define CMD_TYPE(cmd)   (((cmd) >> 29) & 7)
52
53 struct sub_op_bits {
54         int hi;
55         int low;
56 };
57 struct decode_info {
58         char *name;
59         int op_len;
60         int nr_sub_op;
61         struct sub_op_bits *sub_op;
62 };
63
64 #define   MAX_CMD_BUDGET                        0x7fffffff
65 #define   MI_WAIT_FOR_PLANE_C_FLIP_PENDING      (1<<15)
66 #define   MI_WAIT_FOR_PLANE_B_FLIP_PENDING      (1<<9)
67 #define   MI_WAIT_FOR_PLANE_A_FLIP_PENDING      (1<<1)
68
69 #define   MI_WAIT_FOR_SPRITE_C_FLIP_PENDING      (1<<20)
70 #define   MI_WAIT_FOR_SPRITE_B_FLIP_PENDING      (1<<10)
71 #define   MI_WAIT_FOR_SPRITE_A_FLIP_PENDING      (1<<2)
72
73 /* Render Command Map */
74
75 /* MI_* command Opcode (28:23) */
76 #define OP_MI_NOOP                          0x0
77 #define OP_MI_SET_PREDICATE                 0x1  /* HSW+ */
78 #define OP_MI_USER_INTERRUPT                0x2
79 #define OP_MI_WAIT_FOR_EVENT                0x3
80 #define OP_MI_FLUSH                         0x4
81 #define OP_MI_ARB_CHECK                     0x5
82 #define OP_MI_RS_CONTROL                    0x6  /* HSW+ */
83 #define OP_MI_REPORT_HEAD                   0x7
84 #define OP_MI_ARB_ON_OFF                    0x8
85 #define OP_MI_URB_ATOMIC_ALLOC              0x9  /* HSW+ */
86 #define OP_MI_BATCH_BUFFER_END              0xA
87 #define OP_MI_SUSPEND_FLUSH                 0xB
88 #define OP_MI_PREDICATE                     0xC  /* IVB+ */
89 #define OP_MI_TOPOLOGY_FILTER               0xD  /* IVB+ */
90 #define OP_MI_SET_APPID                     0xE  /* IVB+ */
91 #define OP_MI_RS_CONTEXT                    0xF  /* HSW+ */
92 #define OP_MI_LOAD_SCAN_LINES_INCL          0x12 /* HSW+ */
93 #define OP_MI_DISPLAY_FLIP                  0x14
94 #define OP_MI_SEMAPHORE_MBOX                0x16
95 #define OP_MI_SET_CONTEXT                   0x18
96 #define OP_MI_MATH                          0x1A
97 #define OP_MI_URB_CLEAR                     0x19
98 #define OP_MI_SEMAPHORE_SIGNAL              0x1B  /* BDW+ */
99 #define OP_MI_SEMAPHORE_WAIT                0x1C  /* BDW+ */
100
101 #define OP_MI_STORE_DATA_IMM                0x20
102 #define OP_MI_STORE_DATA_INDEX              0x21
103 #define OP_MI_LOAD_REGISTER_IMM             0x22
104 #define OP_MI_UPDATE_GTT                    0x23
105 #define OP_MI_STORE_REGISTER_MEM            0x24
106 #define OP_MI_FLUSH_DW                      0x26
107 #define OP_MI_CLFLUSH                       0x27
108 #define OP_MI_REPORT_PERF_COUNT             0x28
109 #define OP_MI_LOAD_REGISTER_MEM             0x29  /* HSW+ */
110 #define OP_MI_LOAD_REGISTER_REG             0x2A  /* HSW+ */
111 #define OP_MI_RS_STORE_DATA_IMM             0x2B  /* HSW+ */
112 #define OP_MI_LOAD_URB_MEM                  0x2C  /* HSW+ */
113 #define OP_MI_STORE_URM_MEM                 0x2D  /* HSW+ */
114 #define OP_MI_2E                            0x2E  /* BDW+ */
115 #define OP_MI_2F                            0x2F  /* BDW+ */
116 #define OP_MI_BATCH_BUFFER_START            0x31
117
118 /* Bit definition for dword 0 */
119 #define _CMDBIT_BB_START_IN_PPGTT       (1UL << 8)
120
121 #define OP_MI_CONDITIONAL_BATCH_BUFFER_END  0x36
122
123 #define BATCH_BUFFER_ADDR_MASK ((1UL << 32) - (1U << 2))
124 #define BATCH_BUFFER_ADDR_HIGH_MASK ((1UL << 16) - (1U))
125 #define BATCH_BUFFER_ADR_SPACE_BIT(x)   (((x) >> 8) & 1U)
126 #define BATCH_BUFFER_2ND_LEVEL_BIT(x)   ((x) >> 22 & 1U)
127
128 /* 2D command: Opcode (28:22) */
129 #define OP_2D(x)    ((2<<7) | x)
130
131 #define OP_XY_SETUP_BLT                             OP_2D(0x1)
132 #define OP_XY_SETUP_CLIP_BLT                        OP_2D(0x3)
133 #define OP_XY_SETUP_MONO_PATTERN_SL_BLT             OP_2D(0x11)
134 #define OP_XY_PIXEL_BLT                             OP_2D(0x24)
135 #define OP_XY_SCANLINES_BLT                         OP_2D(0x25)
136 #define OP_XY_TEXT_BLT                              OP_2D(0x26)
137 #define OP_XY_TEXT_IMMEDIATE_BLT                    OP_2D(0x31)
138 #define OP_XY_COLOR_BLT                             OP_2D(0x50)
139 #define OP_XY_PAT_BLT                               OP_2D(0x51)
140 #define OP_XY_MONO_PAT_BLT                          OP_2D(0x52)
141 #define OP_XY_SRC_COPY_BLT                          OP_2D(0x53)
142 #define OP_XY_MONO_SRC_COPY_BLT                     OP_2D(0x54)
143 #define OP_XY_FULL_BLT                              OP_2D(0x55)
144 #define OP_XY_FULL_MONO_SRC_BLT                     OP_2D(0x56)
145 #define OP_XY_FULL_MONO_PATTERN_BLT                 OP_2D(0x57)
146 #define OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT        OP_2D(0x58)
147 #define OP_XY_MONO_PAT_FIXED_BLT                    OP_2D(0x59)
148 #define OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT           OP_2D(0x71)
149 #define OP_XY_PAT_BLT_IMMEDIATE                     OP_2D(0x72)
150 #define OP_XY_SRC_COPY_CHROMA_BLT                   OP_2D(0x73)
151 #define OP_XY_FULL_IMMEDIATE_PATTERN_BLT            OP_2D(0x74)
152 #define OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT   OP_2D(0x75)
153 #define OP_XY_PAT_CHROMA_BLT                        OP_2D(0x76)
154 #define OP_XY_PAT_CHROMA_BLT_IMMEDIATE              OP_2D(0x77)
155
156 /* 3D/Media Command: Pipeline Type(28:27) Opcode(26:24) Sub Opcode(23:16) */
157 #define OP_3D_MEDIA(sub_type, opcode, sub_opcode) \
158         ((3 << 13) | ((sub_type) << 11) | ((opcode) << 8) | (sub_opcode))
159
160 #define OP_STATE_PREFETCH                       OP_3D_MEDIA(0x0, 0x0, 0x03)
161
162 #define OP_STATE_BASE_ADDRESS                   OP_3D_MEDIA(0x0, 0x1, 0x01)
163 #define OP_STATE_SIP                            OP_3D_MEDIA(0x0, 0x1, 0x02)
164 #define OP_3D_MEDIA_0_1_4                       OP_3D_MEDIA(0x0, 0x1, 0x04)
165
166 #define OP_3DSTATE_VF_STATISTICS_GM45           OP_3D_MEDIA(0x1, 0x0, 0x0B)
167
168 #define OP_PIPELINE_SELECT                      OP_3D_MEDIA(0x1, 0x1, 0x04)
169
170 #define OP_MEDIA_VFE_STATE                      OP_3D_MEDIA(0x2, 0x0, 0x0)
171 #define OP_MEDIA_CURBE_LOAD                     OP_3D_MEDIA(0x2, 0x0, 0x1)
172 #define OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD      OP_3D_MEDIA(0x2, 0x0, 0x2)
173 #define OP_MEDIA_GATEWAY_STATE                  OP_3D_MEDIA(0x2, 0x0, 0x3)
174 #define OP_MEDIA_STATE_FLUSH                    OP_3D_MEDIA(0x2, 0x0, 0x4)
175
176 #define OP_MEDIA_OBJECT                         OP_3D_MEDIA(0x2, 0x1, 0x0)
177 #define OP_MEDIA_OBJECT_PRT                     OP_3D_MEDIA(0x2, 0x1, 0x2)
178 #define OP_MEDIA_OBJECT_WALKER                  OP_3D_MEDIA(0x2, 0x1, 0x3)
179 #define OP_GPGPU_WALKER                         OP_3D_MEDIA(0x2, 0x1, 0x5)
180
181 #define OP_3DSTATE_CLEAR_PARAMS                 OP_3D_MEDIA(0x3, 0x0, 0x04) /* IVB+ */
182 #define OP_3DSTATE_DEPTH_BUFFER                 OP_3D_MEDIA(0x3, 0x0, 0x05) /* IVB+ */
183 #define OP_3DSTATE_STENCIL_BUFFER               OP_3D_MEDIA(0x3, 0x0, 0x06) /* IVB+ */
184 #define OP_3DSTATE_HIER_DEPTH_BUFFER            OP_3D_MEDIA(0x3, 0x0, 0x07) /* IVB+ */
185 #define OP_3DSTATE_VERTEX_BUFFERS               OP_3D_MEDIA(0x3, 0x0, 0x08)
186 #define OP_3DSTATE_VERTEX_ELEMENTS              OP_3D_MEDIA(0x3, 0x0, 0x09)
187 #define OP_3DSTATE_INDEX_BUFFER                 OP_3D_MEDIA(0x3, 0x0, 0x0A)
188 #define OP_3DSTATE_VF_STATISTICS                OP_3D_MEDIA(0x3, 0x0, 0x0B)
189 #define OP_3DSTATE_VF                           OP_3D_MEDIA(0x3, 0x0, 0x0C)  /* HSW+ */
190 #define OP_3DSTATE_CC_STATE_POINTERS            OP_3D_MEDIA(0x3, 0x0, 0x0E)
191 #define OP_3DSTATE_SCISSOR_STATE_POINTERS       OP_3D_MEDIA(0x3, 0x0, 0x0F)
192 #define OP_3DSTATE_VS                           OP_3D_MEDIA(0x3, 0x0, 0x10)
193 #define OP_3DSTATE_GS                           OP_3D_MEDIA(0x3, 0x0, 0x11)
194 #define OP_3DSTATE_CLIP                         OP_3D_MEDIA(0x3, 0x0, 0x12)
195 #define OP_3DSTATE_SF                           OP_3D_MEDIA(0x3, 0x0, 0x13)
196 #define OP_3DSTATE_WM                           OP_3D_MEDIA(0x3, 0x0, 0x14)
197 #define OP_3DSTATE_CONSTANT_VS                  OP_3D_MEDIA(0x3, 0x0, 0x15)
198 #define OP_3DSTATE_CONSTANT_GS                  OP_3D_MEDIA(0x3, 0x0, 0x16)
199 #define OP_3DSTATE_CONSTANT_PS                  OP_3D_MEDIA(0x3, 0x0, 0x17)
200 #define OP_3DSTATE_SAMPLE_MASK                  OP_3D_MEDIA(0x3, 0x0, 0x18)
201 #define OP_3DSTATE_CONSTANT_HS                  OP_3D_MEDIA(0x3, 0x0, 0x19) /* IVB+ */
202 #define OP_3DSTATE_CONSTANT_DS                  OP_3D_MEDIA(0x3, 0x0, 0x1A) /* IVB+ */
203 #define OP_3DSTATE_HS                           OP_3D_MEDIA(0x3, 0x0, 0x1B) /* IVB+ */
204 #define OP_3DSTATE_TE                           OP_3D_MEDIA(0x3, 0x0, 0x1C) /* IVB+ */
205 #define OP_3DSTATE_DS                           OP_3D_MEDIA(0x3, 0x0, 0x1D) /* IVB+ */
206 #define OP_3DSTATE_STREAMOUT                    OP_3D_MEDIA(0x3, 0x0, 0x1E) /* IVB+ */
207 #define OP_3DSTATE_SBE                          OP_3D_MEDIA(0x3, 0x0, 0x1F) /* IVB+ */
208 #define OP_3DSTATE_PS                           OP_3D_MEDIA(0x3, 0x0, 0x20) /* IVB+ */
209 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP OP_3D_MEDIA(0x3, 0x0, 0x21) /* IVB+ */
210 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC   OP_3D_MEDIA(0x3, 0x0, 0x23) /* IVB+ */
211 #define OP_3DSTATE_BLEND_STATE_POINTERS         OP_3D_MEDIA(0x3, 0x0, 0x24) /* IVB+ */
212 #define OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x25) /* IVB+ */
213 #define OP_3DSTATE_BINDING_TABLE_POINTERS_VS    OP_3D_MEDIA(0x3, 0x0, 0x26) /* IVB+ */
214 #define OP_3DSTATE_BINDING_TABLE_POINTERS_HS    OP_3D_MEDIA(0x3, 0x0, 0x27) /* IVB+ */
215 #define OP_3DSTATE_BINDING_TABLE_POINTERS_DS    OP_3D_MEDIA(0x3, 0x0, 0x28) /* IVB+ */
216 #define OP_3DSTATE_BINDING_TABLE_POINTERS_GS    OP_3D_MEDIA(0x3, 0x0, 0x29) /* IVB+ */
217 #define OP_3DSTATE_BINDING_TABLE_POINTERS_PS    OP_3D_MEDIA(0x3, 0x0, 0x2A) /* IVB+ */
218 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_VS    OP_3D_MEDIA(0x3, 0x0, 0x2B) /* IVB+ */
219 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_HS    OP_3D_MEDIA(0x3, 0x0, 0x2C) /* IVB+ */
220 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_DS    OP_3D_MEDIA(0x3, 0x0, 0x2D) /* IVB+ */
221 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_GS    OP_3D_MEDIA(0x3, 0x0, 0x2E) /* IVB+ */
222 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_PS    OP_3D_MEDIA(0x3, 0x0, 0x2F) /* IVB+ */
223 #define OP_3DSTATE_URB_VS                       OP_3D_MEDIA(0x3, 0x0, 0x30) /* IVB+ */
224 #define OP_3DSTATE_URB_HS                       OP_3D_MEDIA(0x3, 0x0, 0x31) /* IVB+ */
225 #define OP_3DSTATE_URB_DS                       OP_3D_MEDIA(0x3, 0x0, 0x32) /* IVB+ */
226 #define OP_3DSTATE_URB_GS                       OP_3D_MEDIA(0x3, 0x0, 0x33) /* IVB+ */
227 #define OP_3DSTATE_GATHER_CONSTANT_VS           OP_3D_MEDIA(0x3, 0x0, 0x34) /* HSW+ */
228 #define OP_3DSTATE_GATHER_CONSTANT_GS           OP_3D_MEDIA(0x3, 0x0, 0x35) /* HSW+ */
229 #define OP_3DSTATE_GATHER_CONSTANT_HS           OP_3D_MEDIA(0x3, 0x0, 0x36) /* HSW+ */
230 #define OP_3DSTATE_GATHER_CONSTANT_DS           OP_3D_MEDIA(0x3, 0x0, 0x37) /* HSW+ */
231 #define OP_3DSTATE_GATHER_CONSTANT_PS           OP_3D_MEDIA(0x3, 0x0, 0x38) /* HSW+ */
232 #define OP_3DSTATE_DX9_CONSTANTF_VS             OP_3D_MEDIA(0x3, 0x0, 0x39) /* HSW+ */
233 #define OP_3DSTATE_DX9_CONSTANTF_PS             OP_3D_MEDIA(0x3, 0x0, 0x3A) /* HSW+ */
234 #define OP_3DSTATE_DX9_CONSTANTI_VS             OP_3D_MEDIA(0x3, 0x0, 0x3B) /* HSW+ */
235 #define OP_3DSTATE_DX9_CONSTANTI_PS             OP_3D_MEDIA(0x3, 0x0, 0x3C) /* HSW+ */
236 #define OP_3DSTATE_DX9_CONSTANTB_VS             OP_3D_MEDIA(0x3, 0x0, 0x3D) /* HSW+ */
237 #define OP_3DSTATE_DX9_CONSTANTB_PS             OP_3D_MEDIA(0x3, 0x0, 0x3E) /* HSW+ */
238 #define OP_3DSTATE_DX9_LOCAL_VALID_VS           OP_3D_MEDIA(0x3, 0x0, 0x3F) /* HSW+ */
239 #define OP_3DSTATE_DX9_LOCAL_VALID_PS           OP_3D_MEDIA(0x3, 0x0, 0x40) /* HSW+ */
240 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_VS       OP_3D_MEDIA(0x3, 0x0, 0x41) /* HSW+ */
241 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_PS       OP_3D_MEDIA(0x3, 0x0, 0x42) /* HSW+ */
242 #define OP_3DSTATE_BINDING_TABLE_EDIT_VS        OP_3D_MEDIA(0x3, 0x0, 0x43) /* HSW+ */
243 #define OP_3DSTATE_BINDING_TABLE_EDIT_GS        OP_3D_MEDIA(0x3, 0x0, 0x44) /* HSW+ */
244 #define OP_3DSTATE_BINDING_TABLE_EDIT_HS        OP_3D_MEDIA(0x3, 0x0, 0x45) /* HSW+ */
245 #define OP_3DSTATE_BINDING_TABLE_EDIT_DS        OP_3D_MEDIA(0x3, 0x0, 0x46) /* HSW+ */
246 #define OP_3DSTATE_BINDING_TABLE_EDIT_PS        OP_3D_MEDIA(0x3, 0x0, 0x47) /* HSW+ */
247
248 #define OP_3DSTATE_VF_INSTANCING                OP_3D_MEDIA(0x3, 0x0, 0x49) /* BDW+ */
249 #define OP_3DSTATE_VF_SGVS                      OP_3D_MEDIA(0x3, 0x0, 0x4A) /* BDW+ */
250 #define OP_3DSTATE_VF_TOPOLOGY                  OP_3D_MEDIA(0x3, 0x0, 0x4B) /* BDW+ */
251 #define OP_3DSTATE_WM_CHROMAKEY                 OP_3D_MEDIA(0x3, 0x0, 0x4C) /* BDW+ */
252 #define OP_3DSTATE_PS_BLEND                     OP_3D_MEDIA(0x3, 0x0, 0x4D) /* BDW+ */
253 #define OP_3DSTATE_WM_DEPTH_STENCIL             OP_3D_MEDIA(0x3, 0x0, 0x4E) /* BDW+ */
254 #define OP_3DSTATE_PS_EXTRA                     OP_3D_MEDIA(0x3, 0x0, 0x4F) /* BDW+ */
255 #define OP_3DSTATE_RASTER                       OP_3D_MEDIA(0x3, 0x0, 0x50) /* BDW+ */
256 #define OP_3DSTATE_SBE_SWIZ                     OP_3D_MEDIA(0x3, 0x0, 0x51) /* BDW+ */
257 #define OP_3DSTATE_WM_HZ_OP                     OP_3D_MEDIA(0x3, 0x0, 0x52) /* BDW+ */
258 #define OP_3DSTATE_COMPONENT_PACKING            OP_3D_MEDIA(0x3, 0x0, 0x55) /* SKL+ */
259
260 #define OP_3DSTATE_DRAWING_RECTANGLE            OP_3D_MEDIA(0x3, 0x1, 0x00)
261 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD0        OP_3D_MEDIA(0x3, 0x1, 0x02)
262 #define OP_3DSTATE_CHROMA_KEY                   OP_3D_MEDIA(0x3, 0x1, 0x04)
263 #define OP_SNB_3DSTATE_DEPTH_BUFFER             OP_3D_MEDIA(0x3, 0x1, 0x05)
264 #define OP_3DSTATE_POLY_STIPPLE_OFFSET          OP_3D_MEDIA(0x3, 0x1, 0x06)
265 #define OP_3DSTATE_POLY_STIPPLE_PATTERN         OP_3D_MEDIA(0x3, 0x1, 0x07)
266 #define OP_3DSTATE_LINE_STIPPLE                 OP_3D_MEDIA(0x3, 0x1, 0x08)
267 #define OP_3DSTATE_AA_LINE_PARAMS               OP_3D_MEDIA(0x3, 0x1, 0x0A)
268 #define OP_3DSTATE_GS_SVB_INDEX                 OP_3D_MEDIA(0x3, 0x1, 0x0B)
269 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD1        OP_3D_MEDIA(0x3, 0x1, 0x0C)
270 #define OP_3DSTATE_MULTISAMPLE_BDW              OP_3D_MEDIA(0x3, 0x0, 0x0D)
271 #define OP_SNB_3DSTATE_STENCIL_BUFFER           OP_3D_MEDIA(0x3, 0x1, 0x0E)
272 #define OP_SNB_3DSTATE_HIER_DEPTH_BUFFER        OP_3D_MEDIA(0x3, 0x1, 0x0F)
273 #define OP_SNB_3DSTATE_CLEAR_PARAMS             OP_3D_MEDIA(0x3, 0x1, 0x10)
274 #define OP_3DSTATE_MONOFILTER_SIZE              OP_3D_MEDIA(0x3, 0x1, 0x11)
275 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS       OP_3D_MEDIA(0x3, 0x1, 0x12) /* IVB+ */
276 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS       OP_3D_MEDIA(0x3, 0x1, 0x13) /* IVB+ */
277 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS       OP_3D_MEDIA(0x3, 0x1, 0x14) /* IVB+ */
278 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS       OP_3D_MEDIA(0x3, 0x1, 0x15) /* IVB+ */
279 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS       OP_3D_MEDIA(0x3, 0x1, 0x16) /* IVB+ */
280 #define OP_3DSTATE_SO_DECL_LIST                 OP_3D_MEDIA(0x3, 0x1, 0x17)
281 #define OP_3DSTATE_SO_BUFFER                    OP_3D_MEDIA(0x3, 0x1, 0x18)
282 #define OP_3DSTATE_BINDING_TABLE_POOL_ALLOC     OP_3D_MEDIA(0x3, 0x1, 0x19) /* HSW+ */
283 #define OP_3DSTATE_GATHER_POOL_ALLOC            OP_3D_MEDIA(0x3, 0x1, 0x1A) /* HSW+ */
284 #define OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1B) /* HSW+ */
285 #define OP_3DSTATE_SAMPLE_PATTERN               OP_3D_MEDIA(0x3, 0x1, 0x1C)
286 #define OP_PIPE_CONTROL                         OP_3D_MEDIA(0x3, 0x2, 0x00)
287 #define OP_3DPRIMITIVE                          OP_3D_MEDIA(0x3, 0x3, 0x00)
288
289 /* VCCP Command Parser */
290
291 /*
292  * Below MFX and VBE cmd definition is from vaapi intel driver project (BSD License)
293  * git://anongit.freedesktop.org/vaapi/intel-driver
294  * src/i965_defines.h
295  *
296  */
297
298 #define OP_MFX(pipeline, op, sub_opa, sub_opb)     \
299         (3 << 13 | \
300          (pipeline) << 11 | \
301          (op) << 8 | \
302          (sub_opa) << 5 | \
303          (sub_opb))
304
305 #define OP_MFX_PIPE_MODE_SELECT                    OP_MFX(2, 0, 0, 0)  /* ALL */
306 #define OP_MFX_SURFACE_STATE                       OP_MFX(2, 0, 0, 1)  /* ALL */
307 #define OP_MFX_PIPE_BUF_ADDR_STATE                 OP_MFX(2, 0, 0, 2)  /* ALL */
308 #define OP_MFX_IND_OBJ_BASE_ADDR_STATE             OP_MFX(2, 0, 0, 3)  /* ALL */
309 #define OP_MFX_BSP_BUF_BASE_ADDR_STATE             OP_MFX(2, 0, 0, 4)  /* ALL */
310 #define OP_2_0_0_5                                 OP_MFX(2, 0, 0, 5)  /* ALL */
311 #define OP_MFX_STATE_POINTER                       OP_MFX(2, 0, 0, 6)  /* ALL */
312 #define OP_MFX_QM_STATE                            OP_MFX(2, 0, 0, 7)  /* IVB+ */
313 #define OP_MFX_FQM_STATE                           OP_MFX(2, 0, 0, 8)  /* IVB+ */
314 #define OP_MFX_PAK_INSERT_OBJECT                   OP_MFX(2, 0, 2, 8)  /* IVB+ */
315 #define OP_MFX_STITCH_OBJECT                       OP_MFX(2, 0, 2, 0xA)  /* IVB+ */
316
317 #define OP_MFD_IT_OBJECT                           OP_MFX(2, 0, 1, 9) /* ALL */
318
319 #define OP_MFX_WAIT                                OP_MFX(1, 0, 0, 0) /* IVB+ */
320 #define OP_MFX_AVC_IMG_STATE                       OP_MFX(2, 1, 0, 0) /* ALL */
321 #define OP_MFX_AVC_QM_STATE                        OP_MFX(2, 1, 0, 1) /* ALL */
322 #define OP_MFX_AVC_DIRECTMODE_STATE                OP_MFX(2, 1, 0, 2) /* ALL */
323 #define OP_MFX_AVC_SLICE_STATE                     OP_MFX(2, 1, 0, 3) /* ALL */
324 #define OP_MFX_AVC_REF_IDX_STATE                   OP_MFX(2, 1, 0, 4) /* ALL */
325 #define OP_MFX_AVC_WEIGHTOFFSET_STATE              OP_MFX(2, 1, 0, 5) /* ALL */
326 #define OP_MFD_AVC_PICID_STATE                     OP_MFX(2, 1, 1, 5) /* HSW+ */
327 #define OP_MFD_AVC_DPB_STATE                       OP_MFX(2, 1, 1, 6) /* IVB+ */
328 #define OP_MFD_AVC_SLICEADDR                       OP_MFX(2, 1, 1, 7) /* IVB+ */
329 #define OP_MFD_AVC_BSD_OBJECT                      OP_MFX(2, 1, 1, 8) /* ALL */
330 #define OP_MFC_AVC_PAK_OBJECT                      OP_MFX(2, 1, 2, 9) /* ALL */
331
332 #define OP_MFX_VC1_PRED_PIPE_STATE                 OP_MFX(2, 2, 0, 1) /* ALL */
333 #define OP_MFX_VC1_DIRECTMODE_STATE                OP_MFX(2, 2, 0, 2) /* ALL */
334 #define OP_MFD_VC1_SHORT_PIC_STATE                 OP_MFX(2, 2, 1, 0) /* IVB+ */
335 #define OP_MFD_VC1_LONG_PIC_STATE                  OP_MFX(2, 2, 1, 1) /* IVB+ */
336 #define OP_MFD_VC1_BSD_OBJECT                      OP_MFX(2, 2, 1, 8) /* ALL */
337
338 #define OP_MFX_MPEG2_PIC_STATE                     OP_MFX(2, 3, 0, 0) /* ALL */
339 #define OP_MFX_MPEG2_QM_STATE                      OP_MFX(2, 3, 0, 1) /* ALL */
340 #define OP_MFD_MPEG2_BSD_OBJECT                    OP_MFX(2, 3, 1, 8) /* ALL */
341 #define OP_MFC_MPEG2_SLICEGROUP_STATE              OP_MFX(2, 3, 2, 3) /* ALL */
342 #define OP_MFC_MPEG2_PAK_OBJECT                    OP_MFX(2, 3, 2, 9) /* ALL */
343
344 #define OP_MFX_2_6_0_0                             OP_MFX(2, 6, 0, 0) /* IVB+ */
345 #define OP_MFX_2_6_0_8                             OP_MFX(2, 6, 0, 8) /* IVB+ */
346 #define OP_MFX_2_6_0_9                             OP_MFX(2, 6, 0, 9) /* IVB+ */
347
348 #define OP_MFX_JPEG_PIC_STATE                      OP_MFX(2, 7, 0, 0)
349 #define OP_MFX_JPEG_HUFF_TABLE_STATE               OP_MFX(2, 7, 0, 2)
350 #define OP_MFD_JPEG_BSD_OBJECT                     OP_MFX(2, 7, 1, 8)
351
352 #define OP_VEB(pipeline, op, sub_opa, sub_opb) \
353         (3 << 13 | \
354          (pipeline) << 11 | \
355          (op) << 8 | \
356          (sub_opa) << 5 | \
357          (sub_opb))
358
359 #define OP_VEB_SURFACE_STATE                       OP_VEB(2, 4, 0, 0)
360 #define OP_VEB_STATE                               OP_VEB(2, 4, 0, 2)
361 #define OP_VEB_DNDI_IECP_STATE                     OP_VEB(2, 4, 0, 3)
362
363 struct parser_exec_state;
364
365 typedef int (*parser_cmd_handler)(struct parser_exec_state *s);
366
367 #define GVT_CMD_HASH_BITS   7
368
369 /* which DWords need address fix */
370 #define ADDR_FIX_1(x1)                  (1 << (x1))
371 #define ADDR_FIX_2(x1, x2)              (ADDR_FIX_1(x1) | ADDR_FIX_1(x2))
372 #define ADDR_FIX_3(x1, x2, x3)          (ADDR_FIX_1(x1) | ADDR_FIX_2(x2, x3))
373 #define ADDR_FIX_4(x1, x2, x3, x4)      (ADDR_FIX_1(x1) | ADDR_FIX_3(x2, x3, x4))
374 #define ADDR_FIX_5(x1, x2, x3, x4, x5)  (ADDR_FIX_1(x1) | ADDR_FIX_4(x2, x3, x4, x5))
375
376 struct cmd_info {
377         char *name;
378         u32 opcode;
379
380 #define F_LEN_MASK      (1U<<0)
381 #define F_LEN_CONST  1U
382 #define F_LEN_VAR    0U
383
384 /*
385  * command has its own ip advance logic
386  * e.g. MI_BATCH_START, MI_BATCH_END
387  */
388 #define F_IP_ADVANCE_CUSTOM (1<<1)
389
390 #define F_POST_HANDLE   (1<<2)
391         u32 flag;
392
393 #define R_RCS   (1 << RCS)
394 #define R_VCS1  (1 << VCS)
395 #define R_VCS2  (1 << VCS2)
396 #define R_VCS   (R_VCS1 | R_VCS2)
397 #define R_BCS   (1 << BCS)
398 #define R_VECS  (1 << VECS)
399 #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
400         /* rings that support this cmd: BLT/RCS/VCS/VECS */
401         uint16_t rings;
402
403         /* devices that support this cmd: SNB/IVB/HSW/... */
404         uint16_t devices;
405
406         /* which DWords are address that need fix up.
407          * bit 0 means a 32-bit non address operand in command
408          * bit 1 means address operand, which could be 32-bit
409          * or 64-bit depending on different architectures.(
410          * defined by "gmadr_bytes_in_cmd" in intel_gvt.
411          * No matter the address length, each address only takes
412          * one bit in the bitmap.
413          */
414         uint16_t addr_bitmap;
415
416         /* flag == F_LEN_CONST : command length
417          * flag == F_LEN_VAR : length bias bits
418          * Note: length is in DWord
419          */
420         uint8_t len;
421
422         parser_cmd_handler handler;
423 };
424
425 struct cmd_entry {
426         struct hlist_node hlist;
427         struct cmd_info *info;
428 };
429
430 enum {
431         RING_BUFFER_INSTRUCTION,
432         BATCH_BUFFER_INSTRUCTION,
433         BATCH_BUFFER_2ND_LEVEL,
434 };
435
436 enum {
437         GTT_BUFFER,
438         PPGTT_BUFFER
439 };
440
441 struct parser_exec_state {
442         struct intel_vgpu *vgpu;
443         int ring_id;
444
445         int buf_type;
446
447         /* batch buffer address type */
448         int buf_addr_type;
449
450         /* graphics memory address of ring buffer start */
451         unsigned long ring_start;
452         unsigned long ring_size;
453         unsigned long ring_head;
454         unsigned long ring_tail;
455
456         /* instruction graphics memory address */
457         unsigned long ip_gma;
458
459         /* mapped va of the instr_gma */
460         void *ip_va;
461         void *rb_va;
462
463         void *ret_bb_va;
464         /* next instruction when return from  batch buffer to ring buffer */
465         unsigned long ret_ip_gma_ring;
466
467         /* next instruction when return from 2nd batch buffer to batch buffer */
468         unsigned long ret_ip_gma_bb;
469
470         /* batch buffer address type (GTT or PPGTT)
471          * used when ret from 2nd level batch buffer
472          */
473         int saved_buf_addr_type;
474         bool is_ctx_wa;
475
476         struct cmd_info *info;
477
478         struct intel_vgpu_workload *workload;
479 };
480
481 #define gmadr_dw_number(s)      \
482         (s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2)
483
484 static unsigned long bypass_scan_mask = 0;
485
486 /* ring ALL, type = 0 */
487 static struct sub_op_bits sub_op_mi[] = {
488         {31, 29},
489         {28, 23},
490 };
491
492 static struct decode_info decode_info_mi = {
493         "MI",
494         OP_LEN_MI,
495         ARRAY_SIZE(sub_op_mi),
496         sub_op_mi,
497 };
498
499 /* ring RCS, command type 2 */
500 static struct sub_op_bits sub_op_2d[] = {
501         {31, 29},
502         {28, 22},
503 };
504
505 static struct decode_info decode_info_2d = {
506         "2D",
507         OP_LEN_2D,
508         ARRAY_SIZE(sub_op_2d),
509         sub_op_2d,
510 };
511
512 /* ring RCS, command type 3 */
513 static struct sub_op_bits sub_op_3d_media[] = {
514         {31, 29},
515         {28, 27},
516         {26, 24},
517         {23, 16},
518 };
519
520 static struct decode_info decode_info_3d_media = {
521         "3D_Media",
522         OP_LEN_3D_MEDIA,
523         ARRAY_SIZE(sub_op_3d_media),
524         sub_op_3d_media,
525 };
526
527 /* ring VCS, command type 3 */
528 static struct sub_op_bits sub_op_mfx_vc[] = {
529         {31, 29},
530         {28, 27},
531         {26, 24},
532         {23, 21},
533         {20, 16},
534 };
535
536 static struct decode_info decode_info_mfx_vc = {
537         "MFX_VC",
538         OP_LEN_MFX_VC,
539         ARRAY_SIZE(sub_op_mfx_vc),
540         sub_op_mfx_vc,
541 };
542
543 /* ring VECS, command type 3 */
544 static struct sub_op_bits sub_op_vebox[] = {
545         {31, 29},
546         {28, 27},
547         {26, 24},
548         {23, 21},
549         {20, 16},
550 };
551
552 static struct decode_info decode_info_vebox = {
553         "VEBOX",
554         OP_LEN_VEBOX,
555         ARRAY_SIZE(sub_op_vebox),
556         sub_op_vebox,
557 };
558
559 static struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
560         [RCS] = {
561                 &decode_info_mi,
562                 NULL,
563                 NULL,
564                 &decode_info_3d_media,
565                 NULL,
566                 NULL,
567                 NULL,
568                 NULL,
569         },
570
571         [VCS] = {
572                 &decode_info_mi,
573                 NULL,
574                 NULL,
575                 &decode_info_mfx_vc,
576                 NULL,
577                 NULL,
578                 NULL,
579                 NULL,
580         },
581
582         [BCS] = {
583                 &decode_info_mi,
584                 NULL,
585                 &decode_info_2d,
586                 NULL,
587                 NULL,
588                 NULL,
589                 NULL,
590                 NULL,
591         },
592
593         [VECS] = {
594                 &decode_info_mi,
595                 NULL,
596                 NULL,
597                 &decode_info_vebox,
598                 NULL,
599                 NULL,
600                 NULL,
601                 NULL,
602         },
603
604         [VCS2] = {
605                 &decode_info_mi,
606                 NULL,
607                 NULL,
608                 &decode_info_mfx_vc,
609                 NULL,
610                 NULL,
611                 NULL,
612                 NULL,
613         },
614 };
615
616 static inline u32 get_opcode(u32 cmd, int ring_id)
617 {
618         struct decode_info *d_info;
619
620         d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)];
621         if (d_info == NULL)
622                 return INVALID_OP;
623
624         return cmd >> (32 - d_info->op_len);
625 }
626
627 static inline struct cmd_info *find_cmd_entry(struct intel_gvt *gvt,
628                 unsigned int opcode, int ring_id)
629 {
630         struct cmd_entry *e;
631
632         hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) {
633                 if ((opcode == e->info->opcode) &&
634                                 (e->info->rings & (1 << ring_id)))
635                         return e->info;
636         }
637         return NULL;
638 }
639
640 static inline struct cmd_info *get_cmd_info(struct intel_gvt *gvt,
641                 u32 cmd, int ring_id)
642 {
643         u32 opcode;
644
645         opcode = get_opcode(cmd, ring_id);
646         if (opcode == INVALID_OP)
647                 return NULL;
648
649         return find_cmd_entry(gvt, opcode, ring_id);
650 }
651
652 static inline u32 sub_op_val(u32 cmd, u32 hi, u32 low)
653 {
654         return (cmd >> low) & ((1U << (hi - low + 1)) - 1);
655 }
656
657 static inline void print_opcode(u32 cmd, int ring_id)
658 {
659         struct decode_info *d_info;
660         int i;
661
662         d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)];
663         if (d_info == NULL)
664                 return;
665
666         gvt_dbg_cmd("opcode=0x%x %s sub_ops:",
667                         cmd >> (32 - d_info->op_len), d_info->name);
668
669         for (i = 0; i < d_info->nr_sub_op; i++)
670                 pr_err("0x%x ", sub_op_val(cmd, d_info->sub_op[i].hi,
671                                         d_info->sub_op[i].low));
672
673         pr_err("\n");
674 }
675
676 static inline u32 *cmd_ptr(struct parser_exec_state *s, int index)
677 {
678         return s->ip_va + (index << 2);
679 }
680
681 static inline u32 cmd_val(struct parser_exec_state *s, int index)
682 {
683         return *cmd_ptr(s, index);
684 }
685
686 static void parser_exec_state_dump(struct parser_exec_state *s)
687 {
688         int cnt = 0;
689         int i;
690
691         gvt_dbg_cmd("  vgpu%d RING%d: ring_start(%08lx) ring_end(%08lx)"
692                         " ring_head(%08lx) ring_tail(%08lx)\n", s->vgpu->id,
693                         s->ring_id, s->ring_start, s->ring_start + s->ring_size,
694                         s->ring_head, s->ring_tail);
695
696         gvt_dbg_cmd("  %s %s ip_gma(%08lx) ",
697                         s->buf_type == RING_BUFFER_INSTRUCTION ?
698                         "RING_BUFFER" : "BATCH_BUFFER",
699                         s->buf_addr_type == GTT_BUFFER ?
700                         "GTT" : "PPGTT", s->ip_gma);
701
702         if (s->ip_va == NULL) {
703                 gvt_dbg_cmd(" ip_va(NULL)");
704                 return;
705         }
706
707         gvt_dbg_cmd("  ip_va=%p: %08x %08x %08x %08x\n",
708                         s->ip_va, cmd_val(s, 0), cmd_val(s, 1),
709                         cmd_val(s, 2), cmd_val(s, 3));
710
711         print_opcode(cmd_val(s, 0), s->ring_id);
712
713         s->ip_va = (u32 *)((((u64)s->ip_va) >> 12) << 12);
714
715         while (cnt < 1024) {
716                 gvt_dbg_cmd("ip_va=%p: ", s->ip_va);
717                 for (i = 0; i < 8; i++)
718                         gvt_dbg_cmd("%08x ", cmd_val(s, i));
719                 gvt_dbg_cmd("\n");
720
721                 s->ip_va += 8 * sizeof(u32);
722                 cnt += 8;
723         }
724 }
725
726 static inline void update_ip_va(struct parser_exec_state *s)
727 {
728         unsigned long len = 0;
729
730         if (WARN_ON(s->ring_head == s->ring_tail))
731                 return;
732
733         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
734                 unsigned long ring_top = s->ring_start + s->ring_size;
735
736                 if (s->ring_head > s->ring_tail) {
737                         if (s->ip_gma >= s->ring_head && s->ip_gma < ring_top)
738                                 len = (s->ip_gma - s->ring_head);
739                         else if (s->ip_gma >= s->ring_start &&
740                                         s->ip_gma <= s->ring_tail)
741                                 len = (ring_top - s->ring_head) +
742                                         (s->ip_gma - s->ring_start);
743                 } else
744                         len = (s->ip_gma - s->ring_head);
745
746                 s->ip_va = s->rb_va + len;
747         } else {/* shadow batch buffer */
748                 s->ip_va = s->ret_bb_va;
749         }
750 }
751
752 static inline int ip_gma_set(struct parser_exec_state *s,
753                 unsigned long ip_gma)
754 {
755         WARN_ON(!IS_ALIGNED(ip_gma, 4));
756
757         s->ip_gma = ip_gma;
758         update_ip_va(s);
759         return 0;
760 }
761
762 static inline int ip_gma_advance(struct parser_exec_state *s,
763                 unsigned int dw_len)
764 {
765         s->ip_gma += (dw_len << 2);
766
767         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
768                 if (s->ip_gma >= s->ring_start + s->ring_size)
769                         s->ip_gma -= s->ring_size;
770                 update_ip_va(s);
771         } else {
772                 s->ip_va += (dw_len << 2);
773         }
774
775         return 0;
776 }
777
778 static inline int get_cmd_length(struct cmd_info *info, u32 cmd)
779 {
780         if ((info->flag & F_LEN_MASK) == F_LEN_CONST)
781                 return info->len;
782         else
783                 return (cmd & ((1U << info->len) - 1)) + 2;
784         return 0;
785 }
786
787 static inline int cmd_length(struct parser_exec_state *s)
788 {
789         return get_cmd_length(s->info, cmd_val(s, 0));
790 }
791
792 /* do not remove this, some platform may need clflush here */
793 #define patch_value(s, addr, val) do { \
794         *addr = val; \
795 } while (0)
796
797 static bool is_shadowed_mmio(unsigned int offset)
798 {
799         bool ret = false;
800
801         if ((offset == 0x2168) || /*BB current head register UDW */
802             (offset == 0x2140) || /*BB current header register */
803             (offset == 0x211c) || /*second BB header register UDW */
804             (offset == 0x2114)) { /*second BB header register UDW */
805                 ret = true;
806         }
807         return ret;
808 }
809
810 static inline bool is_force_nonpriv_mmio(unsigned int offset)
811 {
812         return (offset >= 0x24d0 && offset < 0x2500);
813 }
814
815 static int force_nonpriv_reg_handler(struct parser_exec_state *s,
816                                      unsigned int offset, unsigned int index)
817 {
818         struct intel_gvt *gvt = s->vgpu->gvt;
819         unsigned int data = cmd_val(s, index + 1);
820         u32 ring_base;
821         u32 nopid;
822         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
823
824         ring_base = dev_priv->engine[s->ring_id]->mmio_base;
825         nopid = i915_mmio_reg_offset(RING_NOPID(ring_base));
826
827         if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data) &&
828                         data != nopid) {
829                 gvt_err("Unexpected forcenonpriv 0x%x LRI write, value=0x%x\n",
830                         offset, data);
831                 patch_value(s, cmd_ptr(s, index), nopid);
832                 return 0;
833         }
834         return 0;
835 }
836
837 static inline bool is_mocs_mmio(unsigned int offset)
838 {
839         return ((offset >= 0xc800) && (offset <= 0xcff8)) ||
840                 ((offset >= 0xb020) && (offset <= 0xb0a0));
841 }
842
843 static int mocs_cmd_reg_handler(struct parser_exec_state *s,
844                                 unsigned int offset, unsigned int index)
845 {
846         if (!is_mocs_mmio(offset))
847                 return -EINVAL;
848         vgpu_vreg(s->vgpu, offset) = cmd_val(s, index + 1);
849         return 0;
850 }
851
852 static int cmd_reg_handler(struct parser_exec_state *s,
853         unsigned int offset, unsigned int index, char *cmd)
854 {
855         struct intel_vgpu *vgpu = s->vgpu;
856         struct intel_gvt *gvt = vgpu->gvt;
857
858         if (offset + 4 > gvt->device_info.mmio_size) {
859                 gvt_vgpu_err("%s access to (%x) outside of MMIO range\n",
860                                 cmd, offset);
861                 return -EFAULT;
862         }
863
864         if (!intel_gvt_mmio_is_cmd_access(gvt, offset)) {
865                 gvt_vgpu_err("%s access to non-render register (%x)\n",
866                                 cmd, offset);
867                 return 0;
868         }
869
870         if (is_shadowed_mmio(offset)) {
871                 gvt_vgpu_err("found access of shadowed MMIO %x\n", offset);
872                 return 0;
873         }
874
875         if (is_mocs_mmio(offset) &&
876             mocs_cmd_reg_handler(s, offset, index))
877                 return -EINVAL;
878
879         if (is_force_nonpriv_mmio(offset) &&
880                 force_nonpriv_reg_handler(s, offset, index))
881                 return -EPERM;
882
883         if (offset == i915_mmio_reg_offset(DERRMR) ||
884                 offset == i915_mmio_reg_offset(FORCEWAKE_MT)) {
885                 /* Writing to HW VGT_PVINFO_PAGE offset will be discarded */
886                 patch_value(s, cmd_ptr(s, index), VGT_PVINFO_PAGE);
887         }
888
889         /* TODO: Update the global mask if this MMIO is a masked-MMIO */
890         intel_gvt_mmio_set_cmd_accessed(gvt, offset);
891         return 0;
892 }
893
894 #define cmd_reg(s, i) \
895         (cmd_val(s, i) & GENMASK(22, 2))
896
897 #define cmd_reg_inhibit(s, i) \
898         (cmd_val(s, i) & GENMASK(22, 18))
899
900 #define cmd_gma(s, i) \
901         (cmd_val(s, i) & GENMASK(31, 2))
902
903 #define cmd_gma_hi(s, i) \
904         (cmd_val(s, i) & GENMASK(15, 0))
905
906 static int cmd_handler_lri(struct parser_exec_state *s)
907 {
908         int i, ret = 0;
909         int cmd_len = cmd_length(s);
910         struct intel_gvt *gvt = s->vgpu->gvt;
911
912         for (i = 1; i < cmd_len; i += 2) {
913                 if (IS_BROADWELL(gvt->dev_priv) &&
914                                 (s->ring_id != RCS)) {
915                         if (s->ring_id == BCS &&
916                                         cmd_reg(s, i) ==
917                                         i915_mmio_reg_offset(DERRMR))
918                                 ret |= 0;
919                         else
920                                 ret |= (cmd_reg_inhibit(s, i)) ?
921                                         -EBADRQC : 0;
922                 }
923                 if (ret)
924                         break;
925                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lri");
926                 if (ret)
927                         break;
928         }
929         return ret;
930 }
931
932 static int cmd_handler_lrr(struct parser_exec_state *s)
933 {
934         int i, ret = 0;
935         int cmd_len = cmd_length(s);
936
937         for (i = 1; i < cmd_len; i += 2) {
938                 if (IS_BROADWELL(s->vgpu->gvt->dev_priv))
939                         ret |= ((cmd_reg_inhibit(s, i) ||
940                                         (cmd_reg_inhibit(s, i + 1)))) ?
941                                 -EBADRQC : 0;
942                 if (ret)
943                         break;
944                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrr-src");
945                 if (ret)
946                         break;
947                 ret |= cmd_reg_handler(s, cmd_reg(s, i + 1), i, "lrr-dst");
948                 if (ret)
949                         break;
950         }
951         return ret;
952 }
953
954 static inline int cmd_address_audit(struct parser_exec_state *s,
955                 unsigned long guest_gma, int op_size, bool index_mode);
956
957 static int cmd_handler_lrm(struct parser_exec_state *s)
958 {
959         struct intel_gvt *gvt = s->vgpu->gvt;
960         int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
961         unsigned long gma;
962         int i, ret = 0;
963         int cmd_len = cmd_length(s);
964
965         for (i = 1; i < cmd_len;) {
966                 if (IS_BROADWELL(gvt->dev_priv))
967                         ret |= (cmd_reg_inhibit(s, i)) ? -EBADRQC : 0;
968                 if (ret)
969                         break;
970                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrm");
971                 if (ret)
972                         break;
973                 if (cmd_val(s, 0) & (1 << 22)) {
974                         gma = cmd_gma(s, i + 1);
975                         if (gmadr_bytes == 8)
976                                 gma |= (cmd_gma_hi(s, i + 2)) << 32;
977                         ret |= cmd_address_audit(s, gma, sizeof(u32), false);
978                         if (ret)
979                                 break;
980                 }
981                 i += gmadr_dw_number(s) + 1;
982         }
983         return ret;
984 }
985
986 static int cmd_handler_srm(struct parser_exec_state *s)
987 {
988         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
989         unsigned long gma;
990         int i, ret = 0;
991         int cmd_len = cmd_length(s);
992
993         for (i = 1; i < cmd_len;) {
994                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "srm");
995                 if (ret)
996                         break;
997                 if (cmd_val(s, 0) & (1 << 22)) {
998                         gma = cmd_gma(s, i + 1);
999                         if (gmadr_bytes == 8)
1000                                 gma |= (cmd_gma_hi(s, i + 2)) << 32;
1001                         ret |= cmd_address_audit(s, gma, sizeof(u32), false);
1002                         if (ret)
1003                                 break;
1004                 }
1005                 i += gmadr_dw_number(s) + 1;
1006         }
1007         return ret;
1008 }
1009
1010 struct cmd_interrupt_event {
1011         int pipe_control_notify;
1012         int mi_flush_dw;
1013         int mi_user_interrupt;
1014 };
1015
1016 static struct cmd_interrupt_event cmd_interrupt_events[] = {
1017         [RCS] = {
1018                 .pipe_control_notify = RCS_PIPE_CONTROL,
1019                 .mi_flush_dw = INTEL_GVT_EVENT_RESERVED,
1020                 .mi_user_interrupt = RCS_MI_USER_INTERRUPT,
1021         },
1022         [BCS] = {
1023                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1024                 .mi_flush_dw = BCS_MI_FLUSH_DW,
1025                 .mi_user_interrupt = BCS_MI_USER_INTERRUPT,
1026         },
1027         [VCS] = {
1028                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1029                 .mi_flush_dw = VCS_MI_FLUSH_DW,
1030                 .mi_user_interrupt = VCS_MI_USER_INTERRUPT,
1031         },
1032         [VCS2] = {
1033                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1034                 .mi_flush_dw = VCS2_MI_FLUSH_DW,
1035                 .mi_user_interrupt = VCS2_MI_USER_INTERRUPT,
1036         },
1037         [VECS] = {
1038                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1039                 .mi_flush_dw = VECS_MI_FLUSH_DW,
1040                 .mi_user_interrupt = VECS_MI_USER_INTERRUPT,
1041         },
1042 };
1043
1044 static int cmd_handler_pipe_control(struct parser_exec_state *s)
1045 {
1046         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1047         unsigned long gma;
1048         bool index_mode = false;
1049         unsigned int post_sync;
1050         int ret = 0;
1051
1052         post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14;
1053
1054         /* LRI post sync */
1055         if (cmd_val(s, 1) & PIPE_CONTROL_MMIO_WRITE)
1056                 ret = cmd_reg_handler(s, cmd_reg(s, 2), 1, "pipe_ctrl");
1057         /* post sync */
1058         else if (post_sync) {
1059                 if (post_sync == 2)
1060                         ret = cmd_reg_handler(s, 0x2350, 1, "pipe_ctrl");
1061                 else if (post_sync == 3)
1062                         ret = cmd_reg_handler(s, 0x2358, 1, "pipe_ctrl");
1063                 else if (post_sync == 1) {
1064                         /* check ggtt*/
1065                         if ((cmd_val(s, 1) & PIPE_CONTROL_GLOBAL_GTT_IVB)) {
1066                                 gma = cmd_val(s, 2) & GENMASK(31, 3);
1067                                 if (gmadr_bytes == 8)
1068                                         gma |= (cmd_gma_hi(s, 3)) << 32;
1069                                 /* Store Data Index */
1070                                 if (cmd_val(s, 1) & (1 << 21))
1071                                         index_mode = true;
1072                                 ret |= cmd_address_audit(s, gma, sizeof(u64),
1073                                                 index_mode);
1074                         }
1075                 }
1076         }
1077
1078         if (ret)
1079                 return ret;
1080
1081         if (cmd_val(s, 1) & PIPE_CONTROL_NOTIFY)
1082                 set_bit(cmd_interrupt_events[s->ring_id].pipe_control_notify,
1083                                 s->workload->pending_events);
1084         return 0;
1085 }
1086
1087 static int cmd_handler_mi_user_interrupt(struct parser_exec_state *s)
1088 {
1089         set_bit(cmd_interrupt_events[s->ring_id].mi_user_interrupt,
1090                         s->workload->pending_events);
1091         return 0;
1092 }
1093
1094 static int cmd_advance_default(struct parser_exec_state *s)
1095 {
1096         return ip_gma_advance(s, cmd_length(s));
1097 }
1098
1099 static int cmd_handler_mi_batch_buffer_end(struct parser_exec_state *s)
1100 {
1101         int ret;
1102
1103         if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1104                 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1105                 ret = ip_gma_set(s, s->ret_ip_gma_bb);
1106                 s->buf_addr_type = s->saved_buf_addr_type;
1107         } else {
1108                 s->buf_type = RING_BUFFER_INSTRUCTION;
1109                 s->buf_addr_type = GTT_BUFFER;
1110                 if (s->ret_ip_gma_ring >= s->ring_start + s->ring_size)
1111                         s->ret_ip_gma_ring -= s->ring_size;
1112                 ret = ip_gma_set(s, s->ret_ip_gma_ring);
1113         }
1114         return ret;
1115 }
1116
1117 struct mi_display_flip_command_info {
1118         int pipe;
1119         int plane;
1120         int event;
1121         i915_reg_t stride_reg;
1122         i915_reg_t ctrl_reg;
1123         i915_reg_t surf_reg;
1124         u64 stride_val;
1125         u64 tile_val;
1126         u64 surf_val;
1127         bool async_flip;
1128 };
1129
1130 struct plane_code_mapping {
1131         int pipe;
1132         int plane;
1133         int event;
1134 };
1135
1136 static int gen8_decode_mi_display_flip(struct parser_exec_state *s,
1137                 struct mi_display_flip_command_info *info)
1138 {
1139         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1140         struct plane_code_mapping gen8_plane_code[] = {
1141                 [0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE},
1142                 [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE},
1143                 [2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE},
1144                 [3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE},
1145                 [4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE},
1146                 [5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE},
1147         };
1148         u32 dword0, dword1, dword2;
1149         u32 v;
1150
1151         dword0 = cmd_val(s, 0);
1152         dword1 = cmd_val(s, 1);
1153         dword2 = cmd_val(s, 2);
1154
1155         v = (dword0 & GENMASK(21, 19)) >> 19;
1156         if (WARN_ON(v >= ARRAY_SIZE(gen8_plane_code)))
1157                 return -EBADRQC;
1158
1159         info->pipe = gen8_plane_code[v].pipe;
1160         info->plane = gen8_plane_code[v].plane;
1161         info->event = gen8_plane_code[v].event;
1162         info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1163         info->tile_val = (dword1 & 0x1);
1164         info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1165         info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1166
1167         if (info->plane == PLANE_A) {
1168                 info->ctrl_reg = DSPCNTR(info->pipe);
1169                 info->stride_reg = DSPSTRIDE(info->pipe);
1170                 info->surf_reg = DSPSURF(info->pipe);
1171         } else if (info->plane == PLANE_B) {
1172                 info->ctrl_reg = SPRCTL(info->pipe);
1173                 info->stride_reg = SPRSTRIDE(info->pipe);
1174                 info->surf_reg = SPRSURF(info->pipe);
1175         } else {
1176                 WARN_ON(1);
1177                 return -EBADRQC;
1178         }
1179         return 0;
1180 }
1181
1182 static int skl_decode_mi_display_flip(struct parser_exec_state *s,
1183                 struct mi_display_flip_command_info *info)
1184 {
1185         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1186         struct intel_vgpu *vgpu = s->vgpu;
1187         u32 dword0 = cmd_val(s, 0);
1188         u32 dword1 = cmd_val(s, 1);
1189         u32 dword2 = cmd_val(s, 2);
1190         u32 plane = (dword0 & GENMASK(12, 8)) >> 8;
1191
1192         info->plane = PRIMARY_PLANE;
1193
1194         switch (plane) {
1195         case MI_DISPLAY_FLIP_SKL_PLANE_1_A:
1196                 info->pipe = PIPE_A;
1197                 info->event = PRIMARY_A_FLIP_DONE;
1198                 break;
1199         case MI_DISPLAY_FLIP_SKL_PLANE_1_B:
1200                 info->pipe = PIPE_B;
1201                 info->event = PRIMARY_B_FLIP_DONE;
1202                 break;
1203         case MI_DISPLAY_FLIP_SKL_PLANE_1_C:
1204                 info->pipe = PIPE_C;
1205                 info->event = PRIMARY_C_FLIP_DONE;
1206                 break;
1207
1208         case MI_DISPLAY_FLIP_SKL_PLANE_2_A:
1209                 info->pipe = PIPE_A;
1210                 info->event = SPRITE_A_FLIP_DONE;
1211                 info->plane = SPRITE_PLANE;
1212                 break;
1213         case MI_DISPLAY_FLIP_SKL_PLANE_2_B:
1214                 info->pipe = PIPE_B;
1215                 info->event = SPRITE_B_FLIP_DONE;
1216                 info->plane = SPRITE_PLANE;
1217                 break;
1218         case MI_DISPLAY_FLIP_SKL_PLANE_2_C:
1219                 info->pipe = PIPE_C;
1220                 info->event = SPRITE_C_FLIP_DONE;
1221                 info->plane = SPRITE_PLANE;
1222                 break;
1223
1224         default:
1225                 gvt_vgpu_err("unknown plane code %d\n", plane);
1226                 return -EBADRQC;
1227         }
1228
1229         info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1230         info->tile_val = (dword1 & GENMASK(2, 0));
1231         info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1232         info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1233
1234         info->ctrl_reg = DSPCNTR(info->pipe);
1235         info->stride_reg = DSPSTRIDE(info->pipe);
1236         info->surf_reg = DSPSURF(info->pipe);
1237
1238         return 0;
1239 }
1240
1241 static int gen8_check_mi_display_flip(struct parser_exec_state *s,
1242                 struct mi_display_flip_command_info *info)
1243 {
1244         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1245         u32 stride, tile;
1246
1247         if (!info->async_flip)
1248                 return 0;
1249
1250         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1251                 stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);
1252                 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &
1253                                 GENMASK(12, 10)) >> 10;
1254         } else {
1255                 stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) &
1256                                 GENMASK(15, 6)) >> 6;
1257                 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;
1258         }
1259
1260         if (stride != info->stride_val)
1261                 gvt_dbg_cmd("cannot change stride during async flip\n");
1262
1263         if (tile != info->tile_val)
1264                 gvt_dbg_cmd("cannot change tile during async flip\n");
1265
1266         return 0;
1267 }
1268
1269 static int gen8_update_plane_mmio_from_mi_display_flip(
1270                 struct parser_exec_state *s,
1271                 struct mi_display_flip_command_info *info)
1272 {
1273         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1274         struct intel_vgpu *vgpu = s->vgpu;
1275
1276         set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),
1277                       info->surf_val << 12);
1278         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1279                 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),
1280                               info->stride_val);
1281                 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),
1282                               info->tile_val << 10);
1283         } else {
1284                 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6),
1285                               info->stride_val << 6);
1286                 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),
1287                               info->tile_val << 10);
1288         }
1289
1290         vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(info->pipe))++;
1291         intel_vgpu_trigger_virtual_event(vgpu, info->event);
1292         return 0;
1293 }
1294
1295 static int decode_mi_display_flip(struct parser_exec_state *s,
1296                 struct mi_display_flip_command_info *info)
1297 {
1298         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1299
1300         if (IS_BROADWELL(dev_priv))
1301                 return gen8_decode_mi_display_flip(s, info);
1302         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
1303                 return skl_decode_mi_display_flip(s, info);
1304
1305         return -ENODEV;
1306 }
1307
1308 static int check_mi_display_flip(struct parser_exec_state *s,
1309                 struct mi_display_flip_command_info *info)
1310 {
1311         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1312
1313         if (IS_BROADWELL(dev_priv)
1314                 || IS_SKYLAKE(dev_priv)
1315                 || IS_KABYLAKE(dev_priv))
1316                 return gen8_check_mi_display_flip(s, info);
1317         return -ENODEV;
1318 }
1319
1320 static int update_plane_mmio_from_mi_display_flip(
1321                 struct parser_exec_state *s,
1322                 struct mi_display_flip_command_info *info)
1323 {
1324         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1325
1326         if (IS_BROADWELL(dev_priv)
1327                 || IS_SKYLAKE(dev_priv)
1328                 || IS_KABYLAKE(dev_priv))
1329                 return gen8_update_plane_mmio_from_mi_display_flip(s, info);
1330         return -ENODEV;
1331 }
1332
1333 static int cmd_handler_mi_display_flip(struct parser_exec_state *s)
1334 {
1335         struct mi_display_flip_command_info info;
1336         struct intel_vgpu *vgpu = s->vgpu;
1337         int ret;
1338         int i;
1339         int len = cmd_length(s);
1340
1341         ret = decode_mi_display_flip(s, &info);
1342         if (ret) {
1343                 gvt_vgpu_err("fail to decode MI display flip command\n");
1344                 return ret;
1345         }
1346
1347         ret = check_mi_display_flip(s, &info);
1348         if (ret) {
1349                 gvt_vgpu_err("invalid MI display flip command\n");
1350                 return ret;
1351         }
1352
1353         ret = update_plane_mmio_from_mi_display_flip(s, &info);
1354         if (ret) {
1355                 gvt_vgpu_err("fail to update plane mmio\n");
1356                 return ret;
1357         }
1358
1359         for (i = 0; i < len; i++)
1360                 patch_value(s, cmd_ptr(s, i), MI_NOOP);
1361         return 0;
1362 }
1363
1364 static bool is_wait_for_flip_pending(u32 cmd)
1365 {
1366         return cmd & (MI_WAIT_FOR_PLANE_A_FLIP_PENDING |
1367                         MI_WAIT_FOR_PLANE_B_FLIP_PENDING |
1368                         MI_WAIT_FOR_PLANE_C_FLIP_PENDING |
1369                         MI_WAIT_FOR_SPRITE_A_FLIP_PENDING |
1370                         MI_WAIT_FOR_SPRITE_B_FLIP_PENDING |
1371                         MI_WAIT_FOR_SPRITE_C_FLIP_PENDING);
1372 }
1373
1374 static int cmd_handler_mi_wait_for_event(struct parser_exec_state *s)
1375 {
1376         u32 cmd = cmd_val(s, 0);
1377
1378         if (!is_wait_for_flip_pending(cmd))
1379                 return 0;
1380
1381         patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1382         return 0;
1383 }
1384
1385 static unsigned long get_gma_bb_from_cmd(struct parser_exec_state *s, int index)
1386 {
1387         unsigned long addr;
1388         unsigned long gma_high, gma_low;
1389         struct intel_vgpu *vgpu = s->vgpu;
1390         int gmadr_bytes = vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1391
1392         if (WARN_ON(gmadr_bytes != 4 && gmadr_bytes != 8)) {
1393                 gvt_vgpu_err("invalid gma bytes %d\n", gmadr_bytes);
1394                 return INTEL_GVT_INVALID_ADDR;
1395         }
1396
1397         gma_low = cmd_val(s, index) & BATCH_BUFFER_ADDR_MASK;
1398         if (gmadr_bytes == 4) {
1399                 addr = gma_low;
1400         } else {
1401                 gma_high = cmd_val(s, index + 1) & BATCH_BUFFER_ADDR_HIGH_MASK;
1402                 addr = (((unsigned long)gma_high) << 32) | gma_low;
1403         }
1404         return addr;
1405 }
1406
1407 static inline int cmd_address_audit(struct parser_exec_state *s,
1408                 unsigned long guest_gma, int op_size, bool index_mode)
1409 {
1410         struct intel_vgpu *vgpu = s->vgpu;
1411         u32 max_surface_size = vgpu->gvt->device_info.max_surface_size;
1412         int i;
1413         int ret;
1414
1415         if (op_size > max_surface_size) {
1416                 gvt_vgpu_err("command address audit fail name %s\n",
1417                         s->info->name);
1418                 return -EFAULT;
1419         }
1420
1421         if (index_mode) {
1422                 if (guest_gma >= I915_GTT_PAGE_SIZE / sizeof(u64)) {
1423                         ret = -EFAULT;
1424                         goto err;
1425                 }
1426         } else if (!intel_gvt_ggtt_validate_range(vgpu, guest_gma, op_size)) {
1427                 ret = -EFAULT;
1428                 goto err;
1429         }
1430
1431         return 0;
1432
1433 err:
1434         gvt_vgpu_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n",
1435                         s->info->name, guest_gma, op_size);
1436
1437         pr_err("cmd dump: ");
1438         for (i = 0; i < cmd_length(s); i++) {
1439                 if (!(i % 4))
1440                         pr_err("\n%08x ", cmd_val(s, i));
1441                 else
1442                         pr_err("%08x ", cmd_val(s, i));
1443         }
1444         pr_err("\nvgpu%d: aperture 0x%llx - 0x%llx, hidden 0x%llx - 0x%llx\n",
1445                         vgpu->id,
1446                         vgpu_aperture_gmadr_base(vgpu),
1447                         vgpu_aperture_gmadr_end(vgpu),
1448                         vgpu_hidden_gmadr_base(vgpu),
1449                         vgpu_hidden_gmadr_end(vgpu));
1450         return ret;
1451 }
1452
1453 static int cmd_handler_mi_store_data_imm(struct parser_exec_state *s)
1454 {
1455         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1456         int op_size = (cmd_length(s) - 3) * sizeof(u32);
1457         int core_id = (cmd_val(s, 2) & (1 << 0)) ? 1 : 0;
1458         unsigned long gma, gma_low, gma_high;
1459         int ret = 0;
1460
1461         /* check ppggt */
1462         if (!(cmd_val(s, 0) & (1 << 22)))
1463                 return 0;
1464
1465         gma = cmd_val(s, 2) & GENMASK(31, 2);
1466
1467         if (gmadr_bytes == 8) {
1468                 gma_low = cmd_val(s, 1) & GENMASK(31, 2);
1469                 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1470                 gma = (gma_high << 32) | gma_low;
1471                 core_id = (cmd_val(s, 1) & (1 << 0)) ? 1 : 0;
1472         }
1473         ret = cmd_address_audit(s, gma + op_size * core_id, op_size, false);
1474         return ret;
1475 }
1476
1477 static inline int unexpected_cmd(struct parser_exec_state *s)
1478 {
1479         struct intel_vgpu *vgpu = s->vgpu;
1480
1481         gvt_vgpu_err("Unexpected %s in command buffer!\n", s->info->name);
1482
1483         return -EBADRQC;
1484 }
1485
1486 static int cmd_handler_mi_semaphore_wait(struct parser_exec_state *s)
1487 {
1488         return unexpected_cmd(s);
1489 }
1490
1491 static int cmd_handler_mi_report_perf_count(struct parser_exec_state *s)
1492 {
1493         return unexpected_cmd(s);
1494 }
1495
1496 static int cmd_handler_mi_op_2e(struct parser_exec_state *s)
1497 {
1498         return unexpected_cmd(s);
1499 }
1500
1501 static int cmd_handler_mi_op_2f(struct parser_exec_state *s)
1502 {
1503         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1504         int op_size = (1 << ((cmd_val(s, 0) & GENMASK(20, 19)) >> 19)) *
1505                         sizeof(u32);
1506         unsigned long gma, gma_high;
1507         int ret = 0;
1508
1509         if (!(cmd_val(s, 0) & (1 << 22)))
1510                 return ret;
1511
1512         gma = cmd_val(s, 1) & GENMASK(31, 2);
1513         if (gmadr_bytes == 8) {
1514                 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1515                 gma = (gma_high << 32) | gma;
1516         }
1517         ret = cmd_address_audit(s, gma, op_size, false);
1518         return ret;
1519 }
1520
1521 static int cmd_handler_mi_store_data_index(struct parser_exec_state *s)
1522 {
1523         return unexpected_cmd(s);
1524 }
1525
1526 static int cmd_handler_mi_clflush(struct parser_exec_state *s)
1527 {
1528         return unexpected_cmd(s);
1529 }
1530
1531 static int cmd_handler_mi_conditional_batch_buffer_end(
1532                 struct parser_exec_state *s)
1533 {
1534         return unexpected_cmd(s);
1535 }
1536
1537 static int cmd_handler_mi_update_gtt(struct parser_exec_state *s)
1538 {
1539         return unexpected_cmd(s);
1540 }
1541
1542 static int cmd_handler_mi_flush_dw(struct parser_exec_state *s)
1543 {
1544         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1545         unsigned long gma;
1546         bool index_mode = false;
1547         int ret = 0;
1548
1549         /* Check post-sync and ppgtt bit */
1550         if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) {
1551                 gma = cmd_val(s, 1) & GENMASK(31, 3);
1552                 if (gmadr_bytes == 8)
1553                         gma |= (cmd_val(s, 2) & GENMASK(15, 0)) << 32;
1554                 /* Store Data Index */
1555                 if (cmd_val(s, 0) & (1 << 21))
1556                         index_mode = true;
1557                 ret = cmd_address_audit(s, gma, sizeof(u64), index_mode);
1558         }
1559         /* Check notify bit */
1560         if ((cmd_val(s, 0) & (1 << 8)))
1561                 set_bit(cmd_interrupt_events[s->ring_id].mi_flush_dw,
1562                                 s->workload->pending_events);
1563         return ret;
1564 }
1565
1566 static void addr_type_update_snb(struct parser_exec_state *s)
1567 {
1568         if ((s->buf_type == RING_BUFFER_INSTRUCTION) &&
1569                         (BATCH_BUFFER_ADR_SPACE_BIT(cmd_val(s, 0)) == 1)) {
1570                 s->buf_addr_type = PPGTT_BUFFER;
1571         }
1572 }
1573
1574
1575 static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm,
1576                 unsigned long gma, unsigned long end_gma, void *va)
1577 {
1578         unsigned long copy_len, offset;
1579         unsigned long len = 0;
1580         unsigned long gpa;
1581
1582         while (gma != end_gma) {
1583                 gpa = intel_vgpu_gma_to_gpa(mm, gma);
1584                 if (gpa == INTEL_GVT_INVALID_ADDR) {
1585                         gvt_vgpu_err("invalid gma address: %lx\n", gma);
1586                         return -EFAULT;
1587                 }
1588
1589                 offset = gma & (I915_GTT_PAGE_SIZE - 1);
1590
1591                 copy_len = (end_gma - gma) >= (I915_GTT_PAGE_SIZE - offset) ?
1592                         I915_GTT_PAGE_SIZE - offset : end_gma - gma;
1593
1594                 intel_gvt_hypervisor_read_gpa(vgpu, gpa, va + len, copy_len);
1595
1596                 len += copy_len;
1597                 gma += copy_len;
1598         }
1599         return len;
1600 }
1601
1602
1603 /*
1604  * Check whether a batch buffer needs to be scanned. Currently
1605  * the only criteria is based on privilege.
1606  */
1607 static int batch_buffer_needs_scan(struct parser_exec_state *s)
1608 {
1609         struct intel_gvt *gvt = s->vgpu->gvt;
1610
1611         if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)
1612                 || IS_KABYLAKE(gvt->dev_priv)) {
1613                 /* BDW decides privilege based on address space */
1614                 if (cmd_val(s, 0) & (1 << 8) &&
1615                         !(s->vgpu->scan_nonprivbb & (1 << s->ring_id)))
1616                         return 0;
1617         }
1618         return 1;
1619 }
1620
1621 static int find_bb_size(struct parser_exec_state *s, unsigned long *bb_size)
1622 {
1623         unsigned long gma = 0;
1624         struct cmd_info *info;
1625         uint32_t cmd_len = 0;
1626         bool bb_end = false;
1627         struct intel_vgpu *vgpu = s->vgpu;
1628         u32 cmd;
1629         struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1630                 s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1631
1632         *bb_size = 0;
1633
1634         /* get the start gm address of the batch buffer */
1635         gma = get_gma_bb_from_cmd(s, 1);
1636         if (gma == INTEL_GVT_INVALID_ADDR)
1637                 return -EFAULT;
1638
1639         cmd = cmd_val(s, 0);
1640         info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
1641         if (info == NULL) {
1642                 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",
1643                                 cmd, get_opcode(cmd, s->ring_id),
1644                                 (s->buf_addr_type == PPGTT_BUFFER) ?
1645                                 "ppgtt" : "ggtt", s->ring_id, s->workload);
1646                 return -EBADRQC;
1647         }
1648         do {
1649                 if (copy_gma_to_hva(s->vgpu, mm,
1650                                 gma, gma + 4, &cmd) < 0)
1651                         return -EFAULT;
1652                 info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
1653                 if (info == NULL) {
1654                         gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",
1655                                 cmd, get_opcode(cmd, s->ring_id),
1656                                 (s->buf_addr_type == PPGTT_BUFFER) ?
1657                                 "ppgtt" : "ggtt", s->ring_id, s->workload);
1658                         return -EBADRQC;
1659                 }
1660
1661                 if (info->opcode == OP_MI_BATCH_BUFFER_END) {
1662                         bb_end = true;
1663                 } else if (info->opcode == OP_MI_BATCH_BUFFER_START) {
1664                         if (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0)
1665                                 /* chained batch buffer */
1666                                 bb_end = true;
1667                 }
1668                 cmd_len = get_cmd_length(info, cmd) << 2;
1669                 *bb_size += cmd_len;
1670                 gma += cmd_len;
1671         } while (!bb_end);
1672
1673         return 0;
1674 }
1675
1676 static int perform_bb_shadow(struct parser_exec_state *s)
1677 {
1678         struct intel_vgpu *vgpu = s->vgpu;
1679         struct intel_vgpu_shadow_bb *bb;
1680         unsigned long gma = 0;
1681         unsigned long bb_size;
1682         int ret = 0;
1683         struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1684                 s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1685         unsigned long gma_start_offset = 0;
1686
1687         /* get the start gm address of the batch buffer */
1688         gma = get_gma_bb_from_cmd(s, 1);
1689         if (gma == INTEL_GVT_INVALID_ADDR)
1690                 return -EFAULT;
1691
1692         ret = find_bb_size(s, &bb_size);
1693         if (ret)
1694                 return ret;
1695
1696         bb = kzalloc(sizeof(*bb), GFP_KERNEL);
1697         if (!bb)
1698                 return -ENOMEM;
1699
1700         bb->ppgtt = (s->buf_addr_type == GTT_BUFFER) ? false : true;
1701
1702         /* the gma_start_offset stores the batch buffer's start gma's
1703          * offset relative to page boundary. so for non-privileged batch
1704          * buffer, the shadowed gem object holds exactly the same page
1705          * layout as original gem object. This is for the convience of
1706          * replacing the whole non-privilged batch buffer page to this
1707          * shadowed one in PPGTT at the same gma address. (this replacing
1708          * action is not implemented yet now, but may be necessary in
1709          * future).
1710          * for prileged batch buffer, we just change start gma address to
1711          * that of shadowed page.
1712          */
1713         if (bb->ppgtt)
1714                 gma_start_offset = gma & ~I915_GTT_PAGE_MASK;
1715
1716         bb->obj = i915_gem_object_create(s->vgpu->gvt->dev_priv,
1717                          roundup(bb_size + gma_start_offset, PAGE_SIZE));
1718         if (IS_ERR(bb->obj)) {
1719                 ret = PTR_ERR(bb->obj);
1720                 goto err_free_bb;
1721         }
1722
1723         ret = i915_gem_obj_prepare_shmem_write(bb->obj, &bb->clflush);
1724         if (ret)
1725                 goto err_free_obj;
1726
1727         bb->va = i915_gem_object_pin_map(bb->obj, I915_MAP_WB);
1728         if (IS_ERR(bb->va)) {
1729                 ret = PTR_ERR(bb->va);
1730                 goto err_finish_shmem_access;
1731         }
1732
1733         if (bb->clflush & CLFLUSH_BEFORE) {
1734                 drm_clflush_virt_range(bb->va, bb->obj->base.size);
1735                 bb->clflush &= ~CLFLUSH_BEFORE;
1736         }
1737
1738         ret = copy_gma_to_hva(s->vgpu, mm,
1739                               gma, gma + bb_size,
1740                               bb->va + gma_start_offset);
1741         if (ret < 0) {
1742                 gvt_vgpu_err("fail to copy guest ring buffer\n");
1743                 ret = -EFAULT;
1744                 goto err_unmap;
1745         }
1746
1747         INIT_LIST_HEAD(&bb->list);
1748         list_add(&bb->list, &s->workload->shadow_bb);
1749
1750         bb->accessing = true;
1751         bb->bb_start_cmd_va = s->ip_va;
1752
1753         if ((s->buf_type == BATCH_BUFFER_INSTRUCTION) && (!s->is_ctx_wa))
1754                 bb->bb_offset = s->ip_va - s->rb_va;
1755         else
1756                 bb->bb_offset = 0;
1757
1758         /*
1759          * ip_va saves the virtual address of the shadow batch buffer, while
1760          * ip_gma saves the graphics address of the original batch buffer.
1761          * As the shadow batch buffer is just a copy from the originial one,
1762          * it should be right to use shadow batch buffer'va and original batch
1763          * buffer's gma in pair. After all, we don't want to pin the shadow
1764          * buffer here (too early).
1765          */
1766         s->ip_va = bb->va + gma_start_offset;
1767         s->ip_gma = gma;
1768         return 0;
1769 err_unmap:
1770         i915_gem_object_unpin_map(bb->obj);
1771 err_finish_shmem_access:
1772         i915_gem_obj_finish_shmem_access(bb->obj);
1773 err_free_obj:
1774         i915_gem_object_put(bb->obj);
1775 err_free_bb:
1776         kfree(bb);
1777         return ret;
1778 }
1779
1780 static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s)
1781 {
1782         bool second_level;
1783         int ret = 0;
1784         struct intel_vgpu *vgpu = s->vgpu;
1785
1786         if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1787                 gvt_vgpu_err("Found MI_BATCH_BUFFER_START in 2nd level BB\n");
1788                 return -EFAULT;
1789         }
1790
1791         second_level = BATCH_BUFFER_2ND_LEVEL_BIT(cmd_val(s, 0)) == 1;
1792         if (second_level && (s->buf_type != BATCH_BUFFER_INSTRUCTION)) {
1793                 gvt_vgpu_err("Jumping to 2nd level BB from RB is not allowed\n");
1794                 return -EFAULT;
1795         }
1796
1797         s->saved_buf_addr_type = s->buf_addr_type;
1798         addr_type_update_snb(s);
1799         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
1800                 s->ret_ip_gma_ring = s->ip_gma + cmd_length(s) * sizeof(u32);
1801                 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1802         } else if (second_level) {
1803                 s->buf_type = BATCH_BUFFER_2ND_LEVEL;
1804                 s->ret_ip_gma_bb = s->ip_gma + cmd_length(s) * sizeof(u32);
1805                 s->ret_bb_va = s->ip_va + cmd_length(s) * sizeof(u32);
1806         }
1807
1808         if (batch_buffer_needs_scan(s)) {
1809                 ret = perform_bb_shadow(s);
1810                 if (ret < 0)
1811                         gvt_vgpu_err("invalid shadow batch buffer\n");
1812         } else {
1813                 /* emulate a batch buffer end to do return right */
1814                 ret = cmd_handler_mi_batch_buffer_end(s);
1815                 if (ret < 0)
1816                         return ret;
1817         }
1818         return ret;
1819 }
1820
1821 static struct cmd_info cmd_info[] = {
1822         {"MI_NOOP", OP_MI_NOOP, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
1823
1824         {"MI_SET_PREDICATE", OP_MI_SET_PREDICATE, F_LEN_CONST, R_ALL, D_ALL,
1825                 0, 1, NULL},
1826
1827         {"MI_USER_INTERRUPT", OP_MI_USER_INTERRUPT, F_LEN_CONST, R_ALL, D_ALL,
1828                 0, 1, cmd_handler_mi_user_interrupt},
1829
1830         {"MI_WAIT_FOR_EVENT", OP_MI_WAIT_FOR_EVENT, F_LEN_CONST, R_RCS | R_BCS,
1831                 D_ALL, 0, 1, cmd_handler_mi_wait_for_event},
1832
1833         {"MI_FLUSH", OP_MI_FLUSH, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
1834
1835         {"MI_ARB_CHECK", OP_MI_ARB_CHECK, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1836                 NULL},
1837
1838         {"MI_RS_CONTROL", OP_MI_RS_CONTROL, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1839                 NULL},
1840
1841         {"MI_REPORT_HEAD", OP_MI_REPORT_HEAD, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1842                 NULL},
1843
1844         {"MI_ARB_ON_OFF", OP_MI_ARB_ON_OFF, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1845                 NULL},
1846
1847         {"MI_URB_ATOMIC_ALLOC", OP_MI_URB_ATOMIC_ALLOC, F_LEN_CONST, R_RCS,
1848                 D_ALL, 0, 1, NULL},
1849
1850         {"MI_BATCH_BUFFER_END", OP_MI_BATCH_BUFFER_END,
1851                 F_IP_ADVANCE_CUSTOM | F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1852                 cmd_handler_mi_batch_buffer_end},
1853
1854         {"MI_SUSPEND_FLUSH", OP_MI_SUSPEND_FLUSH, F_LEN_CONST, R_ALL, D_ALL,
1855                 0, 1, NULL},
1856
1857         {"MI_PREDICATE", OP_MI_PREDICATE, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1858                 NULL},
1859
1860         {"MI_TOPOLOGY_FILTER", OP_MI_TOPOLOGY_FILTER, F_LEN_CONST, R_ALL,
1861                 D_ALL, 0, 1, NULL},
1862
1863         {"MI_SET_APPID", OP_MI_SET_APPID, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1864                 NULL},
1865
1866         {"MI_RS_CONTEXT", OP_MI_RS_CONTEXT, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1867                 NULL},
1868
1869         {"MI_DISPLAY_FLIP", OP_MI_DISPLAY_FLIP, F_LEN_VAR | F_POST_HANDLE,
1870                 R_RCS | R_BCS, D_ALL, 0, 8, cmd_handler_mi_display_flip},
1871
1872         {"MI_SEMAPHORE_MBOX", OP_MI_SEMAPHORE_MBOX, F_LEN_VAR, R_ALL, D_ALL,
1873                 0, 8, NULL},
1874
1875         {"MI_MATH", OP_MI_MATH, F_LEN_VAR, R_ALL, D_ALL, 0, 8, NULL},
1876
1877         {"MI_URB_CLEAR", OP_MI_URB_CLEAR, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1878
1879         {"ME_SEMAPHORE_SIGNAL", OP_MI_SEMAPHORE_SIGNAL, F_LEN_VAR, R_ALL,
1880                 D_BDW_PLUS, 0, 8, NULL},
1881
1882         {"ME_SEMAPHORE_WAIT", OP_MI_SEMAPHORE_WAIT, F_LEN_VAR, R_ALL, D_BDW_PLUS,
1883                 ADDR_FIX_1(2), 8, cmd_handler_mi_semaphore_wait},
1884
1885         {"MI_STORE_DATA_IMM", OP_MI_STORE_DATA_IMM, F_LEN_VAR, R_ALL, D_BDW_PLUS,
1886                 ADDR_FIX_1(1), 10, cmd_handler_mi_store_data_imm},
1887
1888         {"MI_STORE_DATA_INDEX", OP_MI_STORE_DATA_INDEX, F_LEN_VAR, R_ALL, D_ALL,
1889                 0, 8, cmd_handler_mi_store_data_index},
1890
1891         {"MI_LOAD_REGISTER_IMM", OP_MI_LOAD_REGISTER_IMM, F_LEN_VAR, R_ALL,
1892                 D_ALL, 0, 8, cmd_handler_lri},
1893
1894         {"MI_UPDATE_GTT", OP_MI_UPDATE_GTT, F_LEN_VAR, R_ALL, D_BDW_PLUS, 0, 10,
1895                 cmd_handler_mi_update_gtt},
1896
1897         {"MI_STORE_REGISTER_MEM", OP_MI_STORE_REGISTER_MEM, F_LEN_VAR, R_ALL,
1898                 D_ALL, ADDR_FIX_1(2), 8, cmd_handler_srm},
1899
1900         {"MI_FLUSH_DW", OP_MI_FLUSH_DW, F_LEN_VAR, R_ALL, D_ALL, 0, 6,
1901                 cmd_handler_mi_flush_dw},
1902
1903         {"MI_CLFLUSH", OP_MI_CLFLUSH, F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(1),
1904                 10, cmd_handler_mi_clflush},
1905
1906         {"MI_REPORT_PERF_COUNT", OP_MI_REPORT_PERF_COUNT, F_LEN_VAR, R_ALL,
1907                 D_ALL, ADDR_FIX_1(1), 6, cmd_handler_mi_report_perf_count},
1908
1909         {"MI_LOAD_REGISTER_MEM", OP_MI_LOAD_REGISTER_MEM, F_LEN_VAR, R_ALL,
1910                 D_ALL, ADDR_FIX_1(2), 8, cmd_handler_lrm},
1911
1912         {"MI_LOAD_REGISTER_REG", OP_MI_LOAD_REGISTER_REG, F_LEN_VAR, R_ALL,
1913                 D_ALL, 0, 8, cmd_handler_lrr},
1914
1915         {"MI_RS_STORE_DATA_IMM", OP_MI_RS_STORE_DATA_IMM, F_LEN_VAR, R_RCS,
1916                 D_ALL, 0, 8, NULL},
1917
1918         {"MI_LOAD_URB_MEM", OP_MI_LOAD_URB_MEM, F_LEN_VAR, R_RCS, D_ALL,
1919                 ADDR_FIX_1(2), 8, NULL},
1920
1921         {"MI_STORE_URM_MEM", OP_MI_STORE_URM_MEM, F_LEN_VAR, R_RCS, D_ALL,
1922                 ADDR_FIX_1(2), 8, NULL},
1923
1924         {"MI_OP_2E", OP_MI_2E, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_2(1, 2),
1925                 8, cmd_handler_mi_op_2e},
1926
1927         {"MI_OP_2F", OP_MI_2F, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_1(1),
1928                 8, cmd_handler_mi_op_2f},
1929
1930         {"MI_BATCH_BUFFER_START", OP_MI_BATCH_BUFFER_START,
1931                 F_IP_ADVANCE_CUSTOM, R_ALL, D_ALL, 0, 8,
1932                 cmd_handler_mi_batch_buffer_start},
1933
1934         {"MI_CONDITIONAL_BATCH_BUFFER_END", OP_MI_CONDITIONAL_BATCH_BUFFER_END,
1935                 F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
1936                 cmd_handler_mi_conditional_batch_buffer_end},
1937
1938         {"MI_LOAD_SCAN_LINES_INCL", OP_MI_LOAD_SCAN_LINES_INCL, F_LEN_CONST,
1939                 R_RCS | R_BCS, D_ALL, 0, 2, NULL},
1940
1941         {"XY_SETUP_BLT", OP_XY_SETUP_BLT, F_LEN_VAR, R_BCS, D_ALL,
1942                 ADDR_FIX_2(4, 7), 8, NULL},
1943
1944         {"XY_SETUP_CLIP_BLT", OP_XY_SETUP_CLIP_BLT, F_LEN_VAR, R_BCS, D_ALL,
1945                 0, 8, NULL},
1946
1947         {"XY_SETUP_MONO_PATTERN_SL_BLT", OP_XY_SETUP_MONO_PATTERN_SL_BLT,
1948                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
1949
1950         {"XY_PIXEL_BLT", OP_XY_PIXEL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
1951
1952         {"XY_SCANLINES_BLT", OP_XY_SCANLINES_BLT, F_LEN_VAR, R_BCS, D_ALL,
1953                 0, 8, NULL},
1954
1955         {"XY_TEXT_BLT", OP_XY_TEXT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1956                 ADDR_FIX_1(3), 8, NULL},
1957
1958         {"XY_TEXT_IMMEDIATE_BLT", OP_XY_TEXT_IMMEDIATE_BLT, F_LEN_VAR, R_BCS,
1959                 D_ALL, 0, 8, NULL},
1960
1961         {"XY_COLOR_BLT", OP_XY_COLOR_BLT, F_LEN_VAR, R_BCS, D_ALL,
1962                 ADDR_FIX_1(4), 8, NULL},
1963
1964         {"XY_PAT_BLT", OP_XY_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1965                 ADDR_FIX_2(4, 5), 8, NULL},
1966
1967         {"XY_MONO_PAT_BLT", OP_XY_MONO_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1968                 ADDR_FIX_1(4), 8, NULL},
1969
1970         {"XY_SRC_COPY_BLT", OP_XY_SRC_COPY_BLT, F_LEN_VAR, R_BCS, D_ALL,
1971                 ADDR_FIX_2(4, 7), 8, NULL},
1972
1973         {"XY_MONO_SRC_COPY_BLT", OP_XY_MONO_SRC_COPY_BLT, F_LEN_VAR, R_BCS,
1974                 D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
1975
1976         {"XY_FULL_BLT", OP_XY_FULL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
1977
1978         {"XY_FULL_MONO_SRC_BLT", OP_XY_FULL_MONO_SRC_BLT, F_LEN_VAR, R_BCS,
1979                 D_ALL, ADDR_FIX_3(4, 5, 8), 8, NULL},
1980
1981         {"XY_FULL_MONO_PATTERN_BLT", OP_XY_FULL_MONO_PATTERN_BLT, F_LEN_VAR,
1982                 R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
1983
1984         {"XY_FULL_MONO_PATTERN_MONO_SRC_BLT",
1985                 OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT,
1986                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
1987
1988         {"XY_MONO_PAT_FIXED_BLT", OP_XY_MONO_PAT_FIXED_BLT, F_LEN_VAR, R_BCS,
1989                 D_ALL, ADDR_FIX_1(4), 8, NULL},
1990
1991         {"XY_MONO_SRC_COPY_IMMEDIATE_BLT", OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT,
1992                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
1993
1994         {"XY_PAT_BLT_IMMEDIATE", OP_XY_PAT_BLT_IMMEDIATE, F_LEN_VAR, R_BCS,
1995                 D_ALL, ADDR_FIX_1(4), 8, NULL},
1996
1997         {"XY_SRC_COPY_CHROMA_BLT", OP_XY_SRC_COPY_CHROMA_BLT, F_LEN_VAR, R_BCS,
1998                 D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
1999
2000         {"XY_FULL_IMMEDIATE_PATTERN_BLT", OP_XY_FULL_IMMEDIATE_PATTERN_BLT,
2001                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2002
2003         {"XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT",
2004                 OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT,
2005                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2006
2007         {"XY_PAT_CHROMA_BLT", OP_XY_PAT_CHROMA_BLT, F_LEN_VAR, R_BCS, D_ALL,
2008                 ADDR_FIX_2(4, 5), 8, NULL},
2009
2010         {"XY_PAT_CHROMA_BLT_IMMEDIATE", OP_XY_PAT_CHROMA_BLT_IMMEDIATE,
2011                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2012
2013         {"3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP",
2014                 OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP,
2015                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2016
2017         {"3DSTATE_VIEWPORT_STATE_POINTERS_CC",
2018                 OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
2019                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2020
2021         {"3DSTATE_BLEND_STATE_POINTERS",
2022                 OP_3DSTATE_BLEND_STATE_POINTERS,
2023                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2024
2025         {"3DSTATE_DEPTH_STENCIL_STATE_POINTERS",
2026                 OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
2027                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2028
2029         {"3DSTATE_BINDING_TABLE_POINTERS_VS",
2030                 OP_3DSTATE_BINDING_TABLE_POINTERS_VS,
2031                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2032
2033         {"3DSTATE_BINDING_TABLE_POINTERS_HS",
2034                 OP_3DSTATE_BINDING_TABLE_POINTERS_HS,
2035                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2036
2037         {"3DSTATE_BINDING_TABLE_POINTERS_DS",
2038                 OP_3DSTATE_BINDING_TABLE_POINTERS_DS,
2039                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2040
2041         {"3DSTATE_BINDING_TABLE_POINTERS_GS",
2042                 OP_3DSTATE_BINDING_TABLE_POINTERS_GS,
2043                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2044
2045         {"3DSTATE_BINDING_TABLE_POINTERS_PS",
2046                 OP_3DSTATE_BINDING_TABLE_POINTERS_PS,
2047                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2048
2049         {"3DSTATE_SAMPLER_STATE_POINTERS_VS",
2050                 OP_3DSTATE_SAMPLER_STATE_POINTERS_VS,
2051                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2052
2053         {"3DSTATE_SAMPLER_STATE_POINTERS_HS",
2054                 OP_3DSTATE_SAMPLER_STATE_POINTERS_HS,
2055                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2056
2057         {"3DSTATE_SAMPLER_STATE_POINTERS_DS",
2058                 OP_3DSTATE_SAMPLER_STATE_POINTERS_DS,
2059                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2060
2061         {"3DSTATE_SAMPLER_STATE_POINTERS_GS",
2062                 OP_3DSTATE_SAMPLER_STATE_POINTERS_GS,
2063                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2064
2065         {"3DSTATE_SAMPLER_STATE_POINTERS_PS",
2066                 OP_3DSTATE_SAMPLER_STATE_POINTERS_PS,
2067                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2068
2069         {"3DSTATE_URB_VS", OP_3DSTATE_URB_VS, F_LEN_VAR, R_RCS, D_ALL,
2070                 0, 8, NULL},
2071
2072         {"3DSTATE_URB_HS", OP_3DSTATE_URB_HS, F_LEN_VAR, R_RCS, D_ALL,
2073                 0, 8, NULL},
2074
2075         {"3DSTATE_URB_DS", OP_3DSTATE_URB_DS, F_LEN_VAR, R_RCS, D_ALL,
2076                 0, 8, NULL},
2077
2078         {"3DSTATE_URB_GS", OP_3DSTATE_URB_GS, F_LEN_VAR, R_RCS, D_ALL,
2079                 0, 8, NULL},
2080
2081         {"3DSTATE_GATHER_CONSTANT_VS", OP_3DSTATE_GATHER_CONSTANT_VS,
2082                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2083
2084         {"3DSTATE_GATHER_CONSTANT_GS", OP_3DSTATE_GATHER_CONSTANT_GS,
2085                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2086
2087         {"3DSTATE_GATHER_CONSTANT_HS", OP_3DSTATE_GATHER_CONSTANT_HS,
2088                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2089
2090         {"3DSTATE_GATHER_CONSTANT_DS", OP_3DSTATE_GATHER_CONSTANT_DS,
2091                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2092
2093         {"3DSTATE_GATHER_CONSTANT_PS", OP_3DSTATE_GATHER_CONSTANT_PS,
2094                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2095
2096         {"3DSTATE_DX9_CONSTANTF_VS", OP_3DSTATE_DX9_CONSTANTF_VS,
2097                 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2098
2099         {"3DSTATE_DX9_CONSTANTF_PS", OP_3DSTATE_DX9_CONSTANTF_PS,
2100                 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2101
2102         {"3DSTATE_DX9_CONSTANTI_VS", OP_3DSTATE_DX9_CONSTANTI_VS,
2103                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2104
2105         {"3DSTATE_DX9_CONSTANTI_PS", OP_3DSTATE_DX9_CONSTANTI_PS,
2106                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2107
2108         {"3DSTATE_DX9_CONSTANTB_VS", OP_3DSTATE_DX9_CONSTANTB_VS,
2109                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2110
2111         {"3DSTATE_DX9_CONSTANTB_PS", OP_3DSTATE_DX9_CONSTANTB_PS,
2112                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2113
2114         {"3DSTATE_DX9_LOCAL_VALID_VS", OP_3DSTATE_DX9_LOCAL_VALID_VS,
2115                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2116
2117         {"3DSTATE_DX9_LOCAL_VALID_PS", OP_3DSTATE_DX9_LOCAL_VALID_PS,
2118                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2119
2120         {"3DSTATE_DX9_GENERATE_ACTIVE_VS", OP_3DSTATE_DX9_GENERATE_ACTIVE_VS,
2121                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2122
2123         {"3DSTATE_DX9_GENERATE_ACTIVE_PS", OP_3DSTATE_DX9_GENERATE_ACTIVE_PS,
2124                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2125
2126         {"3DSTATE_BINDING_TABLE_EDIT_VS", OP_3DSTATE_BINDING_TABLE_EDIT_VS,
2127                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2128
2129         {"3DSTATE_BINDING_TABLE_EDIT_GS", OP_3DSTATE_BINDING_TABLE_EDIT_GS,
2130                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2131
2132         {"3DSTATE_BINDING_TABLE_EDIT_HS", OP_3DSTATE_BINDING_TABLE_EDIT_HS,
2133                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2134
2135         {"3DSTATE_BINDING_TABLE_EDIT_DS", OP_3DSTATE_BINDING_TABLE_EDIT_DS,
2136                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2137
2138         {"3DSTATE_BINDING_TABLE_EDIT_PS", OP_3DSTATE_BINDING_TABLE_EDIT_PS,
2139                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2140
2141         {"3DSTATE_VF_INSTANCING", OP_3DSTATE_VF_INSTANCING, F_LEN_VAR, R_RCS,
2142                 D_BDW_PLUS, 0, 8, NULL},
2143
2144         {"3DSTATE_VF_SGVS", OP_3DSTATE_VF_SGVS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2145                 NULL},
2146
2147         {"3DSTATE_VF_TOPOLOGY", OP_3DSTATE_VF_TOPOLOGY, F_LEN_VAR, R_RCS,
2148                 D_BDW_PLUS, 0, 8, NULL},
2149
2150         {"3DSTATE_WM_CHROMAKEY", OP_3DSTATE_WM_CHROMAKEY, F_LEN_VAR, R_RCS,
2151                 D_BDW_PLUS, 0, 8, NULL},
2152
2153         {"3DSTATE_PS_BLEND", OP_3DSTATE_PS_BLEND, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2154                 8, NULL},
2155
2156         {"3DSTATE_WM_DEPTH_STENCIL", OP_3DSTATE_WM_DEPTH_STENCIL, F_LEN_VAR,
2157                 R_RCS, D_BDW_PLUS, 0, 8, NULL},
2158
2159         {"3DSTATE_PS_EXTRA", OP_3DSTATE_PS_EXTRA, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2160                 8, NULL},
2161
2162         {"3DSTATE_RASTER", OP_3DSTATE_RASTER, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2163                 NULL},
2164
2165         {"3DSTATE_SBE_SWIZ", OP_3DSTATE_SBE_SWIZ, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2166                 NULL},
2167
2168         {"3DSTATE_WM_HZ_OP", OP_3DSTATE_WM_HZ_OP, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2169                 NULL},
2170
2171         {"3DSTATE_VERTEX_BUFFERS", OP_3DSTATE_VERTEX_BUFFERS, F_LEN_VAR, R_RCS,
2172                 D_BDW_PLUS, 0, 8, NULL},
2173
2174         {"3DSTATE_VERTEX_ELEMENTS", OP_3DSTATE_VERTEX_ELEMENTS, F_LEN_VAR,
2175                 R_RCS, D_ALL, 0, 8, NULL},
2176
2177         {"3DSTATE_INDEX_BUFFER", OP_3DSTATE_INDEX_BUFFER, F_LEN_VAR, R_RCS,
2178                 D_BDW_PLUS, ADDR_FIX_1(2), 8, NULL},
2179
2180         {"3DSTATE_VF_STATISTICS", OP_3DSTATE_VF_STATISTICS, F_LEN_CONST,
2181                 R_RCS, D_ALL, 0, 1, NULL},
2182
2183         {"3DSTATE_VF", OP_3DSTATE_VF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2184
2185         {"3DSTATE_CC_STATE_POINTERS", OP_3DSTATE_CC_STATE_POINTERS, F_LEN_VAR,
2186                 R_RCS, D_ALL, 0, 8, NULL},
2187
2188         {"3DSTATE_SCISSOR_STATE_POINTERS", OP_3DSTATE_SCISSOR_STATE_POINTERS,
2189                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2190
2191         {"3DSTATE_GS", OP_3DSTATE_GS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2192
2193         {"3DSTATE_CLIP", OP_3DSTATE_CLIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2194
2195         {"3DSTATE_WM", OP_3DSTATE_WM, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2196
2197         {"3DSTATE_CONSTANT_GS", OP_3DSTATE_CONSTANT_GS, F_LEN_VAR, R_RCS,
2198                 D_BDW_PLUS, 0, 8, NULL},
2199
2200         {"3DSTATE_CONSTANT_PS", OP_3DSTATE_CONSTANT_PS, F_LEN_VAR, R_RCS,
2201                 D_BDW_PLUS, 0, 8, NULL},
2202
2203         {"3DSTATE_SAMPLE_MASK", OP_3DSTATE_SAMPLE_MASK, F_LEN_VAR, R_RCS,
2204                 D_ALL, 0, 8, NULL},
2205
2206         {"3DSTATE_CONSTANT_HS", OP_3DSTATE_CONSTANT_HS, F_LEN_VAR, R_RCS,
2207                 D_BDW_PLUS, 0, 8, NULL},
2208
2209         {"3DSTATE_CONSTANT_DS", OP_3DSTATE_CONSTANT_DS, F_LEN_VAR, R_RCS,
2210                 D_BDW_PLUS, 0, 8, NULL},
2211
2212         {"3DSTATE_HS", OP_3DSTATE_HS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2213
2214         {"3DSTATE_TE", OP_3DSTATE_TE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2215
2216         {"3DSTATE_DS", OP_3DSTATE_DS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2217
2218         {"3DSTATE_STREAMOUT", OP_3DSTATE_STREAMOUT, F_LEN_VAR, R_RCS,
2219                 D_ALL, 0, 8, NULL},
2220
2221         {"3DSTATE_SBE", OP_3DSTATE_SBE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2222
2223         {"3DSTATE_PS", OP_3DSTATE_PS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2224
2225         {"3DSTATE_DRAWING_RECTANGLE", OP_3DSTATE_DRAWING_RECTANGLE, F_LEN_VAR,
2226                 R_RCS, D_ALL, 0, 8, NULL},
2227
2228         {"3DSTATE_SAMPLER_PALETTE_LOAD0", OP_3DSTATE_SAMPLER_PALETTE_LOAD0,
2229                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2230
2231         {"3DSTATE_CHROMA_KEY", OP_3DSTATE_CHROMA_KEY, F_LEN_VAR, R_RCS, D_ALL,
2232                 0, 8, NULL},
2233
2234         {"3DSTATE_DEPTH_BUFFER", OP_3DSTATE_DEPTH_BUFFER, F_LEN_VAR, R_RCS,
2235                 D_ALL, ADDR_FIX_1(2), 8, NULL},
2236
2237         {"3DSTATE_POLY_STIPPLE_OFFSET", OP_3DSTATE_POLY_STIPPLE_OFFSET,
2238                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2239
2240         {"3DSTATE_POLY_STIPPLE_PATTERN", OP_3DSTATE_POLY_STIPPLE_PATTERN,
2241                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2242
2243         {"3DSTATE_LINE_STIPPLE", OP_3DSTATE_LINE_STIPPLE, F_LEN_VAR, R_RCS,
2244                 D_ALL, 0, 8, NULL},
2245
2246         {"3DSTATE_AA_LINE_PARAMS", OP_3DSTATE_AA_LINE_PARAMS, F_LEN_VAR, R_RCS,
2247                 D_ALL, 0, 8, NULL},
2248
2249         {"3DSTATE_GS_SVB_INDEX", OP_3DSTATE_GS_SVB_INDEX, F_LEN_VAR, R_RCS,
2250                 D_ALL, 0, 8, NULL},
2251
2252         {"3DSTATE_SAMPLER_PALETTE_LOAD1", OP_3DSTATE_SAMPLER_PALETTE_LOAD1,
2253                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2254
2255         {"3DSTATE_MULTISAMPLE", OP_3DSTATE_MULTISAMPLE_BDW, F_LEN_VAR, R_RCS,
2256                 D_BDW_PLUS, 0, 8, NULL},
2257
2258         {"3DSTATE_STENCIL_BUFFER", OP_3DSTATE_STENCIL_BUFFER, F_LEN_VAR, R_RCS,
2259                 D_ALL, ADDR_FIX_1(2), 8, NULL},
2260
2261         {"3DSTATE_HIER_DEPTH_BUFFER", OP_3DSTATE_HIER_DEPTH_BUFFER, F_LEN_VAR,
2262                 R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL},
2263
2264         {"3DSTATE_CLEAR_PARAMS", OP_3DSTATE_CLEAR_PARAMS, F_LEN_VAR,
2265                 R_RCS, D_ALL, 0, 8, NULL},
2266
2267         {"3DSTATE_PUSH_CONSTANT_ALLOC_VS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
2268                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2269
2270         {"3DSTATE_PUSH_CONSTANT_ALLOC_HS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS,
2271                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2272
2273         {"3DSTATE_PUSH_CONSTANT_ALLOC_DS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS,
2274                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2275
2276         {"3DSTATE_PUSH_CONSTANT_ALLOC_GS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS,
2277                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2278
2279         {"3DSTATE_PUSH_CONSTANT_ALLOC_PS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS,
2280                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2281
2282         {"3DSTATE_MONOFILTER_SIZE", OP_3DSTATE_MONOFILTER_SIZE, F_LEN_VAR,
2283                 R_RCS, D_ALL, 0, 8, NULL},
2284
2285         {"3DSTATE_SO_DECL_LIST", OP_3DSTATE_SO_DECL_LIST, F_LEN_VAR, R_RCS,
2286                 D_ALL, 0, 9, NULL},
2287
2288         {"3DSTATE_SO_BUFFER", OP_3DSTATE_SO_BUFFER, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2289                 ADDR_FIX_2(2, 4), 8, NULL},
2290
2291         {"3DSTATE_BINDING_TABLE_POOL_ALLOC",
2292                 OP_3DSTATE_BINDING_TABLE_POOL_ALLOC,
2293                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2294
2295         {"3DSTATE_GATHER_POOL_ALLOC", OP_3DSTATE_GATHER_POOL_ALLOC,
2296                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2297
2298         {"3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC",
2299                 OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC,
2300                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2301
2302         {"3DSTATE_SAMPLE_PATTERN", OP_3DSTATE_SAMPLE_PATTERN, F_LEN_VAR, R_RCS,
2303                 D_BDW_PLUS, 0, 8, NULL},
2304
2305         {"PIPE_CONTROL", OP_PIPE_CONTROL, F_LEN_VAR, R_RCS, D_ALL,
2306                 ADDR_FIX_1(2), 8, cmd_handler_pipe_control},
2307
2308         {"3DPRIMITIVE", OP_3DPRIMITIVE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2309
2310         {"PIPELINE_SELECT", OP_PIPELINE_SELECT, F_LEN_CONST, R_RCS, D_ALL, 0,
2311                 1, NULL},
2312
2313         {"STATE_PREFETCH", OP_STATE_PREFETCH, F_LEN_VAR, R_RCS, D_ALL,
2314                 ADDR_FIX_1(1), 8, NULL},
2315
2316         {"STATE_SIP", OP_STATE_SIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2317
2318         {"STATE_BASE_ADDRESS", OP_STATE_BASE_ADDRESS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2319                 ADDR_FIX_5(1, 3, 4, 5, 6), 8, NULL},
2320
2321         {"OP_3D_MEDIA_0_1_4", OP_3D_MEDIA_0_1_4, F_LEN_VAR, R_RCS, D_ALL,
2322                 ADDR_FIX_1(1), 8, NULL},
2323
2324         {"3DSTATE_VS", OP_3DSTATE_VS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2325
2326         {"3DSTATE_SF", OP_3DSTATE_SF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2327
2328         {"3DSTATE_CONSTANT_VS", OP_3DSTATE_CONSTANT_VS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2329                 0, 8, NULL},
2330
2331         {"3DSTATE_COMPONENT_PACKING", OP_3DSTATE_COMPONENT_PACKING, F_LEN_VAR, R_RCS,
2332                 D_SKL_PLUS, 0, 8, NULL},
2333
2334         {"MEDIA_INTERFACE_DESCRIPTOR_LOAD", OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD,
2335                 F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2336
2337         {"MEDIA_GATEWAY_STATE", OP_MEDIA_GATEWAY_STATE, F_LEN_VAR, R_RCS, D_ALL,
2338                 0, 16, NULL},
2339
2340         {"MEDIA_STATE_FLUSH", OP_MEDIA_STATE_FLUSH, F_LEN_VAR, R_RCS, D_ALL,
2341                 0, 16, NULL},
2342
2343         {"MEDIA_OBJECT", OP_MEDIA_OBJECT, F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2344
2345         {"MEDIA_CURBE_LOAD", OP_MEDIA_CURBE_LOAD, F_LEN_VAR, R_RCS, D_ALL,
2346                 0, 16, NULL},
2347
2348         {"MEDIA_OBJECT_PRT", OP_MEDIA_OBJECT_PRT, F_LEN_VAR, R_RCS, D_ALL,
2349                 0, 16, NULL},
2350
2351         {"MEDIA_OBJECT_WALKER", OP_MEDIA_OBJECT_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2352                 0, 16, NULL},
2353
2354         {"GPGPU_WALKER", OP_GPGPU_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2355                 0, 8, NULL},
2356
2357         {"MEDIA_VFE_STATE", OP_MEDIA_VFE_STATE, F_LEN_VAR, R_RCS, D_ALL, 0, 16,
2358                 NULL},
2359
2360         {"3DSTATE_VF_STATISTICS_GM45", OP_3DSTATE_VF_STATISTICS_GM45,
2361                 F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2362
2363         {"MFX_PIPE_MODE_SELECT", OP_MFX_PIPE_MODE_SELECT, F_LEN_VAR,
2364                 R_VCS, D_ALL, 0, 12, NULL},
2365
2366         {"MFX_SURFACE_STATE", OP_MFX_SURFACE_STATE, F_LEN_VAR,
2367                 R_VCS, D_ALL, 0, 12, NULL},
2368
2369         {"MFX_PIPE_BUF_ADDR_STATE", OP_MFX_PIPE_BUF_ADDR_STATE, F_LEN_VAR,
2370                 R_VCS, D_BDW_PLUS, 0, 12, NULL},
2371
2372         {"MFX_IND_OBJ_BASE_ADDR_STATE", OP_MFX_IND_OBJ_BASE_ADDR_STATE,
2373                 F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2374
2375         {"MFX_BSP_BUF_BASE_ADDR_STATE", OP_MFX_BSP_BUF_BASE_ADDR_STATE,
2376                 F_LEN_VAR, R_VCS, D_BDW_PLUS, ADDR_FIX_3(1, 3, 5), 12, NULL},
2377
2378         {"OP_2_0_0_5", OP_2_0_0_5, F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2379
2380         {"MFX_STATE_POINTER", OP_MFX_STATE_POINTER, F_LEN_VAR,
2381                 R_VCS, D_ALL, 0, 12, NULL},
2382
2383         {"MFX_QM_STATE", OP_MFX_QM_STATE, F_LEN_VAR,
2384                 R_VCS, D_ALL, 0, 12, NULL},
2385
2386         {"MFX_FQM_STATE", OP_MFX_FQM_STATE, F_LEN_VAR,
2387                 R_VCS, D_ALL, 0, 12, NULL},
2388
2389         {"MFX_PAK_INSERT_OBJECT", OP_MFX_PAK_INSERT_OBJECT, F_LEN_VAR,
2390                 R_VCS, D_ALL, 0, 12, NULL},
2391
2392         {"MFX_STITCH_OBJECT", OP_MFX_STITCH_OBJECT, F_LEN_VAR,
2393                 R_VCS, D_ALL, 0, 12, NULL},
2394
2395         {"MFD_IT_OBJECT", OP_MFD_IT_OBJECT, F_LEN_VAR,
2396                 R_VCS, D_ALL, 0, 12, NULL},
2397
2398         {"MFX_WAIT", OP_MFX_WAIT, F_LEN_VAR,
2399                 R_VCS, D_ALL, 0, 6, NULL},
2400
2401         {"MFX_AVC_IMG_STATE", OP_MFX_AVC_IMG_STATE, F_LEN_VAR,
2402                 R_VCS, D_ALL, 0, 12, NULL},
2403
2404         {"MFX_AVC_QM_STATE", OP_MFX_AVC_QM_STATE, F_LEN_VAR,
2405                 R_VCS, D_ALL, 0, 12, NULL},
2406
2407         {"MFX_AVC_DIRECTMODE_STATE", OP_MFX_AVC_DIRECTMODE_STATE, F_LEN_VAR,
2408                 R_VCS, D_ALL, 0, 12, NULL},
2409
2410         {"MFX_AVC_SLICE_STATE", OP_MFX_AVC_SLICE_STATE, F_LEN_VAR,
2411                 R_VCS, D_ALL, 0, 12, NULL},
2412
2413         {"MFX_AVC_REF_IDX_STATE", OP_MFX_AVC_REF_IDX_STATE, F_LEN_VAR,
2414                 R_VCS, D_ALL, 0, 12, NULL},
2415
2416         {"MFX_AVC_WEIGHTOFFSET_STATE", OP_MFX_AVC_WEIGHTOFFSET_STATE, F_LEN_VAR,
2417                 R_VCS, D_ALL, 0, 12, NULL},
2418
2419         {"MFD_AVC_PICID_STATE", OP_MFD_AVC_PICID_STATE, F_LEN_VAR,
2420                 R_VCS, D_ALL, 0, 12, NULL},
2421         {"MFD_AVC_DPB_STATE", OP_MFD_AVC_DPB_STATE, F_LEN_VAR,
2422                 R_VCS, D_ALL, 0, 12, NULL},
2423
2424         {"MFD_AVC_BSD_OBJECT", OP_MFD_AVC_BSD_OBJECT, F_LEN_VAR,
2425                 R_VCS, D_ALL, 0, 12, NULL},
2426
2427         {"MFD_AVC_SLICEADDR", OP_MFD_AVC_SLICEADDR, F_LEN_VAR,
2428                 R_VCS, D_ALL, ADDR_FIX_1(2), 12, NULL},
2429
2430         {"MFC_AVC_PAK_OBJECT", OP_MFC_AVC_PAK_OBJECT, F_LEN_VAR,
2431                 R_VCS, D_ALL, 0, 12, NULL},
2432
2433         {"MFX_VC1_PRED_PIPE_STATE", OP_MFX_VC1_PRED_PIPE_STATE, F_LEN_VAR,
2434                 R_VCS, D_ALL, 0, 12, NULL},
2435
2436         {"MFX_VC1_DIRECTMODE_STATE", OP_MFX_VC1_DIRECTMODE_STATE, F_LEN_VAR,
2437                 R_VCS, D_ALL, 0, 12, NULL},
2438
2439         {"MFD_VC1_SHORT_PIC_STATE", OP_MFD_VC1_SHORT_PIC_STATE, F_LEN_VAR,
2440                 R_VCS, D_ALL, 0, 12, NULL},
2441
2442         {"MFD_VC1_LONG_PIC_STATE", OP_MFD_VC1_LONG_PIC_STATE, F_LEN_VAR,
2443                 R_VCS, D_ALL, 0, 12, NULL},
2444
2445         {"MFD_VC1_BSD_OBJECT", OP_MFD_VC1_BSD_OBJECT, F_LEN_VAR,
2446                 R_VCS, D_ALL, 0, 12, NULL},
2447
2448         {"MFC_MPEG2_SLICEGROUP_STATE", OP_MFC_MPEG2_SLICEGROUP_STATE, F_LEN_VAR,
2449                 R_VCS, D_ALL, 0, 12, NULL},
2450
2451         {"MFC_MPEG2_PAK_OBJECT", OP_MFC_MPEG2_PAK_OBJECT, F_LEN_VAR,
2452                 R_VCS, D_ALL, 0, 12, NULL},
2453
2454         {"MFX_MPEG2_PIC_STATE", OP_MFX_MPEG2_PIC_STATE, F_LEN_VAR,
2455                 R_VCS, D_ALL, 0, 12, NULL},
2456
2457         {"MFX_MPEG2_QM_STATE", OP_MFX_MPEG2_QM_STATE, F_LEN_VAR,
2458                 R_VCS, D_ALL, 0, 12, NULL},
2459
2460         {"MFD_MPEG2_BSD_OBJECT", OP_MFD_MPEG2_BSD_OBJECT, F_LEN_VAR,
2461                 R_VCS, D_ALL, 0, 12, NULL},
2462
2463         {"MFX_2_6_0_0", OP_MFX_2_6_0_0, F_LEN_VAR, R_VCS, D_ALL,
2464                 0, 16, NULL},
2465
2466         {"MFX_2_6_0_9", OP_MFX_2_6_0_9, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2467
2468         {"MFX_2_6_0_8", OP_MFX_2_6_0_8, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2469
2470         {"MFX_JPEG_PIC_STATE", OP_MFX_JPEG_PIC_STATE, F_LEN_VAR,
2471                 R_VCS, D_ALL, 0, 12, NULL},
2472
2473         {"MFX_JPEG_HUFF_TABLE_STATE", OP_MFX_JPEG_HUFF_TABLE_STATE, F_LEN_VAR,
2474                 R_VCS, D_ALL, 0, 12, NULL},
2475
2476         {"MFD_JPEG_BSD_OBJECT", OP_MFD_JPEG_BSD_OBJECT, F_LEN_VAR,
2477                 R_VCS, D_ALL, 0, 12, NULL},
2478
2479         {"VEBOX_STATE", OP_VEB_STATE, F_LEN_VAR, R_VECS, D_ALL, 0, 12, NULL},
2480
2481         {"VEBOX_SURFACE_STATE", OP_VEB_SURFACE_STATE, F_LEN_VAR, R_VECS, D_ALL,
2482                 0, 12, NULL},
2483
2484         {"VEB_DI_IECP", OP_VEB_DNDI_IECP_STATE, F_LEN_VAR, R_VECS, D_BDW_PLUS,
2485                 0, 20, NULL},
2486 };
2487
2488 static void add_cmd_entry(struct intel_gvt *gvt, struct cmd_entry *e)
2489 {
2490         hash_add(gvt->cmd_table, &e->hlist, e->info->opcode);
2491 }
2492
2493 /* call the cmd handler, and advance ip */
2494 static int cmd_parser_exec(struct parser_exec_state *s)
2495 {
2496         struct intel_vgpu *vgpu = s->vgpu;
2497         struct cmd_info *info;
2498         u32 cmd;
2499         int ret = 0;
2500
2501         cmd = cmd_val(s, 0);
2502
2503         info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
2504         if (info == NULL) {
2505                 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",
2506                                 cmd, get_opcode(cmd, s->ring_id),
2507                                 (s->buf_addr_type == PPGTT_BUFFER) ?
2508                                 "ppgtt" : "ggtt", s->ring_id, s->workload);
2509                 return -EBADRQC;
2510         }
2511
2512         s->info = info;
2513
2514         trace_gvt_command(vgpu->id, s->ring_id, s->ip_gma, s->ip_va,
2515                           cmd_length(s), s->buf_type, s->buf_addr_type,
2516                           s->workload, info->name);
2517
2518         if (info->handler) {
2519                 ret = info->handler(s);
2520                 if (ret < 0) {
2521                         gvt_vgpu_err("%s handler error\n", info->name);
2522                         return ret;
2523                 }
2524         }
2525
2526         if (!(info->flag & F_IP_ADVANCE_CUSTOM)) {
2527                 ret = cmd_advance_default(s);
2528                 if (ret) {
2529                         gvt_vgpu_err("%s IP advance error\n", info->name);
2530                         return ret;
2531                 }
2532         }
2533         return 0;
2534 }
2535
2536 static inline bool gma_out_of_range(unsigned long gma,
2537                 unsigned long gma_head, unsigned int gma_tail)
2538 {
2539         if (gma_tail >= gma_head)
2540                 return (gma < gma_head) || (gma > gma_tail);
2541         else
2542                 return (gma > gma_tail) && (gma < gma_head);
2543 }
2544
2545 /* Keep the consistent return type, e.g EBADRQC for unknown
2546  * cmd, EFAULT for invalid address, EPERM for nonpriv. later
2547  * works as the input of VM healthy status.
2548  */
2549 static int command_scan(struct parser_exec_state *s,
2550                 unsigned long rb_head, unsigned long rb_tail,
2551                 unsigned long rb_start, unsigned long rb_len)
2552 {
2553
2554         unsigned long gma_head, gma_tail, gma_bottom;
2555         int ret = 0;
2556         struct intel_vgpu *vgpu = s->vgpu;
2557
2558         gma_head = rb_start + rb_head;
2559         gma_tail = rb_start + rb_tail;
2560         gma_bottom = rb_start +  rb_len;
2561
2562         while (s->ip_gma != gma_tail) {
2563                 if (s->buf_type == RING_BUFFER_INSTRUCTION) {
2564                         if (!(s->ip_gma >= rb_start) ||
2565                                 !(s->ip_gma < gma_bottom)) {
2566                                 gvt_vgpu_err("ip_gma %lx out of ring scope."
2567                                         "(base:0x%lx, bottom: 0x%lx)\n",
2568                                         s->ip_gma, rb_start,
2569                                         gma_bottom);
2570                                 parser_exec_state_dump(s);
2571                                 return -EFAULT;
2572                         }
2573                         if (gma_out_of_range(s->ip_gma, gma_head, gma_tail)) {
2574                                 gvt_vgpu_err("ip_gma %lx out of range."
2575                                         "base 0x%lx head 0x%lx tail 0x%lx\n",
2576                                         s->ip_gma, rb_start,
2577                                         rb_head, rb_tail);
2578                                 parser_exec_state_dump(s);
2579                                 break;
2580                         }
2581                 }
2582                 ret = cmd_parser_exec(s);
2583                 if (ret) {
2584                         gvt_vgpu_err("cmd parser error\n");
2585                         parser_exec_state_dump(s);
2586                         break;
2587                 }
2588         }
2589
2590         return ret;
2591 }
2592
2593 static int scan_workload(struct intel_vgpu_workload *workload)
2594 {
2595         unsigned long gma_head, gma_tail, gma_bottom;
2596         struct parser_exec_state s;
2597         int ret = 0;
2598
2599         /* ring base is page aligned */
2600         if (WARN_ON(!IS_ALIGNED(workload->rb_start, I915_GTT_PAGE_SIZE)))
2601                 return -EINVAL;
2602
2603         gma_head = workload->rb_start + workload->rb_head;
2604         gma_tail = workload->rb_start + workload->rb_tail;
2605         gma_bottom = workload->rb_start +  _RING_CTL_BUF_SIZE(workload->rb_ctl);
2606
2607         s.buf_type = RING_BUFFER_INSTRUCTION;
2608         s.buf_addr_type = GTT_BUFFER;
2609         s.vgpu = workload->vgpu;
2610         s.ring_id = workload->ring_id;
2611         s.ring_start = workload->rb_start;
2612         s.ring_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2613         s.ring_head = gma_head;
2614         s.ring_tail = gma_tail;
2615         s.rb_va = workload->shadow_ring_buffer_va;
2616         s.workload = workload;
2617         s.is_ctx_wa = false;
2618
2619         if ((bypass_scan_mask & (1 << workload->ring_id)) ||
2620                 gma_head == gma_tail)
2621                 return 0;
2622
2623         if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) {
2624                 ret = -EINVAL;
2625                 goto out;
2626         }
2627
2628         ret = ip_gma_set(&s, gma_head);
2629         if (ret)
2630                 goto out;
2631
2632         ret = command_scan(&s, workload->rb_head, workload->rb_tail,
2633                 workload->rb_start, _RING_CTL_BUF_SIZE(workload->rb_ctl));
2634
2635 out:
2636         return ret;
2637 }
2638
2639 static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2640 {
2641
2642         unsigned long gma_head, gma_tail, gma_bottom, ring_size, ring_tail;
2643         struct parser_exec_state s;
2644         int ret = 0;
2645         struct intel_vgpu_workload *workload = container_of(wa_ctx,
2646                                 struct intel_vgpu_workload,
2647                                 wa_ctx);
2648
2649         /* ring base is page aligned */
2650         if (WARN_ON(!IS_ALIGNED(wa_ctx->indirect_ctx.guest_gma,
2651                                         I915_GTT_PAGE_SIZE)))
2652                 return -EINVAL;
2653
2654         ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(uint32_t);
2655         ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES,
2656                         PAGE_SIZE);
2657         gma_head = wa_ctx->indirect_ctx.guest_gma;
2658         gma_tail = wa_ctx->indirect_ctx.guest_gma + ring_tail;
2659         gma_bottom = wa_ctx->indirect_ctx.guest_gma + ring_size;
2660
2661         s.buf_type = RING_BUFFER_INSTRUCTION;
2662         s.buf_addr_type = GTT_BUFFER;
2663         s.vgpu = workload->vgpu;
2664         s.ring_id = workload->ring_id;
2665         s.ring_start = wa_ctx->indirect_ctx.guest_gma;
2666         s.ring_size = ring_size;
2667         s.ring_head = gma_head;
2668         s.ring_tail = gma_tail;
2669         s.rb_va = wa_ctx->indirect_ctx.shadow_va;
2670         s.workload = workload;
2671         s.is_ctx_wa = true;
2672
2673         if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) {
2674                 ret = -EINVAL;
2675                 goto out;
2676         }
2677
2678         ret = ip_gma_set(&s, gma_head);
2679         if (ret)
2680                 goto out;
2681
2682         ret = command_scan(&s, 0, ring_tail,
2683                 wa_ctx->indirect_ctx.guest_gma, ring_size);
2684 out:
2685         return ret;
2686 }
2687
2688 static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload)
2689 {
2690         struct intel_vgpu *vgpu = workload->vgpu;
2691         struct intel_vgpu_submission *s = &vgpu->submission;
2692         unsigned long gma_head, gma_tail, gma_top, guest_rb_size;
2693         void *shadow_ring_buffer_va;
2694         int ring_id = workload->ring_id;
2695         int ret;
2696
2697         guest_rb_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2698
2699         /* calculate workload ring buffer size */
2700         workload->rb_len = (workload->rb_tail + guest_rb_size -
2701                         workload->rb_head) % guest_rb_size;
2702
2703         gma_head = workload->rb_start + workload->rb_head;
2704         gma_tail = workload->rb_start + workload->rb_tail;
2705         gma_top = workload->rb_start + guest_rb_size;
2706
2707         if (workload->rb_len > s->ring_scan_buffer_size[ring_id]) {
2708                 void *p;
2709
2710                 /* realloc the new ring buffer if needed */
2711                 p = krealloc(s->ring_scan_buffer[ring_id], workload->rb_len,
2712                                 GFP_KERNEL);
2713                 if (!p) {
2714                         gvt_vgpu_err("fail to re-alloc ring scan buffer\n");
2715                         return -ENOMEM;
2716                 }
2717                 s->ring_scan_buffer[ring_id] = p;
2718                 s->ring_scan_buffer_size[ring_id] = workload->rb_len;
2719         }
2720
2721         shadow_ring_buffer_va = s->ring_scan_buffer[ring_id];
2722
2723         /* get shadow ring buffer va */
2724         workload->shadow_ring_buffer_va = shadow_ring_buffer_va;
2725
2726         /* head > tail --> copy head <-> top */
2727         if (gma_head > gma_tail) {
2728                 ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm,
2729                                       gma_head, gma_top, shadow_ring_buffer_va);
2730                 if (ret < 0) {
2731                         gvt_vgpu_err("fail to copy guest ring buffer\n");
2732                         return ret;
2733                 }
2734                 shadow_ring_buffer_va += ret;
2735                 gma_head = workload->rb_start;
2736         }
2737
2738         /* copy head or start <-> tail */
2739         ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, gma_head, gma_tail,
2740                                 shadow_ring_buffer_va);
2741         if (ret < 0) {
2742                 gvt_vgpu_err("fail to copy guest ring buffer\n");
2743                 return ret;
2744         }
2745         return 0;
2746 }
2747
2748 int intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload *workload)
2749 {
2750         int ret;
2751         struct intel_vgpu *vgpu = workload->vgpu;
2752
2753         ret = shadow_workload_ring_buffer(workload);
2754         if (ret) {
2755                 gvt_vgpu_err("fail to shadow workload ring_buffer\n");
2756                 return ret;
2757         }
2758
2759         ret = scan_workload(workload);
2760         if (ret) {
2761                 gvt_vgpu_err("scan workload error\n");
2762                 return ret;
2763         }
2764         return 0;
2765 }
2766
2767 static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2768 {
2769         int ctx_size = wa_ctx->indirect_ctx.size;
2770         unsigned long guest_gma = wa_ctx->indirect_ctx.guest_gma;
2771         struct intel_vgpu_workload *workload = container_of(wa_ctx,
2772                                         struct intel_vgpu_workload,
2773                                         wa_ctx);
2774         struct intel_vgpu *vgpu = workload->vgpu;
2775         struct drm_i915_gem_object *obj;
2776         int ret = 0;
2777         void *map;
2778
2779         obj = i915_gem_object_create(workload->vgpu->gvt->dev_priv,
2780                                      roundup(ctx_size + CACHELINE_BYTES,
2781                                              PAGE_SIZE));
2782         if (IS_ERR(obj))
2783                 return PTR_ERR(obj);
2784
2785         /* get the va of the shadow batch buffer */
2786         map = i915_gem_object_pin_map(obj, I915_MAP_WB);
2787         if (IS_ERR(map)) {
2788                 gvt_vgpu_err("failed to vmap shadow indirect ctx\n");
2789                 ret = PTR_ERR(map);
2790                 goto put_obj;
2791         }
2792
2793         ret = i915_gem_object_set_to_cpu_domain(obj, false);
2794         if (ret) {
2795                 gvt_vgpu_err("failed to set shadow indirect ctx to CPU\n");
2796                 goto unmap_src;
2797         }
2798
2799         ret = copy_gma_to_hva(workload->vgpu,
2800                                 workload->vgpu->gtt.ggtt_mm,
2801                                 guest_gma, guest_gma + ctx_size,
2802                                 map);
2803         if (ret < 0) {
2804                 gvt_vgpu_err("fail to copy guest indirect ctx\n");
2805                 goto unmap_src;
2806         }
2807
2808         wa_ctx->indirect_ctx.obj = obj;
2809         wa_ctx->indirect_ctx.shadow_va = map;
2810         return 0;
2811
2812 unmap_src:
2813         i915_gem_object_unpin_map(obj);
2814 put_obj:
2815         i915_gem_object_put(obj);
2816         return ret;
2817 }
2818
2819 static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2820 {
2821         uint32_t per_ctx_start[CACHELINE_DWORDS] = {0};
2822         unsigned char *bb_start_sva;
2823
2824         if (!wa_ctx->per_ctx.valid)
2825                 return 0;
2826
2827         per_ctx_start[0] = 0x18800001;
2828         per_ctx_start[1] = wa_ctx->per_ctx.guest_gma;
2829
2830         bb_start_sva = (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
2831                                 wa_ctx->indirect_ctx.size;
2832
2833         memcpy(bb_start_sva, per_ctx_start, CACHELINE_BYTES);
2834
2835         return 0;
2836 }
2837
2838 int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2839 {
2840         int ret;
2841         struct intel_vgpu_workload *workload = container_of(wa_ctx,
2842                                         struct intel_vgpu_workload,
2843                                         wa_ctx);
2844         struct intel_vgpu *vgpu = workload->vgpu;
2845
2846         if (wa_ctx->indirect_ctx.size == 0)
2847                 return 0;
2848
2849         ret = shadow_indirect_ctx(wa_ctx);
2850         if (ret) {
2851                 gvt_vgpu_err("fail to shadow indirect ctx\n");
2852                 return ret;
2853         }
2854
2855         combine_wa_ctx(wa_ctx);
2856
2857         ret = scan_wa_ctx(wa_ctx);
2858         if (ret) {
2859                 gvt_vgpu_err("scan wa ctx error\n");
2860                 return ret;
2861         }
2862
2863         return 0;
2864 }
2865
2866 static struct cmd_info *find_cmd_entry_any_ring(struct intel_gvt *gvt,
2867                 unsigned int opcode, unsigned long rings)
2868 {
2869         struct cmd_info *info = NULL;
2870         unsigned int ring;
2871
2872         for_each_set_bit(ring, &rings, I915_NUM_ENGINES) {
2873                 info = find_cmd_entry(gvt, opcode, ring);
2874                 if (info)
2875                         break;
2876         }
2877         return info;
2878 }
2879
2880 static int init_cmd_table(struct intel_gvt *gvt)
2881 {
2882         int i;
2883         struct cmd_entry *e;
2884         struct cmd_info *info;
2885         unsigned int gen_type;
2886
2887         gen_type = intel_gvt_get_device_type(gvt);
2888
2889         for (i = 0; i < ARRAY_SIZE(cmd_info); i++) {
2890                 if (!(cmd_info[i].devices & gen_type))
2891                         continue;
2892
2893                 e = kzalloc(sizeof(*e), GFP_KERNEL);
2894                 if (!e)
2895                         return -ENOMEM;
2896
2897                 e->info = &cmd_info[i];
2898                 info = find_cmd_entry_any_ring(gvt,
2899                                 e->info->opcode, e->info->rings);
2900                 if (info) {
2901                         gvt_err("%s %s duplicated\n", e->info->name,
2902                                         info->name);
2903                         return -EEXIST;
2904                 }
2905
2906                 INIT_HLIST_NODE(&e->hlist);
2907                 add_cmd_entry(gvt, e);
2908                 gvt_dbg_cmd("add %-30s op %04x flag %x devs %02x rings %02x\n",
2909                                 e->info->name, e->info->opcode, e->info->flag,
2910                                 e->info->devices, e->info->rings);
2911         }
2912         return 0;
2913 }
2914
2915 static void clean_cmd_table(struct intel_gvt *gvt)
2916 {
2917         struct hlist_node *tmp;
2918         struct cmd_entry *e;
2919         int i;
2920
2921         hash_for_each_safe(gvt->cmd_table, i, tmp, e, hlist)
2922                 kfree(e);
2923
2924         hash_init(gvt->cmd_table);
2925 }
2926
2927 void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt)
2928 {
2929         clean_cmd_table(gvt);
2930 }
2931
2932 int intel_gvt_init_cmd_parser(struct intel_gvt *gvt)
2933 {
2934         int ret;
2935
2936         ret = init_cmd_table(gvt);
2937         if (ret) {
2938                 intel_gvt_clean_cmd_parser(gvt);
2939                 return ret;
2940         }
2941         return 0;
2942 }