718ca08f95751af6303f1eb1b651f14cafe3ddc4
[muen/linux.git] / drivers / gpu / drm / i915 / gvt / cmd_parser.c
1 /*
2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21  * SOFTWARE.
22  *
23  * Authors:
24  *    Ke Yu
25  *    Kevin Tian <kevin.tian@intel.com>
26  *    Zhiyuan Lv <zhiyuan.lv@intel.com>
27  *
28  * Contributors:
29  *    Min He <min.he@intel.com>
30  *    Ping Gao <ping.a.gao@intel.com>
31  *    Tina Zhang <tina.zhang@intel.com>
32  *    Yulei Zhang <yulei.zhang@intel.com>
33  *    Zhi Wang <zhi.a.wang@intel.com>
34  *
35  */
36
37 #include <linux/slab.h>
38 #include "i915_drv.h"
39 #include "gvt.h"
40 #include "i915_pvinfo.h"
41 #include "trace.h"
42
43 #define INVALID_OP    (~0U)
44
45 #define OP_LEN_MI           9
46 #define OP_LEN_2D           10
47 #define OP_LEN_3D_MEDIA     16
48 #define OP_LEN_MFX_VC       16
49 #define OP_LEN_VEBOX        16
50
51 #define CMD_TYPE(cmd)   (((cmd) >> 29) & 7)
52
53 struct sub_op_bits {
54         int hi;
55         int low;
56 };
57 struct decode_info {
58         char *name;
59         int op_len;
60         int nr_sub_op;
61         struct sub_op_bits *sub_op;
62 };
63
64 #define   MAX_CMD_BUDGET                        0x7fffffff
65 #define   MI_WAIT_FOR_PLANE_C_FLIP_PENDING      (1<<15)
66 #define   MI_WAIT_FOR_PLANE_B_FLIP_PENDING      (1<<9)
67 #define   MI_WAIT_FOR_PLANE_A_FLIP_PENDING      (1<<1)
68
69 #define   MI_WAIT_FOR_SPRITE_C_FLIP_PENDING      (1<<20)
70 #define   MI_WAIT_FOR_SPRITE_B_FLIP_PENDING      (1<<10)
71 #define   MI_WAIT_FOR_SPRITE_A_FLIP_PENDING      (1<<2)
72
73 /* Render Command Map */
74
75 /* MI_* command Opcode (28:23) */
76 #define OP_MI_NOOP                          0x0
77 #define OP_MI_SET_PREDICATE                 0x1  /* HSW+ */
78 #define OP_MI_USER_INTERRUPT                0x2
79 #define OP_MI_WAIT_FOR_EVENT                0x3
80 #define OP_MI_FLUSH                         0x4
81 #define OP_MI_ARB_CHECK                     0x5
82 #define OP_MI_RS_CONTROL                    0x6  /* HSW+ */
83 #define OP_MI_REPORT_HEAD                   0x7
84 #define OP_MI_ARB_ON_OFF                    0x8
85 #define OP_MI_URB_ATOMIC_ALLOC              0x9  /* HSW+ */
86 #define OP_MI_BATCH_BUFFER_END              0xA
87 #define OP_MI_SUSPEND_FLUSH                 0xB
88 #define OP_MI_PREDICATE                     0xC  /* IVB+ */
89 #define OP_MI_TOPOLOGY_FILTER               0xD  /* IVB+ */
90 #define OP_MI_SET_APPID                     0xE  /* IVB+ */
91 #define OP_MI_RS_CONTEXT                    0xF  /* HSW+ */
92 #define OP_MI_LOAD_SCAN_LINES_INCL          0x12 /* HSW+ */
93 #define OP_MI_DISPLAY_FLIP                  0x14
94 #define OP_MI_SEMAPHORE_MBOX                0x16
95 #define OP_MI_SET_CONTEXT                   0x18
96 #define OP_MI_MATH                          0x1A
97 #define OP_MI_URB_CLEAR                     0x19
98 #define OP_MI_SEMAPHORE_SIGNAL              0x1B  /* BDW+ */
99 #define OP_MI_SEMAPHORE_WAIT                0x1C  /* BDW+ */
100
101 #define OP_MI_STORE_DATA_IMM                0x20
102 #define OP_MI_STORE_DATA_INDEX              0x21
103 #define OP_MI_LOAD_REGISTER_IMM             0x22
104 #define OP_MI_UPDATE_GTT                    0x23
105 #define OP_MI_STORE_REGISTER_MEM            0x24
106 #define OP_MI_FLUSH_DW                      0x26
107 #define OP_MI_CLFLUSH                       0x27
108 #define OP_MI_REPORT_PERF_COUNT             0x28
109 #define OP_MI_LOAD_REGISTER_MEM             0x29  /* HSW+ */
110 #define OP_MI_LOAD_REGISTER_REG             0x2A  /* HSW+ */
111 #define OP_MI_RS_STORE_DATA_IMM             0x2B  /* HSW+ */
112 #define OP_MI_LOAD_URB_MEM                  0x2C  /* HSW+ */
113 #define OP_MI_STORE_URM_MEM                 0x2D  /* HSW+ */
114 #define OP_MI_2E                            0x2E  /* BDW+ */
115 #define OP_MI_2F                            0x2F  /* BDW+ */
116 #define OP_MI_BATCH_BUFFER_START            0x31
117
118 /* Bit definition for dword 0 */
119 #define _CMDBIT_BB_START_IN_PPGTT       (1UL << 8)
120
121 #define OP_MI_CONDITIONAL_BATCH_BUFFER_END  0x36
122
123 #define BATCH_BUFFER_ADDR_MASK ((1UL << 32) - (1U << 2))
124 #define BATCH_BUFFER_ADDR_HIGH_MASK ((1UL << 16) - (1U))
125 #define BATCH_BUFFER_ADR_SPACE_BIT(x)   (((x) >> 8) & 1U)
126 #define BATCH_BUFFER_2ND_LEVEL_BIT(x)   ((x) >> 22 & 1U)
127
128 /* 2D command: Opcode (28:22) */
129 #define OP_2D(x)    ((2<<7) | x)
130
131 #define OP_XY_SETUP_BLT                             OP_2D(0x1)
132 #define OP_XY_SETUP_CLIP_BLT                        OP_2D(0x3)
133 #define OP_XY_SETUP_MONO_PATTERN_SL_BLT             OP_2D(0x11)
134 #define OP_XY_PIXEL_BLT                             OP_2D(0x24)
135 #define OP_XY_SCANLINES_BLT                         OP_2D(0x25)
136 #define OP_XY_TEXT_BLT                              OP_2D(0x26)
137 #define OP_XY_TEXT_IMMEDIATE_BLT                    OP_2D(0x31)
138 #define OP_XY_COLOR_BLT                             OP_2D(0x50)
139 #define OP_XY_PAT_BLT                               OP_2D(0x51)
140 #define OP_XY_MONO_PAT_BLT                          OP_2D(0x52)
141 #define OP_XY_SRC_COPY_BLT                          OP_2D(0x53)
142 #define OP_XY_MONO_SRC_COPY_BLT                     OP_2D(0x54)
143 #define OP_XY_FULL_BLT                              OP_2D(0x55)
144 #define OP_XY_FULL_MONO_SRC_BLT                     OP_2D(0x56)
145 #define OP_XY_FULL_MONO_PATTERN_BLT                 OP_2D(0x57)
146 #define OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT        OP_2D(0x58)
147 #define OP_XY_MONO_PAT_FIXED_BLT                    OP_2D(0x59)
148 #define OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT           OP_2D(0x71)
149 #define OP_XY_PAT_BLT_IMMEDIATE                     OP_2D(0x72)
150 #define OP_XY_SRC_COPY_CHROMA_BLT                   OP_2D(0x73)
151 #define OP_XY_FULL_IMMEDIATE_PATTERN_BLT            OP_2D(0x74)
152 #define OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT   OP_2D(0x75)
153 #define OP_XY_PAT_CHROMA_BLT                        OP_2D(0x76)
154 #define OP_XY_PAT_CHROMA_BLT_IMMEDIATE              OP_2D(0x77)
155
156 /* 3D/Media Command: Pipeline Type(28:27) Opcode(26:24) Sub Opcode(23:16) */
157 #define OP_3D_MEDIA(sub_type, opcode, sub_opcode) \
158         ((3 << 13) | ((sub_type) << 11) | ((opcode) << 8) | (sub_opcode))
159
160 #define OP_STATE_PREFETCH                       OP_3D_MEDIA(0x0, 0x0, 0x03)
161
162 #define OP_STATE_BASE_ADDRESS                   OP_3D_MEDIA(0x0, 0x1, 0x01)
163 #define OP_STATE_SIP                            OP_3D_MEDIA(0x0, 0x1, 0x02)
164 #define OP_3D_MEDIA_0_1_4                       OP_3D_MEDIA(0x0, 0x1, 0x04)
165
166 #define OP_3DSTATE_VF_STATISTICS_GM45           OP_3D_MEDIA(0x1, 0x0, 0x0B)
167
168 #define OP_PIPELINE_SELECT                      OP_3D_MEDIA(0x1, 0x1, 0x04)
169
170 #define OP_MEDIA_VFE_STATE                      OP_3D_MEDIA(0x2, 0x0, 0x0)
171 #define OP_MEDIA_CURBE_LOAD                     OP_3D_MEDIA(0x2, 0x0, 0x1)
172 #define OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD      OP_3D_MEDIA(0x2, 0x0, 0x2)
173 #define OP_MEDIA_GATEWAY_STATE                  OP_3D_MEDIA(0x2, 0x0, 0x3)
174 #define OP_MEDIA_STATE_FLUSH                    OP_3D_MEDIA(0x2, 0x0, 0x4)
175
176 #define OP_MEDIA_OBJECT                         OP_3D_MEDIA(0x2, 0x1, 0x0)
177 #define OP_MEDIA_OBJECT_PRT                     OP_3D_MEDIA(0x2, 0x1, 0x2)
178 #define OP_MEDIA_OBJECT_WALKER                  OP_3D_MEDIA(0x2, 0x1, 0x3)
179 #define OP_GPGPU_WALKER                         OP_3D_MEDIA(0x2, 0x1, 0x5)
180
181 #define OP_3DSTATE_CLEAR_PARAMS                 OP_3D_MEDIA(0x3, 0x0, 0x04) /* IVB+ */
182 #define OP_3DSTATE_DEPTH_BUFFER                 OP_3D_MEDIA(0x3, 0x0, 0x05) /* IVB+ */
183 #define OP_3DSTATE_STENCIL_BUFFER               OP_3D_MEDIA(0x3, 0x0, 0x06) /* IVB+ */
184 #define OP_3DSTATE_HIER_DEPTH_BUFFER            OP_3D_MEDIA(0x3, 0x0, 0x07) /* IVB+ */
185 #define OP_3DSTATE_VERTEX_BUFFERS               OP_3D_MEDIA(0x3, 0x0, 0x08)
186 #define OP_3DSTATE_VERTEX_ELEMENTS              OP_3D_MEDIA(0x3, 0x0, 0x09)
187 #define OP_3DSTATE_INDEX_BUFFER                 OP_3D_MEDIA(0x3, 0x0, 0x0A)
188 #define OP_3DSTATE_VF_STATISTICS                OP_3D_MEDIA(0x3, 0x0, 0x0B)
189 #define OP_3DSTATE_VF                           OP_3D_MEDIA(0x3, 0x0, 0x0C)  /* HSW+ */
190 #define OP_3DSTATE_CC_STATE_POINTERS            OP_3D_MEDIA(0x3, 0x0, 0x0E)
191 #define OP_3DSTATE_SCISSOR_STATE_POINTERS       OP_3D_MEDIA(0x3, 0x0, 0x0F)
192 #define OP_3DSTATE_VS                           OP_3D_MEDIA(0x3, 0x0, 0x10)
193 #define OP_3DSTATE_GS                           OP_3D_MEDIA(0x3, 0x0, 0x11)
194 #define OP_3DSTATE_CLIP                         OP_3D_MEDIA(0x3, 0x0, 0x12)
195 #define OP_3DSTATE_SF                           OP_3D_MEDIA(0x3, 0x0, 0x13)
196 #define OP_3DSTATE_WM                           OP_3D_MEDIA(0x3, 0x0, 0x14)
197 #define OP_3DSTATE_CONSTANT_VS                  OP_3D_MEDIA(0x3, 0x0, 0x15)
198 #define OP_3DSTATE_CONSTANT_GS                  OP_3D_MEDIA(0x3, 0x0, 0x16)
199 #define OP_3DSTATE_CONSTANT_PS                  OP_3D_MEDIA(0x3, 0x0, 0x17)
200 #define OP_3DSTATE_SAMPLE_MASK                  OP_3D_MEDIA(0x3, 0x0, 0x18)
201 #define OP_3DSTATE_CONSTANT_HS                  OP_3D_MEDIA(0x3, 0x0, 0x19) /* IVB+ */
202 #define OP_3DSTATE_CONSTANT_DS                  OP_3D_MEDIA(0x3, 0x0, 0x1A) /* IVB+ */
203 #define OP_3DSTATE_HS                           OP_3D_MEDIA(0x3, 0x0, 0x1B) /* IVB+ */
204 #define OP_3DSTATE_TE                           OP_3D_MEDIA(0x3, 0x0, 0x1C) /* IVB+ */
205 #define OP_3DSTATE_DS                           OP_3D_MEDIA(0x3, 0x0, 0x1D) /* IVB+ */
206 #define OP_3DSTATE_STREAMOUT                    OP_3D_MEDIA(0x3, 0x0, 0x1E) /* IVB+ */
207 #define OP_3DSTATE_SBE                          OP_3D_MEDIA(0x3, 0x0, 0x1F) /* IVB+ */
208 #define OP_3DSTATE_PS                           OP_3D_MEDIA(0x3, 0x0, 0x20) /* IVB+ */
209 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP OP_3D_MEDIA(0x3, 0x0, 0x21) /* IVB+ */
210 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC   OP_3D_MEDIA(0x3, 0x0, 0x23) /* IVB+ */
211 #define OP_3DSTATE_BLEND_STATE_POINTERS         OP_3D_MEDIA(0x3, 0x0, 0x24) /* IVB+ */
212 #define OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x25) /* IVB+ */
213 #define OP_3DSTATE_BINDING_TABLE_POINTERS_VS    OP_3D_MEDIA(0x3, 0x0, 0x26) /* IVB+ */
214 #define OP_3DSTATE_BINDING_TABLE_POINTERS_HS    OP_3D_MEDIA(0x3, 0x0, 0x27) /* IVB+ */
215 #define OP_3DSTATE_BINDING_TABLE_POINTERS_DS    OP_3D_MEDIA(0x3, 0x0, 0x28) /* IVB+ */
216 #define OP_3DSTATE_BINDING_TABLE_POINTERS_GS    OP_3D_MEDIA(0x3, 0x0, 0x29) /* IVB+ */
217 #define OP_3DSTATE_BINDING_TABLE_POINTERS_PS    OP_3D_MEDIA(0x3, 0x0, 0x2A) /* IVB+ */
218 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_VS    OP_3D_MEDIA(0x3, 0x0, 0x2B) /* IVB+ */
219 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_HS    OP_3D_MEDIA(0x3, 0x0, 0x2C) /* IVB+ */
220 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_DS    OP_3D_MEDIA(0x3, 0x0, 0x2D) /* IVB+ */
221 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_GS    OP_3D_MEDIA(0x3, 0x0, 0x2E) /* IVB+ */
222 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_PS    OP_3D_MEDIA(0x3, 0x0, 0x2F) /* IVB+ */
223 #define OP_3DSTATE_URB_VS                       OP_3D_MEDIA(0x3, 0x0, 0x30) /* IVB+ */
224 #define OP_3DSTATE_URB_HS                       OP_3D_MEDIA(0x3, 0x0, 0x31) /* IVB+ */
225 #define OP_3DSTATE_URB_DS                       OP_3D_MEDIA(0x3, 0x0, 0x32) /* IVB+ */
226 #define OP_3DSTATE_URB_GS                       OP_3D_MEDIA(0x3, 0x0, 0x33) /* IVB+ */
227 #define OP_3DSTATE_GATHER_CONSTANT_VS           OP_3D_MEDIA(0x3, 0x0, 0x34) /* HSW+ */
228 #define OP_3DSTATE_GATHER_CONSTANT_GS           OP_3D_MEDIA(0x3, 0x0, 0x35) /* HSW+ */
229 #define OP_3DSTATE_GATHER_CONSTANT_HS           OP_3D_MEDIA(0x3, 0x0, 0x36) /* HSW+ */
230 #define OP_3DSTATE_GATHER_CONSTANT_DS           OP_3D_MEDIA(0x3, 0x0, 0x37) /* HSW+ */
231 #define OP_3DSTATE_GATHER_CONSTANT_PS           OP_3D_MEDIA(0x3, 0x0, 0x38) /* HSW+ */
232 #define OP_3DSTATE_DX9_CONSTANTF_VS             OP_3D_MEDIA(0x3, 0x0, 0x39) /* HSW+ */
233 #define OP_3DSTATE_DX9_CONSTANTF_PS             OP_3D_MEDIA(0x3, 0x0, 0x3A) /* HSW+ */
234 #define OP_3DSTATE_DX9_CONSTANTI_VS             OP_3D_MEDIA(0x3, 0x0, 0x3B) /* HSW+ */
235 #define OP_3DSTATE_DX9_CONSTANTI_PS             OP_3D_MEDIA(0x3, 0x0, 0x3C) /* HSW+ */
236 #define OP_3DSTATE_DX9_CONSTANTB_VS             OP_3D_MEDIA(0x3, 0x0, 0x3D) /* HSW+ */
237 #define OP_3DSTATE_DX9_CONSTANTB_PS             OP_3D_MEDIA(0x3, 0x0, 0x3E) /* HSW+ */
238 #define OP_3DSTATE_DX9_LOCAL_VALID_VS           OP_3D_MEDIA(0x3, 0x0, 0x3F) /* HSW+ */
239 #define OP_3DSTATE_DX9_LOCAL_VALID_PS           OP_3D_MEDIA(0x3, 0x0, 0x40) /* HSW+ */
240 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_VS       OP_3D_MEDIA(0x3, 0x0, 0x41) /* HSW+ */
241 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_PS       OP_3D_MEDIA(0x3, 0x0, 0x42) /* HSW+ */
242 #define OP_3DSTATE_BINDING_TABLE_EDIT_VS        OP_3D_MEDIA(0x3, 0x0, 0x43) /* HSW+ */
243 #define OP_3DSTATE_BINDING_TABLE_EDIT_GS        OP_3D_MEDIA(0x3, 0x0, 0x44) /* HSW+ */
244 #define OP_3DSTATE_BINDING_TABLE_EDIT_HS        OP_3D_MEDIA(0x3, 0x0, 0x45) /* HSW+ */
245 #define OP_3DSTATE_BINDING_TABLE_EDIT_DS        OP_3D_MEDIA(0x3, 0x0, 0x46) /* HSW+ */
246 #define OP_3DSTATE_BINDING_TABLE_EDIT_PS        OP_3D_MEDIA(0x3, 0x0, 0x47) /* HSW+ */
247
248 #define OP_3DSTATE_VF_INSTANCING                OP_3D_MEDIA(0x3, 0x0, 0x49) /* BDW+ */
249 #define OP_3DSTATE_VF_SGVS                      OP_3D_MEDIA(0x3, 0x0, 0x4A) /* BDW+ */
250 #define OP_3DSTATE_VF_TOPOLOGY                  OP_3D_MEDIA(0x3, 0x0, 0x4B) /* BDW+ */
251 #define OP_3DSTATE_WM_CHROMAKEY                 OP_3D_MEDIA(0x3, 0x0, 0x4C) /* BDW+ */
252 #define OP_3DSTATE_PS_BLEND                     OP_3D_MEDIA(0x3, 0x0, 0x4D) /* BDW+ */
253 #define OP_3DSTATE_WM_DEPTH_STENCIL             OP_3D_MEDIA(0x3, 0x0, 0x4E) /* BDW+ */
254 #define OP_3DSTATE_PS_EXTRA                     OP_3D_MEDIA(0x3, 0x0, 0x4F) /* BDW+ */
255 #define OP_3DSTATE_RASTER                       OP_3D_MEDIA(0x3, 0x0, 0x50) /* BDW+ */
256 #define OP_3DSTATE_SBE_SWIZ                     OP_3D_MEDIA(0x3, 0x0, 0x51) /* BDW+ */
257 #define OP_3DSTATE_WM_HZ_OP                     OP_3D_MEDIA(0x3, 0x0, 0x52) /* BDW+ */
258 #define OP_3DSTATE_COMPONENT_PACKING            OP_3D_MEDIA(0x3, 0x0, 0x55) /* SKL+ */
259
260 #define OP_3DSTATE_DRAWING_RECTANGLE            OP_3D_MEDIA(0x3, 0x1, 0x00)
261 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD0        OP_3D_MEDIA(0x3, 0x1, 0x02)
262 #define OP_3DSTATE_CHROMA_KEY                   OP_3D_MEDIA(0x3, 0x1, 0x04)
263 #define OP_SNB_3DSTATE_DEPTH_BUFFER             OP_3D_MEDIA(0x3, 0x1, 0x05)
264 #define OP_3DSTATE_POLY_STIPPLE_OFFSET          OP_3D_MEDIA(0x3, 0x1, 0x06)
265 #define OP_3DSTATE_POLY_STIPPLE_PATTERN         OP_3D_MEDIA(0x3, 0x1, 0x07)
266 #define OP_3DSTATE_LINE_STIPPLE                 OP_3D_MEDIA(0x3, 0x1, 0x08)
267 #define OP_3DSTATE_AA_LINE_PARAMS               OP_3D_MEDIA(0x3, 0x1, 0x0A)
268 #define OP_3DSTATE_GS_SVB_INDEX                 OP_3D_MEDIA(0x3, 0x1, 0x0B)
269 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD1        OP_3D_MEDIA(0x3, 0x1, 0x0C)
270 #define OP_3DSTATE_MULTISAMPLE_BDW              OP_3D_MEDIA(0x3, 0x0, 0x0D)
271 #define OP_SNB_3DSTATE_STENCIL_BUFFER           OP_3D_MEDIA(0x3, 0x1, 0x0E)
272 #define OP_SNB_3DSTATE_HIER_DEPTH_BUFFER        OP_3D_MEDIA(0x3, 0x1, 0x0F)
273 #define OP_SNB_3DSTATE_CLEAR_PARAMS             OP_3D_MEDIA(0x3, 0x1, 0x10)
274 #define OP_3DSTATE_MONOFILTER_SIZE              OP_3D_MEDIA(0x3, 0x1, 0x11)
275 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS       OP_3D_MEDIA(0x3, 0x1, 0x12) /* IVB+ */
276 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS       OP_3D_MEDIA(0x3, 0x1, 0x13) /* IVB+ */
277 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS       OP_3D_MEDIA(0x3, 0x1, 0x14) /* IVB+ */
278 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS       OP_3D_MEDIA(0x3, 0x1, 0x15) /* IVB+ */
279 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS       OP_3D_MEDIA(0x3, 0x1, 0x16) /* IVB+ */
280 #define OP_3DSTATE_SO_DECL_LIST                 OP_3D_MEDIA(0x3, 0x1, 0x17)
281 #define OP_3DSTATE_SO_BUFFER                    OP_3D_MEDIA(0x3, 0x1, 0x18)
282 #define OP_3DSTATE_BINDING_TABLE_POOL_ALLOC     OP_3D_MEDIA(0x3, 0x1, 0x19) /* HSW+ */
283 #define OP_3DSTATE_GATHER_POOL_ALLOC            OP_3D_MEDIA(0x3, 0x1, 0x1A) /* HSW+ */
284 #define OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1B) /* HSW+ */
285 #define OP_3DSTATE_SAMPLE_PATTERN               OP_3D_MEDIA(0x3, 0x1, 0x1C)
286 #define OP_PIPE_CONTROL                         OP_3D_MEDIA(0x3, 0x2, 0x00)
287 #define OP_3DPRIMITIVE                          OP_3D_MEDIA(0x3, 0x3, 0x00)
288
289 /* VCCP Command Parser */
290
291 /*
292  * Below MFX and VBE cmd definition is from vaapi intel driver project (BSD License)
293  * git://anongit.freedesktop.org/vaapi/intel-driver
294  * src/i965_defines.h
295  *
296  */
297
298 #define OP_MFX(pipeline, op, sub_opa, sub_opb)     \
299         (3 << 13 | \
300          (pipeline) << 11 | \
301          (op) << 8 | \
302          (sub_opa) << 5 | \
303          (sub_opb))
304
305 #define OP_MFX_PIPE_MODE_SELECT                    OP_MFX(2, 0, 0, 0)  /* ALL */
306 #define OP_MFX_SURFACE_STATE                       OP_MFX(2, 0, 0, 1)  /* ALL */
307 #define OP_MFX_PIPE_BUF_ADDR_STATE                 OP_MFX(2, 0, 0, 2)  /* ALL */
308 #define OP_MFX_IND_OBJ_BASE_ADDR_STATE             OP_MFX(2, 0, 0, 3)  /* ALL */
309 #define OP_MFX_BSP_BUF_BASE_ADDR_STATE             OP_MFX(2, 0, 0, 4)  /* ALL */
310 #define OP_2_0_0_5                                 OP_MFX(2, 0, 0, 5)  /* ALL */
311 #define OP_MFX_STATE_POINTER                       OP_MFX(2, 0, 0, 6)  /* ALL */
312 #define OP_MFX_QM_STATE                            OP_MFX(2, 0, 0, 7)  /* IVB+ */
313 #define OP_MFX_FQM_STATE                           OP_MFX(2, 0, 0, 8)  /* IVB+ */
314 #define OP_MFX_PAK_INSERT_OBJECT                   OP_MFX(2, 0, 2, 8)  /* IVB+ */
315 #define OP_MFX_STITCH_OBJECT                       OP_MFX(2, 0, 2, 0xA)  /* IVB+ */
316
317 #define OP_MFD_IT_OBJECT                           OP_MFX(2, 0, 1, 9) /* ALL */
318
319 #define OP_MFX_WAIT                                OP_MFX(1, 0, 0, 0) /* IVB+ */
320 #define OP_MFX_AVC_IMG_STATE                       OP_MFX(2, 1, 0, 0) /* ALL */
321 #define OP_MFX_AVC_QM_STATE                        OP_MFX(2, 1, 0, 1) /* ALL */
322 #define OP_MFX_AVC_DIRECTMODE_STATE                OP_MFX(2, 1, 0, 2) /* ALL */
323 #define OP_MFX_AVC_SLICE_STATE                     OP_MFX(2, 1, 0, 3) /* ALL */
324 #define OP_MFX_AVC_REF_IDX_STATE                   OP_MFX(2, 1, 0, 4) /* ALL */
325 #define OP_MFX_AVC_WEIGHTOFFSET_STATE              OP_MFX(2, 1, 0, 5) /* ALL */
326 #define OP_MFD_AVC_PICID_STATE                     OP_MFX(2, 1, 1, 5) /* HSW+ */
327 #define OP_MFD_AVC_DPB_STATE                       OP_MFX(2, 1, 1, 6) /* IVB+ */
328 #define OP_MFD_AVC_SLICEADDR                       OP_MFX(2, 1, 1, 7) /* IVB+ */
329 #define OP_MFD_AVC_BSD_OBJECT                      OP_MFX(2, 1, 1, 8) /* ALL */
330 #define OP_MFC_AVC_PAK_OBJECT                      OP_MFX(2, 1, 2, 9) /* ALL */
331
332 #define OP_MFX_VC1_PRED_PIPE_STATE                 OP_MFX(2, 2, 0, 1) /* ALL */
333 #define OP_MFX_VC1_DIRECTMODE_STATE                OP_MFX(2, 2, 0, 2) /* ALL */
334 #define OP_MFD_VC1_SHORT_PIC_STATE                 OP_MFX(2, 2, 1, 0) /* IVB+ */
335 #define OP_MFD_VC1_LONG_PIC_STATE                  OP_MFX(2, 2, 1, 1) /* IVB+ */
336 #define OP_MFD_VC1_BSD_OBJECT                      OP_MFX(2, 2, 1, 8) /* ALL */
337
338 #define OP_MFX_MPEG2_PIC_STATE                     OP_MFX(2, 3, 0, 0) /* ALL */
339 #define OP_MFX_MPEG2_QM_STATE                      OP_MFX(2, 3, 0, 1) /* ALL */
340 #define OP_MFD_MPEG2_BSD_OBJECT                    OP_MFX(2, 3, 1, 8) /* ALL */
341 #define OP_MFC_MPEG2_SLICEGROUP_STATE              OP_MFX(2, 3, 2, 3) /* ALL */
342 #define OP_MFC_MPEG2_PAK_OBJECT                    OP_MFX(2, 3, 2, 9) /* ALL */
343
344 #define OP_MFX_2_6_0_0                             OP_MFX(2, 6, 0, 0) /* IVB+ */
345 #define OP_MFX_2_6_0_8                             OP_MFX(2, 6, 0, 8) /* IVB+ */
346 #define OP_MFX_2_6_0_9                             OP_MFX(2, 6, 0, 9) /* IVB+ */
347
348 #define OP_MFX_JPEG_PIC_STATE                      OP_MFX(2, 7, 0, 0)
349 #define OP_MFX_JPEG_HUFF_TABLE_STATE               OP_MFX(2, 7, 0, 2)
350 #define OP_MFD_JPEG_BSD_OBJECT                     OP_MFX(2, 7, 1, 8)
351
352 #define OP_VEB(pipeline, op, sub_opa, sub_opb) \
353         (3 << 13 | \
354          (pipeline) << 11 | \
355          (op) << 8 | \
356          (sub_opa) << 5 | \
357          (sub_opb))
358
359 #define OP_VEB_SURFACE_STATE                       OP_VEB(2, 4, 0, 0)
360 #define OP_VEB_STATE                               OP_VEB(2, 4, 0, 2)
361 #define OP_VEB_DNDI_IECP_STATE                     OP_VEB(2, 4, 0, 3)
362
363 struct parser_exec_state;
364
365 typedef int (*parser_cmd_handler)(struct parser_exec_state *s);
366
367 #define GVT_CMD_HASH_BITS   7
368
369 /* which DWords need address fix */
370 #define ADDR_FIX_1(x1)                  (1 << (x1))
371 #define ADDR_FIX_2(x1, x2)              (ADDR_FIX_1(x1) | ADDR_FIX_1(x2))
372 #define ADDR_FIX_3(x1, x2, x3)          (ADDR_FIX_1(x1) | ADDR_FIX_2(x2, x3))
373 #define ADDR_FIX_4(x1, x2, x3, x4)      (ADDR_FIX_1(x1) | ADDR_FIX_3(x2, x3, x4))
374 #define ADDR_FIX_5(x1, x2, x3, x4, x5)  (ADDR_FIX_1(x1) | ADDR_FIX_4(x2, x3, x4, x5))
375
376 struct cmd_info {
377         char *name;
378         u32 opcode;
379
380 #define F_LEN_MASK      (1U<<0)
381 #define F_LEN_CONST  1U
382 #define F_LEN_VAR    0U
383
384 /*
385  * command has its own ip advance logic
386  * e.g. MI_BATCH_START, MI_BATCH_END
387  */
388 #define F_IP_ADVANCE_CUSTOM (1<<1)
389
390 #define F_POST_HANDLE   (1<<2)
391         u32 flag;
392
393 #define R_RCS   (1 << RCS)
394 #define R_VCS1  (1 << VCS)
395 #define R_VCS2  (1 << VCS2)
396 #define R_VCS   (R_VCS1 | R_VCS2)
397 #define R_BCS   (1 << BCS)
398 #define R_VECS  (1 << VECS)
399 #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
400         /* rings that support this cmd: BLT/RCS/VCS/VECS */
401         uint16_t rings;
402
403         /* devices that support this cmd: SNB/IVB/HSW/... */
404         uint16_t devices;
405
406         /* which DWords are address that need fix up.
407          * bit 0 means a 32-bit non address operand in command
408          * bit 1 means address operand, which could be 32-bit
409          * or 64-bit depending on different architectures.(
410          * defined by "gmadr_bytes_in_cmd" in intel_gvt.
411          * No matter the address length, each address only takes
412          * one bit in the bitmap.
413          */
414         uint16_t addr_bitmap;
415
416         /* flag == F_LEN_CONST : command length
417          * flag == F_LEN_VAR : length bias bits
418          * Note: length is in DWord
419          */
420         uint8_t len;
421
422         parser_cmd_handler handler;
423 };
424
425 struct cmd_entry {
426         struct hlist_node hlist;
427         struct cmd_info *info;
428 };
429
430 enum {
431         RING_BUFFER_INSTRUCTION,
432         BATCH_BUFFER_INSTRUCTION,
433         BATCH_BUFFER_2ND_LEVEL,
434 };
435
436 enum {
437         GTT_BUFFER,
438         PPGTT_BUFFER
439 };
440
441 struct parser_exec_state {
442         struct intel_vgpu *vgpu;
443         int ring_id;
444
445         int buf_type;
446
447         /* batch buffer address type */
448         int buf_addr_type;
449
450         /* graphics memory address of ring buffer start */
451         unsigned long ring_start;
452         unsigned long ring_size;
453         unsigned long ring_head;
454         unsigned long ring_tail;
455
456         /* instruction graphics memory address */
457         unsigned long ip_gma;
458
459         /* mapped va of the instr_gma */
460         void *ip_va;
461         void *rb_va;
462
463         void *ret_bb_va;
464         /* next instruction when return from  batch buffer to ring buffer */
465         unsigned long ret_ip_gma_ring;
466
467         /* next instruction when return from 2nd batch buffer to batch buffer */
468         unsigned long ret_ip_gma_bb;
469
470         /* batch buffer address type (GTT or PPGTT)
471          * used when ret from 2nd level batch buffer
472          */
473         int saved_buf_addr_type;
474         bool is_ctx_wa;
475
476         struct cmd_info *info;
477
478         struct intel_vgpu_workload *workload;
479 };
480
481 #define gmadr_dw_number(s)      \
482         (s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2)
483
484 static unsigned long bypass_scan_mask = 0;
485
486 /* ring ALL, type = 0 */
487 static struct sub_op_bits sub_op_mi[] = {
488         {31, 29},
489         {28, 23},
490 };
491
492 static struct decode_info decode_info_mi = {
493         "MI",
494         OP_LEN_MI,
495         ARRAY_SIZE(sub_op_mi),
496         sub_op_mi,
497 };
498
499 /* ring RCS, command type 2 */
500 static struct sub_op_bits sub_op_2d[] = {
501         {31, 29},
502         {28, 22},
503 };
504
505 static struct decode_info decode_info_2d = {
506         "2D",
507         OP_LEN_2D,
508         ARRAY_SIZE(sub_op_2d),
509         sub_op_2d,
510 };
511
512 /* ring RCS, command type 3 */
513 static struct sub_op_bits sub_op_3d_media[] = {
514         {31, 29},
515         {28, 27},
516         {26, 24},
517         {23, 16},
518 };
519
520 static struct decode_info decode_info_3d_media = {
521         "3D_Media",
522         OP_LEN_3D_MEDIA,
523         ARRAY_SIZE(sub_op_3d_media),
524         sub_op_3d_media,
525 };
526
527 /* ring VCS, command type 3 */
528 static struct sub_op_bits sub_op_mfx_vc[] = {
529         {31, 29},
530         {28, 27},
531         {26, 24},
532         {23, 21},
533         {20, 16},
534 };
535
536 static struct decode_info decode_info_mfx_vc = {
537         "MFX_VC",
538         OP_LEN_MFX_VC,
539         ARRAY_SIZE(sub_op_mfx_vc),
540         sub_op_mfx_vc,
541 };
542
543 /* ring VECS, command type 3 */
544 static struct sub_op_bits sub_op_vebox[] = {
545         {31, 29},
546         {28, 27},
547         {26, 24},
548         {23, 21},
549         {20, 16},
550 };
551
552 static struct decode_info decode_info_vebox = {
553         "VEBOX",
554         OP_LEN_VEBOX,
555         ARRAY_SIZE(sub_op_vebox),
556         sub_op_vebox,
557 };
558
559 static struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
560         [RCS] = {
561                 &decode_info_mi,
562                 NULL,
563                 NULL,
564                 &decode_info_3d_media,
565                 NULL,
566                 NULL,
567                 NULL,
568                 NULL,
569         },
570
571         [VCS] = {
572                 &decode_info_mi,
573                 NULL,
574                 NULL,
575                 &decode_info_mfx_vc,
576                 NULL,
577                 NULL,
578                 NULL,
579                 NULL,
580         },
581
582         [BCS] = {
583                 &decode_info_mi,
584                 NULL,
585                 &decode_info_2d,
586                 NULL,
587                 NULL,
588                 NULL,
589                 NULL,
590                 NULL,
591         },
592
593         [VECS] = {
594                 &decode_info_mi,
595                 NULL,
596                 NULL,
597                 &decode_info_vebox,
598                 NULL,
599                 NULL,
600                 NULL,
601                 NULL,
602         },
603
604         [VCS2] = {
605                 &decode_info_mi,
606                 NULL,
607                 NULL,
608                 &decode_info_mfx_vc,
609                 NULL,
610                 NULL,
611                 NULL,
612                 NULL,
613         },
614 };
615
616 static inline u32 get_opcode(u32 cmd, int ring_id)
617 {
618         struct decode_info *d_info;
619
620         d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)];
621         if (d_info == NULL)
622                 return INVALID_OP;
623
624         return cmd >> (32 - d_info->op_len);
625 }
626
627 static inline struct cmd_info *find_cmd_entry(struct intel_gvt *gvt,
628                 unsigned int opcode, int ring_id)
629 {
630         struct cmd_entry *e;
631
632         hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) {
633                 if ((opcode == e->info->opcode) &&
634                                 (e->info->rings & (1 << ring_id)))
635                         return e->info;
636         }
637         return NULL;
638 }
639
640 static inline struct cmd_info *get_cmd_info(struct intel_gvt *gvt,
641                 u32 cmd, int ring_id)
642 {
643         u32 opcode;
644
645         opcode = get_opcode(cmd, ring_id);
646         if (opcode == INVALID_OP)
647                 return NULL;
648
649         return find_cmd_entry(gvt, opcode, ring_id);
650 }
651
652 static inline u32 sub_op_val(u32 cmd, u32 hi, u32 low)
653 {
654         return (cmd >> low) & ((1U << (hi - low + 1)) - 1);
655 }
656
657 static inline void print_opcode(u32 cmd, int ring_id)
658 {
659         struct decode_info *d_info;
660         int i;
661
662         d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)];
663         if (d_info == NULL)
664                 return;
665
666         gvt_dbg_cmd("opcode=0x%x %s sub_ops:",
667                         cmd >> (32 - d_info->op_len), d_info->name);
668
669         for (i = 0; i < d_info->nr_sub_op; i++)
670                 pr_err("0x%x ", sub_op_val(cmd, d_info->sub_op[i].hi,
671                                         d_info->sub_op[i].low));
672
673         pr_err("\n");
674 }
675
676 static inline u32 *cmd_ptr(struct parser_exec_state *s, int index)
677 {
678         return s->ip_va + (index << 2);
679 }
680
681 static inline u32 cmd_val(struct parser_exec_state *s, int index)
682 {
683         return *cmd_ptr(s, index);
684 }
685
686 static void parser_exec_state_dump(struct parser_exec_state *s)
687 {
688         int cnt = 0;
689         int i;
690
691         gvt_dbg_cmd("  vgpu%d RING%d: ring_start(%08lx) ring_end(%08lx)"
692                         " ring_head(%08lx) ring_tail(%08lx)\n", s->vgpu->id,
693                         s->ring_id, s->ring_start, s->ring_start + s->ring_size,
694                         s->ring_head, s->ring_tail);
695
696         gvt_dbg_cmd("  %s %s ip_gma(%08lx) ",
697                         s->buf_type == RING_BUFFER_INSTRUCTION ?
698                         "RING_BUFFER" : "BATCH_BUFFER",
699                         s->buf_addr_type == GTT_BUFFER ?
700                         "GTT" : "PPGTT", s->ip_gma);
701
702         if (s->ip_va == NULL) {
703                 gvt_dbg_cmd(" ip_va(NULL)");
704                 return;
705         }
706
707         gvt_dbg_cmd("  ip_va=%p: %08x %08x %08x %08x\n",
708                         s->ip_va, cmd_val(s, 0), cmd_val(s, 1),
709                         cmd_val(s, 2), cmd_val(s, 3));
710
711         print_opcode(cmd_val(s, 0), s->ring_id);
712
713         s->ip_va = (u32 *)((((u64)s->ip_va) >> 12) << 12);
714
715         while (cnt < 1024) {
716                 gvt_dbg_cmd("ip_va=%p: ", s->ip_va);
717                 for (i = 0; i < 8; i++)
718                         gvt_dbg_cmd("%08x ", cmd_val(s, i));
719                 gvt_dbg_cmd("\n");
720
721                 s->ip_va += 8 * sizeof(u32);
722                 cnt += 8;
723         }
724 }
725
726 static inline void update_ip_va(struct parser_exec_state *s)
727 {
728         unsigned long len = 0;
729
730         if (WARN_ON(s->ring_head == s->ring_tail))
731                 return;
732
733         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
734                 unsigned long ring_top = s->ring_start + s->ring_size;
735
736                 if (s->ring_head > s->ring_tail) {
737                         if (s->ip_gma >= s->ring_head && s->ip_gma < ring_top)
738                                 len = (s->ip_gma - s->ring_head);
739                         else if (s->ip_gma >= s->ring_start &&
740                                         s->ip_gma <= s->ring_tail)
741                                 len = (ring_top - s->ring_head) +
742                                         (s->ip_gma - s->ring_start);
743                 } else
744                         len = (s->ip_gma - s->ring_head);
745
746                 s->ip_va = s->rb_va + len;
747         } else {/* shadow batch buffer */
748                 s->ip_va = s->ret_bb_va;
749         }
750 }
751
752 static inline int ip_gma_set(struct parser_exec_state *s,
753                 unsigned long ip_gma)
754 {
755         WARN_ON(!IS_ALIGNED(ip_gma, 4));
756
757         s->ip_gma = ip_gma;
758         update_ip_va(s);
759         return 0;
760 }
761
762 static inline int ip_gma_advance(struct parser_exec_state *s,
763                 unsigned int dw_len)
764 {
765         s->ip_gma += (dw_len << 2);
766
767         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
768                 if (s->ip_gma >= s->ring_start + s->ring_size)
769                         s->ip_gma -= s->ring_size;
770                 update_ip_va(s);
771         } else {
772                 s->ip_va += (dw_len << 2);
773         }
774
775         return 0;
776 }
777
778 static inline int get_cmd_length(struct cmd_info *info, u32 cmd)
779 {
780         if ((info->flag & F_LEN_MASK) == F_LEN_CONST)
781                 return info->len;
782         else
783                 return (cmd & ((1U << info->len) - 1)) + 2;
784         return 0;
785 }
786
787 static inline int cmd_length(struct parser_exec_state *s)
788 {
789         return get_cmd_length(s->info, cmd_val(s, 0));
790 }
791
792 /* do not remove this, some platform may need clflush here */
793 #define patch_value(s, addr, val) do { \
794         *addr = val; \
795 } while (0)
796
797 static bool is_shadowed_mmio(unsigned int offset)
798 {
799         bool ret = false;
800
801         if ((offset == 0x2168) || /*BB current head register UDW */
802             (offset == 0x2140) || /*BB current header register */
803             (offset == 0x211c) || /*second BB header register UDW */
804             (offset == 0x2114)) { /*second BB header register UDW */
805                 ret = true;
806         }
807         return ret;
808 }
809
810 static inline bool is_force_nonpriv_mmio(unsigned int offset)
811 {
812         return (offset >= 0x24d0 && offset < 0x2500);
813 }
814
815 static int force_nonpriv_reg_handler(struct parser_exec_state *s,
816                 unsigned int offset, unsigned int index, char *cmd)
817 {
818         struct intel_gvt *gvt = s->vgpu->gvt;
819         unsigned int data;
820         u32 ring_base;
821         u32 nopid;
822         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
823
824         if (!strcmp(cmd, "lri"))
825                 data = cmd_val(s, index + 1);
826         else {
827                 gvt_err("Unexpected forcenonpriv 0x%x write from cmd %s\n",
828                         offset, cmd);
829                 return -EINVAL;
830         }
831
832         ring_base = dev_priv->engine[s->ring_id]->mmio_base;
833         nopid = i915_mmio_reg_offset(RING_NOPID(ring_base));
834
835         if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data) &&
836                         data != nopid) {
837                 gvt_err("Unexpected forcenonpriv 0x%x LRI write, value=0x%x\n",
838                         offset, data);
839                 patch_value(s, cmd_ptr(s, index), nopid);
840                 return 0;
841         }
842         return 0;
843 }
844
845 static inline bool is_mocs_mmio(unsigned int offset)
846 {
847         return ((offset >= 0xc800) && (offset <= 0xcff8)) ||
848                 ((offset >= 0xb020) && (offset <= 0xb0a0));
849 }
850
851 static int mocs_cmd_reg_handler(struct parser_exec_state *s,
852                                 unsigned int offset, unsigned int index)
853 {
854         if (!is_mocs_mmio(offset))
855                 return -EINVAL;
856         vgpu_vreg(s->vgpu, offset) = cmd_val(s, index + 1);
857         return 0;
858 }
859
860 static int cmd_reg_handler(struct parser_exec_state *s,
861         unsigned int offset, unsigned int index, char *cmd)
862 {
863         struct intel_vgpu *vgpu = s->vgpu;
864         struct intel_gvt *gvt = vgpu->gvt;
865
866         if (offset + 4 > gvt->device_info.mmio_size) {
867                 gvt_vgpu_err("%s access to (%x) outside of MMIO range\n",
868                                 cmd, offset);
869                 return -EFAULT;
870         }
871
872         if (!intel_gvt_mmio_is_cmd_access(gvt, offset)) {
873                 gvt_vgpu_err("%s access to non-render register (%x)\n",
874                                 cmd, offset);
875                 return 0;
876         }
877
878         if (is_shadowed_mmio(offset)) {
879                 gvt_vgpu_err("found access of shadowed MMIO %x\n", offset);
880                 return 0;
881         }
882
883         if (is_mocs_mmio(offset) &&
884             mocs_cmd_reg_handler(s, offset, index))
885                 return -EINVAL;
886
887         if (is_force_nonpriv_mmio(offset) &&
888                 force_nonpriv_reg_handler(s, offset, index, cmd))
889                 return -EPERM;
890
891         if (offset == i915_mmio_reg_offset(DERRMR) ||
892                 offset == i915_mmio_reg_offset(FORCEWAKE_MT)) {
893                 /* Writing to HW VGT_PVINFO_PAGE offset will be discarded */
894                 patch_value(s, cmd_ptr(s, index), VGT_PVINFO_PAGE);
895         }
896
897         /* TODO: Update the global mask if this MMIO is a masked-MMIO */
898         intel_gvt_mmio_set_cmd_accessed(gvt, offset);
899         return 0;
900 }
901
902 #define cmd_reg(s, i) \
903         (cmd_val(s, i) & GENMASK(22, 2))
904
905 #define cmd_reg_inhibit(s, i) \
906         (cmd_val(s, i) & GENMASK(22, 18))
907
908 #define cmd_gma(s, i) \
909         (cmd_val(s, i) & GENMASK(31, 2))
910
911 #define cmd_gma_hi(s, i) \
912         (cmd_val(s, i) & GENMASK(15, 0))
913
914 static int cmd_handler_lri(struct parser_exec_state *s)
915 {
916         int i, ret = 0;
917         int cmd_len = cmd_length(s);
918         struct intel_gvt *gvt = s->vgpu->gvt;
919
920         for (i = 1; i < cmd_len; i += 2) {
921                 if (IS_BROADWELL(gvt->dev_priv) &&
922                                 (s->ring_id != RCS)) {
923                         if (s->ring_id == BCS &&
924                                         cmd_reg(s, i) ==
925                                         i915_mmio_reg_offset(DERRMR))
926                                 ret |= 0;
927                         else
928                                 ret |= (cmd_reg_inhibit(s, i)) ?
929                                         -EBADRQC : 0;
930                 }
931                 if (ret)
932                         break;
933                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lri");
934                 if (ret)
935                         break;
936         }
937         return ret;
938 }
939
940 static int cmd_handler_lrr(struct parser_exec_state *s)
941 {
942         int i, ret = 0;
943         int cmd_len = cmd_length(s);
944
945         for (i = 1; i < cmd_len; i += 2) {
946                 if (IS_BROADWELL(s->vgpu->gvt->dev_priv))
947                         ret |= ((cmd_reg_inhibit(s, i) ||
948                                         (cmd_reg_inhibit(s, i + 1)))) ?
949                                 -EBADRQC : 0;
950                 if (ret)
951                         break;
952                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrr-src");
953                 if (ret)
954                         break;
955                 ret |= cmd_reg_handler(s, cmd_reg(s, i + 1), i, "lrr-dst");
956                 if (ret)
957                         break;
958         }
959         return ret;
960 }
961
962 static inline int cmd_address_audit(struct parser_exec_state *s,
963                 unsigned long guest_gma, int op_size, bool index_mode);
964
965 static int cmd_handler_lrm(struct parser_exec_state *s)
966 {
967         struct intel_gvt *gvt = s->vgpu->gvt;
968         int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
969         unsigned long gma;
970         int i, ret = 0;
971         int cmd_len = cmd_length(s);
972
973         for (i = 1; i < cmd_len;) {
974                 if (IS_BROADWELL(gvt->dev_priv))
975                         ret |= (cmd_reg_inhibit(s, i)) ? -EBADRQC : 0;
976                 if (ret)
977                         break;
978                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrm");
979                 if (ret)
980                         break;
981                 if (cmd_val(s, 0) & (1 << 22)) {
982                         gma = cmd_gma(s, i + 1);
983                         if (gmadr_bytes == 8)
984                                 gma |= (cmd_gma_hi(s, i + 2)) << 32;
985                         ret |= cmd_address_audit(s, gma, sizeof(u32), false);
986                         if (ret)
987                                 break;
988                 }
989                 i += gmadr_dw_number(s) + 1;
990         }
991         return ret;
992 }
993
994 static int cmd_handler_srm(struct parser_exec_state *s)
995 {
996         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
997         unsigned long gma;
998         int i, ret = 0;
999         int cmd_len = cmd_length(s);
1000
1001         for (i = 1; i < cmd_len;) {
1002                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "srm");
1003                 if (ret)
1004                         break;
1005                 if (cmd_val(s, 0) & (1 << 22)) {
1006                         gma = cmd_gma(s, i + 1);
1007                         if (gmadr_bytes == 8)
1008                                 gma |= (cmd_gma_hi(s, i + 2)) << 32;
1009                         ret |= cmd_address_audit(s, gma, sizeof(u32), false);
1010                         if (ret)
1011                                 break;
1012                 }
1013                 i += gmadr_dw_number(s) + 1;
1014         }
1015         return ret;
1016 }
1017
1018 struct cmd_interrupt_event {
1019         int pipe_control_notify;
1020         int mi_flush_dw;
1021         int mi_user_interrupt;
1022 };
1023
1024 static struct cmd_interrupt_event cmd_interrupt_events[] = {
1025         [RCS] = {
1026                 .pipe_control_notify = RCS_PIPE_CONTROL,
1027                 .mi_flush_dw = INTEL_GVT_EVENT_RESERVED,
1028                 .mi_user_interrupt = RCS_MI_USER_INTERRUPT,
1029         },
1030         [BCS] = {
1031                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1032                 .mi_flush_dw = BCS_MI_FLUSH_DW,
1033                 .mi_user_interrupt = BCS_MI_USER_INTERRUPT,
1034         },
1035         [VCS] = {
1036                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1037                 .mi_flush_dw = VCS_MI_FLUSH_DW,
1038                 .mi_user_interrupt = VCS_MI_USER_INTERRUPT,
1039         },
1040         [VCS2] = {
1041                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1042                 .mi_flush_dw = VCS2_MI_FLUSH_DW,
1043                 .mi_user_interrupt = VCS2_MI_USER_INTERRUPT,
1044         },
1045         [VECS] = {
1046                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1047                 .mi_flush_dw = VECS_MI_FLUSH_DW,
1048                 .mi_user_interrupt = VECS_MI_USER_INTERRUPT,
1049         },
1050 };
1051
1052 static int cmd_handler_pipe_control(struct parser_exec_state *s)
1053 {
1054         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1055         unsigned long gma;
1056         bool index_mode = false;
1057         unsigned int post_sync;
1058         int ret = 0;
1059
1060         post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14;
1061
1062         /* LRI post sync */
1063         if (cmd_val(s, 1) & PIPE_CONTROL_MMIO_WRITE)
1064                 ret = cmd_reg_handler(s, cmd_reg(s, 2), 1, "pipe_ctrl");
1065         /* post sync */
1066         else if (post_sync) {
1067                 if (post_sync == 2)
1068                         ret = cmd_reg_handler(s, 0x2350, 1, "pipe_ctrl");
1069                 else if (post_sync == 3)
1070                         ret = cmd_reg_handler(s, 0x2358, 1, "pipe_ctrl");
1071                 else if (post_sync == 1) {
1072                         /* check ggtt*/
1073                         if ((cmd_val(s, 1) & PIPE_CONTROL_GLOBAL_GTT_IVB)) {
1074                                 gma = cmd_val(s, 2) & GENMASK(31, 3);
1075                                 if (gmadr_bytes == 8)
1076                                         gma |= (cmd_gma_hi(s, 3)) << 32;
1077                                 /* Store Data Index */
1078                                 if (cmd_val(s, 1) & (1 << 21))
1079                                         index_mode = true;
1080                                 ret |= cmd_address_audit(s, gma, sizeof(u64),
1081                                                 index_mode);
1082                         }
1083                 }
1084         }
1085
1086         if (ret)
1087                 return ret;
1088
1089         if (cmd_val(s, 1) & PIPE_CONTROL_NOTIFY)
1090                 set_bit(cmd_interrupt_events[s->ring_id].pipe_control_notify,
1091                                 s->workload->pending_events);
1092         return 0;
1093 }
1094
1095 static int cmd_handler_mi_user_interrupt(struct parser_exec_state *s)
1096 {
1097         set_bit(cmd_interrupt_events[s->ring_id].mi_user_interrupt,
1098                         s->workload->pending_events);
1099         patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1100         return 0;
1101 }
1102
1103 static int cmd_advance_default(struct parser_exec_state *s)
1104 {
1105         return ip_gma_advance(s, cmd_length(s));
1106 }
1107
1108 static int cmd_handler_mi_batch_buffer_end(struct parser_exec_state *s)
1109 {
1110         int ret;
1111
1112         if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1113                 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1114                 ret = ip_gma_set(s, s->ret_ip_gma_bb);
1115                 s->buf_addr_type = s->saved_buf_addr_type;
1116         } else {
1117                 s->buf_type = RING_BUFFER_INSTRUCTION;
1118                 s->buf_addr_type = GTT_BUFFER;
1119                 if (s->ret_ip_gma_ring >= s->ring_start + s->ring_size)
1120                         s->ret_ip_gma_ring -= s->ring_size;
1121                 ret = ip_gma_set(s, s->ret_ip_gma_ring);
1122         }
1123         return ret;
1124 }
1125
1126 struct mi_display_flip_command_info {
1127         int pipe;
1128         int plane;
1129         int event;
1130         i915_reg_t stride_reg;
1131         i915_reg_t ctrl_reg;
1132         i915_reg_t surf_reg;
1133         u64 stride_val;
1134         u64 tile_val;
1135         u64 surf_val;
1136         bool async_flip;
1137 };
1138
1139 struct plane_code_mapping {
1140         int pipe;
1141         int plane;
1142         int event;
1143 };
1144
1145 static int gen8_decode_mi_display_flip(struct parser_exec_state *s,
1146                 struct mi_display_flip_command_info *info)
1147 {
1148         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1149         struct plane_code_mapping gen8_plane_code[] = {
1150                 [0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE},
1151                 [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE},
1152                 [2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE},
1153                 [3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE},
1154                 [4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE},
1155                 [5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE},
1156         };
1157         u32 dword0, dword1, dword2;
1158         u32 v;
1159
1160         dword0 = cmd_val(s, 0);
1161         dword1 = cmd_val(s, 1);
1162         dword2 = cmd_val(s, 2);
1163
1164         v = (dword0 & GENMASK(21, 19)) >> 19;
1165         if (WARN_ON(v >= ARRAY_SIZE(gen8_plane_code)))
1166                 return -EBADRQC;
1167
1168         info->pipe = gen8_plane_code[v].pipe;
1169         info->plane = gen8_plane_code[v].plane;
1170         info->event = gen8_plane_code[v].event;
1171         info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1172         info->tile_val = (dword1 & 0x1);
1173         info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1174         info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1175
1176         if (info->plane == PLANE_A) {
1177                 info->ctrl_reg = DSPCNTR(info->pipe);
1178                 info->stride_reg = DSPSTRIDE(info->pipe);
1179                 info->surf_reg = DSPSURF(info->pipe);
1180         } else if (info->plane == PLANE_B) {
1181                 info->ctrl_reg = SPRCTL(info->pipe);
1182                 info->stride_reg = SPRSTRIDE(info->pipe);
1183                 info->surf_reg = SPRSURF(info->pipe);
1184         } else {
1185                 WARN_ON(1);
1186                 return -EBADRQC;
1187         }
1188         return 0;
1189 }
1190
1191 static int skl_decode_mi_display_flip(struct parser_exec_state *s,
1192                 struct mi_display_flip_command_info *info)
1193 {
1194         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1195         struct intel_vgpu *vgpu = s->vgpu;
1196         u32 dword0 = cmd_val(s, 0);
1197         u32 dword1 = cmd_val(s, 1);
1198         u32 dword2 = cmd_val(s, 2);
1199         u32 plane = (dword0 & GENMASK(12, 8)) >> 8;
1200
1201         info->plane = PRIMARY_PLANE;
1202
1203         switch (plane) {
1204         case MI_DISPLAY_FLIP_SKL_PLANE_1_A:
1205                 info->pipe = PIPE_A;
1206                 info->event = PRIMARY_A_FLIP_DONE;
1207                 break;
1208         case MI_DISPLAY_FLIP_SKL_PLANE_1_B:
1209                 info->pipe = PIPE_B;
1210                 info->event = PRIMARY_B_FLIP_DONE;
1211                 break;
1212         case MI_DISPLAY_FLIP_SKL_PLANE_1_C:
1213                 info->pipe = PIPE_C;
1214                 info->event = PRIMARY_C_FLIP_DONE;
1215                 break;
1216
1217         case MI_DISPLAY_FLIP_SKL_PLANE_2_A:
1218                 info->pipe = PIPE_A;
1219                 info->event = SPRITE_A_FLIP_DONE;
1220                 info->plane = SPRITE_PLANE;
1221                 break;
1222         case MI_DISPLAY_FLIP_SKL_PLANE_2_B:
1223                 info->pipe = PIPE_B;
1224                 info->event = SPRITE_B_FLIP_DONE;
1225                 info->plane = SPRITE_PLANE;
1226                 break;
1227         case MI_DISPLAY_FLIP_SKL_PLANE_2_C:
1228                 info->pipe = PIPE_C;
1229                 info->event = SPRITE_C_FLIP_DONE;
1230                 info->plane = SPRITE_PLANE;
1231                 break;
1232
1233         default:
1234                 gvt_vgpu_err("unknown plane code %d\n", plane);
1235                 return -EBADRQC;
1236         }
1237
1238         info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1239         info->tile_val = (dword1 & GENMASK(2, 0));
1240         info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1241         info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1242
1243         info->ctrl_reg = DSPCNTR(info->pipe);
1244         info->stride_reg = DSPSTRIDE(info->pipe);
1245         info->surf_reg = DSPSURF(info->pipe);
1246
1247         return 0;
1248 }
1249
1250 static int gen8_check_mi_display_flip(struct parser_exec_state *s,
1251                 struct mi_display_flip_command_info *info)
1252 {
1253         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1254         u32 stride, tile;
1255
1256         if (!info->async_flip)
1257                 return 0;
1258
1259         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1260                 stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);
1261                 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &
1262                                 GENMASK(12, 10)) >> 10;
1263         } else {
1264                 stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) &
1265                                 GENMASK(15, 6)) >> 6;
1266                 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;
1267         }
1268
1269         if (stride != info->stride_val)
1270                 gvt_dbg_cmd("cannot change stride during async flip\n");
1271
1272         if (tile != info->tile_val)
1273                 gvt_dbg_cmd("cannot change tile during async flip\n");
1274
1275         return 0;
1276 }
1277
1278 static int gen8_update_plane_mmio_from_mi_display_flip(
1279                 struct parser_exec_state *s,
1280                 struct mi_display_flip_command_info *info)
1281 {
1282         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1283         struct intel_vgpu *vgpu = s->vgpu;
1284
1285         set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),
1286                       info->surf_val << 12);
1287         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1288                 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),
1289                               info->stride_val);
1290                 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),
1291                               info->tile_val << 10);
1292         } else {
1293                 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6),
1294                               info->stride_val << 6);
1295                 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),
1296                               info->tile_val << 10);
1297         }
1298
1299         vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(info->pipe))++;
1300         intel_vgpu_trigger_virtual_event(vgpu, info->event);
1301         return 0;
1302 }
1303
1304 static int decode_mi_display_flip(struct parser_exec_state *s,
1305                 struct mi_display_flip_command_info *info)
1306 {
1307         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1308
1309         if (IS_BROADWELL(dev_priv))
1310                 return gen8_decode_mi_display_flip(s, info);
1311         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
1312                 return skl_decode_mi_display_flip(s, info);
1313
1314         return -ENODEV;
1315 }
1316
1317 static int check_mi_display_flip(struct parser_exec_state *s,
1318                 struct mi_display_flip_command_info *info)
1319 {
1320         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1321
1322         if (IS_BROADWELL(dev_priv)
1323                 || IS_SKYLAKE(dev_priv)
1324                 || IS_KABYLAKE(dev_priv))
1325                 return gen8_check_mi_display_flip(s, info);
1326         return -ENODEV;
1327 }
1328
1329 static int update_plane_mmio_from_mi_display_flip(
1330                 struct parser_exec_state *s,
1331                 struct mi_display_flip_command_info *info)
1332 {
1333         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1334
1335         if (IS_BROADWELL(dev_priv)
1336                 || IS_SKYLAKE(dev_priv)
1337                 || IS_KABYLAKE(dev_priv))
1338                 return gen8_update_plane_mmio_from_mi_display_flip(s, info);
1339         return -ENODEV;
1340 }
1341
1342 static int cmd_handler_mi_display_flip(struct parser_exec_state *s)
1343 {
1344         struct mi_display_flip_command_info info;
1345         struct intel_vgpu *vgpu = s->vgpu;
1346         int ret;
1347         int i;
1348         int len = cmd_length(s);
1349
1350         ret = decode_mi_display_flip(s, &info);
1351         if (ret) {
1352                 gvt_vgpu_err("fail to decode MI display flip command\n");
1353                 return ret;
1354         }
1355
1356         ret = check_mi_display_flip(s, &info);
1357         if (ret) {
1358                 gvt_vgpu_err("invalid MI display flip command\n");
1359                 return ret;
1360         }
1361
1362         ret = update_plane_mmio_from_mi_display_flip(s, &info);
1363         if (ret) {
1364                 gvt_vgpu_err("fail to update plane mmio\n");
1365                 return ret;
1366         }
1367
1368         for (i = 0; i < len; i++)
1369                 patch_value(s, cmd_ptr(s, i), MI_NOOP);
1370         return 0;
1371 }
1372
1373 static bool is_wait_for_flip_pending(u32 cmd)
1374 {
1375         return cmd & (MI_WAIT_FOR_PLANE_A_FLIP_PENDING |
1376                         MI_WAIT_FOR_PLANE_B_FLIP_PENDING |
1377                         MI_WAIT_FOR_PLANE_C_FLIP_PENDING |
1378                         MI_WAIT_FOR_SPRITE_A_FLIP_PENDING |
1379                         MI_WAIT_FOR_SPRITE_B_FLIP_PENDING |
1380                         MI_WAIT_FOR_SPRITE_C_FLIP_PENDING);
1381 }
1382
1383 static int cmd_handler_mi_wait_for_event(struct parser_exec_state *s)
1384 {
1385         u32 cmd = cmd_val(s, 0);
1386
1387         if (!is_wait_for_flip_pending(cmd))
1388                 return 0;
1389
1390         patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1391         return 0;
1392 }
1393
1394 static unsigned long get_gma_bb_from_cmd(struct parser_exec_state *s, int index)
1395 {
1396         unsigned long addr;
1397         unsigned long gma_high, gma_low;
1398         struct intel_vgpu *vgpu = s->vgpu;
1399         int gmadr_bytes = vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1400
1401         if (WARN_ON(gmadr_bytes != 4 && gmadr_bytes != 8)) {
1402                 gvt_vgpu_err("invalid gma bytes %d\n", gmadr_bytes);
1403                 return INTEL_GVT_INVALID_ADDR;
1404         }
1405
1406         gma_low = cmd_val(s, index) & BATCH_BUFFER_ADDR_MASK;
1407         if (gmadr_bytes == 4) {
1408                 addr = gma_low;
1409         } else {
1410                 gma_high = cmd_val(s, index + 1) & BATCH_BUFFER_ADDR_HIGH_MASK;
1411                 addr = (((unsigned long)gma_high) << 32) | gma_low;
1412         }
1413         return addr;
1414 }
1415
1416 static inline int cmd_address_audit(struct parser_exec_state *s,
1417                 unsigned long guest_gma, int op_size, bool index_mode)
1418 {
1419         struct intel_vgpu *vgpu = s->vgpu;
1420         u32 max_surface_size = vgpu->gvt->device_info.max_surface_size;
1421         int i;
1422         int ret;
1423
1424         if (op_size > max_surface_size) {
1425                 gvt_vgpu_err("command address audit fail name %s\n",
1426                         s->info->name);
1427                 return -EFAULT;
1428         }
1429
1430         if (index_mode) {
1431                 if (guest_gma >= I915_GTT_PAGE_SIZE / sizeof(u64)) {
1432                         ret = -EFAULT;
1433                         goto err;
1434                 }
1435         } else if (!intel_gvt_ggtt_validate_range(vgpu, guest_gma, op_size)) {
1436                 ret = -EFAULT;
1437                 goto err;
1438         }
1439
1440         return 0;
1441
1442 err:
1443         gvt_vgpu_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n",
1444                         s->info->name, guest_gma, op_size);
1445
1446         pr_err("cmd dump: ");
1447         for (i = 0; i < cmd_length(s); i++) {
1448                 if (!(i % 4))
1449                         pr_err("\n%08x ", cmd_val(s, i));
1450                 else
1451                         pr_err("%08x ", cmd_val(s, i));
1452         }
1453         pr_err("\nvgpu%d: aperture 0x%llx - 0x%llx, hidden 0x%llx - 0x%llx\n",
1454                         vgpu->id,
1455                         vgpu_aperture_gmadr_base(vgpu),
1456                         vgpu_aperture_gmadr_end(vgpu),
1457                         vgpu_hidden_gmadr_base(vgpu),
1458                         vgpu_hidden_gmadr_end(vgpu));
1459         return ret;
1460 }
1461
1462 static int cmd_handler_mi_store_data_imm(struct parser_exec_state *s)
1463 {
1464         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1465         int op_size = (cmd_length(s) - 3) * sizeof(u32);
1466         int core_id = (cmd_val(s, 2) & (1 << 0)) ? 1 : 0;
1467         unsigned long gma, gma_low, gma_high;
1468         int ret = 0;
1469
1470         /* check ppggt */
1471         if (!(cmd_val(s, 0) & (1 << 22)))
1472                 return 0;
1473
1474         gma = cmd_val(s, 2) & GENMASK(31, 2);
1475
1476         if (gmadr_bytes == 8) {
1477                 gma_low = cmd_val(s, 1) & GENMASK(31, 2);
1478                 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1479                 gma = (gma_high << 32) | gma_low;
1480                 core_id = (cmd_val(s, 1) & (1 << 0)) ? 1 : 0;
1481         }
1482         ret = cmd_address_audit(s, gma + op_size * core_id, op_size, false);
1483         return ret;
1484 }
1485
1486 static inline int unexpected_cmd(struct parser_exec_state *s)
1487 {
1488         struct intel_vgpu *vgpu = s->vgpu;
1489
1490         gvt_vgpu_err("Unexpected %s in command buffer!\n", s->info->name);
1491
1492         return -EBADRQC;
1493 }
1494
1495 static int cmd_handler_mi_semaphore_wait(struct parser_exec_state *s)
1496 {
1497         return unexpected_cmd(s);
1498 }
1499
1500 static int cmd_handler_mi_report_perf_count(struct parser_exec_state *s)
1501 {
1502         return unexpected_cmd(s);
1503 }
1504
1505 static int cmd_handler_mi_op_2e(struct parser_exec_state *s)
1506 {
1507         return unexpected_cmd(s);
1508 }
1509
1510 static int cmd_handler_mi_op_2f(struct parser_exec_state *s)
1511 {
1512         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1513         int op_size = (1 << ((cmd_val(s, 0) & GENMASK(20, 19)) >> 19)) *
1514                         sizeof(u32);
1515         unsigned long gma, gma_high;
1516         int ret = 0;
1517
1518         if (!(cmd_val(s, 0) & (1 << 22)))
1519                 return ret;
1520
1521         gma = cmd_val(s, 1) & GENMASK(31, 2);
1522         if (gmadr_bytes == 8) {
1523                 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1524                 gma = (gma_high << 32) | gma;
1525         }
1526         ret = cmd_address_audit(s, gma, op_size, false);
1527         return ret;
1528 }
1529
1530 static int cmd_handler_mi_store_data_index(struct parser_exec_state *s)
1531 {
1532         return unexpected_cmd(s);
1533 }
1534
1535 static int cmd_handler_mi_clflush(struct parser_exec_state *s)
1536 {
1537         return unexpected_cmd(s);
1538 }
1539
1540 static int cmd_handler_mi_conditional_batch_buffer_end(
1541                 struct parser_exec_state *s)
1542 {
1543         return unexpected_cmd(s);
1544 }
1545
1546 static int cmd_handler_mi_update_gtt(struct parser_exec_state *s)
1547 {
1548         return unexpected_cmd(s);
1549 }
1550
1551 static int cmd_handler_mi_flush_dw(struct parser_exec_state *s)
1552 {
1553         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1554         unsigned long gma;
1555         bool index_mode = false;
1556         int ret = 0;
1557
1558         /* Check post-sync and ppgtt bit */
1559         if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) {
1560                 gma = cmd_val(s, 1) & GENMASK(31, 3);
1561                 if (gmadr_bytes == 8)
1562                         gma |= (cmd_val(s, 2) & GENMASK(15, 0)) << 32;
1563                 /* Store Data Index */
1564                 if (cmd_val(s, 0) & (1 << 21))
1565                         index_mode = true;
1566                 ret = cmd_address_audit(s, gma, sizeof(u64), index_mode);
1567         }
1568         /* Check notify bit */
1569         if ((cmd_val(s, 0) & (1 << 8)))
1570                 set_bit(cmd_interrupt_events[s->ring_id].mi_flush_dw,
1571                                 s->workload->pending_events);
1572         return ret;
1573 }
1574
1575 static void addr_type_update_snb(struct parser_exec_state *s)
1576 {
1577         if ((s->buf_type == RING_BUFFER_INSTRUCTION) &&
1578                         (BATCH_BUFFER_ADR_SPACE_BIT(cmd_val(s, 0)) == 1)) {
1579                 s->buf_addr_type = PPGTT_BUFFER;
1580         }
1581 }
1582
1583
1584 static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm,
1585                 unsigned long gma, unsigned long end_gma, void *va)
1586 {
1587         unsigned long copy_len, offset;
1588         unsigned long len = 0;
1589         unsigned long gpa;
1590
1591         while (gma != end_gma) {
1592                 gpa = intel_vgpu_gma_to_gpa(mm, gma);
1593                 if (gpa == INTEL_GVT_INVALID_ADDR) {
1594                         gvt_vgpu_err("invalid gma address: %lx\n", gma);
1595                         return -EFAULT;
1596                 }
1597
1598                 offset = gma & (I915_GTT_PAGE_SIZE - 1);
1599
1600                 copy_len = (end_gma - gma) >= (I915_GTT_PAGE_SIZE - offset) ?
1601                         I915_GTT_PAGE_SIZE - offset : end_gma - gma;
1602
1603                 intel_gvt_hypervisor_read_gpa(vgpu, gpa, va + len, copy_len);
1604
1605                 len += copy_len;
1606                 gma += copy_len;
1607         }
1608         return len;
1609 }
1610
1611
1612 /*
1613  * Check whether a batch buffer needs to be scanned. Currently
1614  * the only criteria is based on privilege.
1615  */
1616 static int batch_buffer_needs_scan(struct parser_exec_state *s)
1617 {
1618         struct intel_gvt *gvt = s->vgpu->gvt;
1619
1620         if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)
1621                 || IS_KABYLAKE(gvt->dev_priv)) {
1622                 /* BDW decides privilege based on address space */
1623                 if (cmd_val(s, 0) & (1 << 8) &&
1624                         !(s->vgpu->scan_nonprivbb & (1 << s->ring_id)))
1625                         return 0;
1626         }
1627         return 1;
1628 }
1629
1630 static int find_bb_size(struct parser_exec_state *s, unsigned long *bb_size)
1631 {
1632         unsigned long gma = 0;
1633         struct cmd_info *info;
1634         uint32_t cmd_len = 0;
1635         bool bb_end = false;
1636         struct intel_vgpu *vgpu = s->vgpu;
1637         u32 cmd;
1638         struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1639                 s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1640
1641         *bb_size = 0;
1642
1643         /* get the start gm address of the batch buffer */
1644         gma = get_gma_bb_from_cmd(s, 1);
1645         if (gma == INTEL_GVT_INVALID_ADDR)
1646                 return -EFAULT;
1647
1648         cmd = cmd_val(s, 0);
1649         info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
1650         if (info == NULL) {
1651                 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",
1652                                 cmd, get_opcode(cmd, s->ring_id),
1653                                 (s->buf_addr_type == PPGTT_BUFFER) ?
1654                                 "ppgtt" : "ggtt", s->ring_id, s->workload);
1655                 return -EBADRQC;
1656         }
1657         do {
1658                 if (copy_gma_to_hva(s->vgpu, mm,
1659                                 gma, gma + 4, &cmd) < 0)
1660                         return -EFAULT;
1661                 info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
1662                 if (info == NULL) {
1663                         gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",
1664                                 cmd, get_opcode(cmd, s->ring_id),
1665                                 (s->buf_addr_type == PPGTT_BUFFER) ?
1666                                 "ppgtt" : "ggtt", s->ring_id, s->workload);
1667                         return -EBADRQC;
1668                 }
1669
1670                 if (info->opcode == OP_MI_BATCH_BUFFER_END) {
1671                         bb_end = true;
1672                 } else if (info->opcode == OP_MI_BATCH_BUFFER_START) {
1673                         if (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0)
1674                                 /* chained batch buffer */
1675                                 bb_end = true;
1676                 }
1677                 cmd_len = get_cmd_length(info, cmd) << 2;
1678                 *bb_size += cmd_len;
1679                 gma += cmd_len;
1680         } while (!bb_end);
1681
1682         return 0;
1683 }
1684
1685 static int perform_bb_shadow(struct parser_exec_state *s)
1686 {
1687         struct intel_vgpu *vgpu = s->vgpu;
1688         struct intel_vgpu_shadow_bb *bb;
1689         unsigned long gma = 0;
1690         unsigned long bb_size;
1691         int ret = 0;
1692         struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1693                 s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1694         unsigned long gma_start_offset = 0;
1695
1696         /* get the start gm address of the batch buffer */
1697         gma = get_gma_bb_from_cmd(s, 1);
1698         if (gma == INTEL_GVT_INVALID_ADDR)
1699                 return -EFAULT;
1700
1701         ret = find_bb_size(s, &bb_size);
1702         if (ret)
1703                 return ret;
1704
1705         bb = kzalloc(sizeof(*bb), GFP_KERNEL);
1706         if (!bb)
1707                 return -ENOMEM;
1708
1709         bb->ppgtt = (s->buf_addr_type == GTT_BUFFER) ? false : true;
1710
1711         /* the gma_start_offset stores the batch buffer's start gma's
1712          * offset relative to page boundary. so for non-privileged batch
1713          * buffer, the shadowed gem object holds exactly the same page
1714          * layout as original gem object. This is for the convience of
1715          * replacing the whole non-privilged batch buffer page to this
1716          * shadowed one in PPGTT at the same gma address. (this replacing
1717          * action is not implemented yet now, but may be necessary in
1718          * future).
1719          * for prileged batch buffer, we just change start gma address to
1720          * that of shadowed page.
1721          */
1722         if (bb->ppgtt)
1723                 gma_start_offset = gma & ~I915_GTT_PAGE_MASK;
1724
1725         bb->obj = i915_gem_object_create(s->vgpu->gvt->dev_priv,
1726                          roundup(bb_size + gma_start_offset, PAGE_SIZE));
1727         if (IS_ERR(bb->obj)) {
1728                 ret = PTR_ERR(bb->obj);
1729                 goto err_free_bb;
1730         }
1731
1732         ret = i915_gem_obj_prepare_shmem_write(bb->obj, &bb->clflush);
1733         if (ret)
1734                 goto err_free_obj;
1735
1736         bb->va = i915_gem_object_pin_map(bb->obj, I915_MAP_WB);
1737         if (IS_ERR(bb->va)) {
1738                 ret = PTR_ERR(bb->va);
1739                 goto err_finish_shmem_access;
1740         }
1741
1742         if (bb->clflush & CLFLUSH_BEFORE) {
1743                 drm_clflush_virt_range(bb->va, bb->obj->base.size);
1744                 bb->clflush &= ~CLFLUSH_BEFORE;
1745         }
1746
1747         ret = copy_gma_to_hva(s->vgpu, mm,
1748                               gma, gma + bb_size,
1749                               bb->va + gma_start_offset);
1750         if (ret < 0) {
1751                 gvt_vgpu_err("fail to copy guest ring buffer\n");
1752                 ret = -EFAULT;
1753                 goto err_unmap;
1754         }
1755
1756         INIT_LIST_HEAD(&bb->list);
1757         list_add(&bb->list, &s->workload->shadow_bb);
1758
1759         bb->accessing = true;
1760         bb->bb_start_cmd_va = s->ip_va;
1761
1762         if ((s->buf_type == BATCH_BUFFER_INSTRUCTION) && (!s->is_ctx_wa))
1763                 bb->bb_offset = s->ip_va - s->rb_va;
1764         else
1765                 bb->bb_offset = 0;
1766
1767         /*
1768          * ip_va saves the virtual address of the shadow batch buffer, while
1769          * ip_gma saves the graphics address of the original batch buffer.
1770          * As the shadow batch buffer is just a copy from the originial one,
1771          * it should be right to use shadow batch buffer'va and original batch
1772          * buffer's gma in pair. After all, we don't want to pin the shadow
1773          * buffer here (too early).
1774          */
1775         s->ip_va = bb->va + gma_start_offset;
1776         s->ip_gma = gma;
1777         return 0;
1778 err_unmap:
1779         i915_gem_object_unpin_map(bb->obj);
1780 err_finish_shmem_access:
1781         i915_gem_obj_finish_shmem_access(bb->obj);
1782 err_free_obj:
1783         i915_gem_object_put(bb->obj);
1784 err_free_bb:
1785         kfree(bb);
1786         return ret;
1787 }
1788
1789 static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s)
1790 {
1791         bool second_level;
1792         int ret = 0;
1793         struct intel_vgpu *vgpu = s->vgpu;
1794
1795         if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1796                 gvt_vgpu_err("Found MI_BATCH_BUFFER_START in 2nd level BB\n");
1797                 return -EFAULT;
1798         }
1799
1800         second_level = BATCH_BUFFER_2ND_LEVEL_BIT(cmd_val(s, 0)) == 1;
1801         if (second_level && (s->buf_type != BATCH_BUFFER_INSTRUCTION)) {
1802                 gvt_vgpu_err("Jumping to 2nd level BB from RB is not allowed\n");
1803                 return -EFAULT;
1804         }
1805
1806         s->saved_buf_addr_type = s->buf_addr_type;
1807         addr_type_update_snb(s);
1808         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
1809                 s->ret_ip_gma_ring = s->ip_gma + cmd_length(s) * sizeof(u32);
1810                 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1811         } else if (second_level) {
1812                 s->buf_type = BATCH_BUFFER_2ND_LEVEL;
1813                 s->ret_ip_gma_bb = s->ip_gma + cmd_length(s) * sizeof(u32);
1814                 s->ret_bb_va = s->ip_va + cmd_length(s) * sizeof(u32);
1815         }
1816
1817         if (batch_buffer_needs_scan(s)) {
1818                 ret = perform_bb_shadow(s);
1819                 if (ret < 0)
1820                         gvt_vgpu_err("invalid shadow batch buffer\n");
1821         } else {
1822                 /* emulate a batch buffer end to do return right */
1823                 ret = cmd_handler_mi_batch_buffer_end(s);
1824                 if (ret < 0)
1825                         return ret;
1826         }
1827         return ret;
1828 }
1829
1830 static struct cmd_info cmd_info[] = {
1831         {"MI_NOOP", OP_MI_NOOP, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
1832
1833         {"MI_SET_PREDICATE", OP_MI_SET_PREDICATE, F_LEN_CONST, R_ALL, D_ALL,
1834                 0, 1, NULL},
1835
1836         {"MI_USER_INTERRUPT", OP_MI_USER_INTERRUPT, F_LEN_CONST, R_ALL, D_ALL,
1837                 0, 1, cmd_handler_mi_user_interrupt},
1838
1839         {"MI_WAIT_FOR_EVENT", OP_MI_WAIT_FOR_EVENT, F_LEN_CONST, R_RCS | R_BCS,
1840                 D_ALL, 0, 1, cmd_handler_mi_wait_for_event},
1841
1842         {"MI_FLUSH", OP_MI_FLUSH, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
1843
1844         {"MI_ARB_CHECK", OP_MI_ARB_CHECK, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1845                 NULL},
1846
1847         {"MI_RS_CONTROL", OP_MI_RS_CONTROL, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1848                 NULL},
1849
1850         {"MI_REPORT_HEAD", OP_MI_REPORT_HEAD, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1851                 NULL},
1852
1853         {"MI_ARB_ON_OFF", OP_MI_ARB_ON_OFF, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1854                 NULL},
1855
1856         {"MI_URB_ATOMIC_ALLOC", OP_MI_URB_ATOMIC_ALLOC, F_LEN_CONST, R_RCS,
1857                 D_ALL, 0, 1, NULL},
1858
1859         {"MI_BATCH_BUFFER_END", OP_MI_BATCH_BUFFER_END,
1860                 F_IP_ADVANCE_CUSTOM | F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1861                 cmd_handler_mi_batch_buffer_end},
1862
1863         {"MI_SUSPEND_FLUSH", OP_MI_SUSPEND_FLUSH, F_LEN_CONST, R_ALL, D_ALL,
1864                 0, 1, NULL},
1865
1866         {"MI_PREDICATE", OP_MI_PREDICATE, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1867                 NULL},
1868
1869         {"MI_TOPOLOGY_FILTER", OP_MI_TOPOLOGY_FILTER, F_LEN_CONST, R_ALL,
1870                 D_ALL, 0, 1, NULL},
1871
1872         {"MI_SET_APPID", OP_MI_SET_APPID, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1873                 NULL},
1874
1875         {"MI_RS_CONTEXT", OP_MI_RS_CONTEXT, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1876                 NULL},
1877
1878         {"MI_DISPLAY_FLIP", OP_MI_DISPLAY_FLIP, F_LEN_VAR | F_POST_HANDLE,
1879                 R_RCS | R_BCS, D_ALL, 0, 8, cmd_handler_mi_display_flip},
1880
1881         {"MI_SEMAPHORE_MBOX", OP_MI_SEMAPHORE_MBOX, F_LEN_VAR, R_ALL, D_ALL,
1882                 0, 8, NULL},
1883
1884         {"MI_MATH", OP_MI_MATH, F_LEN_VAR, R_ALL, D_ALL, 0, 8, NULL},
1885
1886         {"MI_URB_CLEAR", OP_MI_URB_CLEAR, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1887
1888         {"ME_SEMAPHORE_SIGNAL", OP_MI_SEMAPHORE_SIGNAL, F_LEN_VAR, R_ALL,
1889                 D_BDW_PLUS, 0, 8, NULL},
1890
1891         {"ME_SEMAPHORE_WAIT", OP_MI_SEMAPHORE_WAIT, F_LEN_VAR, R_ALL, D_BDW_PLUS,
1892                 ADDR_FIX_1(2), 8, cmd_handler_mi_semaphore_wait},
1893
1894         {"MI_STORE_DATA_IMM", OP_MI_STORE_DATA_IMM, F_LEN_VAR, R_ALL, D_BDW_PLUS,
1895                 ADDR_FIX_1(1), 10, cmd_handler_mi_store_data_imm},
1896
1897         {"MI_STORE_DATA_INDEX", OP_MI_STORE_DATA_INDEX, F_LEN_VAR, R_ALL, D_ALL,
1898                 0, 8, cmd_handler_mi_store_data_index},
1899
1900         {"MI_LOAD_REGISTER_IMM", OP_MI_LOAD_REGISTER_IMM, F_LEN_VAR, R_ALL,
1901                 D_ALL, 0, 8, cmd_handler_lri},
1902
1903         {"MI_UPDATE_GTT", OP_MI_UPDATE_GTT, F_LEN_VAR, R_ALL, D_BDW_PLUS, 0, 10,
1904                 cmd_handler_mi_update_gtt},
1905
1906         {"MI_STORE_REGISTER_MEM", OP_MI_STORE_REGISTER_MEM, F_LEN_VAR, R_ALL,
1907                 D_ALL, ADDR_FIX_1(2), 8, cmd_handler_srm},
1908
1909         {"MI_FLUSH_DW", OP_MI_FLUSH_DW, F_LEN_VAR, R_ALL, D_ALL, 0, 6,
1910                 cmd_handler_mi_flush_dw},
1911
1912         {"MI_CLFLUSH", OP_MI_CLFLUSH, F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(1),
1913                 10, cmd_handler_mi_clflush},
1914
1915         {"MI_REPORT_PERF_COUNT", OP_MI_REPORT_PERF_COUNT, F_LEN_VAR, R_ALL,
1916                 D_ALL, ADDR_FIX_1(1), 6, cmd_handler_mi_report_perf_count},
1917
1918         {"MI_LOAD_REGISTER_MEM", OP_MI_LOAD_REGISTER_MEM, F_LEN_VAR, R_ALL,
1919                 D_ALL, ADDR_FIX_1(2), 8, cmd_handler_lrm},
1920
1921         {"MI_LOAD_REGISTER_REG", OP_MI_LOAD_REGISTER_REG, F_LEN_VAR, R_ALL,
1922                 D_ALL, 0, 8, cmd_handler_lrr},
1923
1924         {"MI_RS_STORE_DATA_IMM", OP_MI_RS_STORE_DATA_IMM, F_LEN_VAR, R_RCS,
1925                 D_ALL, 0, 8, NULL},
1926
1927         {"MI_LOAD_URB_MEM", OP_MI_LOAD_URB_MEM, F_LEN_VAR, R_RCS, D_ALL,
1928                 ADDR_FIX_1(2), 8, NULL},
1929
1930         {"MI_STORE_URM_MEM", OP_MI_STORE_URM_MEM, F_LEN_VAR, R_RCS, D_ALL,
1931                 ADDR_FIX_1(2), 8, NULL},
1932
1933         {"MI_OP_2E", OP_MI_2E, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_2(1, 2),
1934                 8, cmd_handler_mi_op_2e},
1935
1936         {"MI_OP_2F", OP_MI_2F, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_1(1),
1937                 8, cmd_handler_mi_op_2f},
1938
1939         {"MI_BATCH_BUFFER_START", OP_MI_BATCH_BUFFER_START,
1940                 F_IP_ADVANCE_CUSTOM, R_ALL, D_ALL, 0, 8,
1941                 cmd_handler_mi_batch_buffer_start},
1942
1943         {"MI_CONDITIONAL_BATCH_BUFFER_END", OP_MI_CONDITIONAL_BATCH_BUFFER_END,
1944                 F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
1945                 cmd_handler_mi_conditional_batch_buffer_end},
1946
1947         {"MI_LOAD_SCAN_LINES_INCL", OP_MI_LOAD_SCAN_LINES_INCL, F_LEN_CONST,
1948                 R_RCS | R_BCS, D_ALL, 0, 2, NULL},
1949
1950         {"XY_SETUP_BLT", OP_XY_SETUP_BLT, F_LEN_VAR, R_BCS, D_ALL,
1951                 ADDR_FIX_2(4, 7), 8, NULL},
1952
1953         {"XY_SETUP_CLIP_BLT", OP_XY_SETUP_CLIP_BLT, F_LEN_VAR, R_BCS, D_ALL,
1954                 0, 8, NULL},
1955
1956         {"XY_SETUP_MONO_PATTERN_SL_BLT", OP_XY_SETUP_MONO_PATTERN_SL_BLT,
1957                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
1958
1959         {"XY_PIXEL_BLT", OP_XY_PIXEL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
1960
1961         {"XY_SCANLINES_BLT", OP_XY_SCANLINES_BLT, F_LEN_VAR, R_BCS, D_ALL,
1962                 0, 8, NULL},
1963
1964         {"XY_TEXT_BLT", OP_XY_TEXT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1965                 ADDR_FIX_1(3), 8, NULL},
1966
1967         {"XY_TEXT_IMMEDIATE_BLT", OP_XY_TEXT_IMMEDIATE_BLT, F_LEN_VAR, R_BCS,
1968                 D_ALL, 0, 8, NULL},
1969
1970         {"XY_COLOR_BLT", OP_XY_COLOR_BLT, F_LEN_VAR, R_BCS, D_ALL,
1971                 ADDR_FIX_1(4), 8, NULL},
1972
1973         {"XY_PAT_BLT", OP_XY_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1974                 ADDR_FIX_2(4, 5), 8, NULL},
1975
1976         {"XY_MONO_PAT_BLT", OP_XY_MONO_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1977                 ADDR_FIX_1(4), 8, NULL},
1978
1979         {"XY_SRC_COPY_BLT", OP_XY_SRC_COPY_BLT, F_LEN_VAR, R_BCS, D_ALL,
1980                 ADDR_FIX_2(4, 7), 8, NULL},
1981
1982         {"XY_MONO_SRC_COPY_BLT", OP_XY_MONO_SRC_COPY_BLT, F_LEN_VAR, R_BCS,
1983                 D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
1984
1985         {"XY_FULL_BLT", OP_XY_FULL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
1986
1987         {"XY_FULL_MONO_SRC_BLT", OP_XY_FULL_MONO_SRC_BLT, F_LEN_VAR, R_BCS,
1988                 D_ALL, ADDR_FIX_3(4, 5, 8), 8, NULL},
1989
1990         {"XY_FULL_MONO_PATTERN_BLT", OP_XY_FULL_MONO_PATTERN_BLT, F_LEN_VAR,
1991                 R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
1992
1993         {"XY_FULL_MONO_PATTERN_MONO_SRC_BLT",
1994                 OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT,
1995                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
1996
1997         {"XY_MONO_PAT_FIXED_BLT", OP_XY_MONO_PAT_FIXED_BLT, F_LEN_VAR, R_BCS,
1998                 D_ALL, ADDR_FIX_1(4), 8, NULL},
1999
2000         {"XY_MONO_SRC_COPY_IMMEDIATE_BLT", OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT,
2001                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2002
2003         {"XY_PAT_BLT_IMMEDIATE", OP_XY_PAT_BLT_IMMEDIATE, F_LEN_VAR, R_BCS,
2004                 D_ALL, ADDR_FIX_1(4), 8, NULL},
2005
2006         {"XY_SRC_COPY_CHROMA_BLT", OP_XY_SRC_COPY_CHROMA_BLT, F_LEN_VAR, R_BCS,
2007                 D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2008
2009         {"XY_FULL_IMMEDIATE_PATTERN_BLT", OP_XY_FULL_IMMEDIATE_PATTERN_BLT,
2010                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2011
2012         {"XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT",
2013                 OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT,
2014                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2015
2016         {"XY_PAT_CHROMA_BLT", OP_XY_PAT_CHROMA_BLT, F_LEN_VAR, R_BCS, D_ALL,
2017                 ADDR_FIX_2(4, 5), 8, NULL},
2018
2019         {"XY_PAT_CHROMA_BLT_IMMEDIATE", OP_XY_PAT_CHROMA_BLT_IMMEDIATE,
2020                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2021
2022         {"3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP",
2023                 OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP,
2024                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2025
2026         {"3DSTATE_VIEWPORT_STATE_POINTERS_CC",
2027                 OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
2028                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2029
2030         {"3DSTATE_BLEND_STATE_POINTERS",
2031                 OP_3DSTATE_BLEND_STATE_POINTERS,
2032                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2033
2034         {"3DSTATE_DEPTH_STENCIL_STATE_POINTERS",
2035                 OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
2036                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2037
2038         {"3DSTATE_BINDING_TABLE_POINTERS_VS",
2039                 OP_3DSTATE_BINDING_TABLE_POINTERS_VS,
2040                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2041
2042         {"3DSTATE_BINDING_TABLE_POINTERS_HS",
2043                 OP_3DSTATE_BINDING_TABLE_POINTERS_HS,
2044                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2045
2046         {"3DSTATE_BINDING_TABLE_POINTERS_DS",
2047                 OP_3DSTATE_BINDING_TABLE_POINTERS_DS,
2048                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2049
2050         {"3DSTATE_BINDING_TABLE_POINTERS_GS",
2051                 OP_3DSTATE_BINDING_TABLE_POINTERS_GS,
2052                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2053
2054         {"3DSTATE_BINDING_TABLE_POINTERS_PS",
2055                 OP_3DSTATE_BINDING_TABLE_POINTERS_PS,
2056                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2057
2058         {"3DSTATE_SAMPLER_STATE_POINTERS_VS",
2059                 OP_3DSTATE_SAMPLER_STATE_POINTERS_VS,
2060                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2061
2062         {"3DSTATE_SAMPLER_STATE_POINTERS_HS",
2063                 OP_3DSTATE_SAMPLER_STATE_POINTERS_HS,
2064                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2065
2066         {"3DSTATE_SAMPLER_STATE_POINTERS_DS",
2067                 OP_3DSTATE_SAMPLER_STATE_POINTERS_DS,
2068                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2069
2070         {"3DSTATE_SAMPLER_STATE_POINTERS_GS",
2071                 OP_3DSTATE_SAMPLER_STATE_POINTERS_GS,
2072                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2073
2074         {"3DSTATE_SAMPLER_STATE_POINTERS_PS",
2075                 OP_3DSTATE_SAMPLER_STATE_POINTERS_PS,
2076                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2077
2078         {"3DSTATE_URB_VS", OP_3DSTATE_URB_VS, F_LEN_VAR, R_RCS, D_ALL,
2079                 0, 8, NULL},
2080
2081         {"3DSTATE_URB_HS", OP_3DSTATE_URB_HS, F_LEN_VAR, R_RCS, D_ALL,
2082                 0, 8, NULL},
2083
2084         {"3DSTATE_URB_DS", OP_3DSTATE_URB_DS, F_LEN_VAR, R_RCS, D_ALL,
2085                 0, 8, NULL},
2086
2087         {"3DSTATE_URB_GS", OP_3DSTATE_URB_GS, F_LEN_VAR, R_RCS, D_ALL,
2088                 0, 8, NULL},
2089
2090         {"3DSTATE_GATHER_CONSTANT_VS", OP_3DSTATE_GATHER_CONSTANT_VS,
2091                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2092
2093         {"3DSTATE_GATHER_CONSTANT_GS", OP_3DSTATE_GATHER_CONSTANT_GS,
2094                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2095
2096         {"3DSTATE_GATHER_CONSTANT_HS", OP_3DSTATE_GATHER_CONSTANT_HS,
2097                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2098
2099         {"3DSTATE_GATHER_CONSTANT_DS", OP_3DSTATE_GATHER_CONSTANT_DS,
2100                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2101
2102         {"3DSTATE_GATHER_CONSTANT_PS", OP_3DSTATE_GATHER_CONSTANT_PS,
2103                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2104
2105         {"3DSTATE_DX9_CONSTANTF_VS", OP_3DSTATE_DX9_CONSTANTF_VS,
2106                 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2107
2108         {"3DSTATE_DX9_CONSTANTF_PS", OP_3DSTATE_DX9_CONSTANTF_PS,
2109                 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2110
2111         {"3DSTATE_DX9_CONSTANTI_VS", OP_3DSTATE_DX9_CONSTANTI_VS,
2112                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2113
2114         {"3DSTATE_DX9_CONSTANTI_PS", OP_3DSTATE_DX9_CONSTANTI_PS,
2115                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2116
2117         {"3DSTATE_DX9_CONSTANTB_VS", OP_3DSTATE_DX9_CONSTANTB_VS,
2118                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2119
2120         {"3DSTATE_DX9_CONSTANTB_PS", OP_3DSTATE_DX9_CONSTANTB_PS,
2121                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2122
2123         {"3DSTATE_DX9_LOCAL_VALID_VS", OP_3DSTATE_DX9_LOCAL_VALID_VS,
2124                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2125
2126         {"3DSTATE_DX9_LOCAL_VALID_PS", OP_3DSTATE_DX9_LOCAL_VALID_PS,
2127                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2128
2129         {"3DSTATE_DX9_GENERATE_ACTIVE_VS", OP_3DSTATE_DX9_GENERATE_ACTIVE_VS,
2130                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2131
2132         {"3DSTATE_DX9_GENERATE_ACTIVE_PS", OP_3DSTATE_DX9_GENERATE_ACTIVE_PS,
2133                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2134
2135         {"3DSTATE_BINDING_TABLE_EDIT_VS", OP_3DSTATE_BINDING_TABLE_EDIT_VS,
2136                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2137
2138         {"3DSTATE_BINDING_TABLE_EDIT_GS", OP_3DSTATE_BINDING_TABLE_EDIT_GS,
2139                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2140
2141         {"3DSTATE_BINDING_TABLE_EDIT_HS", OP_3DSTATE_BINDING_TABLE_EDIT_HS,
2142                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2143
2144         {"3DSTATE_BINDING_TABLE_EDIT_DS", OP_3DSTATE_BINDING_TABLE_EDIT_DS,
2145                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2146
2147         {"3DSTATE_BINDING_TABLE_EDIT_PS", OP_3DSTATE_BINDING_TABLE_EDIT_PS,
2148                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2149
2150         {"3DSTATE_VF_INSTANCING", OP_3DSTATE_VF_INSTANCING, F_LEN_VAR, R_RCS,
2151                 D_BDW_PLUS, 0, 8, NULL},
2152
2153         {"3DSTATE_VF_SGVS", OP_3DSTATE_VF_SGVS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2154                 NULL},
2155
2156         {"3DSTATE_VF_TOPOLOGY", OP_3DSTATE_VF_TOPOLOGY, F_LEN_VAR, R_RCS,
2157                 D_BDW_PLUS, 0, 8, NULL},
2158
2159         {"3DSTATE_WM_CHROMAKEY", OP_3DSTATE_WM_CHROMAKEY, F_LEN_VAR, R_RCS,
2160                 D_BDW_PLUS, 0, 8, NULL},
2161
2162         {"3DSTATE_PS_BLEND", OP_3DSTATE_PS_BLEND, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2163                 8, NULL},
2164
2165         {"3DSTATE_WM_DEPTH_STENCIL", OP_3DSTATE_WM_DEPTH_STENCIL, F_LEN_VAR,
2166                 R_RCS, D_BDW_PLUS, 0, 8, NULL},
2167
2168         {"3DSTATE_PS_EXTRA", OP_3DSTATE_PS_EXTRA, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2169                 8, NULL},
2170
2171         {"3DSTATE_RASTER", OP_3DSTATE_RASTER, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2172                 NULL},
2173
2174         {"3DSTATE_SBE_SWIZ", OP_3DSTATE_SBE_SWIZ, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2175                 NULL},
2176
2177         {"3DSTATE_WM_HZ_OP", OP_3DSTATE_WM_HZ_OP, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2178                 NULL},
2179
2180         {"3DSTATE_VERTEX_BUFFERS", OP_3DSTATE_VERTEX_BUFFERS, F_LEN_VAR, R_RCS,
2181                 D_BDW_PLUS, 0, 8, NULL},
2182
2183         {"3DSTATE_VERTEX_ELEMENTS", OP_3DSTATE_VERTEX_ELEMENTS, F_LEN_VAR,
2184                 R_RCS, D_ALL, 0, 8, NULL},
2185
2186         {"3DSTATE_INDEX_BUFFER", OP_3DSTATE_INDEX_BUFFER, F_LEN_VAR, R_RCS,
2187                 D_BDW_PLUS, ADDR_FIX_1(2), 8, NULL},
2188
2189         {"3DSTATE_VF_STATISTICS", OP_3DSTATE_VF_STATISTICS, F_LEN_CONST,
2190                 R_RCS, D_ALL, 0, 1, NULL},
2191
2192         {"3DSTATE_VF", OP_3DSTATE_VF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2193
2194         {"3DSTATE_CC_STATE_POINTERS", OP_3DSTATE_CC_STATE_POINTERS, F_LEN_VAR,
2195                 R_RCS, D_ALL, 0, 8, NULL},
2196
2197         {"3DSTATE_SCISSOR_STATE_POINTERS", OP_3DSTATE_SCISSOR_STATE_POINTERS,
2198                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2199
2200         {"3DSTATE_GS", OP_3DSTATE_GS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2201
2202         {"3DSTATE_CLIP", OP_3DSTATE_CLIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2203
2204         {"3DSTATE_WM", OP_3DSTATE_WM, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2205
2206         {"3DSTATE_CONSTANT_GS", OP_3DSTATE_CONSTANT_GS, F_LEN_VAR, R_RCS,
2207                 D_BDW_PLUS, 0, 8, NULL},
2208
2209         {"3DSTATE_CONSTANT_PS", OP_3DSTATE_CONSTANT_PS, F_LEN_VAR, R_RCS,
2210                 D_BDW_PLUS, 0, 8, NULL},
2211
2212         {"3DSTATE_SAMPLE_MASK", OP_3DSTATE_SAMPLE_MASK, F_LEN_VAR, R_RCS,
2213                 D_ALL, 0, 8, NULL},
2214
2215         {"3DSTATE_CONSTANT_HS", OP_3DSTATE_CONSTANT_HS, F_LEN_VAR, R_RCS,
2216                 D_BDW_PLUS, 0, 8, NULL},
2217
2218         {"3DSTATE_CONSTANT_DS", OP_3DSTATE_CONSTANT_DS, F_LEN_VAR, R_RCS,
2219                 D_BDW_PLUS, 0, 8, NULL},
2220
2221         {"3DSTATE_HS", OP_3DSTATE_HS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2222
2223         {"3DSTATE_TE", OP_3DSTATE_TE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2224
2225         {"3DSTATE_DS", OP_3DSTATE_DS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2226
2227         {"3DSTATE_STREAMOUT", OP_3DSTATE_STREAMOUT, F_LEN_VAR, R_RCS,
2228                 D_ALL, 0, 8, NULL},
2229
2230         {"3DSTATE_SBE", OP_3DSTATE_SBE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2231
2232         {"3DSTATE_PS", OP_3DSTATE_PS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2233
2234         {"3DSTATE_DRAWING_RECTANGLE", OP_3DSTATE_DRAWING_RECTANGLE, F_LEN_VAR,
2235                 R_RCS, D_ALL, 0, 8, NULL},
2236
2237         {"3DSTATE_SAMPLER_PALETTE_LOAD0", OP_3DSTATE_SAMPLER_PALETTE_LOAD0,
2238                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2239
2240         {"3DSTATE_CHROMA_KEY", OP_3DSTATE_CHROMA_KEY, F_LEN_VAR, R_RCS, D_ALL,
2241                 0, 8, NULL},
2242
2243         {"3DSTATE_DEPTH_BUFFER", OP_3DSTATE_DEPTH_BUFFER, F_LEN_VAR, R_RCS,
2244                 D_ALL, ADDR_FIX_1(2), 8, NULL},
2245
2246         {"3DSTATE_POLY_STIPPLE_OFFSET", OP_3DSTATE_POLY_STIPPLE_OFFSET,
2247                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2248
2249         {"3DSTATE_POLY_STIPPLE_PATTERN", OP_3DSTATE_POLY_STIPPLE_PATTERN,
2250                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2251
2252         {"3DSTATE_LINE_STIPPLE", OP_3DSTATE_LINE_STIPPLE, F_LEN_VAR, R_RCS,
2253                 D_ALL, 0, 8, NULL},
2254
2255         {"3DSTATE_AA_LINE_PARAMS", OP_3DSTATE_AA_LINE_PARAMS, F_LEN_VAR, R_RCS,
2256                 D_ALL, 0, 8, NULL},
2257
2258         {"3DSTATE_GS_SVB_INDEX", OP_3DSTATE_GS_SVB_INDEX, F_LEN_VAR, R_RCS,
2259                 D_ALL, 0, 8, NULL},
2260
2261         {"3DSTATE_SAMPLER_PALETTE_LOAD1", OP_3DSTATE_SAMPLER_PALETTE_LOAD1,
2262                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2263
2264         {"3DSTATE_MULTISAMPLE", OP_3DSTATE_MULTISAMPLE_BDW, F_LEN_VAR, R_RCS,
2265                 D_BDW_PLUS, 0, 8, NULL},
2266
2267         {"3DSTATE_STENCIL_BUFFER", OP_3DSTATE_STENCIL_BUFFER, F_LEN_VAR, R_RCS,
2268                 D_ALL, ADDR_FIX_1(2), 8, NULL},
2269
2270         {"3DSTATE_HIER_DEPTH_BUFFER", OP_3DSTATE_HIER_DEPTH_BUFFER, F_LEN_VAR,
2271                 R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL},
2272
2273         {"3DSTATE_CLEAR_PARAMS", OP_3DSTATE_CLEAR_PARAMS, F_LEN_VAR,
2274                 R_RCS, D_ALL, 0, 8, NULL},
2275
2276         {"3DSTATE_PUSH_CONSTANT_ALLOC_VS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
2277                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2278
2279         {"3DSTATE_PUSH_CONSTANT_ALLOC_HS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS,
2280                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2281
2282         {"3DSTATE_PUSH_CONSTANT_ALLOC_DS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS,
2283                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2284
2285         {"3DSTATE_PUSH_CONSTANT_ALLOC_GS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS,
2286                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2287
2288         {"3DSTATE_PUSH_CONSTANT_ALLOC_PS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS,
2289                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2290
2291         {"3DSTATE_MONOFILTER_SIZE", OP_3DSTATE_MONOFILTER_SIZE, F_LEN_VAR,
2292                 R_RCS, D_ALL, 0, 8, NULL},
2293
2294         {"3DSTATE_SO_DECL_LIST", OP_3DSTATE_SO_DECL_LIST, F_LEN_VAR, R_RCS,
2295                 D_ALL, 0, 9, NULL},
2296
2297         {"3DSTATE_SO_BUFFER", OP_3DSTATE_SO_BUFFER, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2298                 ADDR_FIX_2(2, 4), 8, NULL},
2299
2300         {"3DSTATE_BINDING_TABLE_POOL_ALLOC",
2301                 OP_3DSTATE_BINDING_TABLE_POOL_ALLOC,
2302                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2303
2304         {"3DSTATE_GATHER_POOL_ALLOC", OP_3DSTATE_GATHER_POOL_ALLOC,
2305                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2306
2307         {"3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC",
2308                 OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC,
2309                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2310
2311         {"3DSTATE_SAMPLE_PATTERN", OP_3DSTATE_SAMPLE_PATTERN, F_LEN_VAR, R_RCS,
2312                 D_BDW_PLUS, 0, 8, NULL},
2313
2314         {"PIPE_CONTROL", OP_PIPE_CONTROL, F_LEN_VAR, R_RCS, D_ALL,
2315                 ADDR_FIX_1(2), 8, cmd_handler_pipe_control},
2316
2317         {"3DPRIMITIVE", OP_3DPRIMITIVE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2318
2319         {"PIPELINE_SELECT", OP_PIPELINE_SELECT, F_LEN_CONST, R_RCS, D_ALL, 0,
2320                 1, NULL},
2321
2322         {"STATE_PREFETCH", OP_STATE_PREFETCH, F_LEN_VAR, R_RCS, D_ALL,
2323                 ADDR_FIX_1(1), 8, NULL},
2324
2325         {"STATE_SIP", OP_STATE_SIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2326
2327         {"STATE_BASE_ADDRESS", OP_STATE_BASE_ADDRESS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2328                 ADDR_FIX_5(1, 3, 4, 5, 6), 8, NULL},
2329
2330         {"OP_3D_MEDIA_0_1_4", OP_3D_MEDIA_0_1_4, F_LEN_VAR, R_RCS, D_ALL,
2331                 ADDR_FIX_1(1), 8, NULL},
2332
2333         {"3DSTATE_VS", OP_3DSTATE_VS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2334
2335         {"3DSTATE_SF", OP_3DSTATE_SF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2336
2337         {"3DSTATE_CONSTANT_VS", OP_3DSTATE_CONSTANT_VS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2338                 0, 8, NULL},
2339
2340         {"3DSTATE_COMPONENT_PACKING", OP_3DSTATE_COMPONENT_PACKING, F_LEN_VAR, R_RCS,
2341                 D_SKL_PLUS, 0, 8, NULL},
2342
2343         {"MEDIA_INTERFACE_DESCRIPTOR_LOAD", OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD,
2344                 F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2345
2346         {"MEDIA_GATEWAY_STATE", OP_MEDIA_GATEWAY_STATE, F_LEN_VAR, R_RCS, D_ALL,
2347                 0, 16, NULL},
2348
2349         {"MEDIA_STATE_FLUSH", OP_MEDIA_STATE_FLUSH, F_LEN_VAR, R_RCS, D_ALL,
2350                 0, 16, NULL},
2351
2352         {"MEDIA_OBJECT", OP_MEDIA_OBJECT, F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2353
2354         {"MEDIA_CURBE_LOAD", OP_MEDIA_CURBE_LOAD, F_LEN_VAR, R_RCS, D_ALL,
2355                 0, 16, NULL},
2356
2357         {"MEDIA_OBJECT_PRT", OP_MEDIA_OBJECT_PRT, F_LEN_VAR, R_RCS, D_ALL,
2358                 0, 16, NULL},
2359
2360         {"MEDIA_OBJECT_WALKER", OP_MEDIA_OBJECT_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2361                 0, 16, NULL},
2362
2363         {"GPGPU_WALKER", OP_GPGPU_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2364                 0, 8, NULL},
2365
2366         {"MEDIA_VFE_STATE", OP_MEDIA_VFE_STATE, F_LEN_VAR, R_RCS, D_ALL, 0, 16,
2367                 NULL},
2368
2369         {"3DSTATE_VF_STATISTICS_GM45", OP_3DSTATE_VF_STATISTICS_GM45,
2370                 F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2371
2372         {"MFX_PIPE_MODE_SELECT", OP_MFX_PIPE_MODE_SELECT, F_LEN_VAR,
2373                 R_VCS, D_ALL, 0, 12, NULL},
2374
2375         {"MFX_SURFACE_STATE", OP_MFX_SURFACE_STATE, F_LEN_VAR,
2376                 R_VCS, D_ALL, 0, 12, NULL},
2377
2378         {"MFX_PIPE_BUF_ADDR_STATE", OP_MFX_PIPE_BUF_ADDR_STATE, F_LEN_VAR,
2379                 R_VCS, D_BDW_PLUS, 0, 12, NULL},
2380
2381         {"MFX_IND_OBJ_BASE_ADDR_STATE", OP_MFX_IND_OBJ_BASE_ADDR_STATE,
2382                 F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2383
2384         {"MFX_BSP_BUF_BASE_ADDR_STATE", OP_MFX_BSP_BUF_BASE_ADDR_STATE,
2385                 F_LEN_VAR, R_VCS, D_BDW_PLUS, ADDR_FIX_3(1, 3, 5), 12, NULL},
2386
2387         {"OP_2_0_0_5", OP_2_0_0_5, F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2388
2389         {"MFX_STATE_POINTER", OP_MFX_STATE_POINTER, F_LEN_VAR,
2390                 R_VCS, D_ALL, 0, 12, NULL},
2391
2392         {"MFX_QM_STATE", OP_MFX_QM_STATE, F_LEN_VAR,
2393                 R_VCS, D_ALL, 0, 12, NULL},
2394
2395         {"MFX_FQM_STATE", OP_MFX_FQM_STATE, F_LEN_VAR,
2396                 R_VCS, D_ALL, 0, 12, NULL},
2397
2398         {"MFX_PAK_INSERT_OBJECT", OP_MFX_PAK_INSERT_OBJECT, F_LEN_VAR,
2399                 R_VCS, D_ALL, 0, 12, NULL},
2400
2401         {"MFX_STITCH_OBJECT", OP_MFX_STITCH_OBJECT, F_LEN_VAR,
2402                 R_VCS, D_ALL, 0, 12, NULL},
2403
2404         {"MFD_IT_OBJECT", OP_MFD_IT_OBJECT, F_LEN_VAR,
2405                 R_VCS, D_ALL, 0, 12, NULL},
2406
2407         {"MFX_WAIT", OP_MFX_WAIT, F_LEN_VAR,
2408                 R_VCS, D_ALL, 0, 6, NULL},
2409
2410         {"MFX_AVC_IMG_STATE", OP_MFX_AVC_IMG_STATE, F_LEN_VAR,
2411                 R_VCS, D_ALL, 0, 12, NULL},
2412
2413         {"MFX_AVC_QM_STATE", OP_MFX_AVC_QM_STATE, F_LEN_VAR,
2414                 R_VCS, D_ALL, 0, 12, NULL},
2415
2416         {"MFX_AVC_DIRECTMODE_STATE", OP_MFX_AVC_DIRECTMODE_STATE, F_LEN_VAR,
2417                 R_VCS, D_ALL, 0, 12, NULL},
2418
2419         {"MFX_AVC_SLICE_STATE", OP_MFX_AVC_SLICE_STATE, F_LEN_VAR,
2420                 R_VCS, D_ALL, 0, 12, NULL},
2421
2422         {"MFX_AVC_REF_IDX_STATE", OP_MFX_AVC_REF_IDX_STATE, F_LEN_VAR,
2423                 R_VCS, D_ALL, 0, 12, NULL},
2424
2425         {"MFX_AVC_WEIGHTOFFSET_STATE", OP_MFX_AVC_WEIGHTOFFSET_STATE, F_LEN_VAR,
2426                 R_VCS, D_ALL, 0, 12, NULL},
2427
2428         {"MFD_AVC_PICID_STATE", OP_MFD_AVC_PICID_STATE, F_LEN_VAR,
2429                 R_VCS, D_ALL, 0, 12, NULL},
2430         {"MFD_AVC_DPB_STATE", OP_MFD_AVC_DPB_STATE, F_LEN_VAR,
2431                 R_VCS, D_ALL, 0, 12, NULL},
2432
2433         {"MFD_AVC_BSD_OBJECT", OP_MFD_AVC_BSD_OBJECT, F_LEN_VAR,
2434                 R_VCS, D_ALL, 0, 12, NULL},
2435
2436         {"MFD_AVC_SLICEADDR", OP_MFD_AVC_SLICEADDR, F_LEN_VAR,
2437                 R_VCS, D_ALL, ADDR_FIX_1(2), 12, NULL},
2438
2439         {"MFC_AVC_PAK_OBJECT", OP_MFC_AVC_PAK_OBJECT, F_LEN_VAR,
2440                 R_VCS, D_ALL, 0, 12, NULL},
2441
2442         {"MFX_VC1_PRED_PIPE_STATE", OP_MFX_VC1_PRED_PIPE_STATE, F_LEN_VAR,
2443                 R_VCS, D_ALL, 0, 12, NULL},
2444
2445         {"MFX_VC1_DIRECTMODE_STATE", OP_MFX_VC1_DIRECTMODE_STATE, F_LEN_VAR,
2446                 R_VCS, D_ALL, 0, 12, NULL},
2447
2448         {"MFD_VC1_SHORT_PIC_STATE", OP_MFD_VC1_SHORT_PIC_STATE, F_LEN_VAR,
2449                 R_VCS, D_ALL, 0, 12, NULL},
2450
2451         {"MFD_VC1_LONG_PIC_STATE", OP_MFD_VC1_LONG_PIC_STATE, F_LEN_VAR,
2452                 R_VCS, D_ALL, 0, 12, NULL},
2453
2454         {"MFD_VC1_BSD_OBJECT", OP_MFD_VC1_BSD_OBJECT, F_LEN_VAR,
2455                 R_VCS, D_ALL, 0, 12, NULL},
2456
2457         {"MFC_MPEG2_SLICEGROUP_STATE", OP_MFC_MPEG2_SLICEGROUP_STATE, F_LEN_VAR,
2458                 R_VCS, D_ALL, 0, 12, NULL},
2459
2460         {"MFC_MPEG2_PAK_OBJECT", OP_MFC_MPEG2_PAK_OBJECT, F_LEN_VAR,
2461                 R_VCS, D_ALL, 0, 12, NULL},
2462
2463         {"MFX_MPEG2_PIC_STATE", OP_MFX_MPEG2_PIC_STATE, F_LEN_VAR,
2464                 R_VCS, D_ALL, 0, 12, NULL},
2465
2466         {"MFX_MPEG2_QM_STATE", OP_MFX_MPEG2_QM_STATE, F_LEN_VAR,
2467                 R_VCS, D_ALL, 0, 12, NULL},
2468
2469         {"MFD_MPEG2_BSD_OBJECT", OP_MFD_MPEG2_BSD_OBJECT, F_LEN_VAR,
2470                 R_VCS, D_ALL, 0, 12, NULL},
2471
2472         {"MFX_2_6_0_0", OP_MFX_2_6_0_0, F_LEN_VAR, R_VCS, D_ALL,
2473                 0, 16, NULL},
2474
2475         {"MFX_2_6_0_9", OP_MFX_2_6_0_9, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2476
2477         {"MFX_2_6_0_8", OP_MFX_2_6_0_8, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2478
2479         {"MFX_JPEG_PIC_STATE", OP_MFX_JPEG_PIC_STATE, F_LEN_VAR,
2480                 R_VCS, D_ALL, 0, 12, NULL},
2481
2482         {"MFX_JPEG_HUFF_TABLE_STATE", OP_MFX_JPEG_HUFF_TABLE_STATE, F_LEN_VAR,
2483                 R_VCS, D_ALL, 0, 12, NULL},
2484
2485         {"MFD_JPEG_BSD_OBJECT", OP_MFD_JPEG_BSD_OBJECT, F_LEN_VAR,
2486                 R_VCS, D_ALL, 0, 12, NULL},
2487
2488         {"VEBOX_STATE", OP_VEB_STATE, F_LEN_VAR, R_VECS, D_ALL, 0, 12, NULL},
2489
2490         {"VEBOX_SURFACE_STATE", OP_VEB_SURFACE_STATE, F_LEN_VAR, R_VECS, D_ALL,
2491                 0, 12, NULL},
2492
2493         {"VEB_DI_IECP", OP_VEB_DNDI_IECP_STATE, F_LEN_VAR, R_VECS, D_BDW_PLUS,
2494                 0, 20, NULL},
2495 };
2496
2497 static void add_cmd_entry(struct intel_gvt *gvt, struct cmd_entry *e)
2498 {
2499         hash_add(gvt->cmd_table, &e->hlist, e->info->opcode);
2500 }
2501
2502 /* call the cmd handler, and advance ip */
2503 static int cmd_parser_exec(struct parser_exec_state *s)
2504 {
2505         struct intel_vgpu *vgpu = s->vgpu;
2506         struct cmd_info *info;
2507         u32 cmd;
2508         int ret = 0;
2509
2510         cmd = cmd_val(s, 0);
2511
2512         info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
2513         if (info == NULL) {
2514                 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",
2515                                 cmd, get_opcode(cmd, s->ring_id),
2516                                 (s->buf_addr_type == PPGTT_BUFFER) ?
2517                                 "ppgtt" : "ggtt", s->ring_id, s->workload);
2518                 return -EBADRQC;
2519         }
2520
2521         s->info = info;
2522
2523         trace_gvt_command(vgpu->id, s->ring_id, s->ip_gma, s->ip_va,
2524                           cmd_length(s), s->buf_type, s->buf_addr_type,
2525                           s->workload, info->name);
2526
2527         if (info->handler) {
2528                 ret = info->handler(s);
2529                 if (ret < 0) {
2530                         gvt_vgpu_err("%s handler error\n", info->name);
2531                         return ret;
2532                 }
2533         }
2534
2535         if (!(info->flag & F_IP_ADVANCE_CUSTOM)) {
2536                 ret = cmd_advance_default(s);
2537                 if (ret) {
2538                         gvt_vgpu_err("%s IP advance error\n", info->name);
2539                         return ret;
2540                 }
2541         }
2542         return 0;
2543 }
2544
2545 static inline bool gma_out_of_range(unsigned long gma,
2546                 unsigned long gma_head, unsigned int gma_tail)
2547 {
2548         if (gma_tail >= gma_head)
2549                 return (gma < gma_head) || (gma > gma_tail);
2550         else
2551                 return (gma > gma_tail) && (gma < gma_head);
2552 }
2553
2554 /* Keep the consistent return type, e.g EBADRQC for unknown
2555  * cmd, EFAULT for invalid address, EPERM for nonpriv. later
2556  * works as the input of VM healthy status.
2557  */
2558 static int command_scan(struct parser_exec_state *s,
2559                 unsigned long rb_head, unsigned long rb_tail,
2560                 unsigned long rb_start, unsigned long rb_len)
2561 {
2562
2563         unsigned long gma_head, gma_tail, gma_bottom;
2564         int ret = 0;
2565         struct intel_vgpu *vgpu = s->vgpu;
2566
2567         gma_head = rb_start + rb_head;
2568         gma_tail = rb_start + rb_tail;
2569         gma_bottom = rb_start +  rb_len;
2570
2571         while (s->ip_gma != gma_tail) {
2572                 if (s->buf_type == RING_BUFFER_INSTRUCTION) {
2573                         if (!(s->ip_gma >= rb_start) ||
2574                                 !(s->ip_gma < gma_bottom)) {
2575                                 gvt_vgpu_err("ip_gma %lx out of ring scope."
2576                                         "(base:0x%lx, bottom: 0x%lx)\n",
2577                                         s->ip_gma, rb_start,
2578                                         gma_bottom);
2579                                 parser_exec_state_dump(s);
2580                                 return -EFAULT;
2581                         }
2582                         if (gma_out_of_range(s->ip_gma, gma_head, gma_tail)) {
2583                                 gvt_vgpu_err("ip_gma %lx out of range."
2584                                         "base 0x%lx head 0x%lx tail 0x%lx\n",
2585                                         s->ip_gma, rb_start,
2586                                         rb_head, rb_tail);
2587                                 parser_exec_state_dump(s);
2588                                 break;
2589                         }
2590                 }
2591                 ret = cmd_parser_exec(s);
2592                 if (ret) {
2593                         gvt_vgpu_err("cmd parser error\n");
2594                         parser_exec_state_dump(s);
2595                         break;
2596                 }
2597         }
2598
2599         return ret;
2600 }
2601
2602 static int scan_workload(struct intel_vgpu_workload *workload)
2603 {
2604         unsigned long gma_head, gma_tail, gma_bottom;
2605         struct parser_exec_state s;
2606         int ret = 0;
2607
2608         /* ring base is page aligned */
2609         if (WARN_ON(!IS_ALIGNED(workload->rb_start, I915_GTT_PAGE_SIZE)))
2610                 return -EINVAL;
2611
2612         gma_head = workload->rb_start + workload->rb_head;
2613         gma_tail = workload->rb_start + workload->rb_tail;
2614         gma_bottom = workload->rb_start +  _RING_CTL_BUF_SIZE(workload->rb_ctl);
2615
2616         s.buf_type = RING_BUFFER_INSTRUCTION;
2617         s.buf_addr_type = GTT_BUFFER;
2618         s.vgpu = workload->vgpu;
2619         s.ring_id = workload->ring_id;
2620         s.ring_start = workload->rb_start;
2621         s.ring_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2622         s.ring_head = gma_head;
2623         s.ring_tail = gma_tail;
2624         s.rb_va = workload->shadow_ring_buffer_va;
2625         s.workload = workload;
2626         s.is_ctx_wa = false;
2627
2628         if ((bypass_scan_mask & (1 << workload->ring_id)) ||
2629                 gma_head == gma_tail)
2630                 return 0;
2631
2632         if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) {
2633                 ret = -EINVAL;
2634                 goto out;
2635         }
2636
2637         ret = ip_gma_set(&s, gma_head);
2638         if (ret)
2639                 goto out;
2640
2641         ret = command_scan(&s, workload->rb_head, workload->rb_tail,
2642                 workload->rb_start, _RING_CTL_BUF_SIZE(workload->rb_ctl));
2643
2644 out:
2645         return ret;
2646 }
2647
2648 static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2649 {
2650
2651         unsigned long gma_head, gma_tail, gma_bottom, ring_size, ring_tail;
2652         struct parser_exec_state s;
2653         int ret = 0;
2654         struct intel_vgpu_workload *workload = container_of(wa_ctx,
2655                                 struct intel_vgpu_workload,
2656                                 wa_ctx);
2657
2658         /* ring base is page aligned */
2659         if (WARN_ON(!IS_ALIGNED(wa_ctx->indirect_ctx.guest_gma,
2660                                         I915_GTT_PAGE_SIZE)))
2661                 return -EINVAL;
2662
2663         ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(uint32_t);
2664         ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES,
2665                         PAGE_SIZE);
2666         gma_head = wa_ctx->indirect_ctx.guest_gma;
2667         gma_tail = wa_ctx->indirect_ctx.guest_gma + ring_tail;
2668         gma_bottom = wa_ctx->indirect_ctx.guest_gma + ring_size;
2669
2670         s.buf_type = RING_BUFFER_INSTRUCTION;
2671         s.buf_addr_type = GTT_BUFFER;
2672         s.vgpu = workload->vgpu;
2673         s.ring_id = workload->ring_id;
2674         s.ring_start = wa_ctx->indirect_ctx.guest_gma;
2675         s.ring_size = ring_size;
2676         s.ring_head = gma_head;
2677         s.ring_tail = gma_tail;
2678         s.rb_va = wa_ctx->indirect_ctx.shadow_va;
2679         s.workload = workload;
2680         s.is_ctx_wa = true;
2681
2682         if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) {
2683                 ret = -EINVAL;
2684                 goto out;
2685         }
2686
2687         ret = ip_gma_set(&s, gma_head);
2688         if (ret)
2689                 goto out;
2690
2691         ret = command_scan(&s, 0, ring_tail,
2692                 wa_ctx->indirect_ctx.guest_gma, ring_size);
2693 out:
2694         return ret;
2695 }
2696
2697 static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload)
2698 {
2699         struct intel_vgpu *vgpu = workload->vgpu;
2700         struct intel_vgpu_submission *s = &vgpu->submission;
2701         unsigned long gma_head, gma_tail, gma_top, guest_rb_size;
2702         void *shadow_ring_buffer_va;
2703         int ring_id = workload->ring_id;
2704         int ret;
2705
2706         guest_rb_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2707
2708         /* calculate workload ring buffer size */
2709         workload->rb_len = (workload->rb_tail + guest_rb_size -
2710                         workload->rb_head) % guest_rb_size;
2711
2712         gma_head = workload->rb_start + workload->rb_head;
2713         gma_tail = workload->rb_start + workload->rb_tail;
2714         gma_top = workload->rb_start + guest_rb_size;
2715
2716         if (workload->rb_len > s->ring_scan_buffer_size[ring_id]) {
2717                 void *p;
2718
2719                 /* realloc the new ring buffer if needed */
2720                 p = krealloc(s->ring_scan_buffer[ring_id], workload->rb_len,
2721                                 GFP_KERNEL);
2722                 if (!p) {
2723                         gvt_vgpu_err("fail to re-alloc ring scan buffer\n");
2724                         return -ENOMEM;
2725                 }
2726                 s->ring_scan_buffer[ring_id] = p;
2727                 s->ring_scan_buffer_size[ring_id] = workload->rb_len;
2728         }
2729
2730         shadow_ring_buffer_va = s->ring_scan_buffer[ring_id];
2731
2732         /* get shadow ring buffer va */
2733         workload->shadow_ring_buffer_va = shadow_ring_buffer_va;
2734
2735         /* head > tail --> copy head <-> top */
2736         if (gma_head > gma_tail) {
2737                 ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm,
2738                                       gma_head, gma_top, shadow_ring_buffer_va);
2739                 if (ret < 0) {
2740                         gvt_vgpu_err("fail to copy guest ring buffer\n");
2741                         return ret;
2742                 }
2743                 shadow_ring_buffer_va += ret;
2744                 gma_head = workload->rb_start;
2745         }
2746
2747         /* copy head or start <-> tail */
2748         ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, gma_head, gma_tail,
2749                                 shadow_ring_buffer_va);
2750         if (ret < 0) {
2751                 gvt_vgpu_err("fail to copy guest ring buffer\n");
2752                 return ret;
2753         }
2754         return 0;
2755 }
2756
2757 int intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload *workload)
2758 {
2759         int ret;
2760         struct intel_vgpu *vgpu = workload->vgpu;
2761
2762         ret = shadow_workload_ring_buffer(workload);
2763         if (ret) {
2764                 gvt_vgpu_err("fail to shadow workload ring_buffer\n");
2765                 return ret;
2766         }
2767
2768         ret = scan_workload(workload);
2769         if (ret) {
2770                 gvt_vgpu_err("scan workload error\n");
2771                 return ret;
2772         }
2773         return 0;
2774 }
2775
2776 static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2777 {
2778         int ctx_size = wa_ctx->indirect_ctx.size;
2779         unsigned long guest_gma = wa_ctx->indirect_ctx.guest_gma;
2780         struct intel_vgpu_workload *workload = container_of(wa_ctx,
2781                                         struct intel_vgpu_workload,
2782                                         wa_ctx);
2783         struct intel_vgpu *vgpu = workload->vgpu;
2784         struct drm_i915_gem_object *obj;
2785         int ret = 0;
2786         void *map;
2787
2788         obj = i915_gem_object_create(workload->vgpu->gvt->dev_priv,
2789                                      roundup(ctx_size + CACHELINE_BYTES,
2790                                              PAGE_SIZE));
2791         if (IS_ERR(obj))
2792                 return PTR_ERR(obj);
2793
2794         /* get the va of the shadow batch buffer */
2795         map = i915_gem_object_pin_map(obj, I915_MAP_WB);
2796         if (IS_ERR(map)) {
2797                 gvt_vgpu_err("failed to vmap shadow indirect ctx\n");
2798                 ret = PTR_ERR(map);
2799                 goto put_obj;
2800         }
2801
2802         ret = i915_gem_object_set_to_cpu_domain(obj, false);
2803         if (ret) {
2804                 gvt_vgpu_err("failed to set shadow indirect ctx to CPU\n");
2805                 goto unmap_src;
2806         }
2807
2808         ret = copy_gma_to_hva(workload->vgpu,
2809                                 workload->vgpu->gtt.ggtt_mm,
2810                                 guest_gma, guest_gma + ctx_size,
2811                                 map);
2812         if (ret < 0) {
2813                 gvt_vgpu_err("fail to copy guest indirect ctx\n");
2814                 goto unmap_src;
2815         }
2816
2817         wa_ctx->indirect_ctx.obj = obj;
2818         wa_ctx->indirect_ctx.shadow_va = map;
2819         return 0;
2820
2821 unmap_src:
2822         i915_gem_object_unpin_map(obj);
2823 put_obj:
2824         i915_gem_object_put(obj);
2825         return ret;
2826 }
2827
2828 static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2829 {
2830         uint32_t per_ctx_start[CACHELINE_DWORDS] = {0};
2831         unsigned char *bb_start_sva;
2832
2833         if (!wa_ctx->per_ctx.valid)
2834                 return 0;
2835
2836         per_ctx_start[0] = 0x18800001;
2837         per_ctx_start[1] = wa_ctx->per_ctx.guest_gma;
2838
2839         bb_start_sva = (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
2840                                 wa_ctx->indirect_ctx.size;
2841
2842         memcpy(bb_start_sva, per_ctx_start, CACHELINE_BYTES);
2843
2844         return 0;
2845 }
2846
2847 int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2848 {
2849         int ret;
2850         struct intel_vgpu_workload *workload = container_of(wa_ctx,
2851                                         struct intel_vgpu_workload,
2852                                         wa_ctx);
2853         struct intel_vgpu *vgpu = workload->vgpu;
2854
2855         if (wa_ctx->indirect_ctx.size == 0)
2856                 return 0;
2857
2858         ret = shadow_indirect_ctx(wa_ctx);
2859         if (ret) {
2860                 gvt_vgpu_err("fail to shadow indirect ctx\n");
2861                 return ret;
2862         }
2863
2864         combine_wa_ctx(wa_ctx);
2865
2866         ret = scan_wa_ctx(wa_ctx);
2867         if (ret) {
2868                 gvt_vgpu_err("scan wa ctx error\n");
2869                 return ret;
2870         }
2871
2872         return 0;
2873 }
2874
2875 static struct cmd_info *find_cmd_entry_any_ring(struct intel_gvt *gvt,
2876                 unsigned int opcode, unsigned long rings)
2877 {
2878         struct cmd_info *info = NULL;
2879         unsigned int ring;
2880
2881         for_each_set_bit(ring, &rings, I915_NUM_ENGINES) {
2882                 info = find_cmd_entry(gvt, opcode, ring);
2883                 if (info)
2884                         break;
2885         }
2886         return info;
2887 }
2888
2889 static int init_cmd_table(struct intel_gvt *gvt)
2890 {
2891         int i;
2892         struct cmd_entry *e;
2893         struct cmd_info *info;
2894         unsigned int gen_type;
2895
2896         gen_type = intel_gvt_get_device_type(gvt);
2897
2898         for (i = 0; i < ARRAY_SIZE(cmd_info); i++) {
2899                 if (!(cmd_info[i].devices & gen_type))
2900                         continue;
2901
2902                 e = kzalloc(sizeof(*e), GFP_KERNEL);
2903                 if (!e)
2904                         return -ENOMEM;
2905
2906                 e->info = &cmd_info[i];
2907                 info = find_cmd_entry_any_ring(gvt,
2908                                 e->info->opcode, e->info->rings);
2909                 if (info) {
2910                         gvt_err("%s %s duplicated\n", e->info->name,
2911                                         info->name);
2912                         return -EEXIST;
2913                 }
2914
2915                 INIT_HLIST_NODE(&e->hlist);
2916                 add_cmd_entry(gvt, e);
2917                 gvt_dbg_cmd("add %-30s op %04x flag %x devs %02x rings %02x\n",
2918                                 e->info->name, e->info->opcode, e->info->flag,
2919                                 e->info->devices, e->info->rings);
2920         }
2921         return 0;
2922 }
2923
2924 static void clean_cmd_table(struct intel_gvt *gvt)
2925 {
2926         struct hlist_node *tmp;
2927         struct cmd_entry *e;
2928         int i;
2929
2930         hash_for_each_safe(gvt->cmd_table, i, tmp, e, hlist)
2931                 kfree(e);
2932
2933         hash_init(gvt->cmd_table);
2934 }
2935
2936 void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt)
2937 {
2938         clean_cmd_table(gvt);
2939 }
2940
2941 int intel_gvt_init_cmd_parser(struct intel_gvt *gvt)
2942 {
2943         int ret;
2944
2945         ret = init_cmd_table(gvt);
2946         if (ret) {
2947                 intel_gvt_clean_cmd_parser(gvt);
2948                 return ret;
2949         }
2950         return 0;
2951 }