drm/i915/gvt: let NOPID be the default value of force_to_nonpriv registers
[muen/linux.git] / drivers / gpu / drm / i915 / gvt / cmd_parser.c
1 /*
2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21  * SOFTWARE.
22  *
23  * Authors:
24  *    Ke Yu
25  *    Kevin Tian <kevin.tian@intel.com>
26  *    Zhiyuan Lv <zhiyuan.lv@intel.com>
27  *
28  * Contributors:
29  *    Min He <min.he@intel.com>
30  *    Ping Gao <ping.a.gao@intel.com>
31  *    Tina Zhang <tina.zhang@intel.com>
32  *    Yulei Zhang <yulei.zhang@intel.com>
33  *    Zhi Wang <zhi.a.wang@intel.com>
34  *
35  */
36
37 #include <linux/slab.h>
38 #include "i915_drv.h"
39 #include "gvt.h"
40 #include "i915_pvinfo.h"
41 #include "trace.h"
42
43 #define INVALID_OP    (~0U)
44
45 #define OP_LEN_MI           9
46 #define OP_LEN_2D           10
47 #define OP_LEN_3D_MEDIA     16
48 #define OP_LEN_MFX_VC       16
49 #define OP_LEN_VEBOX        16
50
51 #define CMD_TYPE(cmd)   (((cmd) >> 29) & 7)
52
53 struct sub_op_bits {
54         int hi;
55         int low;
56 };
57 struct decode_info {
58         char *name;
59         int op_len;
60         int nr_sub_op;
61         struct sub_op_bits *sub_op;
62 };
63
64 #define   MAX_CMD_BUDGET                        0x7fffffff
65 #define   MI_WAIT_FOR_PLANE_C_FLIP_PENDING      (1<<15)
66 #define   MI_WAIT_FOR_PLANE_B_FLIP_PENDING      (1<<9)
67 #define   MI_WAIT_FOR_PLANE_A_FLIP_PENDING      (1<<1)
68
69 #define   MI_WAIT_FOR_SPRITE_C_FLIP_PENDING      (1<<20)
70 #define   MI_WAIT_FOR_SPRITE_B_FLIP_PENDING      (1<<10)
71 #define   MI_WAIT_FOR_SPRITE_A_FLIP_PENDING      (1<<2)
72
73 /* Render Command Map */
74
75 /* MI_* command Opcode (28:23) */
76 #define OP_MI_NOOP                          0x0
77 #define OP_MI_SET_PREDICATE                 0x1  /* HSW+ */
78 #define OP_MI_USER_INTERRUPT                0x2
79 #define OP_MI_WAIT_FOR_EVENT                0x3
80 #define OP_MI_FLUSH                         0x4
81 #define OP_MI_ARB_CHECK                     0x5
82 #define OP_MI_RS_CONTROL                    0x6  /* HSW+ */
83 #define OP_MI_REPORT_HEAD                   0x7
84 #define OP_MI_ARB_ON_OFF                    0x8
85 #define OP_MI_URB_ATOMIC_ALLOC              0x9  /* HSW+ */
86 #define OP_MI_BATCH_BUFFER_END              0xA
87 #define OP_MI_SUSPEND_FLUSH                 0xB
88 #define OP_MI_PREDICATE                     0xC  /* IVB+ */
89 #define OP_MI_TOPOLOGY_FILTER               0xD  /* IVB+ */
90 #define OP_MI_SET_APPID                     0xE  /* IVB+ */
91 #define OP_MI_RS_CONTEXT                    0xF  /* HSW+ */
92 #define OP_MI_LOAD_SCAN_LINES_INCL          0x12 /* HSW+ */
93 #define OP_MI_DISPLAY_FLIP                  0x14
94 #define OP_MI_SEMAPHORE_MBOX                0x16
95 #define OP_MI_SET_CONTEXT                   0x18
96 #define OP_MI_MATH                          0x1A
97 #define OP_MI_URB_CLEAR                     0x19
98 #define OP_MI_SEMAPHORE_SIGNAL              0x1B  /* BDW+ */
99 #define OP_MI_SEMAPHORE_WAIT                0x1C  /* BDW+ */
100
101 #define OP_MI_STORE_DATA_IMM                0x20
102 #define OP_MI_STORE_DATA_INDEX              0x21
103 #define OP_MI_LOAD_REGISTER_IMM             0x22
104 #define OP_MI_UPDATE_GTT                    0x23
105 #define OP_MI_STORE_REGISTER_MEM            0x24
106 #define OP_MI_FLUSH_DW                      0x26
107 #define OP_MI_CLFLUSH                       0x27
108 #define OP_MI_REPORT_PERF_COUNT             0x28
109 #define OP_MI_LOAD_REGISTER_MEM             0x29  /* HSW+ */
110 #define OP_MI_LOAD_REGISTER_REG             0x2A  /* HSW+ */
111 #define OP_MI_RS_STORE_DATA_IMM             0x2B  /* HSW+ */
112 #define OP_MI_LOAD_URB_MEM                  0x2C  /* HSW+ */
113 #define OP_MI_STORE_URM_MEM                 0x2D  /* HSW+ */
114 #define OP_MI_2E                            0x2E  /* BDW+ */
115 #define OP_MI_2F                            0x2F  /* BDW+ */
116 #define OP_MI_BATCH_BUFFER_START            0x31
117
118 /* Bit definition for dword 0 */
119 #define _CMDBIT_BB_START_IN_PPGTT       (1UL << 8)
120
121 #define OP_MI_CONDITIONAL_BATCH_BUFFER_END  0x36
122
123 #define BATCH_BUFFER_ADDR_MASK ((1UL << 32) - (1U << 2))
124 #define BATCH_BUFFER_ADDR_HIGH_MASK ((1UL << 16) - (1U))
125 #define BATCH_BUFFER_ADR_SPACE_BIT(x)   (((x) >> 8) & 1U)
126 #define BATCH_BUFFER_2ND_LEVEL_BIT(x)   ((x) >> 22 & 1U)
127
128 /* 2D command: Opcode (28:22) */
129 #define OP_2D(x)    ((2<<7) | x)
130
131 #define OP_XY_SETUP_BLT                             OP_2D(0x1)
132 #define OP_XY_SETUP_CLIP_BLT                        OP_2D(0x3)
133 #define OP_XY_SETUP_MONO_PATTERN_SL_BLT             OP_2D(0x11)
134 #define OP_XY_PIXEL_BLT                             OP_2D(0x24)
135 #define OP_XY_SCANLINES_BLT                         OP_2D(0x25)
136 #define OP_XY_TEXT_BLT                              OP_2D(0x26)
137 #define OP_XY_TEXT_IMMEDIATE_BLT                    OP_2D(0x31)
138 #define OP_XY_COLOR_BLT                             OP_2D(0x50)
139 #define OP_XY_PAT_BLT                               OP_2D(0x51)
140 #define OP_XY_MONO_PAT_BLT                          OP_2D(0x52)
141 #define OP_XY_SRC_COPY_BLT                          OP_2D(0x53)
142 #define OP_XY_MONO_SRC_COPY_BLT                     OP_2D(0x54)
143 #define OP_XY_FULL_BLT                              OP_2D(0x55)
144 #define OP_XY_FULL_MONO_SRC_BLT                     OP_2D(0x56)
145 #define OP_XY_FULL_MONO_PATTERN_BLT                 OP_2D(0x57)
146 #define OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT        OP_2D(0x58)
147 #define OP_XY_MONO_PAT_FIXED_BLT                    OP_2D(0x59)
148 #define OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT           OP_2D(0x71)
149 #define OP_XY_PAT_BLT_IMMEDIATE                     OP_2D(0x72)
150 #define OP_XY_SRC_COPY_CHROMA_BLT                   OP_2D(0x73)
151 #define OP_XY_FULL_IMMEDIATE_PATTERN_BLT            OP_2D(0x74)
152 #define OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT   OP_2D(0x75)
153 #define OP_XY_PAT_CHROMA_BLT                        OP_2D(0x76)
154 #define OP_XY_PAT_CHROMA_BLT_IMMEDIATE              OP_2D(0x77)
155
156 /* 3D/Media Command: Pipeline Type(28:27) Opcode(26:24) Sub Opcode(23:16) */
157 #define OP_3D_MEDIA(sub_type, opcode, sub_opcode) \
158         ((3 << 13) | ((sub_type) << 11) | ((opcode) << 8) | (sub_opcode))
159
160 #define OP_STATE_PREFETCH                       OP_3D_MEDIA(0x0, 0x0, 0x03)
161
162 #define OP_STATE_BASE_ADDRESS                   OP_3D_MEDIA(0x0, 0x1, 0x01)
163 #define OP_STATE_SIP                            OP_3D_MEDIA(0x0, 0x1, 0x02)
164 #define OP_3D_MEDIA_0_1_4                       OP_3D_MEDIA(0x0, 0x1, 0x04)
165
166 #define OP_3DSTATE_VF_STATISTICS_GM45           OP_3D_MEDIA(0x1, 0x0, 0x0B)
167
168 #define OP_PIPELINE_SELECT                      OP_3D_MEDIA(0x1, 0x1, 0x04)
169
170 #define OP_MEDIA_VFE_STATE                      OP_3D_MEDIA(0x2, 0x0, 0x0)
171 #define OP_MEDIA_CURBE_LOAD                     OP_3D_MEDIA(0x2, 0x0, 0x1)
172 #define OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD      OP_3D_MEDIA(0x2, 0x0, 0x2)
173 #define OP_MEDIA_GATEWAY_STATE                  OP_3D_MEDIA(0x2, 0x0, 0x3)
174 #define OP_MEDIA_STATE_FLUSH                    OP_3D_MEDIA(0x2, 0x0, 0x4)
175
176 #define OP_MEDIA_OBJECT                         OP_3D_MEDIA(0x2, 0x1, 0x0)
177 #define OP_MEDIA_OBJECT_PRT                     OP_3D_MEDIA(0x2, 0x1, 0x2)
178 #define OP_MEDIA_OBJECT_WALKER                  OP_3D_MEDIA(0x2, 0x1, 0x3)
179 #define OP_GPGPU_WALKER                         OP_3D_MEDIA(0x2, 0x1, 0x5)
180
181 #define OP_3DSTATE_CLEAR_PARAMS                 OP_3D_MEDIA(0x3, 0x0, 0x04) /* IVB+ */
182 #define OP_3DSTATE_DEPTH_BUFFER                 OP_3D_MEDIA(0x3, 0x0, 0x05) /* IVB+ */
183 #define OP_3DSTATE_STENCIL_BUFFER               OP_3D_MEDIA(0x3, 0x0, 0x06) /* IVB+ */
184 #define OP_3DSTATE_HIER_DEPTH_BUFFER            OP_3D_MEDIA(0x3, 0x0, 0x07) /* IVB+ */
185 #define OP_3DSTATE_VERTEX_BUFFERS               OP_3D_MEDIA(0x3, 0x0, 0x08)
186 #define OP_3DSTATE_VERTEX_ELEMENTS              OP_3D_MEDIA(0x3, 0x0, 0x09)
187 #define OP_3DSTATE_INDEX_BUFFER                 OP_3D_MEDIA(0x3, 0x0, 0x0A)
188 #define OP_3DSTATE_VF_STATISTICS                OP_3D_MEDIA(0x3, 0x0, 0x0B)
189 #define OP_3DSTATE_VF                           OP_3D_MEDIA(0x3, 0x0, 0x0C)  /* HSW+ */
190 #define OP_3DSTATE_CC_STATE_POINTERS            OP_3D_MEDIA(0x3, 0x0, 0x0E)
191 #define OP_3DSTATE_SCISSOR_STATE_POINTERS       OP_3D_MEDIA(0x3, 0x0, 0x0F)
192 #define OP_3DSTATE_VS                           OP_3D_MEDIA(0x3, 0x0, 0x10)
193 #define OP_3DSTATE_GS                           OP_3D_MEDIA(0x3, 0x0, 0x11)
194 #define OP_3DSTATE_CLIP                         OP_3D_MEDIA(0x3, 0x0, 0x12)
195 #define OP_3DSTATE_SF                           OP_3D_MEDIA(0x3, 0x0, 0x13)
196 #define OP_3DSTATE_WM                           OP_3D_MEDIA(0x3, 0x0, 0x14)
197 #define OP_3DSTATE_CONSTANT_VS                  OP_3D_MEDIA(0x3, 0x0, 0x15)
198 #define OP_3DSTATE_CONSTANT_GS                  OP_3D_MEDIA(0x3, 0x0, 0x16)
199 #define OP_3DSTATE_CONSTANT_PS                  OP_3D_MEDIA(0x3, 0x0, 0x17)
200 #define OP_3DSTATE_SAMPLE_MASK                  OP_3D_MEDIA(0x3, 0x0, 0x18)
201 #define OP_3DSTATE_CONSTANT_HS                  OP_3D_MEDIA(0x3, 0x0, 0x19) /* IVB+ */
202 #define OP_3DSTATE_CONSTANT_DS                  OP_3D_MEDIA(0x3, 0x0, 0x1A) /* IVB+ */
203 #define OP_3DSTATE_HS                           OP_3D_MEDIA(0x3, 0x0, 0x1B) /* IVB+ */
204 #define OP_3DSTATE_TE                           OP_3D_MEDIA(0x3, 0x0, 0x1C) /* IVB+ */
205 #define OP_3DSTATE_DS                           OP_3D_MEDIA(0x3, 0x0, 0x1D) /* IVB+ */
206 #define OP_3DSTATE_STREAMOUT                    OP_3D_MEDIA(0x3, 0x0, 0x1E) /* IVB+ */
207 #define OP_3DSTATE_SBE                          OP_3D_MEDIA(0x3, 0x0, 0x1F) /* IVB+ */
208 #define OP_3DSTATE_PS                           OP_3D_MEDIA(0x3, 0x0, 0x20) /* IVB+ */
209 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP OP_3D_MEDIA(0x3, 0x0, 0x21) /* IVB+ */
210 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC   OP_3D_MEDIA(0x3, 0x0, 0x23) /* IVB+ */
211 #define OP_3DSTATE_BLEND_STATE_POINTERS         OP_3D_MEDIA(0x3, 0x0, 0x24) /* IVB+ */
212 #define OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x25) /* IVB+ */
213 #define OP_3DSTATE_BINDING_TABLE_POINTERS_VS    OP_3D_MEDIA(0x3, 0x0, 0x26) /* IVB+ */
214 #define OP_3DSTATE_BINDING_TABLE_POINTERS_HS    OP_3D_MEDIA(0x3, 0x0, 0x27) /* IVB+ */
215 #define OP_3DSTATE_BINDING_TABLE_POINTERS_DS    OP_3D_MEDIA(0x3, 0x0, 0x28) /* IVB+ */
216 #define OP_3DSTATE_BINDING_TABLE_POINTERS_GS    OP_3D_MEDIA(0x3, 0x0, 0x29) /* IVB+ */
217 #define OP_3DSTATE_BINDING_TABLE_POINTERS_PS    OP_3D_MEDIA(0x3, 0x0, 0x2A) /* IVB+ */
218 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_VS    OP_3D_MEDIA(0x3, 0x0, 0x2B) /* IVB+ */
219 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_HS    OP_3D_MEDIA(0x3, 0x0, 0x2C) /* IVB+ */
220 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_DS    OP_3D_MEDIA(0x3, 0x0, 0x2D) /* IVB+ */
221 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_GS    OP_3D_MEDIA(0x3, 0x0, 0x2E) /* IVB+ */
222 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_PS    OP_3D_MEDIA(0x3, 0x0, 0x2F) /* IVB+ */
223 #define OP_3DSTATE_URB_VS                       OP_3D_MEDIA(0x3, 0x0, 0x30) /* IVB+ */
224 #define OP_3DSTATE_URB_HS                       OP_3D_MEDIA(0x3, 0x0, 0x31) /* IVB+ */
225 #define OP_3DSTATE_URB_DS                       OP_3D_MEDIA(0x3, 0x0, 0x32) /* IVB+ */
226 #define OP_3DSTATE_URB_GS                       OP_3D_MEDIA(0x3, 0x0, 0x33) /* IVB+ */
227 #define OP_3DSTATE_GATHER_CONSTANT_VS           OP_3D_MEDIA(0x3, 0x0, 0x34) /* HSW+ */
228 #define OP_3DSTATE_GATHER_CONSTANT_GS           OP_3D_MEDIA(0x3, 0x0, 0x35) /* HSW+ */
229 #define OP_3DSTATE_GATHER_CONSTANT_HS           OP_3D_MEDIA(0x3, 0x0, 0x36) /* HSW+ */
230 #define OP_3DSTATE_GATHER_CONSTANT_DS           OP_3D_MEDIA(0x3, 0x0, 0x37) /* HSW+ */
231 #define OP_3DSTATE_GATHER_CONSTANT_PS           OP_3D_MEDIA(0x3, 0x0, 0x38) /* HSW+ */
232 #define OP_3DSTATE_DX9_CONSTANTF_VS             OP_3D_MEDIA(0x3, 0x0, 0x39) /* HSW+ */
233 #define OP_3DSTATE_DX9_CONSTANTF_PS             OP_3D_MEDIA(0x3, 0x0, 0x3A) /* HSW+ */
234 #define OP_3DSTATE_DX9_CONSTANTI_VS             OP_3D_MEDIA(0x3, 0x0, 0x3B) /* HSW+ */
235 #define OP_3DSTATE_DX9_CONSTANTI_PS             OP_3D_MEDIA(0x3, 0x0, 0x3C) /* HSW+ */
236 #define OP_3DSTATE_DX9_CONSTANTB_VS             OP_3D_MEDIA(0x3, 0x0, 0x3D) /* HSW+ */
237 #define OP_3DSTATE_DX9_CONSTANTB_PS             OP_3D_MEDIA(0x3, 0x0, 0x3E) /* HSW+ */
238 #define OP_3DSTATE_DX9_LOCAL_VALID_VS           OP_3D_MEDIA(0x3, 0x0, 0x3F) /* HSW+ */
239 #define OP_3DSTATE_DX9_LOCAL_VALID_PS           OP_3D_MEDIA(0x3, 0x0, 0x40) /* HSW+ */
240 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_VS       OP_3D_MEDIA(0x3, 0x0, 0x41) /* HSW+ */
241 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_PS       OP_3D_MEDIA(0x3, 0x0, 0x42) /* HSW+ */
242 #define OP_3DSTATE_BINDING_TABLE_EDIT_VS        OP_3D_MEDIA(0x3, 0x0, 0x43) /* HSW+ */
243 #define OP_3DSTATE_BINDING_TABLE_EDIT_GS        OP_3D_MEDIA(0x3, 0x0, 0x44) /* HSW+ */
244 #define OP_3DSTATE_BINDING_TABLE_EDIT_HS        OP_3D_MEDIA(0x3, 0x0, 0x45) /* HSW+ */
245 #define OP_3DSTATE_BINDING_TABLE_EDIT_DS        OP_3D_MEDIA(0x3, 0x0, 0x46) /* HSW+ */
246 #define OP_3DSTATE_BINDING_TABLE_EDIT_PS        OP_3D_MEDIA(0x3, 0x0, 0x47) /* HSW+ */
247
248 #define OP_3DSTATE_VF_INSTANCING                OP_3D_MEDIA(0x3, 0x0, 0x49) /* BDW+ */
249 #define OP_3DSTATE_VF_SGVS                      OP_3D_MEDIA(0x3, 0x0, 0x4A) /* BDW+ */
250 #define OP_3DSTATE_VF_TOPOLOGY                  OP_3D_MEDIA(0x3, 0x0, 0x4B) /* BDW+ */
251 #define OP_3DSTATE_WM_CHROMAKEY                 OP_3D_MEDIA(0x3, 0x0, 0x4C) /* BDW+ */
252 #define OP_3DSTATE_PS_BLEND                     OP_3D_MEDIA(0x3, 0x0, 0x4D) /* BDW+ */
253 #define OP_3DSTATE_WM_DEPTH_STENCIL             OP_3D_MEDIA(0x3, 0x0, 0x4E) /* BDW+ */
254 #define OP_3DSTATE_PS_EXTRA                     OP_3D_MEDIA(0x3, 0x0, 0x4F) /* BDW+ */
255 #define OP_3DSTATE_RASTER                       OP_3D_MEDIA(0x3, 0x0, 0x50) /* BDW+ */
256 #define OP_3DSTATE_SBE_SWIZ                     OP_3D_MEDIA(0x3, 0x0, 0x51) /* BDW+ */
257 #define OP_3DSTATE_WM_HZ_OP                     OP_3D_MEDIA(0x3, 0x0, 0x52) /* BDW+ */
258 #define OP_3DSTATE_COMPONENT_PACKING            OP_3D_MEDIA(0x3, 0x0, 0x55) /* SKL+ */
259
260 #define OP_3DSTATE_DRAWING_RECTANGLE            OP_3D_MEDIA(0x3, 0x1, 0x00)
261 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD0        OP_3D_MEDIA(0x3, 0x1, 0x02)
262 #define OP_3DSTATE_CHROMA_KEY                   OP_3D_MEDIA(0x3, 0x1, 0x04)
263 #define OP_SNB_3DSTATE_DEPTH_BUFFER             OP_3D_MEDIA(0x3, 0x1, 0x05)
264 #define OP_3DSTATE_POLY_STIPPLE_OFFSET          OP_3D_MEDIA(0x3, 0x1, 0x06)
265 #define OP_3DSTATE_POLY_STIPPLE_PATTERN         OP_3D_MEDIA(0x3, 0x1, 0x07)
266 #define OP_3DSTATE_LINE_STIPPLE                 OP_3D_MEDIA(0x3, 0x1, 0x08)
267 #define OP_3DSTATE_AA_LINE_PARAMS               OP_3D_MEDIA(0x3, 0x1, 0x0A)
268 #define OP_3DSTATE_GS_SVB_INDEX                 OP_3D_MEDIA(0x3, 0x1, 0x0B)
269 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD1        OP_3D_MEDIA(0x3, 0x1, 0x0C)
270 #define OP_3DSTATE_MULTISAMPLE_BDW              OP_3D_MEDIA(0x3, 0x0, 0x0D)
271 #define OP_SNB_3DSTATE_STENCIL_BUFFER           OP_3D_MEDIA(0x3, 0x1, 0x0E)
272 #define OP_SNB_3DSTATE_HIER_DEPTH_BUFFER        OP_3D_MEDIA(0x3, 0x1, 0x0F)
273 #define OP_SNB_3DSTATE_CLEAR_PARAMS             OP_3D_MEDIA(0x3, 0x1, 0x10)
274 #define OP_3DSTATE_MONOFILTER_SIZE              OP_3D_MEDIA(0x3, 0x1, 0x11)
275 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS       OP_3D_MEDIA(0x3, 0x1, 0x12) /* IVB+ */
276 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS       OP_3D_MEDIA(0x3, 0x1, 0x13) /* IVB+ */
277 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS       OP_3D_MEDIA(0x3, 0x1, 0x14) /* IVB+ */
278 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS       OP_3D_MEDIA(0x3, 0x1, 0x15) /* IVB+ */
279 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS       OP_3D_MEDIA(0x3, 0x1, 0x16) /* IVB+ */
280 #define OP_3DSTATE_SO_DECL_LIST                 OP_3D_MEDIA(0x3, 0x1, 0x17)
281 #define OP_3DSTATE_SO_BUFFER                    OP_3D_MEDIA(0x3, 0x1, 0x18)
282 #define OP_3DSTATE_BINDING_TABLE_POOL_ALLOC     OP_3D_MEDIA(0x3, 0x1, 0x19) /* HSW+ */
283 #define OP_3DSTATE_GATHER_POOL_ALLOC            OP_3D_MEDIA(0x3, 0x1, 0x1A) /* HSW+ */
284 #define OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1B) /* HSW+ */
285 #define OP_3DSTATE_SAMPLE_PATTERN               OP_3D_MEDIA(0x3, 0x1, 0x1C)
286 #define OP_PIPE_CONTROL                         OP_3D_MEDIA(0x3, 0x2, 0x00)
287 #define OP_3DPRIMITIVE                          OP_3D_MEDIA(0x3, 0x3, 0x00)
288
289 /* VCCP Command Parser */
290
291 /*
292  * Below MFX and VBE cmd definition is from vaapi intel driver project (BSD License)
293  * git://anongit.freedesktop.org/vaapi/intel-driver
294  * src/i965_defines.h
295  *
296  */
297
298 #define OP_MFX(pipeline, op, sub_opa, sub_opb)     \
299         (3 << 13 | \
300          (pipeline) << 11 | \
301          (op) << 8 | \
302          (sub_opa) << 5 | \
303          (sub_opb))
304
305 #define OP_MFX_PIPE_MODE_SELECT                    OP_MFX(2, 0, 0, 0)  /* ALL */
306 #define OP_MFX_SURFACE_STATE                       OP_MFX(2, 0, 0, 1)  /* ALL */
307 #define OP_MFX_PIPE_BUF_ADDR_STATE                 OP_MFX(2, 0, 0, 2)  /* ALL */
308 #define OP_MFX_IND_OBJ_BASE_ADDR_STATE             OP_MFX(2, 0, 0, 3)  /* ALL */
309 #define OP_MFX_BSP_BUF_BASE_ADDR_STATE             OP_MFX(2, 0, 0, 4)  /* ALL */
310 #define OP_2_0_0_5                                 OP_MFX(2, 0, 0, 5)  /* ALL */
311 #define OP_MFX_STATE_POINTER                       OP_MFX(2, 0, 0, 6)  /* ALL */
312 #define OP_MFX_QM_STATE                            OP_MFX(2, 0, 0, 7)  /* IVB+ */
313 #define OP_MFX_FQM_STATE                           OP_MFX(2, 0, 0, 8)  /* IVB+ */
314 #define OP_MFX_PAK_INSERT_OBJECT                   OP_MFX(2, 0, 2, 8)  /* IVB+ */
315 #define OP_MFX_STITCH_OBJECT                       OP_MFX(2, 0, 2, 0xA)  /* IVB+ */
316
317 #define OP_MFD_IT_OBJECT                           OP_MFX(2, 0, 1, 9) /* ALL */
318
319 #define OP_MFX_WAIT                                OP_MFX(1, 0, 0, 0) /* IVB+ */
320 #define OP_MFX_AVC_IMG_STATE                       OP_MFX(2, 1, 0, 0) /* ALL */
321 #define OP_MFX_AVC_QM_STATE                        OP_MFX(2, 1, 0, 1) /* ALL */
322 #define OP_MFX_AVC_DIRECTMODE_STATE                OP_MFX(2, 1, 0, 2) /* ALL */
323 #define OP_MFX_AVC_SLICE_STATE                     OP_MFX(2, 1, 0, 3) /* ALL */
324 #define OP_MFX_AVC_REF_IDX_STATE                   OP_MFX(2, 1, 0, 4) /* ALL */
325 #define OP_MFX_AVC_WEIGHTOFFSET_STATE              OP_MFX(2, 1, 0, 5) /* ALL */
326 #define OP_MFD_AVC_PICID_STATE                     OP_MFX(2, 1, 1, 5) /* HSW+ */
327 #define OP_MFD_AVC_DPB_STATE                       OP_MFX(2, 1, 1, 6) /* IVB+ */
328 #define OP_MFD_AVC_SLICEADDR                       OP_MFX(2, 1, 1, 7) /* IVB+ */
329 #define OP_MFD_AVC_BSD_OBJECT                      OP_MFX(2, 1, 1, 8) /* ALL */
330 #define OP_MFC_AVC_PAK_OBJECT                      OP_MFX(2, 1, 2, 9) /* ALL */
331
332 #define OP_MFX_VC1_PRED_PIPE_STATE                 OP_MFX(2, 2, 0, 1) /* ALL */
333 #define OP_MFX_VC1_DIRECTMODE_STATE                OP_MFX(2, 2, 0, 2) /* ALL */
334 #define OP_MFD_VC1_SHORT_PIC_STATE                 OP_MFX(2, 2, 1, 0) /* IVB+ */
335 #define OP_MFD_VC1_LONG_PIC_STATE                  OP_MFX(2, 2, 1, 1) /* IVB+ */
336 #define OP_MFD_VC1_BSD_OBJECT                      OP_MFX(2, 2, 1, 8) /* ALL */
337
338 #define OP_MFX_MPEG2_PIC_STATE                     OP_MFX(2, 3, 0, 0) /* ALL */
339 #define OP_MFX_MPEG2_QM_STATE                      OP_MFX(2, 3, 0, 1) /* ALL */
340 #define OP_MFD_MPEG2_BSD_OBJECT                    OP_MFX(2, 3, 1, 8) /* ALL */
341 #define OP_MFC_MPEG2_SLICEGROUP_STATE              OP_MFX(2, 3, 2, 3) /* ALL */
342 #define OP_MFC_MPEG2_PAK_OBJECT                    OP_MFX(2, 3, 2, 9) /* ALL */
343
344 #define OP_MFX_2_6_0_0                             OP_MFX(2, 6, 0, 0) /* IVB+ */
345 #define OP_MFX_2_6_0_8                             OP_MFX(2, 6, 0, 8) /* IVB+ */
346 #define OP_MFX_2_6_0_9                             OP_MFX(2, 6, 0, 9) /* IVB+ */
347
348 #define OP_MFX_JPEG_PIC_STATE                      OP_MFX(2, 7, 0, 0)
349 #define OP_MFX_JPEG_HUFF_TABLE_STATE               OP_MFX(2, 7, 0, 2)
350 #define OP_MFD_JPEG_BSD_OBJECT                     OP_MFX(2, 7, 1, 8)
351
352 #define OP_VEB(pipeline, op, sub_opa, sub_opb) \
353         (3 << 13 | \
354          (pipeline) << 11 | \
355          (op) << 8 | \
356          (sub_opa) << 5 | \
357          (sub_opb))
358
359 #define OP_VEB_SURFACE_STATE                       OP_VEB(2, 4, 0, 0)
360 #define OP_VEB_STATE                               OP_VEB(2, 4, 0, 2)
361 #define OP_VEB_DNDI_IECP_STATE                     OP_VEB(2, 4, 0, 3)
362
363 struct parser_exec_state;
364
365 typedef int (*parser_cmd_handler)(struct parser_exec_state *s);
366
367 #define GVT_CMD_HASH_BITS   7
368
369 /* which DWords need address fix */
370 #define ADDR_FIX_1(x1)                  (1 << (x1))
371 #define ADDR_FIX_2(x1, x2)              (ADDR_FIX_1(x1) | ADDR_FIX_1(x2))
372 #define ADDR_FIX_3(x1, x2, x3)          (ADDR_FIX_1(x1) | ADDR_FIX_2(x2, x3))
373 #define ADDR_FIX_4(x1, x2, x3, x4)      (ADDR_FIX_1(x1) | ADDR_FIX_3(x2, x3, x4))
374 #define ADDR_FIX_5(x1, x2, x3, x4, x5)  (ADDR_FIX_1(x1) | ADDR_FIX_4(x2, x3, x4, x5))
375
376 struct cmd_info {
377         char *name;
378         u32 opcode;
379
380 #define F_LEN_MASK      (1U<<0)
381 #define F_LEN_CONST  1U
382 #define F_LEN_VAR    0U
383
384 /*
385  * command has its own ip advance logic
386  * e.g. MI_BATCH_START, MI_BATCH_END
387  */
388 #define F_IP_ADVANCE_CUSTOM (1<<1)
389
390 #define F_POST_HANDLE   (1<<2)
391         u32 flag;
392
393 #define R_RCS   (1 << RCS)
394 #define R_VCS1  (1 << VCS)
395 #define R_VCS2  (1 << VCS2)
396 #define R_VCS   (R_VCS1 | R_VCS2)
397 #define R_BCS   (1 << BCS)
398 #define R_VECS  (1 << VECS)
399 #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
400         /* rings that support this cmd: BLT/RCS/VCS/VECS */
401         uint16_t rings;
402
403         /* devices that support this cmd: SNB/IVB/HSW/... */
404         uint16_t devices;
405
406         /* which DWords are address that need fix up.
407          * bit 0 means a 32-bit non address operand in command
408          * bit 1 means address operand, which could be 32-bit
409          * or 64-bit depending on different architectures.(
410          * defined by "gmadr_bytes_in_cmd" in intel_gvt.
411          * No matter the address length, each address only takes
412          * one bit in the bitmap.
413          */
414         uint16_t addr_bitmap;
415
416         /* flag == F_LEN_CONST : command length
417          * flag == F_LEN_VAR : length bias bits
418          * Note: length is in DWord
419          */
420         uint8_t len;
421
422         parser_cmd_handler handler;
423 };
424
425 struct cmd_entry {
426         struct hlist_node hlist;
427         struct cmd_info *info;
428 };
429
430 enum {
431         RING_BUFFER_INSTRUCTION,
432         BATCH_BUFFER_INSTRUCTION,
433         BATCH_BUFFER_2ND_LEVEL,
434 };
435
436 enum {
437         GTT_BUFFER,
438         PPGTT_BUFFER
439 };
440
441 struct parser_exec_state {
442         struct intel_vgpu *vgpu;
443         int ring_id;
444
445         int buf_type;
446
447         /* batch buffer address type */
448         int buf_addr_type;
449
450         /* graphics memory address of ring buffer start */
451         unsigned long ring_start;
452         unsigned long ring_size;
453         unsigned long ring_head;
454         unsigned long ring_tail;
455
456         /* instruction graphics memory address */
457         unsigned long ip_gma;
458
459         /* mapped va of the instr_gma */
460         void *ip_va;
461         void *rb_va;
462
463         void *ret_bb_va;
464         /* next instruction when return from  batch buffer to ring buffer */
465         unsigned long ret_ip_gma_ring;
466
467         /* next instruction when return from 2nd batch buffer to batch buffer */
468         unsigned long ret_ip_gma_bb;
469
470         /* batch buffer address type (GTT or PPGTT)
471          * used when ret from 2nd level batch buffer
472          */
473         int saved_buf_addr_type;
474         bool is_ctx_wa;
475
476         struct cmd_info *info;
477
478         struct intel_vgpu_workload *workload;
479 };
480
481 #define gmadr_dw_number(s)      \
482         (s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2)
483
484 static unsigned long bypass_scan_mask = 0;
485
486 /* ring ALL, type = 0 */
487 static struct sub_op_bits sub_op_mi[] = {
488         {31, 29},
489         {28, 23},
490 };
491
492 static struct decode_info decode_info_mi = {
493         "MI",
494         OP_LEN_MI,
495         ARRAY_SIZE(sub_op_mi),
496         sub_op_mi,
497 };
498
499 /* ring RCS, command type 2 */
500 static struct sub_op_bits sub_op_2d[] = {
501         {31, 29},
502         {28, 22},
503 };
504
505 static struct decode_info decode_info_2d = {
506         "2D",
507         OP_LEN_2D,
508         ARRAY_SIZE(sub_op_2d),
509         sub_op_2d,
510 };
511
512 /* ring RCS, command type 3 */
513 static struct sub_op_bits sub_op_3d_media[] = {
514         {31, 29},
515         {28, 27},
516         {26, 24},
517         {23, 16},
518 };
519
520 static struct decode_info decode_info_3d_media = {
521         "3D_Media",
522         OP_LEN_3D_MEDIA,
523         ARRAY_SIZE(sub_op_3d_media),
524         sub_op_3d_media,
525 };
526
527 /* ring VCS, command type 3 */
528 static struct sub_op_bits sub_op_mfx_vc[] = {
529         {31, 29},
530         {28, 27},
531         {26, 24},
532         {23, 21},
533         {20, 16},
534 };
535
536 static struct decode_info decode_info_mfx_vc = {
537         "MFX_VC",
538         OP_LEN_MFX_VC,
539         ARRAY_SIZE(sub_op_mfx_vc),
540         sub_op_mfx_vc,
541 };
542
543 /* ring VECS, command type 3 */
544 static struct sub_op_bits sub_op_vebox[] = {
545         {31, 29},
546         {28, 27},
547         {26, 24},
548         {23, 21},
549         {20, 16},
550 };
551
552 static struct decode_info decode_info_vebox = {
553         "VEBOX",
554         OP_LEN_VEBOX,
555         ARRAY_SIZE(sub_op_vebox),
556         sub_op_vebox,
557 };
558
559 static struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
560         [RCS] = {
561                 &decode_info_mi,
562                 NULL,
563                 NULL,
564                 &decode_info_3d_media,
565                 NULL,
566                 NULL,
567                 NULL,
568                 NULL,
569         },
570
571         [VCS] = {
572                 &decode_info_mi,
573                 NULL,
574                 NULL,
575                 &decode_info_mfx_vc,
576                 NULL,
577                 NULL,
578                 NULL,
579                 NULL,
580         },
581
582         [BCS] = {
583                 &decode_info_mi,
584                 NULL,
585                 &decode_info_2d,
586                 NULL,
587                 NULL,
588                 NULL,
589                 NULL,
590                 NULL,
591         },
592
593         [VECS] = {
594                 &decode_info_mi,
595                 NULL,
596                 NULL,
597                 &decode_info_vebox,
598                 NULL,
599                 NULL,
600                 NULL,
601                 NULL,
602         },
603
604         [VCS2] = {
605                 &decode_info_mi,
606                 NULL,
607                 NULL,
608                 &decode_info_mfx_vc,
609                 NULL,
610                 NULL,
611                 NULL,
612                 NULL,
613         },
614 };
615
616 static inline u32 get_opcode(u32 cmd, int ring_id)
617 {
618         struct decode_info *d_info;
619
620         d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)];
621         if (d_info == NULL)
622                 return INVALID_OP;
623
624         return cmd >> (32 - d_info->op_len);
625 }
626
627 static inline struct cmd_info *find_cmd_entry(struct intel_gvt *gvt,
628                 unsigned int opcode, int ring_id)
629 {
630         struct cmd_entry *e;
631
632         hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) {
633                 if ((opcode == e->info->opcode) &&
634                                 (e->info->rings & (1 << ring_id)))
635                         return e->info;
636         }
637         return NULL;
638 }
639
640 static inline struct cmd_info *get_cmd_info(struct intel_gvt *gvt,
641                 u32 cmd, int ring_id)
642 {
643         u32 opcode;
644
645         opcode = get_opcode(cmd, ring_id);
646         if (opcode == INVALID_OP)
647                 return NULL;
648
649         return find_cmd_entry(gvt, opcode, ring_id);
650 }
651
652 static inline u32 sub_op_val(u32 cmd, u32 hi, u32 low)
653 {
654         return (cmd >> low) & ((1U << (hi - low + 1)) - 1);
655 }
656
657 static inline void print_opcode(u32 cmd, int ring_id)
658 {
659         struct decode_info *d_info;
660         int i;
661
662         d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)];
663         if (d_info == NULL)
664                 return;
665
666         gvt_dbg_cmd("opcode=0x%x %s sub_ops:",
667                         cmd >> (32 - d_info->op_len), d_info->name);
668
669         for (i = 0; i < d_info->nr_sub_op; i++)
670                 pr_err("0x%x ", sub_op_val(cmd, d_info->sub_op[i].hi,
671                                         d_info->sub_op[i].low));
672
673         pr_err("\n");
674 }
675
676 static inline u32 *cmd_ptr(struct parser_exec_state *s, int index)
677 {
678         return s->ip_va + (index << 2);
679 }
680
681 static inline u32 cmd_val(struct parser_exec_state *s, int index)
682 {
683         return *cmd_ptr(s, index);
684 }
685
686 static void parser_exec_state_dump(struct parser_exec_state *s)
687 {
688         int cnt = 0;
689         int i;
690
691         gvt_dbg_cmd("  vgpu%d RING%d: ring_start(%08lx) ring_end(%08lx)"
692                         " ring_head(%08lx) ring_tail(%08lx)\n", s->vgpu->id,
693                         s->ring_id, s->ring_start, s->ring_start + s->ring_size,
694                         s->ring_head, s->ring_tail);
695
696         gvt_dbg_cmd("  %s %s ip_gma(%08lx) ",
697                         s->buf_type == RING_BUFFER_INSTRUCTION ?
698                         "RING_BUFFER" : "BATCH_BUFFER",
699                         s->buf_addr_type == GTT_BUFFER ?
700                         "GTT" : "PPGTT", s->ip_gma);
701
702         if (s->ip_va == NULL) {
703                 gvt_dbg_cmd(" ip_va(NULL)");
704                 return;
705         }
706
707         gvt_dbg_cmd("  ip_va=%p: %08x %08x %08x %08x\n",
708                         s->ip_va, cmd_val(s, 0), cmd_val(s, 1),
709                         cmd_val(s, 2), cmd_val(s, 3));
710
711         print_opcode(cmd_val(s, 0), s->ring_id);
712
713         s->ip_va = (u32 *)((((u64)s->ip_va) >> 12) << 12);
714
715         while (cnt < 1024) {
716                 gvt_dbg_cmd("ip_va=%p: ", s->ip_va);
717                 for (i = 0; i < 8; i++)
718                         gvt_dbg_cmd("%08x ", cmd_val(s, i));
719                 gvt_dbg_cmd("\n");
720
721                 s->ip_va += 8 * sizeof(u32);
722                 cnt += 8;
723         }
724 }
725
726 static inline void update_ip_va(struct parser_exec_state *s)
727 {
728         unsigned long len = 0;
729
730         if (WARN_ON(s->ring_head == s->ring_tail))
731                 return;
732
733         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
734                 unsigned long ring_top = s->ring_start + s->ring_size;
735
736                 if (s->ring_head > s->ring_tail) {
737                         if (s->ip_gma >= s->ring_head && s->ip_gma < ring_top)
738                                 len = (s->ip_gma - s->ring_head);
739                         else if (s->ip_gma >= s->ring_start &&
740                                         s->ip_gma <= s->ring_tail)
741                                 len = (ring_top - s->ring_head) +
742                                         (s->ip_gma - s->ring_start);
743                 } else
744                         len = (s->ip_gma - s->ring_head);
745
746                 s->ip_va = s->rb_va + len;
747         } else {/* shadow batch buffer */
748                 s->ip_va = s->ret_bb_va;
749         }
750 }
751
752 static inline int ip_gma_set(struct parser_exec_state *s,
753                 unsigned long ip_gma)
754 {
755         WARN_ON(!IS_ALIGNED(ip_gma, 4));
756
757         s->ip_gma = ip_gma;
758         update_ip_va(s);
759         return 0;
760 }
761
762 static inline int ip_gma_advance(struct parser_exec_state *s,
763                 unsigned int dw_len)
764 {
765         s->ip_gma += (dw_len << 2);
766
767         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
768                 if (s->ip_gma >= s->ring_start + s->ring_size)
769                         s->ip_gma -= s->ring_size;
770                 update_ip_va(s);
771         } else {
772                 s->ip_va += (dw_len << 2);
773         }
774
775         return 0;
776 }
777
778 static inline int get_cmd_length(struct cmd_info *info, u32 cmd)
779 {
780         if ((info->flag & F_LEN_MASK) == F_LEN_CONST)
781                 return info->len;
782         else
783                 return (cmd & ((1U << info->len) - 1)) + 2;
784         return 0;
785 }
786
787 static inline int cmd_length(struct parser_exec_state *s)
788 {
789         return get_cmd_length(s->info, cmd_val(s, 0));
790 }
791
792 /* do not remove this, some platform may need clflush here */
793 #define patch_value(s, addr, val) do { \
794         *addr = val; \
795 } while (0)
796
797 static bool is_shadowed_mmio(unsigned int offset)
798 {
799         bool ret = false;
800
801         if ((offset == 0x2168) || /*BB current head register UDW */
802             (offset == 0x2140) || /*BB current header register */
803             (offset == 0x211c) || /*second BB header register UDW */
804             (offset == 0x2114)) { /*second BB header register UDW */
805                 ret = true;
806         }
807         return ret;
808 }
809
810 static inline bool is_force_nonpriv_mmio(unsigned int offset)
811 {
812         return (offset >= 0x24d0 && offset < 0x2500);
813 }
814
815 static int force_nonpriv_reg_handler(struct parser_exec_state *s,
816                                      unsigned int offset, unsigned int index)
817 {
818         struct intel_gvt *gvt = s->vgpu->gvt;
819         unsigned int data = cmd_val(s, index + 1);
820         u32 ring_base;
821         u32 nopid;
822         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
823
824         ring_base = dev_priv->engine[s->ring_id]->mmio_base;
825         nopid = i915_mmio_reg_offset(RING_NOPID(ring_base));
826
827         if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data) &&
828                         data != nopid) {
829                 gvt_err("Unexpected forcenonpriv 0x%x LRI write, value=0x%x\n",
830                         offset, data);
831                 return -EPERM;
832         }
833         return 0;
834 }
835
836 static inline bool is_mocs_mmio(unsigned int offset)
837 {
838         return ((offset >= 0xc800) && (offset <= 0xcff8)) ||
839                 ((offset >= 0xb020) && (offset <= 0xb0a0));
840 }
841
842 static int mocs_cmd_reg_handler(struct parser_exec_state *s,
843                                 unsigned int offset, unsigned int index)
844 {
845         if (!is_mocs_mmio(offset))
846                 return -EINVAL;
847         vgpu_vreg(s->vgpu, offset) = cmd_val(s, index + 1);
848         return 0;
849 }
850
851 static int cmd_reg_handler(struct parser_exec_state *s,
852         unsigned int offset, unsigned int index, char *cmd)
853 {
854         struct intel_vgpu *vgpu = s->vgpu;
855         struct intel_gvt *gvt = vgpu->gvt;
856
857         if (offset + 4 > gvt->device_info.mmio_size) {
858                 gvt_vgpu_err("%s access to (%x) outside of MMIO range\n",
859                                 cmd, offset);
860                 return -EFAULT;
861         }
862
863         if (!intel_gvt_mmio_is_cmd_access(gvt, offset)) {
864                 gvt_vgpu_err("%s access to non-render register (%x)\n",
865                                 cmd, offset);
866                 return 0;
867         }
868
869         if (is_shadowed_mmio(offset)) {
870                 gvt_vgpu_err("found access of shadowed MMIO %x\n", offset);
871                 return 0;
872         }
873
874         if (is_mocs_mmio(offset) &&
875             mocs_cmd_reg_handler(s, offset, index))
876                 return -EINVAL;
877
878         if (is_force_nonpriv_mmio(offset) &&
879                 force_nonpriv_reg_handler(s, offset, index))
880                 return -EPERM;
881
882         if (offset == i915_mmio_reg_offset(DERRMR) ||
883                 offset == i915_mmio_reg_offset(FORCEWAKE_MT)) {
884                 /* Writing to HW VGT_PVINFO_PAGE offset will be discarded */
885                 patch_value(s, cmd_ptr(s, index), VGT_PVINFO_PAGE);
886         }
887
888         /* TODO: Update the global mask if this MMIO is a masked-MMIO */
889         intel_gvt_mmio_set_cmd_accessed(gvt, offset);
890         return 0;
891 }
892
893 #define cmd_reg(s, i) \
894         (cmd_val(s, i) & GENMASK(22, 2))
895
896 #define cmd_reg_inhibit(s, i) \
897         (cmd_val(s, i) & GENMASK(22, 18))
898
899 #define cmd_gma(s, i) \
900         (cmd_val(s, i) & GENMASK(31, 2))
901
902 #define cmd_gma_hi(s, i) \
903         (cmd_val(s, i) & GENMASK(15, 0))
904
905 static int cmd_handler_lri(struct parser_exec_state *s)
906 {
907         int i, ret = 0;
908         int cmd_len = cmd_length(s);
909         struct intel_gvt *gvt = s->vgpu->gvt;
910
911         for (i = 1; i < cmd_len; i += 2) {
912                 if (IS_BROADWELL(gvt->dev_priv) &&
913                                 (s->ring_id != RCS)) {
914                         if (s->ring_id == BCS &&
915                                         cmd_reg(s, i) ==
916                                         i915_mmio_reg_offset(DERRMR))
917                                 ret |= 0;
918                         else
919                                 ret |= (cmd_reg_inhibit(s, i)) ?
920                                         -EBADRQC : 0;
921                 }
922                 if (ret)
923                         break;
924                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lri");
925                 if (ret)
926                         break;
927         }
928         return ret;
929 }
930
931 static int cmd_handler_lrr(struct parser_exec_state *s)
932 {
933         int i, ret = 0;
934         int cmd_len = cmd_length(s);
935
936         for (i = 1; i < cmd_len; i += 2) {
937                 if (IS_BROADWELL(s->vgpu->gvt->dev_priv))
938                         ret |= ((cmd_reg_inhibit(s, i) ||
939                                         (cmd_reg_inhibit(s, i + 1)))) ?
940                                 -EBADRQC : 0;
941                 if (ret)
942                         break;
943                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrr-src");
944                 if (ret)
945                         break;
946                 ret |= cmd_reg_handler(s, cmd_reg(s, i + 1), i, "lrr-dst");
947                 if (ret)
948                         break;
949         }
950         return ret;
951 }
952
953 static inline int cmd_address_audit(struct parser_exec_state *s,
954                 unsigned long guest_gma, int op_size, bool index_mode);
955
956 static int cmd_handler_lrm(struct parser_exec_state *s)
957 {
958         struct intel_gvt *gvt = s->vgpu->gvt;
959         int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
960         unsigned long gma;
961         int i, ret = 0;
962         int cmd_len = cmd_length(s);
963
964         for (i = 1; i < cmd_len;) {
965                 if (IS_BROADWELL(gvt->dev_priv))
966                         ret |= (cmd_reg_inhibit(s, i)) ? -EBADRQC : 0;
967                 if (ret)
968                         break;
969                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrm");
970                 if (ret)
971                         break;
972                 if (cmd_val(s, 0) & (1 << 22)) {
973                         gma = cmd_gma(s, i + 1);
974                         if (gmadr_bytes == 8)
975                                 gma |= (cmd_gma_hi(s, i + 2)) << 32;
976                         ret |= cmd_address_audit(s, gma, sizeof(u32), false);
977                         if (ret)
978                                 break;
979                 }
980                 i += gmadr_dw_number(s) + 1;
981         }
982         return ret;
983 }
984
985 static int cmd_handler_srm(struct parser_exec_state *s)
986 {
987         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
988         unsigned long gma;
989         int i, ret = 0;
990         int cmd_len = cmd_length(s);
991
992         for (i = 1; i < cmd_len;) {
993                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "srm");
994                 if (ret)
995                         break;
996                 if (cmd_val(s, 0) & (1 << 22)) {
997                         gma = cmd_gma(s, i + 1);
998                         if (gmadr_bytes == 8)
999                                 gma |= (cmd_gma_hi(s, i + 2)) << 32;
1000                         ret |= cmd_address_audit(s, gma, sizeof(u32), false);
1001                         if (ret)
1002                                 break;
1003                 }
1004                 i += gmadr_dw_number(s) + 1;
1005         }
1006         return ret;
1007 }
1008
1009 struct cmd_interrupt_event {
1010         int pipe_control_notify;
1011         int mi_flush_dw;
1012         int mi_user_interrupt;
1013 };
1014
1015 static struct cmd_interrupt_event cmd_interrupt_events[] = {
1016         [RCS] = {
1017                 .pipe_control_notify = RCS_PIPE_CONTROL,
1018                 .mi_flush_dw = INTEL_GVT_EVENT_RESERVED,
1019                 .mi_user_interrupt = RCS_MI_USER_INTERRUPT,
1020         },
1021         [BCS] = {
1022                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1023                 .mi_flush_dw = BCS_MI_FLUSH_DW,
1024                 .mi_user_interrupt = BCS_MI_USER_INTERRUPT,
1025         },
1026         [VCS] = {
1027                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1028                 .mi_flush_dw = VCS_MI_FLUSH_DW,
1029                 .mi_user_interrupt = VCS_MI_USER_INTERRUPT,
1030         },
1031         [VCS2] = {
1032                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1033                 .mi_flush_dw = VCS2_MI_FLUSH_DW,
1034                 .mi_user_interrupt = VCS2_MI_USER_INTERRUPT,
1035         },
1036         [VECS] = {
1037                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1038                 .mi_flush_dw = VECS_MI_FLUSH_DW,
1039                 .mi_user_interrupt = VECS_MI_USER_INTERRUPT,
1040         },
1041 };
1042
1043 static int cmd_handler_pipe_control(struct parser_exec_state *s)
1044 {
1045         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1046         unsigned long gma;
1047         bool index_mode = false;
1048         unsigned int post_sync;
1049         int ret = 0;
1050
1051         post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14;
1052
1053         /* LRI post sync */
1054         if (cmd_val(s, 1) & PIPE_CONTROL_MMIO_WRITE)
1055                 ret = cmd_reg_handler(s, cmd_reg(s, 2), 1, "pipe_ctrl");
1056         /* post sync */
1057         else if (post_sync) {
1058                 if (post_sync == 2)
1059                         ret = cmd_reg_handler(s, 0x2350, 1, "pipe_ctrl");
1060                 else if (post_sync == 3)
1061                         ret = cmd_reg_handler(s, 0x2358, 1, "pipe_ctrl");
1062                 else if (post_sync == 1) {
1063                         /* check ggtt*/
1064                         if ((cmd_val(s, 1) & PIPE_CONTROL_GLOBAL_GTT_IVB)) {
1065                                 gma = cmd_val(s, 2) & GENMASK(31, 3);
1066                                 if (gmadr_bytes == 8)
1067                                         gma |= (cmd_gma_hi(s, 3)) << 32;
1068                                 /* Store Data Index */
1069                                 if (cmd_val(s, 1) & (1 << 21))
1070                                         index_mode = true;
1071                                 ret |= cmd_address_audit(s, gma, sizeof(u64),
1072                                                 index_mode);
1073                         }
1074                 }
1075         }
1076
1077         if (ret)
1078                 return ret;
1079
1080         if (cmd_val(s, 1) & PIPE_CONTROL_NOTIFY)
1081                 set_bit(cmd_interrupt_events[s->ring_id].pipe_control_notify,
1082                                 s->workload->pending_events);
1083         return 0;
1084 }
1085
1086 static int cmd_handler_mi_user_interrupt(struct parser_exec_state *s)
1087 {
1088         set_bit(cmd_interrupt_events[s->ring_id].mi_user_interrupt,
1089                         s->workload->pending_events);
1090         return 0;
1091 }
1092
1093 static int cmd_advance_default(struct parser_exec_state *s)
1094 {
1095         return ip_gma_advance(s, cmd_length(s));
1096 }
1097
1098 static int cmd_handler_mi_batch_buffer_end(struct parser_exec_state *s)
1099 {
1100         int ret;
1101
1102         if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1103                 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1104                 ret = ip_gma_set(s, s->ret_ip_gma_bb);
1105                 s->buf_addr_type = s->saved_buf_addr_type;
1106         } else {
1107                 s->buf_type = RING_BUFFER_INSTRUCTION;
1108                 s->buf_addr_type = GTT_BUFFER;
1109                 if (s->ret_ip_gma_ring >= s->ring_start + s->ring_size)
1110                         s->ret_ip_gma_ring -= s->ring_size;
1111                 ret = ip_gma_set(s, s->ret_ip_gma_ring);
1112         }
1113         return ret;
1114 }
1115
1116 struct mi_display_flip_command_info {
1117         int pipe;
1118         int plane;
1119         int event;
1120         i915_reg_t stride_reg;
1121         i915_reg_t ctrl_reg;
1122         i915_reg_t surf_reg;
1123         u64 stride_val;
1124         u64 tile_val;
1125         u64 surf_val;
1126         bool async_flip;
1127 };
1128
1129 struct plane_code_mapping {
1130         int pipe;
1131         int plane;
1132         int event;
1133 };
1134
1135 static int gen8_decode_mi_display_flip(struct parser_exec_state *s,
1136                 struct mi_display_flip_command_info *info)
1137 {
1138         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1139         struct plane_code_mapping gen8_plane_code[] = {
1140                 [0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE},
1141                 [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE},
1142                 [2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE},
1143                 [3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE},
1144                 [4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE},
1145                 [5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE},
1146         };
1147         u32 dword0, dword1, dword2;
1148         u32 v;
1149
1150         dword0 = cmd_val(s, 0);
1151         dword1 = cmd_val(s, 1);
1152         dword2 = cmd_val(s, 2);
1153
1154         v = (dword0 & GENMASK(21, 19)) >> 19;
1155         if (WARN_ON(v >= ARRAY_SIZE(gen8_plane_code)))
1156                 return -EBADRQC;
1157
1158         info->pipe = gen8_plane_code[v].pipe;
1159         info->plane = gen8_plane_code[v].plane;
1160         info->event = gen8_plane_code[v].event;
1161         info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1162         info->tile_val = (dword1 & 0x1);
1163         info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1164         info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1165
1166         if (info->plane == PLANE_A) {
1167                 info->ctrl_reg = DSPCNTR(info->pipe);
1168                 info->stride_reg = DSPSTRIDE(info->pipe);
1169                 info->surf_reg = DSPSURF(info->pipe);
1170         } else if (info->plane == PLANE_B) {
1171                 info->ctrl_reg = SPRCTL(info->pipe);
1172                 info->stride_reg = SPRSTRIDE(info->pipe);
1173                 info->surf_reg = SPRSURF(info->pipe);
1174         } else {
1175                 WARN_ON(1);
1176                 return -EBADRQC;
1177         }
1178         return 0;
1179 }
1180
1181 static int skl_decode_mi_display_flip(struct parser_exec_state *s,
1182                 struct mi_display_flip_command_info *info)
1183 {
1184         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1185         struct intel_vgpu *vgpu = s->vgpu;
1186         u32 dword0 = cmd_val(s, 0);
1187         u32 dword1 = cmd_val(s, 1);
1188         u32 dword2 = cmd_val(s, 2);
1189         u32 plane = (dword0 & GENMASK(12, 8)) >> 8;
1190
1191         info->plane = PRIMARY_PLANE;
1192
1193         switch (plane) {
1194         case MI_DISPLAY_FLIP_SKL_PLANE_1_A:
1195                 info->pipe = PIPE_A;
1196                 info->event = PRIMARY_A_FLIP_DONE;
1197                 break;
1198         case MI_DISPLAY_FLIP_SKL_PLANE_1_B:
1199                 info->pipe = PIPE_B;
1200                 info->event = PRIMARY_B_FLIP_DONE;
1201                 break;
1202         case MI_DISPLAY_FLIP_SKL_PLANE_1_C:
1203                 info->pipe = PIPE_C;
1204                 info->event = PRIMARY_C_FLIP_DONE;
1205                 break;
1206
1207         case MI_DISPLAY_FLIP_SKL_PLANE_2_A:
1208                 info->pipe = PIPE_A;
1209                 info->event = SPRITE_A_FLIP_DONE;
1210                 info->plane = SPRITE_PLANE;
1211                 break;
1212         case MI_DISPLAY_FLIP_SKL_PLANE_2_B:
1213                 info->pipe = PIPE_B;
1214                 info->event = SPRITE_B_FLIP_DONE;
1215                 info->plane = SPRITE_PLANE;
1216                 break;
1217         case MI_DISPLAY_FLIP_SKL_PLANE_2_C:
1218                 info->pipe = PIPE_C;
1219                 info->event = SPRITE_C_FLIP_DONE;
1220                 info->plane = SPRITE_PLANE;
1221                 break;
1222
1223         default:
1224                 gvt_vgpu_err("unknown plane code %d\n", plane);
1225                 return -EBADRQC;
1226         }
1227
1228         info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1229         info->tile_val = (dword1 & GENMASK(2, 0));
1230         info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1231         info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1232
1233         info->ctrl_reg = DSPCNTR(info->pipe);
1234         info->stride_reg = DSPSTRIDE(info->pipe);
1235         info->surf_reg = DSPSURF(info->pipe);
1236
1237         return 0;
1238 }
1239
1240 static int gen8_check_mi_display_flip(struct parser_exec_state *s,
1241                 struct mi_display_flip_command_info *info)
1242 {
1243         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1244         u32 stride, tile;
1245
1246         if (!info->async_flip)
1247                 return 0;
1248
1249         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1250                 stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);
1251                 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &
1252                                 GENMASK(12, 10)) >> 10;
1253         } else {
1254                 stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) &
1255                                 GENMASK(15, 6)) >> 6;
1256                 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;
1257         }
1258
1259         if (stride != info->stride_val)
1260                 gvt_dbg_cmd("cannot change stride during async flip\n");
1261
1262         if (tile != info->tile_val)
1263                 gvt_dbg_cmd("cannot change tile during async flip\n");
1264
1265         return 0;
1266 }
1267
1268 static int gen8_update_plane_mmio_from_mi_display_flip(
1269                 struct parser_exec_state *s,
1270                 struct mi_display_flip_command_info *info)
1271 {
1272         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1273         struct intel_vgpu *vgpu = s->vgpu;
1274
1275         set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),
1276                       info->surf_val << 12);
1277         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1278                 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),
1279                               info->stride_val);
1280                 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),
1281                               info->tile_val << 10);
1282         } else {
1283                 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6),
1284                               info->stride_val << 6);
1285                 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),
1286                               info->tile_val << 10);
1287         }
1288
1289         vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(info->pipe))++;
1290         intel_vgpu_trigger_virtual_event(vgpu, info->event);
1291         return 0;
1292 }
1293
1294 static int decode_mi_display_flip(struct parser_exec_state *s,
1295                 struct mi_display_flip_command_info *info)
1296 {
1297         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1298
1299         if (IS_BROADWELL(dev_priv))
1300                 return gen8_decode_mi_display_flip(s, info);
1301         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
1302                 return skl_decode_mi_display_flip(s, info);
1303
1304         return -ENODEV;
1305 }
1306
1307 static int check_mi_display_flip(struct parser_exec_state *s,
1308                 struct mi_display_flip_command_info *info)
1309 {
1310         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1311
1312         if (IS_BROADWELL(dev_priv)
1313                 || IS_SKYLAKE(dev_priv)
1314                 || IS_KABYLAKE(dev_priv))
1315                 return gen8_check_mi_display_flip(s, info);
1316         return -ENODEV;
1317 }
1318
1319 static int update_plane_mmio_from_mi_display_flip(
1320                 struct parser_exec_state *s,
1321                 struct mi_display_flip_command_info *info)
1322 {
1323         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1324
1325         if (IS_BROADWELL(dev_priv)
1326                 || IS_SKYLAKE(dev_priv)
1327                 || IS_KABYLAKE(dev_priv))
1328                 return gen8_update_plane_mmio_from_mi_display_flip(s, info);
1329         return -ENODEV;
1330 }
1331
1332 static int cmd_handler_mi_display_flip(struct parser_exec_state *s)
1333 {
1334         struct mi_display_flip_command_info info;
1335         struct intel_vgpu *vgpu = s->vgpu;
1336         int ret;
1337         int i;
1338         int len = cmd_length(s);
1339
1340         ret = decode_mi_display_flip(s, &info);
1341         if (ret) {
1342                 gvt_vgpu_err("fail to decode MI display flip command\n");
1343                 return ret;
1344         }
1345
1346         ret = check_mi_display_flip(s, &info);
1347         if (ret) {
1348                 gvt_vgpu_err("invalid MI display flip command\n");
1349                 return ret;
1350         }
1351
1352         ret = update_plane_mmio_from_mi_display_flip(s, &info);
1353         if (ret) {
1354                 gvt_vgpu_err("fail to update plane mmio\n");
1355                 return ret;
1356         }
1357
1358         for (i = 0; i < len; i++)
1359                 patch_value(s, cmd_ptr(s, i), MI_NOOP);
1360         return 0;
1361 }
1362
1363 static bool is_wait_for_flip_pending(u32 cmd)
1364 {
1365         return cmd & (MI_WAIT_FOR_PLANE_A_FLIP_PENDING |
1366                         MI_WAIT_FOR_PLANE_B_FLIP_PENDING |
1367                         MI_WAIT_FOR_PLANE_C_FLIP_PENDING |
1368                         MI_WAIT_FOR_SPRITE_A_FLIP_PENDING |
1369                         MI_WAIT_FOR_SPRITE_B_FLIP_PENDING |
1370                         MI_WAIT_FOR_SPRITE_C_FLIP_PENDING);
1371 }
1372
1373 static int cmd_handler_mi_wait_for_event(struct parser_exec_state *s)
1374 {
1375         u32 cmd = cmd_val(s, 0);
1376
1377         if (!is_wait_for_flip_pending(cmd))
1378                 return 0;
1379
1380         patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1381         return 0;
1382 }
1383
1384 static unsigned long get_gma_bb_from_cmd(struct parser_exec_state *s, int index)
1385 {
1386         unsigned long addr;
1387         unsigned long gma_high, gma_low;
1388         struct intel_vgpu *vgpu = s->vgpu;
1389         int gmadr_bytes = vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1390
1391         if (WARN_ON(gmadr_bytes != 4 && gmadr_bytes != 8)) {
1392                 gvt_vgpu_err("invalid gma bytes %d\n", gmadr_bytes);
1393                 return INTEL_GVT_INVALID_ADDR;
1394         }
1395
1396         gma_low = cmd_val(s, index) & BATCH_BUFFER_ADDR_MASK;
1397         if (gmadr_bytes == 4) {
1398                 addr = gma_low;
1399         } else {
1400                 gma_high = cmd_val(s, index + 1) & BATCH_BUFFER_ADDR_HIGH_MASK;
1401                 addr = (((unsigned long)gma_high) << 32) | gma_low;
1402         }
1403         return addr;
1404 }
1405
1406 static inline int cmd_address_audit(struct parser_exec_state *s,
1407                 unsigned long guest_gma, int op_size, bool index_mode)
1408 {
1409         struct intel_vgpu *vgpu = s->vgpu;
1410         u32 max_surface_size = vgpu->gvt->device_info.max_surface_size;
1411         int i;
1412         int ret;
1413
1414         if (op_size > max_surface_size) {
1415                 gvt_vgpu_err("command address audit fail name %s\n",
1416                         s->info->name);
1417                 return -EFAULT;
1418         }
1419
1420         if (index_mode) {
1421                 if (guest_gma >= I915_GTT_PAGE_SIZE / sizeof(u64)) {
1422                         ret = -EFAULT;
1423                         goto err;
1424                 }
1425         } else if (!intel_gvt_ggtt_validate_range(vgpu, guest_gma, op_size)) {
1426                 ret = -EFAULT;
1427                 goto err;
1428         }
1429
1430         return 0;
1431
1432 err:
1433         gvt_vgpu_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n",
1434                         s->info->name, guest_gma, op_size);
1435
1436         pr_err("cmd dump: ");
1437         for (i = 0; i < cmd_length(s); i++) {
1438                 if (!(i % 4))
1439                         pr_err("\n%08x ", cmd_val(s, i));
1440                 else
1441                         pr_err("%08x ", cmd_val(s, i));
1442         }
1443         pr_err("\nvgpu%d: aperture 0x%llx - 0x%llx, hidden 0x%llx - 0x%llx\n",
1444                         vgpu->id,
1445                         vgpu_aperture_gmadr_base(vgpu),
1446                         vgpu_aperture_gmadr_end(vgpu),
1447                         vgpu_hidden_gmadr_base(vgpu),
1448                         vgpu_hidden_gmadr_end(vgpu));
1449         return ret;
1450 }
1451
1452 static int cmd_handler_mi_store_data_imm(struct parser_exec_state *s)
1453 {
1454         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1455         int op_size = (cmd_length(s) - 3) * sizeof(u32);
1456         int core_id = (cmd_val(s, 2) & (1 << 0)) ? 1 : 0;
1457         unsigned long gma, gma_low, gma_high;
1458         int ret = 0;
1459
1460         /* check ppggt */
1461         if (!(cmd_val(s, 0) & (1 << 22)))
1462                 return 0;
1463
1464         gma = cmd_val(s, 2) & GENMASK(31, 2);
1465
1466         if (gmadr_bytes == 8) {
1467                 gma_low = cmd_val(s, 1) & GENMASK(31, 2);
1468                 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1469                 gma = (gma_high << 32) | gma_low;
1470                 core_id = (cmd_val(s, 1) & (1 << 0)) ? 1 : 0;
1471         }
1472         ret = cmd_address_audit(s, gma + op_size * core_id, op_size, false);
1473         return ret;
1474 }
1475
1476 static inline int unexpected_cmd(struct parser_exec_state *s)
1477 {
1478         struct intel_vgpu *vgpu = s->vgpu;
1479
1480         gvt_vgpu_err("Unexpected %s in command buffer!\n", s->info->name);
1481
1482         return -EBADRQC;
1483 }
1484
1485 static int cmd_handler_mi_semaphore_wait(struct parser_exec_state *s)
1486 {
1487         return unexpected_cmd(s);
1488 }
1489
1490 static int cmd_handler_mi_report_perf_count(struct parser_exec_state *s)
1491 {
1492         return unexpected_cmd(s);
1493 }
1494
1495 static int cmd_handler_mi_op_2e(struct parser_exec_state *s)
1496 {
1497         return unexpected_cmd(s);
1498 }
1499
1500 static int cmd_handler_mi_op_2f(struct parser_exec_state *s)
1501 {
1502         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1503         int op_size = (1 << ((cmd_val(s, 0) & GENMASK(20, 19)) >> 19)) *
1504                         sizeof(u32);
1505         unsigned long gma, gma_high;
1506         int ret = 0;
1507
1508         if (!(cmd_val(s, 0) & (1 << 22)))
1509                 return ret;
1510
1511         gma = cmd_val(s, 1) & GENMASK(31, 2);
1512         if (gmadr_bytes == 8) {
1513                 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1514                 gma = (gma_high << 32) | gma;
1515         }
1516         ret = cmd_address_audit(s, gma, op_size, false);
1517         return ret;
1518 }
1519
1520 static int cmd_handler_mi_store_data_index(struct parser_exec_state *s)
1521 {
1522         return unexpected_cmd(s);
1523 }
1524
1525 static int cmd_handler_mi_clflush(struct parser_exec_state *s)
1526 {
1527         return unexpected_cmd(s);
1528 }
1529
1530 static int cmd_handler_mi_conditional_batch_buffer_end(
1531                 struct parser_exec_state *s)
1532 {
1533         return unexpected_cmd(s);
1534 }
1535
1536 static int cmd_handler_mi_update_gtt(struct parser_exec_state *s)
1537 {
1538         return unexpected_cmd(s);
1539 }
1540
1541 static int cmd_handler_mi_flush_dw(struct parser_exec_state *s)
1542 {
1543         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1544         unsigned long gma;
1545         bool index_mode = false;
1546         int ret = 0;
1547
1548         /* Check post-sync and ppgtt bit */
1549         if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) {
1550                 gma = cmd_val(s, 1) & GENMASK(31, 3);
1551                 if (gmadr_bytes == 8)
1552                         gma |= (cmd_val(s, 2) & GENMASK(15, 0)) << 32;
1553                 /* Store Data Index */
1554                 if (cmd_val(s, 0) & (1 << 21))
1555                         index_mode = true;
1556                 ret = cmd_address_audit(s, gma, sizeof(u64), index_mode);
1557         }
1558         /* Check notify bit */
1559         if ((cmd_val(s, 0) & (1 << 8)))
1560                 set_bit(cmd_interrupt_events[s->ring_id].mi_flush_dw,
1561                                 s->workload->pending_events);
1562         return ret;
1563 }
1564
1565 static void addr_type_update_snb(struct parser_exec_state *s)
1566 {
1567         if ((s->buf_type == RING_BUFFER_INSTRUCTION) &&
1568                         (BATCH_BUFFER_ADR_SPACE_BIT(cmd_val(s, 0)) == 1)) {
1569                 s->buf_addr_type = PPGTT_BUFFER;
1570         }
1571 }
1572
1573
1574 static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm,
1575                 unsigned long gma, unsigned long end_gma, void *va)
1576 {
1577         unsigned long copy_len, offset;
1578         unsigned long len = 0;
1579         unsigned long gpa;
1580
1581         while (gma != end_gma) {
1582                 gpa = intel_vgpu_gma_to_gpa(mm, gma);
1583                 if (gpa == INTEL_GVT_INVALID_ADDR) {
1584                         gvt_vgpu_err("invalid gma address: %lx\n", gma);
1585                         return -EFAULT;
1586                 }
1587
1588                 offset = gma & (I915_GTT_PAGE_SIZE - 1);
1589
1590                 copy_len = (end_gma - gma) >= (I915_GTT_PAGE_SIZE - offset) ?
1591                         I915_GTT_PAGE_SIZE - offset : end_gma - gma;
1592
1593                 intel_gvt_hypervisor_read_gpa(vgpu, gpa, va + len, copy_len);
1594
1595                 len += copy_len;
1596                 gma += copy_len;
1597         }
1598         return len;
1599 }
1600
1601
1602 /*
1603  * Check whether a batch buffer needs to be scanned. Currently
1604  * the only criteria is based on privilege.
1605  */
1606 static int batch_buffer_needs_scan(struct parser_exec_state *s)
1607 {
1608         struct intel_gvt *gvt = s->vgpu->gvt;
1609
1610         if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)
1611                 || IS_KABYLAKE(gvt->dev_priv)) {
1612                 /* BDW decides privilege based on address space */
1613                 if (cmd_val(s, 0) & (1 << 8) &&
1614                         !(s->vgpu->scan_nonprivbb & (1 << s->ring_id)))
1615                         return 0;
1616         }
1617         return 1;
1618 }
1619
1620 static int find_bb_size(struct parser_exec_state *s, unsigned long *bb_size)
1621 {
1622         unsigned long gma = 0;
1623         struct cmd_info *info;
1624         uint32_t cmd_len = 0;
1625         bool bb_end = false;
1626         struct intel_vgpu *vgpu = s->vgpu;
1627         u32 cmd;
1628         struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1629                 s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1630
1631         *bb_size = 0;
1632
1633         /* get the start gm address of the batch buffer */
1634         gma = get_gma_bb_from_cmd(s, 1);
1635         if (gma == INTEL_GVT_INVALID_ADDR)
1636                 return -EFAULT;
1637
1638         cmd = cmd_val(s, 0);
1639         info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
1640         if (info == NULL) {
1641                 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",
1642                                 cmd, get_opcode(cmd, s->ring_id),
1643                                 (s->buf_addr_type == PPGTT_BUFFER) ?
1644                                 "ppgtt" : "ggtt", s->ring_id, s->workload);
1645                 return -EBADRQC;
1646         }
1647         do {
1648                 if (copy_gma_to_hva(s->vgpu, mm,
1649                                 gma, gma + 4, &cmd) < 0)
1650                         return -EFAULT;
1651                 info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
1652                 if (info == NULL) {
1653                         gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",
1654                                 cmd, get_opcode(cmd, s->ring_id),
1655                                 (s->buf_addr_type == PPGTT_BUFFER) ?
1656                                 "ppgtt" : "ggtt", s->ring_id, s->workload);
1657                         return -EBADRQC;
1658                 }
1659
1660                 if (info->opcode == OP_MI_BATCH_BUFFER_END) {
1661                         bb_end = true;
1662                 } else if (info->opcode == OP_MI_BATCH_BUFFER_START) {
1663                         if (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0)
1664                                 /* chained batch buffer */
1665                                 bb_end = true;
1666                 }
1667                 cmd_len = get_cmd_length(info, cmd) << 2;
1668                 *bb_size += cmd_len;
1669                 gma += cmd_len;
1670         } while (!bb_end);
1671
1672         return 0;
1673 }
1674
1675 static int perform_bb_shadow(struct parser_exec_state *s)
1676 {
1677         struct intel_vgpu *vgpu = s->vgpu;
1678         struct intel_vgpu_shadow_bb *bb;
1679         unsigned long gma = 0;
1680         unsigned long bb_size;
1681         int ret = 0;
1682         struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1683                 s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1684         unsigned long gma_start_offset = 0;
1685
1686         /* get the start gm address of the batch buffer */
1687         gma = get_gma_bb_from_cmd(s, 1);
1688         if (gma == INTEL_GVT_INVALID_ADDR)
1689                 return -EFAULT;
1690
1691         ret = find_bb_size(s, &bb_size);
1692         if (ret)
1693                 return ret;
1694
1695         bb = kzalloc(sizeof(*bb), GFP_KERNEL);
1696         if (!bb)
1697                 return -ENOMEM;
1698
1699         bb->ppgtt = (s->buf_addr_type == GTT_BUFFER) ? false : true;
1700
1701         /* the gma_start_offset stores the batch buffer's start gma's
1702          * offset relative to page boundary. so for non-privileged batch
1703          * buffer, the shadowed gem object holds exactly the same page
1704          * layout as original gem object. This is for the convience of
1705          * replacing the whole non-privilged batch buffer page to this
1706          * shadowed one in PPGTT at the same gma address. (this replacing
1707          * action is not implemented yet now, but may be necessary in
1708          * future).
1709          * for prileged batch buffer, we just change start gma address to
1710          * that of shadowed page.
1711          */
1712         if (bb->ppgtt)
1713                 gma_start_offset = gma & ~I915_GTT_PAGE_MASK;
1714
1715         bb->obj = i915_gem_object_create(s->vgpu->gvt->dev_priv,
1716                          roundup(bb_size + gma_start_offset, PAGE_SIZE));
1717         if (IS_ERR(bb->obj)) {
1718                 ret = PTR_ERR(bb->obj);
1719                 goto err_free_bb;
1720         }
1721
1722         ret = i915_gem_obj_prepare_shmem_write(bb->obj, &bb->clflush);
1723         if (ret)
1724                 goto err_free_obj;
1725
1726         bb->va = i915_gem_object_pin_map(bb->obj, I915_MAP_WB);
1727         if (IS_ERR(bb->va)) {
1728                 ret = PTR_ERR(bb->va);
1729                 goto err_finish_shmem_access;
1730         }
1731
1732         if (bb->clflush & CLFLUSH_BEFORE) {
1733                 drm_clflush_virt_range(bb->va, bb->obj->base.size);
1734                 bb->clflush &= ~CLFLUSH_BEFORE;
1735         }
1736
1737         ret = copy_gma_to_hva(s->vgpu, mm,
1738                               gma, gma + bb_size,
1739                               bb->va + gma_start_offset);
1740         if (ret < 0) {
1741                 gvt_vgpu_err("fail to copy guest ring buffer\n");
1742                 ret = -EFAULT;
1743                 goto err_unmap;
1744         }
1745
1746         INIT_LIST_HEAD(&bb->list);
1747         list_add(&bb->list, &s->workload->shadow_bb);
1748
1749         bb->accessing = true;
1750         bb->bb_start_cmd_va = s->ip_va;
1751
1752         if ((s->buf_type == BATCH_BUFFER_INSTRUCTION) && (!s->is_ctx_wa))
1753                 bb->bb_offset = s->ip_va - s->rb_va;
1754         else
1755                 bb->bb_offset = 0;
1756
1757         /*
1758          * ip_va saves the virtual address of the shadow batch buffer, while
1759          * ip_gma saves the graphics address of the original batch buffer.
1760          * As the shadow batch buffer is just a copy from the originial one,
1761          * it should be right to use shadow batch buffer'va and original batch
1762          * buffer's gma in pair. After all, we don't want to pin the shadow
1763          * buffer here (too early).
1764          */
1765         s->ip_va = bb->va + gma_start_offset;
1766         s->ip_gma = gma;
1767         return 0;
1768 err_unmap:
1769         i915_gem_object_unpin_map(bb->obj);
1770 err_finish_shmem_access:
1771         i915_gem_obj_finish_shmem_access(bb->obj);
1772 err_free_obj:
1773         i915_gem_object_put(bb->obj);
1774 err_free_bb:
1775         kfree(bb);
1776         return ret;
1777 }
1778
1779 static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s)
1780 {
1781         bool second_level;
1782         int ret = 0;
1783         struct intel_vgpu *vgpu = s->vgpu;
1784
1785         if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1786                 gvt_vgpu_err("Found MI_BATCH_BUFFER_START in 2nd level BB\n");
1787                 return -EFAULT;
1788         }
1789
1790         second_level = BATCH_BUFFER_2ND_LEVEL_BIT(cmd_val(s, 0)) == 1;
1791         if (second_level && (s->buf_type != BATCH_BUFFER_INSTRUCTION)) {
1792                 gvt_vgpu_err("Jumping to 2nd level BB from RB is not allowed\n");
1793                 return -EFAULT;
1794         }
1795
1796         s->saved_buf_addr_type = s->buf_addr_type;
1797         addr_type_update_snb(s);
1798         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
1799                 s->ret_ip_gma_ring = s->ip_gma + cmd_length(s) * sizeof(u32);
1800                 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1801         } else if (second_level) {
1802                 s->buf_type = BATCH_BUFFER_2ND_LEVEL;
1803                 s->ret_ip_gma_bb = s->ip_gma + cmd_length(s) * sizeof(u32);
1804                 s->ret_bb_va = s->ip_va + cmd_length(s) * sizeof(u32);
1805         }
1806
1807         if (batch_buffer_needs_scan(s)) {
1808                 ret = perform_bb_shadow(s);
1809                 if (ret < 0)
1810                         gvt_vgpu_err("invalid shadow batch buffer\n");
1811         } else {
1812                 /* emulate a batch buffer end to do return right */
1813                 ret = cmd_handler_mi_batch_buffer_end(s);
1814                 if (ret < 0)
1815                         return ret;
1816         }
1817         return ret;
1818 }
1819
1820 static struct cmd_info cmd_info[] = {
1821         {"MI_NOOP", OP_MI_NOOP, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
1822
1823         {"MI_SET_PREDICATE", OP_MI_SET_PREDICATE, F_LEN_CONST, R_ALL, D_ALL,
1824                 0, 1, NULL},
1825
1826         {"MI_USER_INTERRUPT", OP_MI_USER_INTERRUPT, F_LEN_CONST, R_ALL, D_ALL,
1827                 0, 1, cmd_handler_mi_user_interrupt},
1828
1829         {"MI_WAIT_FOR_EVENT", OP_MI_WAIT_FOR_EVENT, F_LEN_CONST, R_RCS | R_BCS,
1830                 D_ALL, 0, 1, cmd_handler_mi_wait_for_event},
1831
1832         {"MI_FLUSH", OP_MI_FLUSH, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
1833
1834         {"MI_ARB_CHECK", OP_MI_ARB_CHECK, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1835                 NULL},
1836
1837         {"MI_RS_CONTROL", OP_MI_RS_CONTROL, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1838                 NULL},
1839
1840         {"MI_REPORT_HEAD", OP_MI_REPORT_HEAD, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1841                 NULL},
1842
1843         {"MI_ARB_ON_OFF", OP_MI_ARB_ON_OFF, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1844                 NULL},
1845
1846         {"MI_URB_ATOMIC_ALLOC", OP_MI_URB_ATOMIC_ALLOC, F_LEN_CONST, R_RCS,
1847                 D_ALL, 0, 1, NULL},
1848
1849         {"MI_BATCH_BUFFER_END", OP_MI_BATCH_BUFFER_END,
1850                 F_IP_ADVANCE_CUSTOM | F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1851                 cmd_handler_mi_batch_buffer_end},
1852
1853         {"MI_SUSPEND_FLUSH", OP_MI_SUSPEND_FLUSH, F_LEN_CONST, R_ALL, D_ALL,
1854                 0, 1, NULL},
1855
1856         {"MI_PREDICATE", OP_MI_PREDICATE, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1857                 NULL},
1858
1859         {"MI_TOPOLOGY_FILTER", OP_MI_TOPOLOGY_FILTER, F_LEN_CONST, R_ALL,
1860                 D_ALL, 0, 1, NULL},
1861
1862         {"MI_SET_APPID", OP_MI_SET_APPID, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1863                 NULL},
1864
1865         {"MI_RS_CONTEXT", OP_MI_RS_CONTEXT, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1866                 NULL},
1867
1868         {"MI_DISPLAY_FLIP", OP_MI_DISPLAY_FLIP, F_LEN_VAR | F_POST_HANDLE,
1869                 R_RCS | R_BCS, D_ALL, 0, 8, cmd_handler_mi_display_flip},
1870
1871         {"MI_SEMAPHORE_MBOX", OP_MI_SEMAPHORE_MBOX, F_LEN_VAR, R_ALL, D_ALL,
1872                 0, 8, NULL},
1873
1874         {"MI_MATH", OP_MI_MATH, F_LEN_VAR, R_ALL, D_ALL, 0, 8, NULL},
1875
1876         {"MI_URB_CLEAR", OP_MI_URB_CLEAR, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1877
1878         {"ME_SEMAPHORE_SIGNAL", OP_MI_SEMAPHORE_SIGNAL, F_LEN_VAR, R_ALL,
1879                 D_BDW_PLUS, 0, 8, NULL},
1880
1881         {"ME_SEMAPHORE_WAIT", OP_MI_SEMAPHORE_WAIT, F_LEN_VAR, R_ALL, D_BDW_PLUS,
1882                 ADDR_FIX_1(2), 8, cmd_handler_mi_semaphore_wait},
1883
1884         {"MI_STORE_DATA_IMM", OP_MI_STORE_DATA_IMM, F_LEN_VAR, R_ALL, D_BDW_PLUS,
1885                 ADDR_FIX_1(1), 10, cmd_handler_mi_store_data_imm},
1886
1887         {"MI_STORE_DATA_INDEX", OP_MI_STORE_DATA_INDEX, F_LEN_VAR, R_ALL, D_ALL,
1888                 0, 8, cmd_handler_mi_store_data_index},
1889
1890         {"MI_LOAD_REGISTER_IMM", OP_MI_LOAD_REGISTER_IMM, F_LEN_VAR, R_ALL,
1891                 D_ALL, 0, 8, cmd_handler_lri},
1892
1893         {"MI_UPDATE_GTT", OP_MI_UPDATE_GTT, F_LEN_VAR, R_ALL, D_BDW_PLUS, 0, 10,
1894                 cmd_handler_mi_update_gtt},
1895
1896         {"MI_STORE_REGISTER_MEM", OP_MI_STORE_REGISTER_MEM, F_LEN_VAR, R_ALL,
1897                 D_ALL, ADDR_FIX_1(2), 8, cmd_handler_srm},
1898
1899         {"MI_FLUSH_DW", OP_MI_FLUSH_DW, F_LEN_VAR, R_ALL, D_ALL, 0, 6,
1900                 cmd_handler_mi_flush_dw},
1901
1902         {"MI_CLFLUSH", OP_MI_CLFLUSH, F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(1),
1903                 10, cmd_handler_mi_clflush},
1904
1905         {"MI_REPORT_PERF_COUNT", OP_MI_REPORT_PERF_COUNT, F_LEN_VAR, R_ALL,
1906                 D_ALL, ADDR_FIX_1(1), 6, cmd_handler_mi_report_perf_count},
1907
1908         {"MI_LOAD_REGISTER_MEM", OP_MI_LOAD_REGISTER_MEM, F_LEN_VAR, R_ALL,
1909                 D_ALL, ADDR_FIX_1(2), 8, cmd_handler_lrm},
1910
1911         {"MI_LOAD_REGISTER_REG", OP_MI_LOAD_REGISTER_REG, F_LEN_VAR, R_ALL,
1912                 D_ALL, 0, 8, cmd_handler_lrr},
1913
1914         {"MI_RS_STORE_DATA_IMM", OP_MI_RS_STORE_DATA_IMM, F_LEN_VAR, R_RCS,
1915                 D_ALL, 0, 8, NULL},
1916
1917         {"MI_LOAD_URB_MEM", OP_MI_LOAD_URB_MEM, F_LEN_VAR, R_RCS, D_ALL,
1918                 ADDR_FIX_1(2), 8, NULL},
1919
1920         {"MI_STORE_URM_MEM", OP_MI_STORE_URM_MEM, F_LEN_VAR, R_RCS, D_ALL,
1921                 ADDR_FIX_1(2), 8, NULL},
1922
1923         {"MI_OP_2E", OP_MI_2E, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_2(1, 2),
1924                 8, cmd_handler_mi_op_2e},
1925
1926         {"MI_OP_2F", OP_MI_2F, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_1(1),
1927                 8, cmd_handler_mi_op_2f},
1928
1929         {"MI_BATCH_BUFFER_START", OP_MI_BATCH_BUFFER_START,
1930                 F_IP_ADVANCE_CUSTOM, R_ALL, D_ALL, 0, 8,
1931                 cmd_handler_mi_batch_buffer_start},
1932
1933         {"MI_CONDITIONAL_BATCH_BUFFER_END", OP_MI_CONDITIONAL_BATCH_BUFFER_END,
1934                 F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
1935                 cmd_handler_mi_conditional_batch_buffer_end},
1936
1937         {"MI_LOAD_SCAN_LINES_INCL", OP_MI_LOAD_SCAN_LINES_INCL, F_LEN_CONST,
1938                 R_RCS | R_BCS, D_ALL, 0, 2, NULL},
1939
1940         {"XY_SETUP_BLT", OP_XY_SETUP_BLT, F_LEN_VAR, R_BCS, D_ALL,
1941                 ADDR_FIX_2(4, 7), 8, NULL},
1942
1943         {"XY_SETUP_CLIP_BLT", OP_XY_SETUP_CLIP_BLT, F_LEN_VAR, R_BCS, D_ALL,
1944                 0, 8, NULL},
1945
1946         {"XY_SETUP_MONO_PATTERN_SL_BLT", OP_XY_SETUP_MONO_PATTERN_SL_BLT,
1947                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
1948
1949         {"XY_PIXEL_BLT", OP_XY_PIXEL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
1950
1951         {"XY_SCANLINES_BLT", OP_XY_SCANLINES_BLT, F_LEN_VAR, R_BCS, D_ALL,
1952                 0, 8, NULL},
1953
1954         {"XY_TEXT_BLT", OP_XY_TEXT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1955                 ADDR_FIX_1(3), 8, NULL},
1956
1957         {"XY_TEXT_IMMEDIATE_BLT", OP_XY_TEXT_IMMEDIATE_BLT, F_LEN_VAR, R_BCS,
1958                 D_ALL, 0, 8, NULL},
1959
1960         {"XY_COLOR_BLT", OP_XY_COLOR_BLT, F_LEN_VAR, R_BCS, D_ALL,
1961                 ADDR_FIX_1(4), 8, NULL},
1962
1963         {"XY_PAT_BLT", OP_XY_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1964                 ADDR_FIX_2(4, 5), 8, NULL},
1965
1966         {"XY_MONO_PAT_BLT", OP_XY_MONO_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1967                 ADDR_FIX_1(4), 8, NULL},
1968
1969         {"XY_SRC_COPY_BLT", OP_XY_SRC_COPY_BLT, F_LEN_VAR, R_BCS, D_ALL,
1970                 ADDR_FIX_2(4, 7), 8, NULL},
1971
1972         {"XY_MONO_SRC_COPY_BLT", OP_XY_MONO_SRC_COPY_BLT, F_LEN_VAR, R_BCS,
1973                 D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
1974
1975         {"XY_FULL_BLT", OP_XY_FULL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
1976
1977         {"XY_FULL_MONO_SRC_BLT", OP_XY_FULL_MONO_SRC_BLT, F_LEN_VAR, R_BCS,
1978                 D_ALL, ADDR_FIX_3(4, 5, 8), 8, NULL},
1979
1980         {"XY_FULL_MONO_PATTERN_BLT", OP_XY_FULL_MONO_PATTERN_BLT, F_LEN_VAR,
1981                 R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
1982
1983         {"XY_FULL_MONO_PATTERN_MONO_SRC_BLT",
1984                 OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT,
1985                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
1986
1987         {"XY_MONO_PAT_FIXED_BLT", OP_XY_MONO_PAT_FIXED_BLT, F_LEN_VAR, R_BCS,
1988                 D_ALL, ADDR_FIX_1(4), 8, NULL},
1989
1990         {"XY_MONO_SRC_COPY_IMMEDIATE_BLT", OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT,
1991                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
1992
1993         {"XY_PAT_BLT_IMMEDIATE", OP_XY_PAT_BLT_IMMEDIATE, F_LEN_VAR, R_BCS,
1994                 D_ALL, ADDR_FIX_1(4), 8, NULL},
1995
1996         {"XY_SRC_COPY_CHROMA_BLT", OP_XY_SRC_COPY_CHROMA_BLT, F_LEN_VAR, R_BCS,
1997                 D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
1998
1999         {"XY_FULL_IMMEDIATE_PATTERN_BLT", OP_XY_FULL_IMMEDIATE_PATTERN_BLT,
2000                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2001
2002         {"XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT",
2003                 OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT,
2004                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2005
2006         {"XY_PAT_CHROMA_BLT", OP_XY_PAT_CHROMA_BLT, F_LEN_VAR, R_BCS, D_ALL,
2007                 ADDR_FIX_2(4, 5), 8, NULL},
2008
2009         {"XY_PAT_CHROMA_BLT_IMMEDIATE", OP_XY_PAT_CHROMA_BLT_IMMEDIATE,
2010                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2011
2012         {"3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP",
2013                 OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP,
2014                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2015
2016         {"3DSTATE_VIEWPORT_STATE_POINTERS_CC",
2017                 OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
2018                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2019
2020         {"3DSTATE_BLEND_STATE_POINTERS",
2021                 OP_3DSTATE_BLEND_STATE_POINTERS,
2022                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2023
2024         {"3DSTATE_DEPTH_STENCIL_STATE_POINTERS",
2025                 OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
2026                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2027
2028         {"3DSTATE_BINDING_TABLE_POINTERS_VS",
2029                 OP_3DSTATE_BINDING_TABLE_POINTERS_VS,
2030                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2031
2032         {"3DSTATE_BINDING_TABLE_POINTERS_HS",
2033                 OP_3DSTATE_BINDING_TABLE_POINTERS_HS,
2034                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2035
2036         {"3DSTATE_BINDING_TABLE_POINTERS_DS",
2037                 OP_3DSTATE_BINDING_TABLE_POINTERS_DS,
2038                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2039
2040         {"3DSTATE_BINDING_TABLE_POINTERS_GS",
2041                 OP_3DSTATE_BINDING_TABLE_POINTERS_GS,
2042                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2043
2044         {"3DSTATE_BINDING_TABLE_POINTERS_PS",
2045                 OP_3DSTATE_BINDING_TABLE_POINTERS_PS,
2046                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2047
2048         {"3DSTATE_SAMPLER_STATE_POINTERS_VS",
2049                 OP_3DSTATE_SAMPLER_STATE_POINTERS_VS,
2050                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2051
2052         {"3DSTATE_SAMPLER_STATE_POINTERS_HS",
2053                 OP_3DSTATE_SAMPLER_STATE_POINTERS_HS,
2054                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2055
2056         {"3DSTATE_SAMPLER_STATE_POINTERS_DS",
2057                 OP_3DSTATE_SAMPLER_STATE_POINTERS_DS,
2058                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2059
2060         {"3DSTATE_SAMPLER_STATE_POINTERS_GS",
2061                 OP_3DSTATE_SAMPLER_STATE_POINTERS_GS,
2062                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2063
2064         {"3DSTATE_SAMPLER_STATE_POINTERS_PS",
2065                 OP_3DSTATE_SAMPLER_STATE_POINTERS_PS,
2066                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2067
2068         {"3DSTATE_URB_VS", OP_3DSTATE_URB_VS, F_LEN_VAR, R_RCS, D_ALL,
2069                 0, 8, NULL},
2070
2071         {"3DSTATE_URB_HS", OP_3DSTATE_URB_HS, F_LEN_VAR, R_RCS, D_ALL,
2072                 0, 8, NULL},
2073
2074         {"3DSTATE_URB_DS", OP_3DSTATE_URB_DS, F_LEN_VAR, R_RCS, D_ALL,
2075                 0, 8, NULL},
2076
2077         {"3DSTATE_URB_GS", OP_3DSTATE_URB_GS, F_LEN_VAR, R_RCS, D_ALL,
2078                 0, 8, NULL},
2079
2080         {"3DSTATE_GATHER_CONSTANT_VS", OP_3DSTATE_GATHER_CONSTANT_VS,
2081                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2082
2083         {"3DSTATE_GATHER_CONSTANT_GS", OP_3DSTATE_GATHER_CONSTANT_GS,
2084                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2085
2086         {"3DSTATE_GATHER_CONSTANT_HS", OP_3DSTATE_GATHER_CONSTANT_HS,
2087                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2088
2089         {"3DSTATE_GATHER_CONSTANT_DS", OP_3DSTATE_GATHER_CONSTANT_DS,
2090                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2091
2092         {"3DSTATE_GATHER_CONSTANT_PS", OP_3DSTATE_GATHER_CONSTANT_PS,
2093                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2094
2095         {"3DSTATE_DX9_CONSTANTF_VS", OP_3DSTATE_DX9_CONSTANTF_VS,
2096                 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2097
2098         {"3DSTATE_DX9_CONSTANTF_PS", OP_3DSTATE_DX9_CONSTANTF_PS,
2099                 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2100
2101         {"3DSTATE_DX9_CONSTANTI_VS", OP_3DSTATE_DX9_CONSTANTI_VS,
2102                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2103
2104         {"3DSTATE_DX9_CONSTANTI_PS", OP_3DSTATE_DX9_CONSTANTI_PS,
2105                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2106
2107         {"3DSTATE_DX9_CONSTANTB_VS", OP_3DSTATE_DX9_CONSTANTB_VS,
2108                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2109
2110         {"3DSTATE_DX9_CONSTANTB_PS", OP_3DSTATE_DX9_CONSTANTB_PS,
2111                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2112
2113         {"3DSTATE_DX9_LOCAL_VALID_VS", OP_3DSTATE_DX9_LOCAL_VALID_VS,
2114                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2115
2116         {"3DSTATE_DX9_LOCAL_VALID_PS", OP_3DSTATE_DX9_LOCAL_VALID_PS,
2117                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2118
2119         {"3DSTATE_DX9_GENERATE_ACTIVE_VS", OP_3DSTATE_DX9_GENERATE_ACTIVE_VS,
2120                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2121
2122         {"3DSTATE_DX9_GENERATE_ACTIVE_PS", OP_3DSTATE_DX9_GENERATE_ACTIVE_PS,
2123                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2124
2125         {"3DSTATE_BINDING_TABLE_EDIT_VS", OP_3DSTATE_BINDING_TABLE_EDIT_VS,
2126                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2127
2128         {"3DSTATE_BINDING_TABLE_EDIT_GS", OP_3DSTATE_BINDING_TABLE_EDIT_GS,
2129                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2130
2131         {"3DSTATE_BINDING_TABLE_EDIT_HS", OP_3DSTATE_BINDING_TABLE_EDIT_HS,
2132                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2133
2134         {"3DSTATE_BINDING_TABLE_EDIT_DS", OP_3DSTATE_BINDING_TABLE_EDIT_DS,
2135                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2136
2137         {"3DSTATE_BINDING_TABLE_EDIT_PS", OP_3DSTATE_BINDING_TABLE_EDIT_PS,
2138                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2139
2140         {"3DSTATE_VF_INSTANCING", OP_3DSTATE_VF_INSTANCING, F_LEN_VAR, R_RCS,
2141                 D_BDW_PLUS, 0, 8, NULL},
2142
2143         {"3DSTATE_VF_SGVS", OP_3DSTATE_VF_SGVS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2144                 NULL},
2145
2146         {"3DSTATE_VF_TOPOLOGY", OP_3DSTATE_VF_TOPOLOGY, F_LEN_VAR, R_RCS,
2147                 D_BDW_PLUS, 0, 8, NULL},
2148
2149         {"3DSTATE_WM_CHROMAKEY", OP_3DSTATE_WM_CHROMAKEY, F_LEN_VAR, R_RCS,
2150                 D_BDW_PLUS, 0, 8, NULL},
2151
2152         {"3DSTATE_PS_BLEND", OP_3DSTATE_PS_BLEND, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2153                 8, NULL},
2154
2155         {"3DSTATE_WM_DEPTH_STENCIL", OP_3DSTATE_WM_DEPTH_STENCIL, F_LEN_VAR,
2156                 R_RCS, D_BDW_PLUS, 0, 8, NULL},
2157
2158         {"3DSTATE_PS_EXTRA", OP_3DSTATE_PS_EXTRA, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2159                 8, NULL},
2160
2161         {"3DSTATE_RASTER", OP_3DSTATE_RASTER, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2162                 NULL},
2163
2164         {"3DSTATE_SBE_SWIZ", OP_3DSTATE_SBE_SWIZ, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2165                 NULL},
2166
2167         {"3DSTATE_WM_HZ_OP", OP_3DSTATE_WM_HZ_OP, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2168                 NULL},
2169
2170         {"3DSTATE_VERTEX_BUFFERS", OP_3DSTATE_VERTEX_BUFFERS, F_LEN_VAR, R_RCS,
2171                 D_BDW_PLUS, 0, 8, NULL},
2172
2173         {"3DSTATE_VERTEX_ELEMENTS", OP_3DSTATE_VERTEX_ELEMENTS, F_LEN_VAR,
2174                 R_RCS, D_ALL, 0, 8, NULL},
2175
2176         {"3DSTATE_INDEX_BUFFER", OP_3DSTATE_INDEX_BUFFER, F_LEN_VAR, R_RCS,
2177                 D_BDW_PLUS, ADDR_FIX_1(2), 8, NULL},
2178
2179         {"3DSTATE_VF_STATISTICS", OP_3DSTATE_VF_STATISTICS, F_LEN_CONST,
2180                 R_RCS, D_ALL, 0, 1, NULL},
2181
2182         {"3DSTATE_VF", OP_3DSTATE_VF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2183
2184         {"3DSTATE_CC_STATE_POINTERS", OP_3DSTATE_CC_STATE_POINTERS, F_LEN_VAR,
2185                 R_RCS, D_ALL, 0, 8, NULL},
2186
2187         {"3DSTATE_SCISSOR_STATE_POINTERS", OP_3DSTATE_SCISSOR_STATE_POINTERS,
2188                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2189
2190         {"3DSTATE_GS", OP_3DSTATE_GS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2191
2192         {"3DSTATE_CLIP", OP_3DSTATE_CLIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2193
2194         {"3DSTATE_WM", OP_3DSTATE_WM, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2195
2196         {"3DSTATE_CONSTANT_GS", OP_3DSTATE_CONSTANT_GS, F_LEN_VAR, R_RCS,
2197                 D_BDW_PLUS, 0, 8, NULL},
2198
2199         {"3DSTATE_CONSTANT_PS", OP_3DSTATE_CONSTANT_PS, F_LEN_VAR, R_RCS,
2200                 D_BDW_PLUS, 0, 8, NULL},
2201
2202         {"3DSTATE_SAMPLE_MASK", OP_3DSTATE_SAMPLE_MASK, F_LEN_VAR, R_RCS,
2203                 D_ALL, 0, 8, NULL},
2204
2205         {"3DSTATE_CONSTANT_HS", OP_3DSTATE_CONSTANT_HS, F_LEN_VAR, R_RCS,
2206                 D_BDW_PLUS, 0, 8, NULL},
2207
2208         {"3DSTATE_CONSTANT_DS", OP_3DSTATE_CONSTANT_DS, F_LEN_VAR, R_RCS,
2209                 D_BDW_PLUS, 0, 8, NULL},
2210
2211         {"3DSTATE_HS", OP_3DSTATE_HS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2212
2213         {"3DSTATE_TE", OP_3DSTATE_TE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2214
2215         {"3DSTATE_DS", OP_3DSTATE_DS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2216
2217         {"3DSTATE_STREAMOUT", OP_3DSTATE_STREAMOUT, F_LEN_VAR, R_RCS,
2218                 D_ALL, 0, 8, NULL},
2219
2220         {"3DSTATE_SBE", OP_3DSTATE_SBE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2221
2222         {"3DSTATE_PS", OP_3DSTATE_PS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2223
2224         {"3DSTATE_DRAWING_RECTANGLE", OP_3DSTATE_DRAWING_RECTANGLE, F_LEN_VAR,
2225                 R_RCS, D_ALL, 0, 8, NULL},
2226
2227         {"3DSTATE_SAMPLER_PALETTE_LOAD0", OP_3DSTATE_SAMPLER_PALETTE_LOAD0,
2228                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2229
2230         {"3DSTATE_CHROMA_KEY", OP_3DSTATE_CHROMA_KEY, F_LEN_VAR, R_RCS, D_ALL,
2231                 0, 8, NULL},
2232
2233         {"3DSTATE_DEPTH_BUFFER", OP_3DSTATE_DEPTH_BUFFER, F_LEN_VAR, R_RCS,
2234                 D_ALL, ADDR_FIX_1(2), 8, NULL},
2235
2236         {"3DSTATE_POLY_STIPPLE_OFFSET", OP_3DSTATE_POLY_STIPPLE_OFFSET,
2237                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2238
2239         {"3DSTATE_POLY_STIPPLE_PATTERN", OP_3DSTATE_POLY_STIPPLE_PATTERN,
2240                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2241
2242         {"3DSTATE_LINE_STIPPLE", OP_3DSTATE_LINE_STIPPLE, F_LEN_VAR, R_RCS,
2243                 D_ALL, 0, 8, NULL},
2244
2245         {"3DSTATE_AA_LINE_PARAMS", OP_3DSTATE_AA_LINE_PARAMS, F_LEN_VAR, R_RCS,
2246                 D_ALL, 0, 8, NULL},
2247
2248         {"3DSTATE_GS_SVB_INDEX", OP_3DSTATE_GS_SVB_INDEX, F_LEN_VAR, R_RCS,
2249                 D_ALL, 0, 8, NULL},
2250
2251         {"3DSTATE_SAMPLER_PALETTE_LOAD1", OP_3DSTATE_SAMPLER_PALETTE_LOAD1,
2252                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2253
2254         {"3DSTATE_MULTISAMPLE", OP_3DSTATE_MULTISAMPLE_BDW, F_LEN_VAR, R_RCS,
2255                 D_BDW_PLUS, 0, 8, NULL},
2256
2257         {"3DSTATE_STENCIL_BUFFER", OP_3DSTATE_STENCIL_BUFFER, F_LEN_VAR, R_RCS,
2258                 D_ALL, ADDR_FIX_1(2), 8, NULL},
2259
2260         {"3DSTATE_HIER_DEPTH_BUFFER", OP_3DSTATE_HIER_DEPTH_BUFFER, F_LEN_VAR,
2261                 R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL},
2262
2263         {"3DSTATE_CLEAR_PARAMS", OP_3DSTATE_CLEAR_PARAMS, F_LEN_VAR,
2264                 R_RCS, D_ALL, 0, 8, NULL},
2265
2266         {"3DSTATE_PUSH_CONSTANT_ALLOC_VS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
2267                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2268
2269         {"3DSTATE_PUSH_CONSTANT_ALLOC_HS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS,
2270                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2271
2272         {"3DSTATE_PUSH_CONSTANT_ALLOC_DS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS,
2273                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2274
2275         {"3DSTATE_PUSH_CONSTANT_ALLOC_GS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS,
2276                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2277
2278         {"3DSTATE_PUSH_CONSTANT_ALLOC_PS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS,
2279                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2280
2281         {"3DSTATE_MONOFILTER_SIZE", OP_3DSTATE_MONOFILTER_SIZE, F_LEN_VAR,
2282                 R_RCS, D_ALL, 0, 8, NULL},
2283
2284         {"3DSTATE_SO_DECL_LIST", OP_3DSTATE_SO_DECL_LIST, F_LEN_VAR, R_RCS,
2285                 D_ALL, 0, 9, NULL},
2286
2287         {"3DSTATE_SO_BUFFER", OP_3DSTATE_SO_BUFFER, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2288                 ADDR_FIX_2(2, 4), 8, NULL},
2289
2290         {"3DSTATE_BINDING_TABLE_POOL_ALLOC",
2291                 OP_3DSTATE_BINDING_TABLE_POOL_ALLOC,
2292                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2293
2294         {"3DSTATE_GATHER_POOL_ALLOC", OP_3DSTATE_GATHER_POOL_ALLOC,
2295                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2296
2297         {"3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC",
2298                 OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC,
2299                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2300
2301         {"3DSTATE_SAMPLE_PATTERN", OP_3DSTATE_SAMPLE_PATTERN, F_LEN_VAR, R_RCS,
2302                 D_BDW_PLUS, 0, 8, NULL},
2303
2304         {"PIPE_CONTROL", OP_PIPE_CONTROL, F_LEN_VAR, R_RCS, D_ALL,
2305                 ADDR_FIX_1(2), 8, cmd_handler_pipe_control},
2306
2307         {"3DPRIMITIVE", OP_3DPRIMITIVE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2308
2309         {"PIPELINE_SELECT", OP_PIPELINE_SELECT, F_LEN_CONST, R_RCS, D_ALL, 0,
2310                 1, NULL},
2311
2312         {"STATE_PREFETCH", OP_STATE_PREFETCH, F_LEN_VAR, R_RCS, D_ALL,
2313                 ADDR_FIX_1(1), 8, NULL},
2314
2315         {"STATE_SIP", OP_STATE_SIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2316
2317         {"STATE_BASE_ADDRESS", OP_STATE_BASE_ADDRESS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2318                 ADDR_FIX_5(1, 3, 4, 5, 6), 8, NULL},
2319
2320         {"OP_3D_MEDIA_0_1_4", OP_3D_MEDIA_0_1_4, F_LEN_VAR, R_RCS, D_ALL,
2321                 ADDR_FIX_1(1), 8, NULL},
2322
2323         {"3DSTATE_VS", OP_3DSTATE_VS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2324
2325         {"3DSTATE_SF", OP_3DSTATE_SF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2326
2327         {"3DSTATE_CONSTANT_VS", OP_3DSTATE_CONSTANT_VS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2328                 0, 8, NULL},
2329
2330         {"3DSTATE_COMPONENT_PACKING", OP_3DSTATE_COMPONENT_PACKING, F_LEN_VAR, R_RCS,
2331                 D_SKL_PLUS, 0, 8, NULL},
2332
2333         {"MEDIA_INTERFACE_DESCRIPTOR_LOAD", OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD,
2334                 F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2335
2336         {"MEDIA_GATEWAY_STATE", OP_MEDIA_GATEWAY_STATE, F_LEN_VAR, R_RCS, D_ALL,
2337                 0, 16, NULL},
2338
2339         {"MEDIA_STATE_FLUSH", OP_MEDIA_STATE_FLUSH, F_LEN_VAR, R_RCS, D_ALL,
2340                 0, 16, NULL},
2341
2342         {"MEDIA_OBJECT", OP_MEDIA_OBJECT, F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2343
2344         {"MEDIA_CURBE_LOAD", OP_MEDIA_CURBE_LOAD, F_LEN_VAR, R_RCS, D_ALL,
2345                 0, 16, NULL},
2346
2347         {"MEDIA_OBJECT_PRT", OP_MEDIA_OBJECT_PRT, F_LEN_VAR, R_RCS, D_ALL,
2348                 0, 16, NULL},
2349
2350         {"MEDIA_OBJECT_WALKER", OP_MEDIA_OBJECT_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2351                 0, 16, NULL},
2352
2353         {"GPGPU_WALKER", OP_GPGPU_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2354                 0, 8, NULL},
2355
2356         {"MEDIA_VFE_STATE", OP_MEDIA_VFE_STATE, F_LEN_VAR, R_RCS, D_ALL, 0, 16,
2357                 NULL},
2358
2359         {"3DSTATE_VF_STATISTICS_GM45", OP_3DSTATE_VF_STATISTICS_GM45,
2360                 F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2361
2362         {"MFX_PIPE_MODE_SELECT", OP_MFX_PIPE_MODE_SELECT, F_LEN_VAR,
2363                 R_VCS, D_ALL, 0, 12, NULL},
2364
2365         {"MFX_SURFACE_STATE", OP_MFX_SURFACE_STATE, F_LEN_VAR,
2366                 R_VCS, D_ALL, 0, 12, NULL},
2367
2368         {"MFX_PIPE_BUF_ADDR_STATE", OP_MFX_PIPE_BUF_ADDR_STATE, F_LEN_VAR,
2369                 R_VCS, D_BDW_PLUS, 0, 12, NULL},
2370
2371         {"MFX_IND_OBJ_BASE_ADDR_STATE", OP_MFX_IND_OBJ_BASE_ADDR_STATE,
2372                 F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2373
2374         {"MFX_BSP_BUF_BASE_ADDR_STATE", OP_MFX_BSP_BUF_BASE_ADDR_STATE,
2375                 F_LEN_VAR, R_VCS, D_BDW_PLUS, ADDR_FIX_3(1, 3, 5), 12, NULL},
2376
2377         {"OP_2_0_0_5", OP_2_0_0_5, F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2378
2379         {"MFX_STATE_POINTER", OP_MFX_STATE_POINTER, F_LEN_VAR,
2380                 R_VCS, D_ALL, 0, 12, NULL},
2381
2382         {"MFX_QM_STATE", OP_MFX_QM_STATE, F_LEN_VAR,
2383                 R_VCS, D_ALL, 0, 12, NULL},
2384
2385         {"MFX_FQM_STATE", OP_MFX_FQM_STATE, F_LEN_VAR,
2386                 R_VCS, D_ALL, 0, 12, NULL},
2387
2388         {"MFX_PAK_INSERT_OBJECT", OP_MFX_PAK_INSERT_OBJECT, F_LEN_VAR,
2389                 R_VCS, D_ALL, 0, 12, NULL},
2390
2391         {"MFX_STITCH_OBJECT", OP_MFX_STITCH_OBJECT, F_LEN_VAR,
2392                 R_VCS, D_ALL, 0, 12, NULL},
2393
2394         {"MFD_IT_OBJECT", OP_MFD_IT_OBJECT, F_LEN_VAR,
2395                 R_VCS, D_ALL, 0, 12, NULL},
2396
2397         {"MFX_WAIT", OP_MFX_WAIT, F_LEN_VAR,
2398                 R_VCS, D_ALL, 0, 6, NULL},
2399
2400         {"MFX_AVC_IMG_STATE", OP_MFX_AVC_IMG_STATE, F_LEN_VAR,
2401                 R_VCS, D_ALL, 0, 12, NULL},
2402
2403         {"MFX_AVC_QM_STATE", OP_MFX_AVC_QM_STATE, F_LEN_VAR,
2404                 R_VCS, D_ALL, 0, 12, NULL},
2405
2406         {"MFX_AVC_DIRECTMODE_STATE", OP_MFX_AVC_DIRECTMODE_STATE, F_LEN_VAR,
2407                 R_VCS, D_ALL, 0, 12, NULL},
2408
2409         {"MFX_AVC_SLICE_STATE", OP_MFX_AVC_SLICE_STATE, F_LEN_VAR,
2410                 R_VCS, D_ALL, 0, 12, NULL},
2411
2412         {"MFX_AVC_REF_IDX_STATE", OP_MFX_AVC_REF_IDX_STATE, F_LEN_VAR,
2413                 R_VCS, D_ALL, 0, 12, NULL},
2414
2415         {"MFX_AVC_WEIGHTOFFSET_STATE", OP_MFX_AVC_WEIGHTOFFSET_STATE, F_LEN_VAR,
2416                 R_VCS, D_ALL, 0, 12, NULL},
2417
2418         {"MFD_AVC_PICID_STATE", OP_MFD_AVC_PICID_STATE, F_LEN_VAR,
2419                 R_VCS, D_ALL, 0, 12, NULL},
2420         {"MFD_AVC_DPB_STATE", OP_MFD_AVC_DPB_STATE, F_LEN_VAR,
2421                 R_VCS, D_ALL, 0, 12, NULL},
2422
2423         {"MFD_AVC_BSD_OBJECT", OP_MFD_AVC_BSD_OBJECT, F_LEN_VAR,
2424                 R_VCS, D_ALL, 0, 12, NULL},
2425
2426         {"MFD_AVC_SLICEADDR", OP_MFD_AVC_SLICEADDR, F_LEN_VAR,
2427                 R_VCS, D_ALL, ADDR_FIX_1(2), 12, NULL},
2428
2429         {"MFC_AVC_PAK_OBJECT", OP_MFC_AVC_PAK_OBJECT, F_LEN_VAR,
2430                 R_VCS, D_ALL, 0, 12, NULL},
2431
2432         {"MFX_VC1_PRED_PIPE_STATE", OP_MFX_VC1_PRED_PIPE_STATE, F_LEN_VAR,
2433                 R_VCS, D_ALL, 0, 12, NULL},
2434
2435         {"MFX_VC1_DIRECTMODE_STATE", OP_MFX_VC1_DIRECTMODE_STATE, F_LEN_VAR,
2436                 R_VCS, D_ALL, 0, 12, NULL},
2437
2438         {"MFD_VC1_SHORT_PIC_STATE", OP_MFD_VC1_SHORT_PIC_STATE, F_LEN_VAR,
2439                 R_VCS, D_ALL, 0, 12, NULL},
2440
2441         {"MFD_VC1_LONG_PIC_STATE", OP_MFD_VC1_LONG_PIC_STATE, F_LEN_VAR,
2442                 R_VCS, D_ALL, 0, 12, NULL},
2443
2444         {"MFD_VC1_BSD_OBJECT", OP_MFD_VC1_BSD_OBJECT, F_LEN_VAR,
2445                 R_VCS, D_ALL, 0, 12, NULL},
2446
2447         {"MFC_MPEG2_SLICEGROUP_STATE", OP_MFC_MPEG2_SLICEGROUP_STATE, F_LEN_VAR,
2448                 R_VCS, D_ALL, 0, 12, NULL},
2449
2450         {"MFC_MPEG2_PAK_OBJECT", OP_MFC_MPEG2_PAK_OBJECT, F_LEN_VAR,
2451                 R_VCS, D_ALL, 0, 12, NULL},
2452
2453         {"MFX_MPEG2_PIC_STATE", OP_MFX_MPEG2_PIC_STATE, F_LEN_VAR,
2454                 R_VCS, D_ALL, 0, 12, NULL},
2455
2456         {"MFX_MPEG2_QM_STATE", OP_MFX_MPEG2_QM_STATE, F_LEN_VAR,
2457                 R_VCS, D_ALL, 0, 12, NULL},
2458
2459         {"MFD_MPEG2_BSD_OBJECT", OP_MFD_MPEG2_BSD_OBJECT, F_LEN_VAR,
2460                 R_VCS, D_ALL, 0, 12, NULL},
2461
2462         {"MFX_2_6_0_0", OP_MFX_2_6_0_0, F_LEN_VAR, R_VCS, D_ALL,
2463                 0, 16, NULL},
2464
2465         {"MFX_2_6_0_9", OP_MFX_2_6_0_9, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2466
2467         {"MFX_2_6_0_8", OP_MFX_2_6_0_8, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2468
2469         {"MFX_JPEG_PIC_STATE", OP_MFX_JPEG_PIC_STATE, F_LEN_VAR,
2470                 R_VCS, D_ALL, 0, 12, NULL},
2471
2472         {"MFX_JPEG_HUFF_TABLE_STATE", OP_MFX_JPEG_HUFF_TABLE_STATE, F_LEN_VAR,
2473                 R_VCS, D_ALL, 0, 12, NULL},
2474
2475         {"MFD_JPEG_BSD_OBJECT", OP_MFD_JPEG_BSD_OBJECT, F_LEN_VAR,
2476                 R_VCS, D_ALL, 0, 12, NULL},
2477
2478         {"VEBOX_STATE", OP_VEB_STATE, F_LEN_VAR, R_VECS, D_ALL, 0, 12, NULL},
2479
2480         {"VEBOX_SURFACE_STATE", OP_VEB_SURFACE_STATE, F_LEN_VAR, R_VECS, D_ALL,
2481                 0, 12, NULL},
2482
2483         {"VEB_DI_IECP", OP_VEB_DNDI_IECP_STATE, F_LEN_VAR, R_VECS, D_BDW_PLUS,
2484                 0, 20, NULL},
2485 };
2486
2487 static void add_cmd_entry(struct intel_gvt *gvt, struct cmd_entry *e)
2488 {
2489         hash_add(gvt->cmd_table, &e->hlist, e->info->opcode);
2490 }
2491
2492 /* call the cmd handler, and advance ip */
2493 static int cmd_parser_exec(struct parser_exec_state *s)
2494 {
2495         struct intel_vgpu *vgpu = s->vgpu;
2496         struct cmd_info *info;
2497         u32 cmd;
2498         int ret = 0;
2499
2500         cmd = cmd_val(s, 0);
2501
2502         info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
2503         if (info == NULL) {
2504                 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",
2505                                 cmd, get_opcode(cmd, s->ring_id),
2506                                 (s->buf_addr_type == PPGTT_BUFFER) ?
2507                                 "ppgtt" : "ggtt", s->ring_id, s->workload);
2508                 return -EBADRQC;
2509         }
2510
2511         s->info = info;
2512
2513         trace_gvt_command(vgpu->id, s->ring_id, s->ip_gma, s->ip_va,
2514                           cmd_length(s), s->buf_type, s->buf_addr_type,
2515                           s->workload, info->name);
2516
2517         if (info->handler) {
2518                 ret = info->handler(s);
2519                 if (ret < 0) {
2520                         gvt_vgpu_err("%s handler error\n", info->name);
2521                         return ret;
2522                 }
2523         }
2524
2525         if (!(info->flag & F_IP_ADVANCE_CUSTOM)) {
2526                 ret = cmd_advance_default(s);
2527                 if (ret) {
2528                         gvt_vgpu_err("%s IP advance error\n", info->name);
2529                         return ret;
2530                 }
2531         }
2532         return 0;
2533 }
2534
2535 static inline bool gma_out_of_range(unsigned long gma,
2536                 unsigned long gma_head, unsigned int gma_tail)
2537 {
2538         if (gma_tail >= gma_head)
2539                 return (gma < gma_head) || (gma > gma_tail);
2540         else
2541                 return (gma > gma_tail) && (gma < gma_head);
2542 }
2543
2544 /* Keep the consistent return type, e.g EBADRQC for unknown
2545  * cmd, EFAULT for invalid address, EPERM for nonpriv. later
2546  * works as the input of VM healthy status.
2547  */
2548 static int command_scan(struct parser_exec_state *s,
2549                 unsigned long rb_head, unsigned long rb_tail,
2550                 unsigned long rb_start, unsigned long rb_len)
2551 {
2552
2553         unsigned long gma_head, gma_tail, gma_bottom;
2554         int ret = 0;
2555         struct intel_vgpu *vgpu = s->vgpu;
2556
2557         gma_head = rb_start + rb_head;
2558         gma_tail = rb_start + rb_tail;
2559         gma_bottom = rb_start +  rb_len;
2560
2561         while (s->ip_gma != gma_tail) {
2562                 if (s->buf_type == RING_BUFFER_INSTRUCTION) {
2563                         if (!(s->ip_gma >= rb_start) ||
2564                                 !(s->ip_gma < gma_bottom)) {
2565                                 gvt_vgpu_err("ip_gma %lx out of ring scope."
2566                                         "(base:0x%lx, bottom: 0x%lx)\n",
2567                                         s->ip_gma, rb_start,
2568                                         gma_bottom);
2569                                 parser_exec_state_dump(s);
2570                                 return -EFAULT;
2571                         }
2572                         if (gma_out_of_range(s->ip_gma, gma_head, gma_tail)) {
2573                                 gvt_vgpu_err("ip_gma %lx out of range."
2574                                         "base 0x%lx head 0x%lx tail 0x%lx\n",
2575                                         s->ip_gma, rb_start,
2576                                         rb_head, rb_tail);
2577                                 parser_exec_state_dump(s);
2578                                 break;
2579                         }
2580                 }
2581                 ret = cmd_parser_exec(s);
2582                 if (ret) {
2583                         gvt_vgpu_err("cmd parser error\n");
2584                         parser_exec_state_dump(s);
2585                         break;
2586                 }
2587         }
2588
2589         return ret;
2590 }
2591
2592 static int scan_workload(struct intel_vgpu_workload *workload)
2593 {
2594         unsigned long gma_head, gma_tail, gma_bottom;
2595         struct parser_exec_state s;
2596         int ret = 0;
2597
2598         /* ring base is page aligned */
2599         if (WARN_ON(!IS_ALIGNED(workload->rb_start, I915_GTT_PAGE_SIZE)))
2600                 return -EINVAL;
2601
2602         gma_head = workload->rb_start + workload->rb_head;
2603         gma_tail = workload->rb_start + workload->rb_tail;
2604         gma_bottom = workload->rb_start +  _RING_CTL_BUF_SIZE(workload->rb_ctl);
2605
2606         s.buf_type = RING_BUFFER_INSTRUCTION;
2607         s.buf_addr_type = GTT_BUFFER;
2608         s.vgpu = workload->vgpu;
2609         s.ring_id = workload->ring_id;
2610         s.ring_start = workload->rb_start;
2611         s.ring_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2612         s.ring_head = gma_head;
2613         s.ring_tail = gma_tail;
2614         s.rb_va = workload->shadow_ring_buffer_va;
2615         s.workload = workload;
2616         s.is_ctx_wa = false;
2617
2618         if ((bypass_scan_mask & (1 << workload->ring_id)) ||
2619                 gma_head == gma_tail)
2620                 return 0;
2621
2622         if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) {
2623                 ret = -EINVAL;
2624                 goto out;
2625         }
2626
2627         ret = ip_gma_set(&s, gma_head);
2628         if (ret)
2629                 goto out;
2630
2631         ret = command_scan(&s, workload->rb_head, workload->rb_tail,
2632                 workload->rb_start, _RING_CTL_BUF_SIZE(workload->rb_ctl));
2633
2634 out:
2635         return ret;
2636 }
2637
2638 static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2639 {
2640
2641         unsigned long gma_head, gma_tail, gma_bottom, ring_size, ring_tail;
2642         struct parser_exec_state s;
2643         int ret = 0;
2644         struct intel_vgpu_workload *workload = container_of(wa_ctx,
2645                                 struct intel_vgpu_workload,
2646                                 wa_ctx);
2647
2648         /* ring base is page aligned */
2649         if (WARN_ON(!IS_ALIGNED(wa_ctx->indirect_ctx.guest_gma,
2650                                         I915_GTT_PAGE_SIZE)))
2651                 return -EINVAL;
2652
2653         ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(uint32_t);
2654         ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES,
2655                         PAGE_SIZE);
2656         gma_head = wa_ctx->indirect_ctx.guest_gma;
2657         gma_tail = wa_ctx->indirect_ctx.guest_gma + ring_tail;
2658         gma_bottom = wa_ctx->indirect_ctx.guest_gma + ring_size;
2659
2660         s.buf_type = RING_BUFFER_INSTRUCTION;
2661         s.buf_addr_type = GTT_BUFFER;
2662         s.vgpu = workload->vgpu;
2663         s.ring_id = workload->ring_id;
2664         s.ring_start = wa_ctx->indirect_ctx.guest_gma;
2665         s.ring_size = ring_size;
2666         s.ring_head = gma_head;
2667         s.ring_tail = gma_tail;
2668         s.rb_va = wa_ctx->indirect_ctx.shadow_va;
2669         s.workload = workload;
2670         s.is_ctx_wa = true;
2671
2672         if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) {
2673                 ret = -EINVAL;
2674                 goto out;
2675         }
2676
2677         ret = ip_gma_set(&s, gma_head);
2678         if (ret)
2679                 goto out;
2680
2681         ret = command_scan(&s, 0, ring_tail,
2682                 wa_ctx->indirect_ctx.guest_gma, ring_size);
2683 out:
2684         return ret;
2685 }
2686
2687 static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload)
2688 {
2689         struct intel_vgpu *vgpu = workload->vgpu;
2690         struct intel_vgpu_submission *s = &vgpu->submission;
2691         unsigned long gma_head, gma_tail, gma_top, guest_rb_size;
2692         void *shadow_ring_buffer_va;
2693         int ring_id = workload->ring_id;
2694         int ret;
2695
2696         guest_rb_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2697
2698         /* calculate workload ring buffer size */
2699         workload->rb_len = (workload->rb_tail + guest_rb_size -
2700                         workload->rb_head) % guest_rb_size;
2701
2702         gma_head = workload->rb_start + workload->rb_head;
2703         gma_tail = workload->rb_start + workload->rb_tail;
2704         gma_top = workload->rb_start + guest_rb_size;
2705
2706         if (workload->rb_len > s->ring_scan_buffer_size[ring_id]) {
2707                 void *p;
2708
2709                 /* realloc the new ring buffer if needed */
2710                 p = krealloc(s->ring_scan_buffer[ring_id], workload->rb_len,
2711                                 GFP_KERNEL);
2712                 if (!p) {
2713                         gvt_vgpu_err("fail to re-alloc ring scan buffer\n");
2714                         return -ENOMEM;
2715                 }
2716                 s->ring_scan_buffer[ring_id] = p;
2717                 s->ring_scan_buffer_size[ring_id] = workload->rb_len;
2718         }
2719
2720         shadow_ring_buffer_va = s->ring_scan_buffer[ring_id];
2721
2722         /* get shadow ring buffer va */
2723         workload->shadow_ring_buffer_va = shadow_ring_buffer_va;
2724
2725         /* head > tail --> copy head <-> top */
2726         if (gma_head > gma_tail) {
2727                 ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm,
2728                                       gma_head, gma_top, shadow_ring_buffer_va);
2729                 if (ret < 0) {
2730                         gvt_vgpu_err("fail to copy guest ring buffer\n");
2731                         return ret;
2732                 }
2733                 shadow_ring_buffer_va += ret;
2734                 gma_head = workload->rb_start;
2735         }
2736
2737         /* copy head or start <-> tail */
2738         ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, gma_head, gma_tail,
2739                                 shadow_ring_buffer_va);
2740         if (ret < 0) {
2741                 gvt_vgpu_err("fail to copy guest ring buffer\n");
2742                 return ret;
2743         }
2744         return 0;
2745 }
2746
2747 int intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload *workload)
2748 {
2749         int ret;
2750         struct intel_vgpu *vgpu = workload->vgpu;
2751
2752         ret = shadow_workload_ring_buffer(workload);
2753         if (ret) {
2754                 gvt_vgpu_err("fail to shadow workload ring_buffer\n");
2755                 return ret;
2756         }
2757
2758         ret = scan_workload(workload);
2759         if (ret) {
2760                 gvt_vgpu_err("scan workload error\n");
2761                 return ret;
2762         }
2763         return 0;
2764 }
2765
2766 static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2767 {
2768         int ctx_size = wa_ctx->indirect_ctx.size;
2769         unsigned long guest_gma = wa_ctx->indirect_ctx.guest_gma;
2770         struct intel_vgpu_workload *workload = container_of(wa_ctx,
2771                                         struct intel_vgpu_workload,
2772                                         wa_ctx);
2773         struct intel_vgpu *vgpu = workload->vgpu;
2774         struct drm_i915_gem_object *obj;
2775         int ret = 0;
2776         void *map;
2777
2778         obj = i915_gem_object_create(workload->vgpu->gvt->dev_priv,
2779                                      roundup(ctx_size + CACHELINE_BYTES,
2780                                              PAGE_SIZE));
2781         if (IS_ERR(obj))
2782                 return PTR_ERR(obj);
2783
2784         /* get the va of the shadow batch buffer */
2785         map = i915_gem_object_pin_map(obj, I915_MAP_WB);
2786         if (IS_ERR(map)) {
2787                 gvt_vgpu_err("failed to vmap shadow indirect ctx\n");
2788                 ret = PTR_ERR(map);
2789                 goto put_obj;
2790         }
2791
2792         ret = i915_gem_object_set_to_cpu_domain(obj, false);
2793         if (ret) {
2794                 gvt_vgpu_err("failed to set shadow indirect ctx to CPU\n");
2795                 goto unmap_src;
2796         }
2797
2798         ret = copy_gma_to_hva(workload->vgpu,
2799                                 workload->vgpu->gtt.ggtt_mm,
2800                                 guest_gma, guest_gma + ctx_size,
2801                                 map);
2802         if (ret < 0) {
2803                 gvt_vgpu_err("fail to copy guest indirect ctx\n");
2804                 goto unmap_src;
2805         }
2806
2807         wa_ctx->indirect_ctx.obj = obj;
2808         wa_ctx->indirect_ctx.shadow_va = map;
2809         return 0;
2810
2811 unmap_src:
2812         i915_gem_object_unpin_map(obj);
2813 put_obj:
2814         i915_gem_object_put(obj);
2815         return ret;
2816 }
2817
2818 static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2819 {
2820         uint32_t per_ctx_start[CACHELINE_DWORDS] = {0};
2821         unsigned char *bb_start_sva;
2822
2823         if (!wa_ctx->per_ctx.valid)
2824                 return 0;
2825
2826         per_ctx_start[0] = 0x18800001;
2827         per_ctx_start[1] = wa_ctx->per_ctx.guest_gma;
2828
2829         bb_start_sva = (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
2830                                 wa_ctx->indirect_ctx.size;
2831
2832         memcpy(bb_start_sva, per_ctx_start, CACHELINE_BYTES);
2833
2834         return 0;
2835 }
2836
2837 int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2838 {
2839         int ret;
2840         struct intel_vgpu_workload *workload = container_of(wa_ctx,
2841                                         struct intel_vgpu_workload,
2842                                         wa_ctx);
2843         struct intel_vgpu *vgpu = workload->vgpu;
2844
2845         if (wa_ctx->indirect_ctx.size == 0)
2846                 return 0;
2847
2848         ret = shadow_indirect_ctx(wa_ctx);
2849         if (ret) {
2850                 gvt_vgpu_err("fail to shadow indirect ctx\n");
2851                 return ret;
2852         }
2853
2854         combine_wa_ctx(wa_ctx);
2855
2856         ret = scan_wa_ctx(wa_ctx);
2857         if (ret) {
2858                 gvt_vgpu_err("scan wa ctx error\n");
2859                 return ret;
2860         }
2861
2862         return 0;
2863 }
2864
2865 static struct cmd_info *find_cmd_entry_any_ring(struct intel_gvt *gvt,
2866                 unsigned int opcode, unsigned long rings)
2867 {
2868         struct cmd_info *info = NULL;
2869         unsigned int ring;
2870
2871         for_each_set_bit(ring, &rings, I915_NUM_ENGINES) {
2872                 info = find_cmd_entry(gvt, opcode, ring);
2873                 if (info)
2874                         break;
2875         }
2876         return info;
2877 }
2878
2879 static int init_cmd_table(struct intel_gvt *gvt)
2880 {
2881         int i;
2882         struct cmd_entry *e;
2883         struct cmd_info *info;
2884         unsigned int gen_type;
2885
2886         gen_type = intel_gvt_get_device_type(gvt);
2887
2888         for (i = 0; i < ARRAY_SIZE(cmd_info); i++) {
2889                 if (!(cmd_info[i].devices & gen_type))
2890                         continue;
2891
2892                 e = kzalloc(sizeof(*e), GFP_KERNEL);
2893                 if (!e)
2894                         return -ENOMEM;
2895
2896                 e->info = &cmd_info[i];
2897                 info = find_cmd_entry_any_ring(gvt,
2898                                 e->info->opcode, e->info->rings);
2899                 if (info) {
2900                         gvt_err("%s %s duplicated\n", e->info->name,
2901                                         info->name);
2902                         return -EEXIST;
2903                 }
2904
2905                 INIT_HLIST_NODE(&e->hlist);
2906                 add_cmd_entry(gvt, e);
2907                 gvt_dbg_cmd("add %-30s op %04x flag %x devs %02x rings %02x\n",
2908                                 e->info->name, e->info->opcode, e->info->flag,
2909                                 e->info->devices, e->info->rings);
2910         }
2911         return 0;
2912 }
2913
2914 static void clean_cmd_table(struct intel_gvt *gvt)
2915 {
2916         struct hlist_node *tmp;
2917         struct cmd_entry *e;
2918         int i;
2919
2920         hash_for_each_safe(gvt->cmd_table, i, tmp, e, hlist)
2921                 kfree(e);
2922
2923         hash_init(gvt->cmd_table);
2924 }
2925
2926 void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt)
2927 {
2928         clean_cmd_table(gvt);
2929 }
2930
2931 int intel_gvt_init_cmd_parser(struct intel_gvt *gvt)
2932 {
2933         int ret;
2934
2935         ret = init_cmd_table(gvt);
2936         if (ret) {
2937                 intel_gvt_clean_cmd_parser(gvt);
2938                 return ret;
2939         }
2940         return 0;
2941 }