drm/i915: Always backoff after a drm_modeset_lock() deadlock
[muen/linux.git] / drivers / gpu / drm / i915 / gvt / display.c
1 /*
2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21  * SOFTWARE.
22  *
23  * Authors:
24  *    Ke Yu
25  *    Zhiyuan Lv <zhiyuan.lv@intel.com>
26  *
27  * Contributors:
28  *    Terrence Xu <terrence.xu@intel.com>
29  *    Changbin Du <changbin.du@intel.com>
30  *    Bing Niu <bing.niu@intel.com>
31  *    Zhi Wang <zhi.a.wang@intel.com>
32  *
33  */
34
35 #include "i915_drv.h"
36 #include "gvt.h"
37
38 static int get_edp_pipe(struct intel_vgpu *vgpu)
39 {
40         u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP);
41         int pipe = -1;
42
43         switch (data & TRANS_DDI_EDP_INPUT_MASK) {
44         case TRANS_DDI_EDP_INPUT_A_ON:
45         case TRANS_DDI_EDP_INPUT_A_ONOFF:
46                 pipe = PIPE_A;
47                 break;
48         case TRANS_DDI_EDP_INPUT_B_ONOFF:
49                 pipe = PIPE_B;
50                 break;
51         case TRANS_DDI_EDP_INPUT_C_ONOFF:
52                 pipe = PIPE_C;
53                 break;
54         }
55         return pipe;
56 }
57
58 static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)
59 {
60         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
61
62         if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE))
63                 return 0;
64
65         if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))
66                 return 0;
67         return 1;
68 }
69
70 int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
71 {
72         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
73
74         if (WARN_ON(pipe < PIPE_A || pipe >= I915_MAX_PIPES))
75                 return -EINVAL;
76
77         if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE)
78                 return 1;
79
80         if (edp_pipe_is_enabled(vgpu) &&
81                         get_edp_pipe(vgpu) == pipe)
82                 return 1;
83         return 0;
84 }
85
86 static unsigned char virtual_dp_monitor_edid[GVT_EDID_NUM][EDID_SIZE] = {
87         {
88 /* EDID with 1024x768 as its resolution */
89                 /*Header*/
90                 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
91                 /* Vendor & Product Identification */
92                 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
93                 /* Version & Revision */
94                 0x01, 0x04,
95                 /* Basic Display Parameters & Features */
96                 0xa5, 0x34, 0x20, 0x78, 0x23,
97                 /* Color Characteristics */
98                 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
99                 /* Established Timings: maximum resolution is 1024x768 */
100                 0x21, 0x08, 0x00,
101                 /* Standard Timings. All invalid */
102                 0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00,
103                 0x00, 0x40, 0x00, 0x00, 0x00, 0x01,
104                 /* 18 Byte Data Blocks 1: invalid */
105                 0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0,
106                 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
107                 /* 18 Byte Data Blocks 2: invalid */
108                 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
109                 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
110                 /* 18 Byte Data Blocks 3: invalid */
111                 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
112                 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
113                 /* 18 Byte Data Blocks 4: invalid */
114                 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
115                 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
116                 /* Extension Block Count */
117                 0x00,
118                 /* Checksum */
119                 0xef,
120         },
121         {
122 /* EDID with 1920x1200 as its resolution */
123                 /*Header*/
124                 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
125                 /* Vendor & Product Identification */
126                 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
127                 /* Version & Revision */
128                 0x01, 0x04,
129                 /* Basic Display Parameters & Features */
130                 0xa5, 0x34, 0x20, 0x78, 0x23,
131                 /* Color Characteristics */
132                 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
133                 /* Established Timings: maximum resolution is 1024x768 */
134                 0x21, 0x08, 0x00,
135                 /*
136                  * Standard Timings.
137                  * below new resolutions can be supported:
138                  * 1920x1080, 1280x720, 1280x960, 1280x1024,
139                  * 1440x900, 1600x1200, 1680x1050
140                  */
141                 0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00,
142                 0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01,
143                 /* 18 Byte Data Blocks 1: max resolution is 1920x1200 */
144                 0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0,
145                 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
146                 /* 18 Byte Data Blocks 2: invalid */
147                 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
148                 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
149                 /* 18 Byte Data Blocks 3: invalid */
150                 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
151                 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
152                 /* 18 Byte Data Blocks 4: invalid */
153                 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
154                 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
155                 /* Extension Block Count */
156                 0x00,
157                 /* Checksum */
158                 0x45,
159         },
160 };
161
162 #define DPCD_HEADER_SIZE        0xb
163
164 /* let the virtual display supports DP1.2 */
165 static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = {
166         0x12, 0x014, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
167 };
168
169 static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
170 {
171         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
172         int pipe;
173
174         if (IS_BROXTON(dev_priv)) {
175                 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~(BXT_DE_PORT_HP_DDIA |
176                         BXT_DE_PORT_HP_DDIB |
177                         BXT_DE_PORT_HP_DDIC);
178
179                 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
180                         vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
181                                 BXT_DE_PORT_HP_DDIA;
182                 }
183
184                 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
185                         vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
186                                 BXT_DE_PORT_HP_DDIB;
187                 }
188
189                 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
190                         vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
191                                 BXT_DE_PORT_HP_DDIC;
192                 }
193
194                 return;
195         }
196
197         vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT |
198                         SDE_PORTC_HOTPLUG_CPT |
199                         SDE_PORTD_HOTPLUG_CPT);
200
201         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ||
202             IS_COFFEELAKE(dev_priv)) {
203                 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |
204                                 SDE_PORTE_HOTPLUG_SPT);
205                 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=
206                                 SKL_FUSE_DOWNLOAD_STATUS |
207                                 SKL_FUSE_PG_DIST_STATUS(SKL_PG0) |
208                                 SKL_FUSE_PG_DIST_STATUS(SKL_PG1) |
209                                 SKL_FUSE_PG_DIST_STATUS(SKL_PG2);
210                 vgpu_vreg_t(vgpu, LCPLL1_CTL) |=
211                                 LCPLL_PLL_ENABLE |
212                                 LCPLL_PLL_LOCK;
213                 vgpu_vreg_t(vgpu, LCPLL2_CTL) |= LCPLL_PLL_ENABLE;
214
215         }
216
217         if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
218                 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
219                 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
220                         ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
221                         TRANS_DDI_PORT_MASK);
222                 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
223                         (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DVI |
224                         (PORT_B << TRANS_DDI_PORT_SHIFT) |
225                         TRANS_DDI_FUNC_ENABLE);
226                 if (IS_BROADWELL(dev_priv)) {
227                         vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &=
228                                 ~PORT_CLK_SEL_MASK;
229                         vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |=
230                                 PORT_CLK_SEL_LCPLL_810;
231                 }
232                 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE;
233                 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE;
234                 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;
235         }
236
237         if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
238                 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;
239                 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
240                         ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
241                         TRANS_DDI_PORT_MASK);
242                 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
243                         (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DVI |
244                         (PORT_C << TRANS_DDI_PORT_SHIFT) |
245                         TRANS_DDI_FUNC_ENABLE);
246                 if (IS_BROADWELL(dev_priv)) {
247                         vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &=
248                                 ~PORT_CLK_SEL_MASK;
249                         vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |=
250                                 PORT_CLK_SEL_LCPLL_810;
251                 }
252                 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE;
253                 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE;
254                 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
255         }
256
257         if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) {
258                 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
259                 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
260                         ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
261                         TRANS_DDI_PORT_MASK);
262                 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
263                         (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DVI |
264                         (PORT_D << TRANS_DDI_PORT_SHIFT) |
265                         TRANS_DDI_FUNC_ENABLE);
266                 if (IS_BROADWELL(dev_priv)) {
267                         vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &=
268                                 ~PORT_CLK_SEL_MASK;
269                         vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |=
270                                 PORT_CLK_SEL_LCPLL_810;
271                 }
272                 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE;
273                 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE;
274                 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;
275         }
276
277         if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ||
278              IS_COFFEELAKE(dev_priv)) &&
279                         intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {
280                 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;
281         }
282
283         if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
284                 if (IS_BROADWELL(dev_priv))
285                         vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
286                                 GEN8_PORT_DP_A_HOTPLUG;
287                 else
288                         vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;
289
290                 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED;
291         }
292
293         /* Clear host CRT status, so guest couldn't detect this host CRT. */
294         if (IS_BROADWELL(dev_priv))
295                 vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK;
296
297         /* Disable Primary/Sprite/Cursor plane */
298         for_each_pipe(dev_priv, pipe) {
299                 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
300                 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
301                 vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE;
302                 vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
303         }
304
305         vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
306 }
307
308 static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
309 {
310         struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
311
312         kfree(port->edid);
313         port->edid = NULL;
314
315         kfree(port->dpcd);
316         port->dpcd = NULL;
317 }
318
319 static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,
320                                     int type, unsigned int resolution)
321 {
322         struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
323
324         if (WARN_ON(resolution >= GVT_EDID_NUM))
325                 return -EINVAL;
326
327         port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL);
328         if (!port->edid)
329                 return -ENOMEM;
330
331         port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL);
332         if (!port->dpcd) {
333                 kfree(port->edid);
334                 return -ENOMEM;
335         }
336
337         memcpy(port->edid->edid_block, virtual_dp_monitor_edid[resolution],
338                         EDID_SIZE);
339         port->edid->data_valid = true;
340
341         memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE);
342         port->dpcd->data_valid = true;
343         port->dpcd->data[DPCD_SINK_COUNT] = 0x1;
344         port->type = type;
345         port->id = resolution;
346
347         emulate_monitor_status_change(vgpu);
348
349         return 0;
350 }
351
352 /**
353  * intel_gvt_check_vblank_emulation - check if vblank emulation timer should
354  * be turned on/off when a virtual pipe is enabled/disabled.
355  * @gvt: a GVT device
356  *
357  * This function is used to turn on/off vblank timer according to currently
358  * enabled/disabled virtual pipes.
359  *
360  */
361 void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt)
362 {
363         struct intel_gvt_irq *irq = &gvt->irq;
364         struct intel_vgpu *vgpu;
365         int pipe, id;
366         int found = false;
367
368         mutex_lock(&gvt->lock);
369         for_each_active_vgpu(gvt, vgpu, id) {
370                 for (pipe = 0; pipe < I915_MAX_PIPES; pipe++) {
371                         if (pipe_is_enabled(vgpu, pipe)) {
372                                 found = true;
373                                 break;
374                         }
375                 }
376                 if (found)
377                         break;
378         }
379
380         /* all the pipes are disabled */
381         if (!found)
382                 hrtimer_cancel(&irq->vblank_timer.timer);
383         else
384                 hrtimer_start(&irq->vblank_timer.timer,
385                         ktime_add_ns(ktime_get(), irq->vblank_timer.period),
386                         HRTIMER_MODE_ABS);
387         mutex_unlock(&gvt->lock);
388 }
389
390 static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)
391 {
392         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
393         struct intel_vgpu_irq *irq = &vgpu->irq;
394         int vblank_event[] = {
395                 [PIPE_A] = PIPE_A_VBLANK,
396                 [PIPE_B] = PIPE_B_VBLANK,
397                 [PIPE_C] = PIPE_C_VBLANK,
398         };
399         int event;
400
401         if (pipe < PIPE_A || pipe > PIPE_C)
402                 return;
403
404         for_each_set_bit(event, irq->flip_done_event[pipe],
405                         INTEL_GVT_EVENT_MAX) {
406                 clear_bit(event, irq->flip_done_event[pipe]);
407                 if (!pipe_is_enabled(vgpu, pipe))
408                         continue;
409
410                 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
411                 intel_vgpu_trigger_virtual_event(vgpu, event);
412         }
413
414         if (pipe_is_enabled(vgpu, pipe)) {
415                 vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(pipe))++;
416                 intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]);
417         }
418 }
419
420 static void emulate_vblank(struct intel_vgpu *vgpu)
421 {
422         int pipe;
423
424         mutex_lock(&vgpu->vgpu_lock);
425         for_each_pipe(vgpu->gvt->dev_priv, pipe)
426                 emulate_vblank_on_pipe(vgpu, pipe);
427         mutex_unlock(&vgpu->vgpu_lock);
428 }
429
430 /**
431  * intel_gvt_emulate_vblank - trigger vblank events for vGPUs on GVT device
432  * @gvt: a GVT device
433  *
434  * This function is used to trigger vblank interrupts for vGPUs on GVT device
435  *
436  */
437 void intel_gvt_emulate_vblank(struct intel_gvt *gvt)
438 {
439         struct intel_vgpu *vgpu;
440         int id;
441
442         mutex_lock(&gvt->lock);
443         for_each_active_vgpu(gvt, vgpu, id)
444                 emulate_vblank(vgpu);
445         mutex_unlock(&gvt->lock);
446 }
447
448 /**
449  * intel_vgpu_emulate_hotplug - trigger hotplug event for vGPU
450  * @vgpu: a vGPU
451  * @conncted: link state
452  *
453  * This function is used to trigger hotplug interrupt for vGPU
454  *
455  */
456 void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected)
457 {
458         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
459
460         /* TODO: add more platforms support */
461         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
462                 if (connected) {
463                         vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
464                                 SFUSE_STRAP_DDID_DETECTED;
465                         vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
466                 } else {
467                         vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
468                                 ~SFUSE_STRAP_DDID_DETECTED;
469                         vgpu_vreg_t(vgpu, SDEISR) &= ~SDE_PORTD_HOTPLUG_CPT;
470                 }
471                 vgpu_vreg_t(vgpu, SDEIIR) |= SDE_PORTD_HOTPLUG_CPT;
472                 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
473                                 PORTD_HOTPLUG_STATUS_MASK;
474                 intel_vgpu_trigger_virtual_event(vgpu, DP_D_HOTPLUG);
475         }
476 }
477
478 /**
479  * intel_vgpu_clean_display - clean vGPU virtual display emulation
480  * @vgpu: a vGPU
481  *
482  * This function is used to clean vGPU virtual display emulation stuffs
483  *
484  */
485 void intel_vgpu_clean_display(struct intel_vgpu *vgpu)
486 {
487         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
488
489         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ||
490             IS_COFFEELAKE(dev_priv))
491                 clean_virtual_dp_monitor(vgpu, PORT_D);
492         else
493                 clean_virtual_dp_monitor(vgpu, PORT_B);
494 }
495
496 /**
497  * intel_vgpu_init_display- initialize vGPU virtual display emulation
498  * @vgpu: a vGPU
499  * @resolution: resolution index for intel_vgpu_edid
500  *
501  * This function is used to initialize vGPU virtual display emulation stuffs
502  *
503  * Returns:
504  * Zero on success, negative error code if failed.
505  *
506  */
507 int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution)
508 {
509         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
510
511         intel_vgpu_init_i2c_edid(vgpu);
512
513         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ||
514             IS_COFFEELAKE(dev_priv))
515                 return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D,
516                                                 resolution);
517         else
518                 return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B,
519                                                 resolution);
520 }
521
522 /**
523  * intel_vgpu_reset_display- reset vGPU virtual display emulation
524  * @vgpu: a vGPU
525  *
526  * This function is used to reset vGPU virtual display emulation stuffs
527  *
528  */
529 void intel_vgpu_reset_display(struct intel_vgpu *vgpu)
530 {
531         emulate_monitor_status_change(vgpu);
532 }