Merge branch 'akpm' (patches from Andrew)
[muen/linux.git] / drivers / gpu / drm / i915 / gvt / scheduler.c
1 /*
2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21  * SOFTWARE.
22  *
23  * Authors:
24  *    Zhi Wang <zhi.a.wang@intel.com>
25  *
26  * Contributors:
27  *    Ping Gao <ping.a.gao@intel.com>
28  *    Tina Zhang <tina.zhang@intel.com>
29  *    Chanbin Du <changbin.du@intel.com>
30  *    Min He <min.he@intel.com>
31  *    Bing Niu <bing.niu@intel.com>
32  *    Zhenyu Wang <zhenyuw@linux.intel.com>
33  *
34  */
35
36 #include <linux/kthread.h>
37
38 #include "i915_drv.h"
39 #include "gvt.h"
40
41 #define RING_CTX_OFF(x) \
42         offsetof(struct execlist_ring_context, x)
43
44 static void set_context_pdp_root_pointer(
45                 struct execlist_ring_context *ring_context,
46                 u32 pdp[8])
47 {
48         int i;
49
50         for (i = 0; i < 8; i++)
51                 ring_context->pdps[i].val = pdp[7 - i];
52 }
53
54 static void update_shadow_pdps(struct intel_vgpu_workload *workload)
55 {
56         struct drm_i915_gem_object *ctx_obj =
57                 workload->req->hw_context->state->obj;
58         struct execlist_ring_context *shadow_ring_context;
59         struct page *page;
60
61         if (WARN_ON(!workload->shadow_mm))
62                 return;
63
64         if (WARN_ON(!atomic_read(&workload->shadow_mm->pincount)))
65                 return;
66
67         page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
68         shadow_ring_context = kmap(page);
69         set_context_pdp_root_pointer(shadow_ring_context,
70                         (void *)workload->shadow_mm->ppgtt_mm.shadow_pdps);
71         kunmap(page);
72 }
73
74 /*
75  * when populating shadow ctx from guest, we should not overrride oa related
76  * registers, so that they will not be overlapped by guest oa configs. Thus
77  * made it possible to capture oa data from host for both host and guests.
78  */
79 static void sr_oa_regs(struct intel_vgpu_workload *workload,
80                 u32 *reg_state, bool save)
81 {
82         struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv;
83         u32 ctx_oactxctrl = dev_priv->perf.oa.ctx_oactxctrl_offset;
84         u32 ctx_flexeu0 = dev_priv->perf.oa.ctx_flexeu0_offset;
85         int i = 0;
86         u32 flex_mmio[] = {
87                 i915_mmio_reg_offset(EU_PERF_CNTL0),
88                 i915_mmio_reg_offset(EU_PERF_CNTL1),
89                 i915_mmio_reg_offset(EU_PERF_CNTL2),
90                 i915_mmio_reg_offset(EU_PERF_CNTL3),
91                 i915_mmio_reg_offset(EU_PERF_CNTL4),
92                 i915_mmio_reg_offset(EU_PERF_CNTL5),
93                 i915_mmio_reg_offset(EU_PERF_CNTL6),
94         };
95
96         if (workload->ring_id != RCS)
97                 return;
98
99         if (save) {
100                 workload->oactxctrl = reg_state[ctx_oactxctrl + 1];
101
102                 for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) {
103                         u32 state_offset = ctx_flexeu0 + i * 2;
104
105                         workload->flex_mmio[i] = reg_state[state_offset + 1];
106                 }
107         } else {
108                 reg_state[ctx_oactxctrl] =
109                         i915_mmio_reg_offset(GEN8_OACTXCONTROL);
110                 reg_state[ctx_oactxctrl + 1] = workload->oactxctrl;
111
112                 for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) {
113                         u32 state_offset = ctx_flexeu0 + i * 2;
114                         u32 mmio = flex_mmio[i];
115
116                         reg_state[state_offset] = mmio;
117                         reg_state[state_offset + 1] = workload->flex_mmio[i];
118                 }
119         }
120 }
121
122 static int populate_shadow_context(struct intel_vgpu_workload *workload)
123 {
124         struct intel_vgpu *vgpu = workload->vgpu;
125         struct intel_gvt *gvt = vgpu->gvt;
126         int ring_id = workload->ring_id;
127         struct drm_i915_gem_object *ctx_obj =
128                 workload->req->hw_context->state->obj;
129         struct execlist_ring_context *shadow_ring_context;
130         struct page *page;
131         void *dst;
132         unsigned long context_gpa, context_page_num;
133         int i;
134
135         page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
136         shadow_ring_context = kmap(page);
137
138         sr_oa_regs(workload, (u32 *)shadow_ring_context, true);
139 #define COPY_REG(name) \
140         intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \
141                 + RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
142 #define COPY_REG_MASKED(name) {\
143                 intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \
144                                               + RING_CTX_OFF(name.val),\
145                                               &shadow_ring_context->name.val, 4);\
146                 shadow_ring_context->name.val |= 0xffff << 16;\
147         }
148
149         COPY_REG_MASKED(ctx_ctrl);
150         COPY_REG(ctx_timestamp);
151
152         if (ring_id == RCS) {
153                 COPY_REG(bb_per_ctx_ptr);
154                 COPY_REG(rcs_indirect_ctx);
155                 COPY_REG(rcs_indirect_ctx_offset);
156         }
157 #undef COPY_REG
158 #undef COPY_REG_MASKED
159
160         intel_gvt_hypervisor_read_gpa(vgpu,
161                         workload->ring_context_gpa +
162                         sizeof(*shadow_ring_context),
163                         (void *)shadow_ring_context +
164                         sizeof(*shadow_ring_context),
165                         I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
166
167         sr_oa_regs(workload, (u32 *)shadow_ring_context, false);
168         kunmap(page);
169
170         if (IS_RESTORE_INHIBIT(shadow_ring_context->ctx_ctrl.val))
171                 return 0;
172
173         gvt_dbg_sched("ring id %d workload lrca %x", ring_id,
174                         workload->ctx_desc.lrca);
175
176         context_page_num = gvt->dev_priv->engine[ring_id]->context_size;
177
178         context_page_num = context_page_num >> PAGE_SHIFT;
179
180         if (IS_BROADWELL(gvt->dev_priv) && ring_id == RCS)
181                 context_page_num = 19;
182
183         i = 2;
184         while (i < context_page_num) {
185                 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
186                                 (u32)((workload->ctx_desc.lrca + i) <<
187                                 I915_GTT_PAGE_SHIFT));
188                 if (context_gpa == INTEL_GVT_INVALID_ADDR) {
189                         gvt_vgpu_err("Invalid guest context descriptor\n");
190                         return -EFAULT;
191                 }
192
193                 page = i915_gem_object_get_page(ctx_obj, LRC_HEADER_PAGES + i);
194                 dst = kmap(page);
195                 intel_gvt_hypervisor_read_gpa(vgpu, context_gpa, dst,
196                                 I915_GTT_PAGE_SIZE);
197                 kunmap(page);
198                 i++;
199         }
200         return 0;
201 }
202
203 static inline bool is_gvt_request(struct i915_request *req)
204 {
205         return i915_gem_context_force_single_submission(req->gem_context);
206 }
207
208 static void save_ring_hw_state(struct intel_vgpu *vgpu, int ring_id)
209 {
210         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
211         u32 ring_base = dev_priv->engine[ring_id]->mmio_base;
212         i915_reg_t reg;
213
214         reg = RING_INSTDONE(ring_base);
215         vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
216         reg = RING_ACTHD(ring_base);
217         vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
218         reg = RING_ACTHD_UDW(ring_base);
219         vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
220 }
221
222 static int shadow_context_status_change(struct notifier_block *nb,
223                 unsigned long action, void *data)
224 {
225         struct i915_request *req = data;
226         struct intel_gvt *gvt = container_of(nb, struct intel_gvt,
227                                 shadow_ctx_notifier_block[req->engine->id]);
228         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
229         enum intel_engine_id ring_id = req->engine->id;
230         struct intel_vgpu_workload *workload;
231         unsigned long flags;
232
233         if (!is_gvt_request(req)) {
234                 spin_lock_irqsave(&scheduler->mmio_context_lock, flags);
235                 if (action == INTEL_CONTEXT_SCHEDULE_IN &&
236                     scheduler->engine_owner[ring_id]) {
237                         /* Switch ring from vGPU to host. */
238                         intel_gvt_switch_mmio(scheduler->engine_owner[ring_id],
239                                               NULL, ring_id);
240                         scheduler->engine_owner[ring_id] = NULL;
241                 }
242                 spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags);
243
244                 return NOTIFY_OK;
245         }
246
247         workload = scheduler->current_workload[ring_id];
248         if (unlikely(!workload))
249                 return NOTIFY_OK;
250
251         switch (action) {
252         case INTEL_CONTEXT_SCHEDULE_IN:
253                 spin_lock_irqsave(&scheduler->mmio_context_lock, flags);
254                 if (workload->vgpu != scheduler->engine_owner[ring_id]) {
255                         /* Switch ring from host to vGPU or vGPU to vGPU. */
256                         intel_gvt_switch_mmio(scheduler->engine_owner[ring_id],
257                                               workload->vgpu, ring_id);
258                         scheduler->engine_owner[ring_id] = workload->vgpu;
259                 } else
260                         gvt_dbg_sched("skip ring %d mmio switch for vgpu%d\n",
261                                       ring_id, workload->vgpu->id);
262                 spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags);
263                 atomic_set(&workload->shadow_ctx_active, 1);
264                 break;
265         case INTEL_CONTEXT_SCHEDULE_OUT:
266                 save_ring_hw_state(workload->vgpu, ring_id);
267                 atomic_set(&workload->shadow_ctx_active, 0);
268                 break;
269         case INTEL_CONTEXT_SCHEDULE_PREEMPTED:
270                 save_ring_hw_state(workload->vgpu, ring_id);
271                 break;
272         default:
273                 WARN_ON(1);
274                 return NOTIFY_OK;
275         }
276         wake_up(&workload->shadow_ctx_status_wq);
277         return NOTIFY_OK;
278 }
279
280 static void shadow_context_descriptor_update(struct intel_context *ce)
281 {
282         u64 desc = 0;
283
284         desc = ce->lrc_desc;
285
286         /* Update bits 0-11 of the context descriptor which includes flags
287          * like GEN8_CTX_* cached in desc_template
288          */
289         desc &= U64_MAX << 12;
290         desc |= ce->gem_context->desc_template & ((1ULL << 12) - 1);
291
292         ce->lrc_desc = desc;
293 }
294
295 static int copy_workload_to_ring_buffer(struct intel_vgpu_workload *workload)
296 {
297         struct intel_vgpu *vgpu = workload->vgpu;
298         struct i915_request *req = workload->req;
299         void *shadow_ring_buffer_va;
300         u32 *cs;
301
302         if ((IS_KABYLAKE(req->i915) || IS_BROXTON(req->i915)
303                 || IS_COFFEELAKE(req->i915))
304                 && is_inhibit_context(req->hw_context))
305                 intel_vgpu_restore_inhibit_context(vgpu, req);
306
307         /* allocate shadow ring buffer */
308         cs = intel_ring_begin(workload->req, workload->rb_len / sizeof(u32));
309         if (IS_ERR(cs)) {
310                 gvt_vgpu_err("fail to alloc size =%ld shadow  ring buffer\n",
311                         workload->rb_len);
312                 return PTR_ERR(cs);
313         }
314
315         shadow_ring_buffer_va = workload->shadow_ring_buffer_va;
316
317         /* get shadow ring buffer va */
318         workload->shadow_ring_buffer_va = cs;
319
320         memcpy(cs, shadow_ring_buffer_va,
321                         workload->rb_len);
322
323         cs += workload->rb_len / sizeof(u32);
324         intel_ring_advance(workload->req, cs);
325
326         return 0;
327 }
328
329 static void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
330 {
331         if (!wa_ctx->indirect_ctx.obj)
332                 return;
333
334         i915_gem_object_unpin_map(wa_ctx->indirect_ctx.obj);
335         i915_gem_object_put(wa_ctx->indirect_ctx.obj);
336
337         wa_ctx->indirect_ctx.obj = NULL;
338         wa_ctx->indirect_ctx.shadow_va = NULL;
339 }
340
341 static int set_context_ppgtt_from_shadow(struct intel_vgpu_workload *workload,
342                                          struct i915_gem_context *ctx)
343 {
344         struct intel_vgpu_mm *mm = workload->shadow_mm;
345         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
346         int i = 0;
347
348         if (mm->type != INTEL_GVT_MM_PPGTT || !mm->ppgtt_mm.shadowed)
349                 return -EINVAL;
350
351         if (mm->ppgtt_mm.root_entry_type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
352                 px_dma(&ppgtt->pml4) = mm->ppgtt_mm.shadow_pdps[0];
353         } else {
354                 for (i = 0; i < GVT_RING_CTX_NR_PDPS; i++) {
355                         px_dma(ppgtt->pdp.page_directory[i]) =
356                                 mm->ppgtt_mm.shadow_pdps[i];
357                 }
358         }
359
360         return 0;
361 }
362
363 static int
364 intel_gvt_workload_req_alloc(struct intel_vgpu_workload *workload)
365 {
366         struct intel_vgpu *vgpu = workload->vgpu;
367         struct intel_vgpu_submission *s = &vgpu->submission;
368         struct i915_gem_context *shadow_ctx = s->shadow_ctx;
369         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
370         struct intel_engine_cs *engine = dev_priv->engine[workload->ring_id];
371         struct i915_request *rq;
372         int ret = 0;
373
374         lockdep_assert_held(&dev_priv->drm.struct_mutex);
375
376         if (workload->req)
377                 goto out;
378
379         rq = i915_request_alloc(engine, shadow_ctx);
380         if (IS_ERR(rq)) {
381                 gvt_vgpu_err("fail to allocate gem request\n");
382                 ret = PTR_ERR(rq);
383                 goto out;
384         }
385         workload->req = i915_request_get(rq);
386 out:
387         return ret;
388 }
389
390 /**
391  * intel_gvt_scan_and_shadow_workload - audit the workload by scanning and
392  * shadow it as well, include ringbuffer,wa_ctx and ctx.
393  * @workload: an abstract entity for each execlist submission.
394  *
395  * This function is called before the workload submitting to i915, to make
396  * sure the content of the workload is valid.
397  */
398 int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload)
399 {
400         struct intel_vgpu *vgpu = workload->vgpu;
401         struct intel_vgpu_submission *s = &vgpu->submission;
402         struct i915_gem_context *shadow_ctx = s->shadow_ctx;
403         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
404         struct intel_engine_cs *engine = dev_priv->engine[workload->ring_id];
405         struct intel_context *ce;
406         int ret;
407
408         lockdep_assert_held(&dev_priv->drm.struct_mutex);
409
410         if (workload->shadow)
411                 return 0;
412
413         /* pin shadow context by gvt even the shadow context will be pinned
414          * when i915 alloc request. That is because gvt will update the guest
415          * context from shadow context when workload is completed, and at that
416          * moment, i915 may already unpined the shadow context to make the
417          * shadow_ctx pages invalid. So gvt need to pin itself. After update
418          * the guest context, gvt can unpin the shadow_ctx safely.
419          */
420         ce = intel_context_pin(shadow_ctx, engine);
421         if (IS_ERR(ce)) {
422                 gvt_vgpu_err("fail to pin shadow context\n");
423                 return PTR_ERR(ce);
424         }
425
426         shadow_ctx->desc_template &= ~(0x3 << GEN8_CTX_ADDRESSING_MODE_SHIFT);
427         shadow_ctx->desc_template |= workload->ctx_desc.addressing_mode <<
428                                     GEN8_CTX_ADDRESSING_MODE_SHIFT;
429
430         if (!test_and_set_bit(workload->ring_id, s->shadow_ctx_desc_updated))
431                 shadow_context_descriptor_update(ce);
432
433         ret = intel_gvt_scan_and_shadow_ringbuffer(workload);
434         if (ret)
435                 goto err_unpin;
436
437         if ((workload->ring_id == RCS) &&
438             (workload->wa_ctx.indirect_ctx.size != 0)) {
439                 ret = intel_gvt_scan_and_shadow_wa_ctx(&workload->wa_ctx);
440                 if (ret)
441                         goto err_shadow;
442         }
443
444         workload->shadow = true;
445         return 0;
446 err_shadow:
447         release_shadow_wa_ctx(&workload->wa_ctx);
448 err_unpin:
449         intel_context_unpin(ce);
450         return ret;
451 }
452
453 static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload);
454
455 static int prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload)
456 {
457         struct intel_gvt *gvt = workload->vgpu->gvt;
458         const int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
459         struct intel_vgpu_shadow_bb *bb;
460         int ret;
461
462         list_for_each_entry(bb, &workload->shadow_bb, list) {
463                 /* For privilge batch buffer and not wa_ctx, the bb_start_cmd_va
464                  * is only updated into ring_scan_buffer, not real ring address
465                  * allocated in later copy_workload_to_ring_buffer. pls be noted
466                  * shadow_ring_buffer_va is now pointed to real ring buffer va
467                  * in copy_workload_to_ring_buffer.
468                  */
469
470                 if (bb->bb_offset)
471                         bb->bb_start_cmd_va = workload->shadow_ring_buffer_va
472                                 + bb->bb_offset;
473
474                 if (bb->ppgtt) {
475                         /* for non-priv bb, scan&shadow is only for
476                          * debugging purpose, so the content of shadow bb
477                          * is the same as original bb. Therefore,
478                          * here, rather than switch to shadow bb's gma
479                          * address, we directly use original batch buffer's
480                          * gma address, and send original bb to hardware
481                          * directly
482                          */
483                         if (bb->clflush & CLFLUSH_AFTER) {
484                                 drm_clflush_virt_range(bb->va,
485                                                 bb->obj->base.size);
486                                 bb->clflush &= ~CLFLUSH_AFTER;
487                         }
488                         i915_gem_obj_finish_shmem_access(bb->obj);
489                         bb->accessing = false;
490
491                 } else {
492                         bb->vma = i915_gem_object_ggtt_pin(bb->obj,
493                                         NULL, 0, 0, 0);
494                         if (IS_ERR(bb->vma)) {
495                                 ret = PTR_ERR(bb->vma);
496                                 goto err;
497                         }
498
499                         /* relocate shadow batch buffer */
500                         bb->bb_start_cmd_va[1] = i915_ggtt_offset(bb->vma);
501                         if (gmadr_bytes == 8)
502                                 bb->bb_start_cmd_va[2] = 0;
503
504                         /* No one is going to touch shadow bb from now on. */
505                         if (bb->clflush & CLFLUSH_AFTER) {
506                                 drm_clflush_virt_range(bb->va,
507                                                 bb->obj->base.size);
508                                 bb->clflush &= ~CLFLUSH_AFTER;
509                         }
510
511                         ret = i915_gem_object_set_to_gtt_domain(bb->obj,
512                                         false);
513                         if (ret)
514                                 goto err;
515
516                         i915_gem_obj_finish_shmem_access(bb->obj);
517                         bb->accessing = false;
518
519                         ret = i915_vma_move_to_active(bb->vma,
520                                                       workload->req,
521                                                       0);
522                         if (ret)
523                                 goto err;
524                 }
525         }
526         return 0;
527 err:
528         release_shadow_batch_buffer(workload);
529         return ret;
530 }
531
532 static void update_wa_ctx_2_shadow_ctx(struct intel_shadow_wa_ctx *wa_ctx)
533 {
534         struct intel_vgpu_workload *workload =
535                 container_of(wa_ctx, struct intel_vgpu_workload, wa_ctx);
536         struct i915_request *rq = workload->req;
537         struct execlist_ring_context *shadow_ring_context =
538                 (struct execlist_ring_context *)rq->hw_context->lrc_reg_state;
539
540         shadow_ring_context->bb_per_ctx_ptr.val =
541                 (shadow_ring_context->bb_per_ctx_ptr.val &
542                 (~PER_CTX_ADDR_MASK)) | wa_ctx->per_ctx.shadow_gma;
543         shadow_ring_context->rcs_indirect_ctx.val =
544                 (shadow_ring_context->rcs_indirect_ctx.val &
545                 (~INDIRECT_CTX_ADDR_MASK)) | wa_ctx->indirect_ctx.shadow_gma;
546 }
547
548 static int prepare_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
549 {
550         struct i915_vma *vma;
551         unsigned char *per_ctx_va =
552                 (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
553                 wa_ctx->indirect_ctx.size;
554
555         if (wa_ctx->indirect_ctx.size == 0)
556                 return 0;
557
558         vma = i915_gem_object_ggtt_pin(wa_ctx->indirect_ctx.obj, NULL,
559                                        0, CACHELINE_BYTES, 0);
560         if (IS_ERR(vma))
561                 return PTR_ERR(vma);
562
563         /* FIXME: we are not tracking our pinned VMA leaving it
564          * up to the core to fix up the stray pin_count upon
565          * free.
566          */
567
568         wa_ctx->indirect_ctx.shadow_gma = i915_ggtt_offset(vma);
569
570         wa_ctx->per_ctx.shadow_gma = *((unsigned int *)per_ctx_va + 1);
571         memset(per_ctx_va, 0, CACHELINE_BYTES);
572
573         update_wa_ctx_2_shadow_ctx(wa_ctx);
574         return 0;
575 }
576
577 static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload)
578 {
579         struct intel_vgpu *vgpu = workload->vgpu;
580         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
581         struct intel_vgpu_shadow_bb *bb, *pos;
582
583         if (list_empty(&workload->shadow_bb))
584                 return;
585
586         bb = list_first_entry(&workload->shadow_bb,
587                         struct intel_vgpu_shadow_bb, list);
588
589         mutex_lock(&dev_priv->drm.struct_mutex);
590
591         list_for_each_entry_safe(bb, pos, &workload->shadow_bb, list) {
592                 if (bb->obj) {
593                         if (bb->accessing)
594                                 i915_gem_obj_finish_shmem_access(bb->obj);
595
596                         if (bb->va && !IS_ERR(bb->va))
597                                 i915_gem_object_unpin_map(bb->obj);
598
599                         if (bb->vma && !IS_ERR(bb->vma)) {
600                                 i915_vma_unpin(bb->vma);
601                                 i915_vma_close(bb->vma);
602                         }
603                         __i915_gem_object_release_unless_active(bb->obj);
604                 }
605                 list_del(&bb->list);
606                 kfree(bb);
607         }
608
609         mutex_unlock(&dev_priv->drm.struct_mutex);
610 }
611
612 static int prepare_workload(struct intel_vgpu_workload *workload)
613 {
614         struct intel_vgpu *vgpu = workload->vgpu;
615         int ret = 0;
616
617         ret = intel_vgpu_pin_mm(workload->shadow_mm);
618         if (ret) {
619                 gvt_vgpu_err("fail to vgpu pin mm\n");
620                 return ret;
621         }
622
623         update_shadow_pdps(workload);
624
625         ret = intel_vgpu_sync_oos_pages(workload->vgpu);
626         if (ret) {
627                 gvt_vgpu_err("fail to vgpu sync oos pages\n");
628                 goto err_unpin_mm;
629         }
630
631         ret = intel_vgpu_flush_post_shadow(workload->vgpu);
632         if (ret) {
633                 gvt_vgpu_err("fail to flush post shadow\n");
634                 goto err_unpin_mm;
635         }
636
637         ret = copy_workload_to_ring_buffer(workload);
638         if (ret) {
639                 gvt_vgpu_err("fail to generate request\n");
640                 goto err_unpin_mm;
641         }
642
643         ret = prepare_shadow_batch_buffer(workload);
644         if (ret) {
645                 gvt_vgpu_err("fail to prepare_shadow_batch_buffer\n");
646                 goto err_unpin_mm;
647         }
648
649         ret = prepare_shadow_wa_ctx(&workload->wa_ctx);
650         if (ret) {
651                 gvt_vgpu_err("fail to prepare_shadow_wa_ctx\n");
652                 goto err_shadow_batch;
653         }
654
655         if (workload->prepare) {
656                 ret = workload->prepare(workload);
657                 if (ret)
658                         goto err_shadow_wa_ctx;
659         }
660
661         return 0;
662 err_shadow_wa_ctx:
663         release_shadow_wa_ctx(&workload->wa_ctx);
664 err_shadow_batch:
665         release_shadow_batch_buffer(workload);
666 err_unpin_mm:
667         intel_vgpu_unpin_mm(workload->shadow_mm);
668         return ret;
669 }
670
671 static int dispatch_workload(struct intel_vgpu_workload *workload)
672 {
673         struct intel_vgpu *vgpu = workload->vgpu;
674         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
675         struct intel_vgpu_submission *s = &vgpu->submission;
676         struct i915_gem_context *shadow_ctx = s->shadow_ctx;
677         struct i915_request *rq;
678         int ring_id = workload->ring_id;
679         int ret;
680
681         gvt_dbg_sched("ring id %d prepare to dispatch workload %p\n",
682                 ring_id, workload);
683
684         mutex_lock(&vgpu->vgpu_lock);
685         mutex_lock(&dev_priv->drm.struct_mutex);
686
687         ret = set_context_ppgtt_from_shadow(workload, shadow_ctx);
688         if (ret < 0) {
689                 gvt_vgpu_err("workload shadow ppgtt isn't ready\n");
690                 goto err_req;
691         }
692
693         ret = intel_gvt_workload_req_alloc(workload);
694         if (ret)
695                 goto err_req;
696
697         ret = intel_gvt_scan_and_shadow_workload(workload);
698         if (ret)
699                 goto out;
700
701         ret = populate_shadow_context(workload);
702         if (ret) {
703                 release_shadow_wa_ctx(&workload->wa_ctx);
704                 goto out;
705         }
706
707         ret = prepare_workload(workload);
708 out:
709         if (ret) {
710                 /* We might still need to add request with
711                  * clean ctx to retire it properly..
712                  */
713                 rq = fetch_and_zero(&workload->req);
714                 i915_request_put(rq);
715         }
716
717         if (!IS_ERR_OR_NULL(workload->req)) {
718                 gvt_dbg_sched("ring id %d submit workload to i915 %p\n",
719                                 ring_id, workload->req);
720                 i915_request_add(workload->req);
721                 workload->dispatched = true;
722         }
723 err_req:
724         if (ret)
725                 workload->status = ret;
726         mutex_unlock(&dev_priv->drm.struct_mutex);
727         mutex_unlock(&vgpu->vgpu_lock);
728         return ret;
729 }
730
731 static struct intel_vgpu_workload *pick_next_workload(
732                 struct intel_gvt *gvt, int ring_id)
733 {
734         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
735         struct intel_vgpu_workload *workload = NULL;
736
737         mutex_lock(&gvt->sched_lock);
738
739         /*
740          * no current vgpu / will be scheduled out / no workload
741          * bail out
742          */
743         if (!scheduler->current_vgpu) {
744                 gvt_dbg_sched("ring id %d stop - no current vgpu\n", ring_id);
745                 goto out;
746         }
747
748         if (scheduler->need_reschedule) {
749                 gvt_dbg_sched("ring id %d stop - will reschedule\n", ring_id);
750                 goto out;
751         }
752
753         if (!scheduler->current_vgpu->active ||
754             list_empty(workload_q_head(scheduler->current_vgpu, ring_id)))
755                 goto out;
756
757         /*
758          * still have current workload, maybe the workload disptacher
759          * fail to submit it for some reason, resubmit it.
760          */
761         if (scheduler->current_workload[ring_id]) {
762                 workload = scheduler->current_workload[ring_id];
763                 gvt_dbg_sched("ring id %d still have current workload %p\n",
764                                 ring_id, workload);
765                 goto out;
766         }
767
768         /*
769          * pick a workload as current workload
770          * once current workload is set, schedule policy routines
771          * will wait the current workload is finished when trying to
772          * schedule out a vgpu.
773          */
774         scheduler->current_workload[ring_id] = container_of(
775                         workload_q_head(scheduler->current_vgpu, ring_id)->next,
776                         struct intel_vgpu_workload, list);
777
778         workload = scheduler->current_workload[ring_id];
779
780         gvt_dbg_sched("ring id %d pick new workload %p\n", ring_id, workload);
781
782         atomic_inc(&workload->vgpu->submission.running_workload_num);
783 out:
784         mutex_unlock(&gvt->sched_lock);
785         return workload;
786 }
787
788 static void update_guest_context(struct intel_vgpu_workload *workload)
789 {
790         struct i915_request *rq = workload->req;
791         struct intel_vgpu *vgpu = workload->vgpu;
792         struct intel_gvt *gvt = vgpu->gvt;
793         struct drm_i915_gem_object *ctx_obj = rq->hw_context->state->obj;
794         struct execlist_ring_context *shadow_ring_context;
795         struct page *page;
796         void *src;
797         unsigned long context_gpa, context_page_num;
798         int i;
799
800         gvt_dbg_sched("ring id %d workload lrca %x\n", rq->engine->id,
801                       workload->ctx_desc.lrca);
802
803         context_page_num = rq->engine->context_size;
804         context_page_num = context_page_num >> PAGE_SHIFT;
805
806         if (IS_BROADWELL(gvt->dev_priv) && rq->engine->id == RCS)
807                 context_page_num = 19;
808
809         i = 2;
810
811         while (i < context_page_num) {
812                 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
813                                 (u32)((workload->ctx_desc.lrca + i) <<
814                                         I915_GTT_PAGE_SHIFT));
815                 if (context_gpa == INTEL_GVT_INVALID_ADDR) {
816                         gvt_vgpu_err("invalid guest context descriptor\n");
817                         return;
818                 }
819
820                 page = i915_gem_object_get_page(ctx_obj, LRC_HEADER_PAGES + i);
821                 src = kmap(page);
822                 intel_gvt_hypervisor_write_gpa(vgpu, context_gpa, src,
823                                 I915_GTT_PAGE_SIZE);
824                 kunmap(page);
825                 i++;
826         }
827
828         intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa +
829                 RING_CTX_OFF(ring_header.val), &workload->rb_tail, 4);
830
831         page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
832         shadow_ring_context = kmap(page);
833
834 #define COPY_REG(name) \
835         intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa + \
836                 RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
837
838         COPY_REG(ctx_ctrl);
839         COPY_REG(ctx_timestamp);
840
841 #undef COPY_REG
842
843         intel_gvt_hypervisor_write_gpa(vgpu,
844                         workload->ring_context_gpa +
845                         sizeof(*shadow_ring_context),
846                         (void *)shadow_ring_context +
847                         sizeof(*shadow_ring_context),
848                         I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
849
850         kunmap(page);
851 }
852
853 void intel_vgpu_clean_workloads(struct intel_vgpu *vgpu,
854                                 unsigned long engine_mask)
855 {
856         struct intel_vgpu_submission *s = &vgpu->submission;
857         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
858         struct intel_engine_cs *engine;
859         struct intel_vgpu_workload *pos, *n;
860         unsigned int tmp;
861
862         /* free the unsubmited workloads in the queues. */
863         for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
864                 list_for_each_entry_safe(pos, n,
865                         &s->workload_q_head[engine->id], list) {
866                         list_del_init(&pos->list);
867                         intel_vgpu_destroy_workload(pos);
868                 }
869                 clear_bit(engine->id, s->shadow_ctx_desc_updated);
870         }
871 }
872
873 static void complete_current_workload(struct intel_gvt *gvt, int ring_id)
874 {
875         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
876         struct intel_vgpu_workload *workload =
877                 scheduler->current_workload[ring_id];
878         struct intel_vgpu *vgpu = workload->vgpu;
879         struct intel_vgpu_submission *s = &vgpu->submission;
880         struct i915_request *rq = workload->req;
881         int event;
882
883         mutex_lock(&vgpu->vgpu_lock);
884         mutex_lock(&gvt->sched_lock);
885
886         /* For the workload w/ request, needs to wait for the context
887          * switch to make sure request is completed.
888          * For the workload w/o request, directly complete the workload.
889          */
890         if (rq) {
891                 wait_event(workload->shadow_ctx_status_wq,
892                            !atomic_read(&workload->shadow_ctx_active));
893
894                 /* If this request caused GPU hang, req->fence.error will
895                  * be set to -EIO. Use -EIO to set workload status so
896                  * that when this request caused GPU hang, didn't trigger
897                  * context switch interrupt to guest.
898                  */
899                 if (likely(workload->status == -EINPROGRESS)) {
900                         if (workload->req->fence.error == -EIO)
901                                 workload->status = -EIO;
902                         else
903                                 workload->status = 0;
904                 }
905
906                 if (!workload->status && !(vgpu->resetting_eng &
907                                            ENGINE_MASK(ring_id))) {
908                         update_guest_context(workload);
909
910                         for_each_set_bit(event, workload->pending_events,
911                                          INTEL_GVT_EVENT_MAX)
912                                 intel_vgpu_trigger_virtual_event(vgpu, event);
913                 }
914
915                 /* unpin shadow ctx as the shadow_ctx update is done */
916                 mutex_lock(&rq->i915->drm.struct_mutex);
917                 intel_context_unpin(rq->hw_context);
918                 mutex_unlock(&rq->i915->drm.struct_mutex);
919
920                 i915_request_put(fetch_and_zero(&workload->req));
921         }
922
923         gvt_dbg_sched("ring id %d complete workload %p status %d\n",
924                         ring_id, workload, workload->status);
925
926         scheduler->current_workload[ring_id] = NULL;
927
928         list_del_init(&workload->list);
929
930         if (workload->status || (vgpu->resetting_eng & ENGINE_MASK(ring_id))) {
931                 /* if workload->status is not successful means HW GPU
932                  * has occurred GPU hang or something wrong with i915/GVT,
933                  * and GVT won't inject context switch interrupt to guest.
934                  * So this error is a vGPU hang actually to the guest.
935                  * According to this we should emunlate a vGPU hang. If
936                  * there are pending workloads which are already submitted
937                  * from guest, we should clean them up like HW GPU does.
938                  *
939                  * if it is in middle of engine resetting, the pending
940                  * workloads won't be submitted to HW GPU and will be
941                  * cleaned up during the resetting process later, so doing
942                  * the workload clean up here doesn't have any impact.
943                  **/
944                 intel_vgpu_clean_workloads(vgpu, ENGINE_MASK(ring_id));
945         }
946
947         workload->complete(workload);
948
949         atomic_dec(&s->running_workload_num);
950         wake_up(&scheduler->workload_complete_wq);
951
952         if (gvt->scheduler.need_reschedule)
953                 intel_gvt_request_service(gvt, INTEL_GVT_REQUEST_EVENT_SCHED);
954
955         mutex_unlock(&gvt->sched_lock);
956         mutex_unlock(&vgpu->vgpu_lock);
957 }
958
959 struct workload_thread_param {
960         struct intel_gvt *gvt;
961         int ring_id;
962 };
963
964 static int workload_thread(void *priv)
965 {
966         struct workload_thread_param *p = (struct workload_thread_param *)priv;
967         struct intel_gvt *gvt = p->gvt;
968         int ring_id = p->ring_id;
969         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
970         struct intel_vgpu_workload *workload = NULL;
971         struct intel_vgpu *vgpu = NULL;
972         int ret;
973         bool need_force_wake = (INTEL_GEN(gvt->dev_priv) >= 9);
974         DEFINE_WAIT_FUNC(wait, woken_wake_function);
975
976         kfree(p);
977
978         gvt_dbg_core("workload thread for ring %d started\n", ring_id);
979
980         while (!kthread_should_stop()) {
981                 add_wait_queue(&scheduler->waitq[ring_id], &wait);
982                 do {
983                         workload = pick_next_workload(gvt, ring_id);
984                         if (workload)
985                                 break;
986                         wait_woken(&wait, TASK_INTERRUPTIBLE,
987                                    MAX_SCHEDULE_TIMEOUT);
988                 } while (!kthread_should_stop());
989                 remove_wait_queue(&scheduler->waitq[ring_id], &wait);
990
991                 if (!workload)
992                         break;
993
994                 gvt_dbg_sched("ring id %d next workload %p vgpu %d\n",
995                                 workload->ring_id, workload,
996                                 workload->vgpu->id);
997
998                 intel_runtime_pm_get(gvt->dev_priv);
999
1000                 gvt_dbg_sched("ring id %d will dispatch workload %p\n",
1001                                 workload->ring_id, workload);
1002
1003                 if (need_force_wake)
1004                         intel_uncore_forcewake_get(gvt->dev_priv,
1005                                         FORCEWAKE_ALL);
1006
1007                 ret = dispatch_workload(workload);
1008
1009                 if (ret) {
1010                         vgpu = workload->vgpu;
1011                         gvt_vgpu_err("fail to dispatch workload, skip\n");
1012                         goto complete;
1013                 }
1014
1015                 gvt_dbg_sched("ring id %d wait workload %p\n",
1016                                 workload->ring_id, workload);
1017                 i915_request_wait(workload->req, 0, MAX_SCHEDULE_TIMEOUT);
1018
1019 complete:
1020                 gvt_dbg_sched("will complete workload %p, status: %d\n",
1021                                 workload, workload->status);
1022
1023                 complete_current_workload(gvt, ring_id);
1024
1025                 if (need_force_wake)
1026                         intel_uncore_forcewake_put(gvt->dev_priv,
1027                                         FORCEWAKE_ALL);
1028
1029                 intel_runtime_pm_put_unchecked(gvt->dev_priv);
1030                 if (ret && (vgpu_is_vm_unhealthy(ret)))
1031                         enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR);
1032         }
1033         return 0;
1034 }
1035
1036 void intel_gvt_wait_vgpu_idle(struct intel_vgpu *vgpu)
1037 {
1038         struct intel_vgpu_submission *s = &vgpu->submission;
1039         struct intel_gvt *gvt = vgpu->gvt;
1040         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1041
1042         if (atomic_read(&s->running_workload_num)) {
1043                 gvt_dbg_sched("wait vgpu idle\n");
1044
1045                 wait_event(scheduler->workload_complete_wq,
1046                                 !atomic_read(&s->running_workload_num));
1047         }
1048 }
1049
1050 void intel_gvt_clean_workload_scheduler(struct intel_gvt *gvt)
1051 {
1052         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1053         struct intel_engine_cs *engine;
1054         enum intel_engine_id i;
1055
1056         gvt_dbg_core("clean workload scheduler\n");
1057
1058         for_each_engine(engine, gvt->dev_priv, i) {
1059                 atomic_notifier_chain_unregister(
1060                                         &engine->context_status_notifier,
1061                                         &gvt->shadow_ctx_notifier_block[i]);
1062                 kthread_stop(scheduler->thread[i]);
1063         }
1064 }
1065
1066 int intel_gvt_init_workload_scheduler(struct intel_gvt *gvt)
1067 {
1068         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1069         struct workload_thread_param *param = NULL;
1070         struct intel_engine_cs *engine;
1071         enum intel_engine_id i;
1072         int ret;
1073
1074         gvt_dbg_core("init workload scheduler\n");
1075
1076         init_waitqueue_head(&scheduler->workload_complete_wq);
1077
1078         for_each_engine(engine, gvt->dev_priv, i) {
1079                 init_waitqueue_head(&scheduler->waitq[i]);
1080
1081                 param = kzalloc(sizeof(*param), GFP_KERNEL);
1082                 if (!param) {
1083                         ret = -ENOMEM;
1084                         goto err;
1085                 }
1086
1087                 param->gvt = gvt;
1088                 param->ring_id = i;
1089
1090                 scheduler->thread[i] = kthread_run(workload_thread, param,
1091                         "gvt workload %d", i);
1092                 if (IS_ERR(scheduler->thread[i])) {
1093                         gvt_err("fail to create workload thread\n");
1094                         ret = PTR_ERR(scheduler->thread[i]);
1095                         goto err;
1096                 }
1097
1098                 gvt->shadow_ctx_notifier_block[i].notifier_call =
1099                                         shadow_context_status_change;
1100                 atomic_notifier_chain_register(&engine->context_status_notifier,
1101                                         &gvt->shadow_ctx_notifier_block[i]);
1102         }
1103         return 0;
1104 err:
1105         intel_gvt_clean_workload_scheduler(gvt);
1106         kfree(param);
1107         param = NULL;
1108         return ret;
1109 }
1110
1111 static void
1112 i915_context_ppgtt_root_restore(struct intel_vgpu_submission *s)
1113 {
1114         struct i915_hw_ppgtt *i915_ppgtt = s->shadow_ctx->ppgtt;
1115         int i;
1116
1117         if (i915_vm_is_48bit(&i915_ppgtt->vm))
1118                 px_dma(&i915_ppgtt->pml4) = s->i915_context_pml4;
1119         else {
1120                 for (i = 0; i < GEN8_3LVL_PDPES; i++)
1121                         px_dma(i915_ppgtt->pdp.page_directory[i]) =
1122                                                 s->i915_context_pdps[i];
1123         }
1124 }
1125
1126 /**
1127  * intel_vgpu_clean_submission - free submission-related resource for vGPU
1128  * @vgpu: a vGPU
1129  *
1130  * This function is called when a vGPU is being destroyed.
1131  *
1132  */
1133 void intel_vgpu_clean_submission(struct intel_vgpu *vgpu)
1134 {
1135         struct intel_vgpu_submission *s = &vgpu->submission;
1136
1137         intel_vgpu_select_submission_ops(vgpu, ALL_ENGINES, 0);
1138         i915_context_ppgtt_root_restore(s);
1139         i915_gem_context_put(s->shadow_ctx);
1140         kmem_cache_destroy(s->workloads);
1141 }
1142
1143
1144 /**
1145  * intel_vgpu_reset_submission - reset submission-related resource for vGPU
1146  * @vgpu: a vGPU
1147  * @engine_mask: engines expected to be reset
1148  *
1149  * This function is called when a vGPU is being destroyed.
1150  *
1151  */
1152 void intel_vgpu_reset_submission(struct intel_vgpu *vgpu,
1153                 unsigned long engine_mask)
1154 {
1155         struct intel_vgpu_submission *s = &vgpu->submission;
1156
1157         if (!s->active)
1158                 return;
1159
1160         intel_vgpu_clean_workloads(vgpu, engine_mask);
1161         s->ops->reset(vgpu, engine_mask);
1162 }
1163
1164 static void
1165 i915_context_ppgtt_root_save(struct intel_vgpu_submission *s)
1166 {
1167         struct i915_hw_ppgtt *i915_ppgtt = s->shadow_ctx->ppgtt;
1168         int i;
1169
1170         if (i915_vm_is_48bit(&i915_ppgtt->vm))
1171                 s->i915_context_pml4 = px_dma(&i915_ppgtt->pml4);
1172         else {
1173                 for (i = 0; i < GEN8_3LVL_PDPES; i++)
1174                         s->i915_context_pdps[i] =
1175                                 px_dma(i915_ppgtt->pdp.page_directory[i]);
1176         }
1177 }
1178
1179 /**
1180  * intel_vgpu_setup_submission - setup submission-related resource for vGPU
1181  * @vgpu: a vGPU
1182  *
1183  * This function is called when a vGPU is being created.
1184  *
1185  * Returns:
1186  * Zero on success, negative error code if failed.
1187  *
1188  */
1189 int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
1190 {
1191         struct intel_vgpu_submission *s = &vgpu->submission;
1192         enum intel_engine_id i;
1193         struct intel_engine_cs *engine;
1194         int ret;
1195
1196         s->shadow_ctx = i915_gem_context_create_gvt(
1197                         &vgpu->gvt->dev_priv->drm);
1198         if (IS_ERR(s->shadow_ctx))
1199                 return PTR_ERR(s->shadow_ctx);
1200
1201         i915_context_ppgtt_root_save(s);
1202
1203         bitmap_zero(s->shadow_ctx_desc_updated, I915_NUM_ENGINES);
1204
1205         s->workloads = kmem_cache_create_usercopy("gvt-g_vgpu_workload",
1206                                                   sizeof(struct intel_vgpu_workload), 0,
1207                                                   SLAB_HWCACHE_ALIGN,
1208                                                   offsetof(struct intel_vgpu_workload, rb_tail),
1209                                                   sizeof_field(struct intel_vgpu_workload, rb_tail),
1210                                                   NULL);
1211
1212         if (!s->workloads) {
1213                 ret = -ENOMEM;
1214                 goto out_shadow_ctx;
1215         }
1216
1217         for_each_engine(engine, vgpu->gvt->dev_priv, i)
1218                 INIT_LIST_HEAD(&s->workload_q_head[i]);
1219
1220         atomic_set(&s->running_workload_num, 0);
1221         bitmap_zero(s->tlb_handle_pending, I915_NUM_ENGINES);
1222
1223         return 0;
1224
1225 out_shadow_ctx:
1226         i915_gem_context_put(s->shadow_ctx);
1227         return ret;
1228 }
1229
1230 /**
1231  * intel_vgpu_select_submission_ops - select virtual submission interface
1232  * @vgpu: a vGPU
1233  * @engine_mask: either ALL_ENGINES or target engine mask
1234  * @interface: expected vGPU virtual submission interface
1235  *
1236  * This function is called when guest configures submission interface.
1237  *
1238  * Returns:
1239  * Zero on success, negative error code if failed.
1240  *
1241  */
1242 int intel_vgpu_select_submission_ops(struct intel_vgpu *vgpu,
1243                                      unsigned long engine_mask,
1244                                      unsigned int interface)
1245 {
1246         struct intel_vgpu_submission *s = &vgpu->submission;
1247         const struct intel_vgpu_submission_ops *ops[] = {
1248                 [INTEL_VGPU_EXECLIST_SUBMISSION] =
1249                         &intel_vgpu_execlist_submission_ops,
1250         };
1251         int ret;
1252
1253         if (WARN_ON(interface >= ARRAY_SIZE(ops)))
1254                 return -EINVAL;
1255
1256         if (WARN_ON(interface == 0 && engine_mask != ALL_ENGINES))
1257                 return -EINVAL;
1258
1259         if (s->active)
1260                 s->ops->clean(vgpu, engine_mask);
1261
1262         if (interface == 0) {
1263                 s->ops = NULL;
1264                 s->virtual_submission_interface = 0;
1265                 s->active = false;
1266                 gvt_dbg_core("vgpu%d: remove submission ops\n", vgpu->id);
1267                 return 0;
1268         }
1269
1270         ret = ops[interface]->init(vgpu, engine_mask);
1271         if (ret)
1272                 return ret;
1273
1274         s->ops = ops[interface];
1275         s->virtual_submission_interface = interface;
1276         s->active = true;
1277
1278         gvt_dbg_core("vgpu%d: activate ops [ %s ]\n",
1279                         vgpu->id, s->ops->name);
1280
1281         return 0;
1282 }
1283
1284 /**
1285  * intel_vgpu_destroy_workload - destroy a vGPU workload
1286  * @workload: workload to destroy
1287  *
1288  * This function is called when destroy a vGPU workload.
1289  *
1290  */
1291 void intel_vgpu_destroy_workload(struct intel_vgpu_workload *workload)
1292 {
1293         struct intel_vgpu_submission *s = &workload->vgpu->submission;
1294
1295         release_shadow_batch_buffer(workload);
1296         release_shadow_wa_ctx(&workload->wa_ctx);
1297
1298         if (workload->shadow_mm)
1299                 intel_vgpu_mm_put(workload->shadow_mm);
1300
1301         kmem_cache_free(s->workloads, workload);
1302 }
1303
1304 static struct intel_vgpu_workload *
1305 alloc_workload(struct intel_vgpu *vgpu)
1306 {
1307         struct intel_vgpu_submission *s = &vgpu->submission;
1308         struct intel_vgpu_workload *workload;
1309
1310         workload = kmem_cache_zalloc(s->workloads, GFP_KERNEL);
1311         if (!workload)
1312                 return ERR_PTR(-ENOMEM);
1313
1314         INIT_LIST_HEAD(&workload->list);
1315         INIT_LIST_HEAD(&workload->shadow_bb);
1316
1317         init_waitqueue_head(&workload->shadow_ctx_status_wq);
1318         atomic_set(&workload->shadow_ctx_active, 0);
1319
1320         workload->status = -EINPROGRESS;
1321         workload->vgpu = vgpu;
1322
1323         return workload;
1324 }
1325
1326 #define RING_CTX_OFF(x) \
1327         offsetof(struct execlist_ring_context, x)
1328
1329 static void read_guest_pdps(struct intel_vgpu *vgpu,
1330                 u64 ring_context_gpa, u32 pdp[8])
1331 {
1332         u64 gpa;
1333         int i;
1334
1335         gpa = ring_context_gpa + RING_CTX_OFF(pdps[0].val);
1336
1337         for (i = 0; i < 8; i++)
1338                 intel_gvt_hypervisor_read_gpa(vgpu,
1339                                 gpa + i * 8, &pdp[7 - i], 4);
1340 }
1341
1342 static int prepare_mm(struct intel_vgpu_workload *workload)
1343 {
1344         struct execlist_ctx_descriptor_format *desc = &workload->ctx_desc;
1345         struct intel_vgpu_mm *mm;
1346         struct intel_vgpu *vgpu = workload->vgpu;
1347         intel_gvt_gtt_type_t root_entry_type;
1348         u64 pdps[GVT_RING_CTX_NR_PDPS];
1349
1350         switch (desc->addressing_mode) {
1351         case 1: /* legacy 32-bit */
1352                 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY;
1353                 break;
1354         case 3: /* legacy 64-bit */
1355                 root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
1356                 break;
1357         default:
1358                 gvt_vgpu_err("Advanced Context mode(SVM) is not supported!\n");
1359                 return -EINVAL;
1360         }
1361
1362         read_guest_pdps(workload->vgpu, workload->ring_context_gpa, (void *)pdps);
1363
1364         mm = intel_vgpu_get_ppgtt_mm(workload->vgpu, root_entry_type, pdps);
1365         if (IS_ERR(mm))
1366                 return PTR_ERR(mm);
1367
1368         workload->shadow_mm = mm;
1369         return 0;
1370 }
1371
1372 #define same_context(a, b) (((a)->context_id == (b)->context_id) && \
1373                 ((a)->lrca == (b)->lrca))
1374
1375 #define get_last_workload(q) \
1376         (list_empty(q) ? NULL : container_of(q->prev, \
1377         struct intel_vgpu_workload, list))
1378 /**
1379  * intel_vgpu_create_workload - create a vGPU workload
1380  * @vgpu: a vGPU
1381  * @ring_id: ring index
1382  * @desc: a guest context descriptor
1383  *
1384  * This function is called when creating a vGPU workload.
1385  *
1386  * Returns:
1387  * struct intel_vgpu_workload * on success, negative error code in
1388  * pointer if failed.
1389  *
1390  */
1391 struct intel_vgpu_workload *
1392 intel_vgpu_create_workload(struct intel_vgpu *vgpu, int ring_id,
1393                            struct execlist_ctx_descriptor_format *desc)
1394 {
1395         struct intel_vgpu_submission *s = &vgpu->submission;
1396         struct list_head *q = workload_q_head(vgpu, ring_id);
1397         struct intel_vgpu_workload *last_workload = get_last_workload(q);
1398         struct intel_vgpu_workload *workload = NULL;
1399         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1400         u64 ring_context_gpa;
1401         u32 head, tail, start, ctl, ctx_ctl, per_ctx, indirect_ctx;
1402         int ret;
1403
1404         ring_context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
1405                         (u32)((desc->lrca + 1) << I915_GTT_PAGE_SHIFT));
1406         if (ring_context_gpa == INTEL_GVT_INVALID_ADDR) {
1407                 gvt_vgpu_err("invalid guest context LRCA: %x\n", desc->lrca);
1408                 return ERR_PTR(-EINVAL);
1409         }
1410
1411         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1412                         RING_CTX_OFF(ring_header.val), &head, 4);
1413
1414         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1415                         RING_CTX_OFF(ring_tail.val), &tail, 4);
1416
1417         head &= RB_HEAD_OFF_MASK;
1418         tail &= RB_TAIL_OFF_MASK;
1419
1420         if (last_workload && same_context(&last_workload->ctx_desc, desc)) {
1421                 gvt_dbg_el("ring id %d cur workload == last\n", ring_id);
1422                 gvt_dbg_el("ctx head %x real head %lx\n", head,
1423                                 last_workload->rb_tail);
1424                 /*
1425                  * cannot use guest context head pointer here,
1426                  * as it might not be updated at this time
1427                  */
1428                 head = last_workload->rb_tail;
1429         }
1430
1431         gvt_dbg_el("ring id %d begin a new workload\n", ring_id);
1432
1433         /* record some ring buffer register values for scan and shadow */
1434         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1435                         RING_CTX_OFF(rb_start.val), &start, 4);
1436         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1437                         RING_CTX_OFF(rb_ctrl.val), &ctl, 4);
1438         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1439                         RING_CTX_OFF(ctx_ctrl.val), &ctx_ctl, 4);
1440
1441         workload = alloc_workload(vgpu);
1442         if (IS_ERR(workload))
1443                 return workload;
1444
1445         workload->ring_id = ring_id;
1446         workload->ctx_desc = *desc;
1447         workload->ring_context_gpa = ring_context_gpa;
1448         workload->rb_head = head;
1449         workload->rb_tail = tail;
1450         workload->rb_start = start;
1451         workload->rb_ctl = ctl;
1452
1453         if (ring_id == RCS) {
1454                 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1455                         RING_CTX_OFF(bb_per_ctx_ptr.val), &per_ctx, 4);
1456                 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1457                         RING_CTX_OFF(rcs_indirect_ctx.val), &indirect_ctx, 4);
1458
1459                 workload->wa_ctx.indirect_ctx.guest_gma =
1460                         indirect_ctx & INDIRECT_CTX_ADDR_MASK;
1461                 workload->wa_ctx.indirect_ctx.size =
1462                         (indirect_ctx & INDIRECT_CTX_SIZE_MASK) *
1463                         CACHELINE_BYTES;
1464                 workload->wa_ctx.per_ctx.guest_gma =
1465                         per_ctx & PER_CTX_ADDR_MASK;
1466                 workload->wa_ctx.per_ctx.valid = per_ctx & 1;
1467         }
1468
1469         gvt_dbg_el("workload %p ring id %d head %x tail %x start %x ctl %x\n",
1470                         workload, ring_id, head, tail, start, ctl);
1471
1472         ret = prepare_mm(workload);
1473         if (ret) {
1474                 kmem_cache_free(s->workloads, workload);
1475                 return ERR_PTR(ret);
1476         }
1477
1478         /* Only scan and shadow the first workload in the queue
1479          * as there is only one pre-allocated buf-obj for shadow.
1480          */
1481         if (list_empty(workload_q_head(vgpu, ring_id))) {
1482                 intel_runtime_pm_get(dev_priv);
1483                 mutex_lock(&dev_priv->drm.struct_mutex);
1484                 ret = intel_gvt_scan_and_shadow_workload(workload);
1485                 mutex_unlock(&dev_priv->drm.struct_mutex);
1486                 intel_runtime_pm_put_unchecked(dev_priv);
1487         }
1488
1489         if (ret && (vgpu_is_vm_unhealthy(ret))) {
1490                 enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR);
1491                 intel_vgpu_destroy_workload(workload);
1492                 return ERR_PTR(ret);
1493         }
1494
1495         return workload;
1496 }
1497
1498 /**
1499  * intel_vgpu_queue_workload - Qeue a vGPU workload
1500  * @workload: the workload to queue in
1501  */
1502 void intel_vgpu_queue_workload(struct intel_vgpu_workload *workload)
1503 {
1504         list_add_tail(&workload->list,
1505                 workload_q_head(workload->vgpu, workload->ring_id));
1506         intel_gvt_kick_schedule(workload->vgpu->gvt);
1507         wake_up(&workload->vgpu->gvt->scheduler.waitq[workload->ring_id]);
1508 }