fs/proc/proc_sysctl.c: fix NULL pointer dereference in put_links
[muen/linux.git] / drivers / gpu / drm / i915 / gvt / scheduler.c
1 /*
2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21  * SOFTWARE.
22  *
23  * Authors:
24  *    Zhi Wang <zhi.a.wang@intel.com>
25  *
26  * Contributors:
27  *    Ping Gao <ping.a.gao@intel.com>
28  *    Tina Zhang <tina.zhang@intel.com>
29  *    Chanbin Du <changbin.du@intel.com>
30  *    Min He <min.he@intel.com>
31  *    Bing Niu <bing.niu@intel.com>
32  *    Zhenyu Wang <zhenyuw@linux.intel.com>
33  *
34  */
35
36 #include <linux/kthread.h>
37
38 #include "i915_drv.h"
39 #include "gvt.h"
40
41 #define RING_CTX_OFF(x) \
42         offsetof(struct execlist_ring_context, x)
43
44 static void set_context_pdp_root_pointer(
45                 struct execlist_ring_context *ring_context,
46                 u32 pdp[8])
47 {
48         int i;
49
50         for (i = 0; i < 8; i++)
51                 ring_context->pdps[i].val = pdp[7 - i];
52 }
53
54 static void update_shadow_pdps(struct intel_vgpu_workload *workload)
55 {
56         struct drm_i915_gem_object *ctx_obj =
57                 workload->req->hw_context->state->obj;
58         struct execlist_ring_context *shadow_ring_context;
59         struct page *page;
60
61         if (WARN_ON(!workload->shadow_mm))
62                 return;
63
64         if (WARN_ON(!atomic_read(&workload->shadow_mm->pincount)))
65                 return;
66
67         page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
68         shadow_ring_context = kmap(page);
69         set_context_pdp_root_pointer(shadow_ring_context,
70                         (void *)workload->shadow_mm->ppgtt_mm.shadow_pdps);
71         kunmap(page);
72 }
73
74 /*
75  * when populating shadow ctx from guest, we should not overrride oa related
76  * registers, so that they will not be overlapped by guest oa configs. Thus
77  * made it possible to capture oa data from host for both host and guests.
78  */
79 static void sr_oa_regs(struct intel_vgpu_workload *workload,
80                 u32 *reg_state, bool save)
81 {
82         struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv;
83         u32 ctx_oactxctrl = dev_priv->perf.oa.ctx_oactxctrl_offset;
84         u32 ctx_flexeu0 = dev_priv->perf.oa.ctx_flexeu0_offset;
85         int i = 0;
86         u32 flex_mmio[] = {
87                 i915_mmio_reg_offset(EU_PERF_CNTL0),
88                 i915_mmio_reg_offset(EU_PERF_CNTL1),
89                 i915_mmio_reg_offset(EU_PERF_CNTL2),
90                 i915_mmio_reg_offset(EU_PERF_CNTL3),
91                 i915_mmio_reg_offset(EU_PERF_CNTL4),
92                 i915_mmio_reg_offset(EU_PERF_CNTL5),
93                 i915_mmio_reg_offset(EU_PERF_CNTL6),
94         };
95
96         if (workload->ring_id != RCS)
97                 return;
98
99         if (save) {
100                 workload->oactxctrl = reg_state[ctx_oactxctrl + 1];
101
102                 for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) {
103                         u32 state_offset = ctx_flexeu0 + i * 2;
104
105                         workload->flex_mmio[i] = reg_state[state_offset + 1];
106                 }
107         } else {
108                 reg_state[ctx_oactxctrl] =
109                         i915_mmio_reg_offset(GEN8_OACTXCONTROL);
110                 reg_state[ctx_oactxctrl + 1] = workload->oactxctrl;
111
112                 for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) {
113                         u32 state_offset = ctx_flexeu0 + i * 2;
114                         u32 mmio = flex_mmio[i];
115
116                         reg_state[state_offset] = mmio;
117                         reg_state[state_offset + 1] = workload->flex_mmio[i];
118                 }
119         }
120 }
121
122 static int populate_shadow_context(struct intel_vgpu_workload *workload)
123 {
124         struct intel_vgpu *vgpu = workload->vgpu;
125         struct intel_gvt *gvt = vgpu->gvt;
126         int ring_id = workload->ring_id;
127         struct drm_i915_gem_object *ctx_obj =
128                 workload->req->hw_context->state->obj;
129         struct execlist_ring_context *shadow_ring_context;
130         struct page *page;
131         void *dst;
132         unsigned long context_gpa, context_page_num;
133         int i;
134
135         page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
136         shadow_ring_context = kmap(page);
137
138         sr_oa_regs(workload, (u32 *)shadow_ring_context, true);
139 #define COPY_REG(name) \
140         intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \
141                 + RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
142 #define COPY_REG_MASKED(name) {\
143                 intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \
144                                               + RING_CTX_OFF(name.val),\
145                                               &shadow_ring_context->name.val, 4);\
146                 shadow_ring_context->name.val |= 0xffff << 16;\
147         }
148
149         COPY_REG_MASKED(ctx_ctrl);
150         COPY_REG(ctx_timestamp);
151
152         if (ring_id == RCS) {
153                 COPY_REG(bb_per_ctx_ptr);
154                 COPY_REG(rcs_indirect_ctx);
155                 COPY_REG(rcs_indirect_ctx_offset);
156         }
157 #undef COPY_REG
158 #undef COPY_REG_MASKED
159
160         intel_gvt_hypervisor_read_gpa(vgpu,
161                         workload->ring_context_gpa +
162                         sizeof(*shadow_ring_context),
163                         (void *)shadow_ring_context +
164                         sizeof(*shadow_ring_context),
165                         I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
166
167         sr_oa_regs(workload, (u32 *)shadow_ring_context, false);
168         kunmap(page);
169
170         if (IS_RESTORE_INHIBIT(shadow_ring_context->ctx_ctrl.val))
171                 return 0;
172
173         gvt_dbg_sched("ring id %d workload lrca %x", ring_id,
174                         workload->ctx_desc.lrca);
175
176         context_page_num = gvt->dev_priv->engine[ring_id]->context_size;
177
178         context_page_num = context_page_num >> PAGE_SHIFT;
179
180         if (IS_BROADWELL(gvt->dev_priv) && ring_id == RCS)
181                 context_page_num = 19;
182
183         i = 2;
184         while (i < context_page_num) {
185                 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
186                                 (u32)((workload->ctx_desc.lrca + i) <<
187                                 I915_GTT_PAGE_SHIFT));
188                 if (context_gpa == INTEL_GVT_INVALID_ADDR) {
189                         gvt_vgpu_err("Invalid guest context descriptor\n");
190                         return -EFAULT;
191                 }
192
193                 page = i915_gem_object_get_page(ctx_obj, LRC_HEADER_PAGES + i);
194                 dst = kmap(page);
195                 intel_gvt_hypervisor_read_gpa(vgpu, context_gpa, dst,
196                                 I915_GTT_PAGE_SIZE);
197                 kunmap(page);
198                 i++;
199         }
200         return 0;
201 }
202
203 static inline bool is_gvt_request(struct i915_request *req)
204 {
205         return i915_gem_context_force_single_submission(req->gem_context);
206 }
207
208 static void save_ring_hw_state(struct intel_vgpu *vgpu, int ring_id)
209 {
210         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
211         u32 ring_base = dev_priv->engine[ring_id]->mmio_base;
212         i915_reg_t reg;
213
214         reg = RING_INSTDONE(ring_base);
215         vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
216         reg = RING_ACTHD(ring_base);
217         vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
218         reg = RING_ACTHD_UDW(ring_base);
219         vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
220 }
221
222 static int shadow_context_status_change(struct notifier_block *nb,
223                 unsigned long action, void *data)
224 {
225         struct i915_request *req = data;
226         struct intel_gvt *gvt = container_of(nb, struct intel_gvt,
227                                 shadow_ctx_notifier_block[req->engine->id]);
228         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
229         enum intel_engine_id ring_id = req->engine->id;
230         struct intel_vgpu_workload *workload;
231         unsigned long flags;
232
233         if (!is_gvt_request(req)) {
234                 spin_lock_irqsave(&scheduler->mmio_context_lock, flags);
235                 if (action == INTEL_CONTEXT_SCHEDULE_IN &&
236                     scheduler->engine_owner[ring_id]) {
237                         /* Switch ring from vGPU to host. */
238                         intel_gvt_switch_mmio(scheduler->engine_owner[ring_id],
239                                               NULL, ring_id);
240                         scheduler->engine_owner[ring_id] = NULL;
241                 }
242                 spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags);
243
244                 return NOTIFY_OK;
245         }
246
247         workload = scheduler->current_workload[ring_id];
248         if (unlikely(!workload))
249                 return NOTIFY_OK;
250
251         switch (action) {
252         case INTEL_CONTEXT_SCHEDULE_IN:
253                 spin_lock_irqsave(&scheduler->mmio_context_lock, flags);
254                 if (workload->vgpu != scheduler->engine_owner[ring_id]) {
255                         /* Switch ring from host to vGPU or vGPU to vGPU. */
256                         intel_gvt_switch_mmio(scheduler->engine_owner[ring_id],
257                                               workload->vgpu, ring_id);
258                         scheduler->engine_owner[ring_id] = workload->vgpu;
259                 } else
260                         gvt_dbg_sched("skip ring %d mmio switch for vgpu%d\n",
261                                       ring_id, workload->vgpu->id);
262                 spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags);
263                 atomic_set(&workload->shadow_ctx_active, 1);
264                 break;
265         case INTEL_CONTEXT_SCHEDULE_OUT:
266                 save_ring_hw_state(workload->vgpu, ring_id);
267                 atomic_set(&workload->shadow_ctx_active, 0);
268                 break;
269         case INTEL_CONTEXT_SCHEDULE_PREEMPTED:
270                 save_ring_hw_state(workload->vgpu, ring_id);
271                 break;
272         default:
273                 WARN_ON(1);
274                 return NOTIFY_OK;
275         }
276         wake_up(&workload->shadow_ctx_status_wq);
277         return NOTIFY_OK;
278 }
279
280 static void shadow_context_descriptor_update(struct intel_context *ce)
281 {
282         u64 desc = 0;
283
284         desc = ce->lrc_desc;
285
286         /* Update bits 0-11 of the context descriptor which includes flags
287          * like GEN8_CTX_* cached in desc_template
288          */
289         desc &= U64_MAX << 12;
290         desc |= ce->gem_context->desc_template & ((1ULL << 12) - 1);
291
292         ce->lrc_desc = desc;
293 }
294
295 static int copy_workload_to_ring_buffer(struct intel_vgpu_workload *workload)
296 {
297         struct intel_vgpu *vgpu = workload->vgpu;
298         struct i915_request *req = workload->req;
299         void *shadow_ring_buffer_va;
300         u32 *cs;
301
302         if ((IS_KABYLAKE(req->i915) || IS_BROXTON(req->i915)
303                 || IS_COFFEELAKE(req->i915))
304                 && is_inhibit_context(req->hw_context))
305                 intel_vgpu_restore_inhibit_context(vgpu, req);
306
307         /* allocate shadow ring buffer */
308         cs = intel_ring_begin(workload->req, workload->rb_len / sizeof(u32));
309         if (IS_ERR(cs)) {
310                 gvt_vgpu_err("fail to alloc size =%ld shadow  ring buffer\n",
311                         workload->rb_len);
312                 return PTR_ERR(cs);
313         }
314
315         shadow_ring_buffer_va = workload->shadow_ring_buffer_va;
316
317         /* get shadow ring buffer va */
318         workload->shadow_ring_buffer_va = cs;
319
320         memcpy(cs, shadow_ring_buffer_va,
321                         workload->rb_len);
322
323         cs += workload->rb_len / sizeof(u32);
324         intel_ring_advance(workload->req, cs);
325
326         return 0;
327 }
328
329 static void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
330 {
331         if (!wa_ctx->indirect_ctx.obj)
332                 return;
333
334         i915_gem_object_unpin_map(wa_ctx->indirect_ctx.obj);
335         i915_gem_object_put(wa_ctx->indirect_ctx.obj);
336
337         wa_ctx->indirect_ctx.obj = NULL;
338         wa_ctx->indirect_ctx.shadow_va = NULL;
339 }
340
341 static int set_context_ppgtt_from_shadow(struct intel_vgpu_workload *workload,
342                                          struct i915_gem_context *ctx)
343 {
344         struct intel_vgpu_mm *mm = workload->shadow_mm;
345         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
346         int i = 0;
347
348         if (mm->type != INTEL_GVT_MM_PPGTT || !mm->ppgtt_mm.shadowed)
349                 return -1;
350
351         if (mm->ppgtt_mm.root_entry_type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
352                 px_dma(&ppgtt->pml4) = mm->ppgtt_mm.shadow_pdps[0];
353         } else {
354                 for (i = 0; i < GVT_RING_CTX_NR_PDPS; i++) {
355                         px_dma(ppgtt->pdp.page_directory[i]) =
356                                 mm->ppgtt_mm.shadow_pdps[i];
357                 }
358         }
359
360         return 0;
361 }
362
363 static int
364 intel_gvt_workload_req_alloc(struct intel_vgpu_workload *workload)
365 {
366         struct intel_vgpu *vgpu = workload->vgpu;
367         struct intel_vgpu_submission *s = &vgpu->submission;
368         struct i915_gem_context *shadow_ctx = s->shadow_ctx;
369         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
370         struct intel_engine_cs *engine = dev_priv->engine[workload->ring_id];
371         struct i915_request *rq;
372         int ret = 0;
373
374         lockdep_assert_held(&dev_priv->drm.struct_mutex);
375
376         if (workload->req)
377                 goto out;
378
379         rq = i915_request_alloc(engine, shadow_ctx);
380         if (IS_ERR(rq)) {
381                 gvt_vgpu_err("fail to allocate gem request\n");
382                 ret = PTR_ERR(rq);
383                 goto out;
384         }
385         workload->req = i915_request_get(rq);
386 out:
387         return ret;
388 }
389
390 /**
391  * intel_gvt_scan_and_shadow_workload - audit the workload by scanning and
392  * shadow it as well, include ringbuffer,wa_ctx and ctx.
393  * @workload: an abstract entity for each execlist submission.
394  *
395  * This function is called before the workload submitting to i915, to make
396  * sure the content of the workload is valid.
397  */
398 int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload)
399 {
400         struct intel_vgpu *vgpu = workload->vgpu;
401         struct intel_vgpu_submission *s = &vgpu->submission;
402         struct i915_gem_context *shadow_ctx = s->shadow_ctx;
403         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
404         struct intel_engine_cs *engine = dev_priv->engine[workload->ring_id];
405         struct intel_context *ce;
406         int ret;
407
408         lockdep_assert_held(&dev_priv->drm.struct_mutex);
409
410         if (workload->shadow)
411                 return 0;
412
413         ret = set_context_ppgtt_from_shadow(workload, shadow_ctx);
414         if (ret < 0) {
415                 gvt_vgpu_err("workload shadow ppgtt isn't ready\n");
416                 return ret;
417         }
418
419         /* pin shadow context by gvt even the shadow context will be pinned
420          * when i915 alloc request. That is because gvt will update the guest
421          * context from shadow context when workload is completed, and at that
422          * moment, i915 may already unpined the shadow context to make the
423          * shadow_ctx pages invalid. So gvt need to pin itself. After update
424          * the guest context, gvt can unpin the shadow_ctx safely.
425          */
426         ce = intel_context_pin(shadow_ctx, engine);
427         if (IS_ERR(ce)) {
428                 gvt_vgpu_err("fail to pin shadow context\n");
429                 return PTR_ERR(ce);
430         }
431
432         shadow_ctx->desc_template &= ~(0x3 << GEN8_CTX_ADDRESSING_MODE_SHIFT);
433         shadow_ctx->desc_template |= workload->ctx_desc.addressing_mode <<
434                                     GEN8_CTX_ADDRESSING_MODE_SHIFT;
435
436         if (!test_and_set_bit(workload->ring_id, s->shadow_ctx_desc_updated))
437                 shadow_context_descriptor_update(ce);
438
439         ret = intel_gvt_scan_and_shadow_ringbuffer(workload);
440         if (ret)
441                 goto err_unpin;
442
443         if ((workload->ring_id == RCS) &&
444             (workload->wa_ctx.indirect_ctx.size != 0)) {
445                 ret = intel_gvt_scan_and_shadow_wa_ctx(&workload->wa_ctx);
446                 if (ret)
447                         goto err_shadow;
448         }
449
450         workload->shadow = true;
451         return 0;
452 err_shadow:
453         release_shadow_wa_ctx(&workload->wa_ctx);
454 err_unpin:
455         intel_context_unpin(ce);
456         return ret;
457 }
458
459 static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload);
460
461 static int prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload)
462 {
463         struct intel_gvt *gvt = workload->vgpu->gvt;
464         const int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
465         struct intel_vgpu_shadow_bb *bb;
466         int ret;
467
468         list_for_each_entry(bb, &workload->shadow_bb, list) {
469                 /* For privilge batch buffer and not wa_ctx, the bb_start_cmd_va
470                  * is only updated into ring_scan_buffer, not real ring address
471                  * allocated in later copy_workload_to_ring_buffer. pls be noted
472                  * shadow_ring_buffer_va is now pointed to real ring buffer va
473                  * in copy_workload_to_ring_buffer.
474                  */
475
476                 if (bb->bb_offset)
477                         bb->bb_start_cmd_va = workload->shadow_ring_buffer_va
478                                 + bb->bb_offset;
479
480                 if (bb->ppgtt) {
481                         /* for non-priv bb, scan&shadow is only for
482                          * debugging purpose, so the content of shadow bb
483                          * is the same as original bb. Therefore,
484                          * here, rather than switch to shadow bb's gma
485                          * address, we directly use original batch buffer's
486                          * gma address, and send original bb to hardware
487                          * directly
488                          */
489                         if (bb->clflush & CLFLUSH_AFTER) {
490                                 drm_clflush_virt_range(bb->va,
491                                                 bb->obj->base.size);
492                                 bb->clflush &= ~CLFLUSH_AFTER;
493                         }
494                         i915_gem_obj_finish_shmem_access(bb->obj);
495                         bb->accessing = false;
496
497                 } else {
498                         bb->vma = i915_gem_object_ggtt_pin(bb->obj,
499                                         NULL, 0, 0, 0);
500                         if (IS_ERR(bb->vma)) {
501                                 ret = PTR_ERR(bb->vma);
502                                 goto err;
503                         }
504
505                         /* relocate shadow batch buffer */
506                         bb->bb_start_cmd_va[1] = i915_ggtt_offset(bb->vma);
507                         if (gmadr_bytes == 8)
508                                 bb->bb_start_cmd_va[2] = 0;
509
510                         /* No one is going to touch shadow bb from now on. */
511                         if (bb->clflush & CLFLUSH_AFTER) {
512                                 drm_clflush_virt_range(bb->va,
513                                                 bb->obj->base.size);
514                                 bb->clflush &= ~CLFLUSH_AFTER;
515                         }
516
517                         ret = i915_gem_object_set_to_gtt_domain(bb->obj,
518                                         false);
519                         if (ret)
520                                 goto err;
521
522                         i915_gem_obj_finish_shmem_access(bb->obj);
523                         bb->accessing = false;
524
525                         ret = i915_vma_move_to_active(bb->vma,
526                                                       workload->req,
527                                                       0);
528                         if (ret)
529                                 goto err;
530                 }
531         }
532         return 0;
533 err:
534         release_shadow_batch_buffer(workload);
535         return ret;
536 }
537
538 static void update_wa_ctx_2_shadow_ctx(struct intel_shadow_wa_ctx *wa_ctx)
539 {
540         struct intel_vgpu_workload *workload =
541                 container_of(wa_ctx, struct intel_vgpu_workload, wa_ctx);
542         struct i915_request *rq = workload->req;
543         struct execlist_ring_context *shadow_ring_context =
544                 (struct execlist_ring_context *)rq->hw_context->lrc_reg_state;
545
546         shadow_ring_context->bb_per_ctx_ptr.val =
547                 (shadow_ring_context->bb_per_ctx_ptr.val &
548                 (~PER_CTX_ADDR_MASK)) | wa_ctx->per_ctx.shadow_gma;
549         shadow_ring_context->rcs_indirect_ctx.val =
550                 (shadow_ring_context->rcs_indirect_ctx.val &
551                 (~INDIRECT_CTX_ADDR_MASK)) | wa_ctx->indirect_ctx.shadow_gma;
552 }
553
554 static int prepare_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
555 {
556         struct i915_vma *vma;
557         unsigned char *per_ctx_va =
558                 (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
559                 wa_ctx->indirect_ctx.size;
560
561         if (wa_ctx->indirect_ctx.size == 0)
562                 return 0;
563
564         vma = i915_gem_object_ggtt_pin(wa_ctx->indirect_ctx.obj, NULL,
565                                        0, CACHELINE_BYTES, 0);
566         if (IS_ERR(vma))
567                 return PTR_ERR(vma);
568
569         /* FIXME: we are not tracking our pinned VMA leaving it
570          * up to the core to fix up the stray pin_count upon
571          * free.
572          */
573
574         wa_ctx->indirect_ctx.shadow_gma = i915_ggtt_offset(vma);
575
576         wa_ctx->per_ctx.shadow_gma = *((unsigned int *)per_ctx_va + 1);
577         memset(per_ctx_va, 0, CACHELINE_BYTES);
578
579         update_wa_ctx_2_shadow_ctx(wa_ctx);
580         return 0;
581 }
582
583 static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload)
584 {
585         struct intel_vgpu *vgpu = workload->vgpu;
586         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
587         struct intel_vgpu_shadow_bb *bb, *pos;
588
589         if (list_empty(&workload->shadow_bb))
590                 return;
591
592         bb = list_first_entry(&workload->shadow_bb,
593                         struct intel_vgpu_shadow_bb, list);
594
595         mutex_lock(&dev_priv->drm.struct_mutex);
596
597         list_for_each_entry_safe(bb, pos, &workload->shadow_bb, list) {
598                 if (bb->obj) {
599                         if (bb->accessing)
600                                 i915_gem_obj_finish_shmem_access(bb->obj);
601
602                         if (bb->va && !IS_ERR(bb->va))
603                                 i915_gem_object_unpin_map(bb->obj);
604
605                         if (bb->vma && !IS_ERR(bb->vma)) {
606                                 i915_vma_unpin(bb->vma);
607                                 i915_vma_close(bb->vma);
608                         }
609                         __i915_gem_object_release_unless_active(bb->obj);
610                 }
611                 list_del(&bb->list);
612                 kfree(bb);
613         }
614
615         mutex_unlock(&dev_priv->drm.struct_mutex);
616 }
617
618 static int prepare_workload(struct intel_vgpu_workload *workload)
619 {
620         struct intel_vgpu *vgpu = workload->vgpu;
621         int ret = 0;
622
623         ret = intel_vgpu_pin_mm(workload->shadow_mm);
624         if (ret) {
625                 gvt_vgpu_err("fail to vgpu pin mm\n");
626                 return ret;
627         }
628
629         update_shadow_pdps(workload);
630
631         ret = intel_vgpu_sync_oos_pages(workload->vgpu);
632         if (ret) {
633                 gvt_vgpu_err("fail to vgpu sync oos pages\n");
634                 goto err_unpin_mm;
635         }
636
637         ret = intel_vgpu_flush_post_shadow(workload->vgpu);
638         if (ret) {
639                 gvt_vgpu_err("fail to flush post shadow\n");
640                 goto err_unpin_mm;
641         }
642
643         ret = copy_workload_to_ring_buffer(workload);
644         if (ret) {
645                 gvt_vgpu_err("fail to generate request\n");
646                 goto err_unpin_mm;
647         }
648
649         ret = prepare_shadow_batch_buffer(workload);
650         if (ret) {
651                 gvt_vgpu_err("fail to prepare_shadow_batch_buffer\n");
652                 goto err_unpin_mm;
653         }
654
655         ret = prepare_shadow_wa_ctx(&workload->wa_ctx);
656         if (ret) {
657                 gvt_vgpu_err("fail to prepare_shadow_wa_ctx\n");
658                 goto err_shadow_batch;
659         }
660
661         if (workload->prepare) {
662                 ret = workload->prepare(workload);
663                 if (ret)
664                         goto err_shadow_wa_ctx;
665         }
666
667         return 0;
668 err_shadow_wa_ctx:
669         release_shadow_wa_ctx(&workload->wa_ctx);
670 err_shadow_batch:
671         release_shadow_batch_buffer(workload);
672 err_unpin_mm:
673         intel_vgpu_unpin_mm(workload->shadow_mm);
674         return ret;
675 }
676
677 static int dispatch_workload(struct intel_vgpu_workload *workload)
678 {
679         struct intel_vgpu *vgpu = workload->vgpu;
680         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
681         int ring_id = workload->ring_id;
682         int ret;
683
684         gvt_dbg_sched("ring id %d prepare to dispatch workload %p\n",
685                 ring_id, workload);
686
687         mutex_lock(&vgpu->vgpu_lock);
688         mutex_lock(&dev_priv->drm.struct_mutex);
689
690         ret = intel_gvt_workload_req_alloc(workload);
691         if (ret)
692                 goto err_req;
693
694         ret = intel_gvt_scan_and_shadow_workload(workload);
695         if (ret)
696                 goto out;
697
698         ret = populate_shadow_context(workload);
699         if (ret) {
700                 release_shadow_wa_ctx(&workload->wa_ctx);
701                 goto out;
702         }
703
704         ret = prepare_workload(workload);
705 out:
706         if (!IS_ERR_OR_NULL(workload->req)) {
707                 gvt_dbg_sched("ring id %d submit workload to i915 %p\n",
708                                 ring_id, workload->req);
709                 i915_request_add(workload->req);
710                 workload->dispatched = true;
711         }
712 err_req:
713         if (ret)
714                 workload->status = ret;
715         mutex_unlock(&dev_priv->drm.struct_mutex);
716         mutex_unlock(&vgpu->vgpu_lock);
717         return ret;
718 }
719
720 static struct intel_vgpu_workload *pick_next_workload(
721                 struct intel_gvt *gvt, int ring_id)
722 {
723         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
724         struct intel_vgpu_workload *workload = NULL;
725
726         mutex_lock(&gvt->sched_lock);
727
728         /*
729          * no current vgpu / will be scheduled out / no workload
730          * bail out
731          */
732         if (!scheduler->current_vgpu) {
733                 gvt_dbg_sched("ring id %d stop - no current vgpu\n", ring_id);
734                 goto out;
735         }
736
737         if (scheduler->need_reschedule) {
738                 gvt_dbg_sched("ring id %d stop - will reschedule\n", ring_id);
739                 goto out;
740         }
741
742         if (list_empty(workload_q_head(scheduler->current_vgpu, ring_id)))
743                 goto out;
744
745         /*
746          * still have current workload, maybe the workload disptacher
747          * fail to submit it for some reason, resubmit it.
748          */
749         if (scheduler->current_workload[ring_id]) {
750                 workload = scheduler->current_workload[ring_id];
751                 gvt_dbg_sched("ring id %d still have current workload %p\n",
752                                 ring_id, workload);
753                 goto out;
754         }
755
756         /*
757          * pick a workload as current workload
758          * once current workload is set, schedule policy routines
759          * will wait the current workload is finished when trying to
760          * schedule out a vgpu.
761          */
762         scheduler->current_workload[ring_id] = container_of(
763                         workload_q_head(scheduler->current_vgpu, ring_id)->next,
764                         struct intel_vgpu_workload, list);
765
766         workload = scheduler->current_workload[ring_id];
767
768         gvt_dbg_sched("ring id %d pick new workload %p\n", ring_id, workload);
769
770         atomic_inc(&workload->vgpu->submission.running_workload_num);
771 out:
772         mutex_unlock(&gvt->sched_lock);
773         return workload;
774 }
775
776 static void update_guest_context(struct intel_vgpu_workload *workload)
777 {
778         struct i915_request *rq = workload->req;
779         struct intel_vgpu *vgpu = workload->vgpu;
780         struct intel_gvt *gvt = vgpu->gvt;
781         struct drm_i915_gem_object *ctx_obj = rq->hw_context->state->obj;
782         struct execlist_ring_context *shadow_ring_context;
783         struct page *page;
784         void *src;
785         unsigned long context_gpa, context_page_num;
786         int i;
787
788         gvt_dbg_sched("ring id %d workload lrca %x\n", rq->engine->id,
789                       workload->ctx_desc.lrca);
790
791         context_page_num = rq->engine->context_size;
792         context_page_num = context_page_num >> PAGE_SHIFT;
793
794         if (IS_BROADWELL(gvt->dev_priv) && rq->engine->id == RCS)
795                 context_page_num = 19;
796
797         i = 2;
798
799         while (i < context_page_num) {
800                 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
801                                 (u32)((workload->ctx_desc.lrca + i) <<
802                                         I915_GTT_PAGE_SHIFT));
803                 if (context_gpa == INTEL_GVT_INVALID_ADDR) {
804                         gvt_vgpu_err("invalid guest context descriptor\n");
805                         return;
806                 }
807
808                 page = i915_gem_object_get_page(ctx_obj, LRC_HEADER_PAGES + i);
809                 src = kmap(page);
810                 intel_gvt_hypervisor_write_gpa(vgpu, context_gpa, src,
811                                 I915_GTT_PAGE_SIZE);
812                 kunmap(page);
813                 i++;
814         }
815
816         intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa +
817                 RING_CTX_OFF(ring_header.val), &workload->rb_tail, 4);
818
819         page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
820         shadow_ring_context = kmap(page);
821
822 #define COPY_REG(name) \
823         intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa + \
824                 RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
825
826         COPY_REG(ctx_ctrl);
827         COPY_REG(ctx_timestamp);
828
829 #undef COPY_REG
830
831         intel_gvt_hypervisor_write_gpa(vgpu,
832                         workload->ring_context_gpa +
833                         sizeof(*shadow_ring_context),
834                         (void *)shadow_ring_context +
835                         sizeof(*shadow_ring_context),
836                         I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
837
838         kunmap(page);
839 }
840
841 void intel_vgpu_clean_workloads(struct intel_vgpu *vgpu,
842                                 unsigned long engine_mask)
843 {
844         struct intel_vgpu_submission *s = &vgpu->submission;
845         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
846         struct intel_engine_cs *engine;
847         struct intel_vgpu_workload *pos, *n;
848         unsigned int tmp;
849
850         /* free the unsubmited workloads in the queues. */
851         for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
852                 list_for_each_entry_safe(pos, n,
853                         &s->workload_q_head[engine->id], list) {
854                         list_del_init(&pos->list);
855                         intel_vgpu_destroy_workload(pos);
856                 }
857                 clear_bit(engine->id, s->shadow_ctx_desc_updated);
858         }
859 }
860
861 static void complete_current_workload(struct intel_gvt *gvt, int ring_id)
862 {
863         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
864         struct intel_vgpu_workload *workload =
865                 scheduler->current_workload[ring_id];
866         struct intel_vgpu *vgpu = workload->vgpu;
867         struct intel_vgpu_submission *s = &vgpu->submission;
868         struct i915_request *rq = workload->req;
869         int event;
870
871         mutex_lock(&vgpu->vgpu_lock);
872         mutex_lock(&gvt->sched_lock);
873
874         /* For the workload w/ request, needs to wait for the context
875          * switch to make sure request is completed.
876          * For the workload w/o request, directly complete the workload.
877          */
878         if (rq) {
879                 wait_event(workload->shadow_ctx_status_wq,
880                            !atomic_read(&workload->shadow_ctx_active));
881
882                 /* If this request caused GPU hang, req->fence.error will
883                  * be set to -EIO. Use -EIO to set workload status so
884                  * that when this request caused GPU hang, didn't trigger
885                  * context switch interrupt to guest.
886                  */
887                 if (likely(workload->status == -EINPROGRESS)) {
888                         if (workload->req->fence.error == -EIO)
889                                 workload->status = -EIO;
890                         else
891                                 workload->status = 0;
892                 }
893
894                 if (!workload->status && !(vgpu->resetting_eng &
895                                            ENGINE_MASK(ring_id))) {
896                         update_guest_context(workload);
897
898                         for_each_set_bit(event, workload->pending_events,
899                                          INTEL_GVT_EVENT_MAX)
900                                 intel_vgpu_trigger_virtual_event(vgpu, event);
901                 }
902
903                 /* unpin shadow ctx as the shadow_ctx update is done */
904                 mutex_lock(&rq->i915->drm.struct_mutex);
905                 intel_context_unpin(rq->hw_context);
906                 mutex_unlock(&rq->i915->drm.struct_mutex);
907
908                 i915_request_put(fetch_and_zero(&workload->req));
909         }
910
911         gvt_dbg_sched("ring id %d complete workload %p status %d\n",
912                         ring_id, workload, workload->status);
913
914         scheduler->current_workload[ring_id] = NULL;
915
916         list_del_init(&workload->list);
917
918         if (workload->status || (vgpu->resetting_eng & ENGINE_MASK(ring_id))) {
919                 /* if workload->status is not successful means HW GPU
920                  * has occurred GPU hang or something wrong with i915/GVT,
921                  * and GVT won't inject context switch interrupt to guest.
922                  * So this error is a vGPU hang actually to the guest.
923                  * According to this we should emunlate a vGPU hang. If
924                  * there are pending workloads which are already submitted
925                  * from guest, we should clean them up like HW GPU does.
926                  *
927                  * if it is in middle of engine resetting, the pending
928                  * workloads won't be submitted to HW GPU and will be
929                  * cleaned up during the resetting process later, so doing
930                  * the workload clean up here doesn't have any impact.
931                  **/
932                 intel_vgpu_clean_workloads(vgpu, ENGINE_MASK(ring_id));
933         }
934
935         workload->complete(workload);
936
937         atomic_dec(&s->running_workload_num);
938         wake_up(&scheduler->workload_complete_wq);
939
940         if (gvt->scheduler.need_reschedule)
941                 intel_gvt_request_service(gvt, INTEL_GVT_REQUEST_EVENT_SCHED);
942
943         mutex_unlock(&gvt->sched_lock);
944         mutex_unlock(&vgpu->vgpu_lock);
945 }
946
947 struct workload_thread_param {
948         struct intel_gvt *gvt;
949         int ring_id;
950 };
951
952 static int workload_thread(void *priv)
953 {
954         struct workload_thread_param *p = (struct workload_thread_param *)priv;
955         struct intel_gvt *gvt = p->gvt;
956         int ring_id = p->ring_id;
957         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
958         struct intel_vgpu_workload *workload = NULL;
959         struct intel_vgpu *vgpu = NULL;
960         int ret;
961         bool need_force_wake = (INTEL_GEN(gvt->dev_priv) >= 9);
962         DEFINE_WAIT_FUNC(wait, woken_wake_function);
963
964         kfree(p);
965
966         gvt_dbg_core("workload thread for ring %d started\n", ring_id);
967
968         while (!kthread_should_stop()) {
969                 add_wait_queue(&scheduler->waitq[ring_id], &wait);
970                 do {
971                         workload = pick_next_workload(gvt, ring_id);
972                         if (workload)
973                                 break;
974                         wait_woken(&wait, TASK_INTERRUPTIBLE,
975                                    MAX_SCHEDULE_TIMEOUT);
976                 } while (!kthread_should_stop());
977                 remove_wait_queue(&scheduler->waitq[ring_id], &wait);
978
979                 if (!workload)
980                         break;
981
982                 gvt_dbg_sched("ring id %d next workload %p vgpu %d\n",
983                                 workload->ring_id, workload,
984                                 workload->vgpu->id);
985
986                 intel_runtime_pm_get(gvt->dev_priv);
987
988                 gvt_dbg_sched("ring id %d will dispatch workload %p\n",
989                                 workload->ring_id, workload);
990
991                 if (need_force_wake)
992                         intel_uncore_forcewake_get(gvt->dev_priv,
993                                         FORCEWAKE_ALL);
994
995                 ret = dispatch_workload(workload);
996
997                 if (ret) {
998                         vgpu = workload->vgpu;
999                         gvt_vgpu_err("fail to dispatch workload, skip\n");
1000                         goto complete;
1001                 }
1002
1003                 gvt_dbg_sched("ring id %d wait workload %p\n",
1004                                 workload->ring_id, workload);
1005                 i915_request_wait(workload->req, 0, MAX_SCHEDULE_TIMEOUT);
1006
1007 complete:
1008                 gvt_dbg_sched("will complete workload %p, status: %d\n",
1009                                 workload, workload->status);
1010
1011                 complete_current_workload(gvt, ring_id);
1012
1013                 if (need_force_wake)
1014                         intel_uncore_forcewake_put(gvt->dev_priv,
1015                                         FORCEWAKE_ALL);
1016
1017                 intel_runtime_pm_put_unchecked(gvt->dev_priv);
1018                 if (ret && (vgpu_is_vm_unhealthy(ret)))
1019                         enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR);
1020         }
1021         return 0;
1022 }
1023
1024 void intel_gvt_wait_vgpu_idle(struct intel_vgpu *vgpu)
1025 {
1026         struct intel_vgpu_submission *s = &vgpu->submission;
1027         struct intel_gvt *gvt = vgpu->gvt;
1028         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1029
1030         if (atomic_read(&s->running_workload_num)) {
1031                 gvt_dbg_sched("wait vgpu idle\n");
1032
1033                 wait_event(scheduler->workload_complete_wq,
1034                                 !atomic_read(&s->running_workload_num));
1035         }
1036 }
1037
1038 void intel_gvt_clean_workload_scheduler(struct intel_gvt *gvt)
1039 {
1040         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1041         struct intel_engine_cs *engine;
1042         enum intel_engine_id i;
1043
1044         gvt_dbg_core("clean workload scheduler\n");
1045
1046         for_each_engine(engine, gvt->dev_priv, i) {
1047                 atomic_notifier_chain_unregister(
1048                                         &engine->context_status_notifier,
1049                                         &gvt->shadow_ctx_notifier_block[i]);
1050                 kthread_stop(scheduler->thread[i]);
1051         }
1052 }
1053
1054 int intel_gvt_init_workload_scheduler(struct intel_gvt *gvt)
1055 {
1056         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1057         struct workload_thread_param *param = NULL;
1058         struct intel_engine_cs *engine;
1059         enum intel_engine_id i;
1060         int ret;
1061
1062         gvt_dbg_core("init workload scheduler\n");
1063
1064         init_waitqueue_head(&scheduler->workload_complete_wq);
1065
1066         for_each_engine(engine, gvt->dev_priv, i) {
1067                 init_waitqueue_head(&scheduler->waitq[i]);
1068
1069                 param = kzalloc(sizeof(*param), GFP_KERNEL);
1070                 if (!param) {
1071                         ret = -ENOMEM;
1072                         goto err;
1073                 }
1074
1075                 param->gvt = gvt;
1076                 param->ring_id = i;
1077
1078                 scheduler->thread[i] = kthread_run(workload_thread, param,
1079                         "gvt workload %d", i);
1080                 if (IS_ERR(scheduler->thread[i])) {
1081                         gvt_err("fail to create workload thread\n");
1082                         ret = PTR_ERR(scheduler->thread[i]);
1083                         goto err;
1084                 }
1085
1086                 gvt->shadow_ctx_notifier_block[i].notifier_call =
1087                                         shadow_context_status_change;
1088                 atomic_notifier_chain_register(&engine->context_status_notifier,
1089                                         &gvt->shadow_ctx_notifier_block[i]);
1090         }
1091         return 0;
1092 err:
1093         intel_gvt_clean_workload_scheduler(gvt);
1094         kfree(param);
1095         param = NULL;
1096         return ret;
1097 }
1098
1099 static void
1100 i915_context_ppgtt_root_restore(struct intel_vgpu_submission *s)
1101 {
1102         struct i915_hw_ppgtt *i915_ppgtt = s->shadow_ctx->ppgtt;
1103         int i;
1104
1105         if (i915_vm_is_48bit(&i915_ppgtt->vm))
1106                 px_dma(&i915_ppgtt->pml4) = s->i915_context_pml4;
1107         else {
1108                 for (i = 0; i < GEN8_3LVL_PDPES; i++)
1109                         px_dma(i915_ppgtt->pdp.page_directory[i]) =
1110                                                 s->i915_context_pdps[i];
1111         }
1112 }
1113
1114 /**
1115  * intel_vgpu_clean_submission - free submission-related resource for vGPU
1116  * @vgpu: a vGPU
1117  *
1118  * This function is called when a vGPU is being destroyed.
1119  *
1120  */
1121 void intel_vgpu_clean_submission(struct intel_vgpu *vgpu)
1122 {
1123         struct intel_vgpu_submission *s = &vgpu->submission;
1124
1125         intel_vgpu_select_submission_ops(vgpu, ALL_ENGINES, 0);
1126         i915_context_ppgtt_root_restore(s);
1127         i915_gem_context_put(s->shadow_ctx);
1128         kmem_cache_destroy(s->workloads);
1129 }
1130
1131
1132 /**
1133  * intel_vgpu_reset_submission - reset submission-related resource for vGPU
1134  * @vgpu: a vGPU
1135  * @engine_mask: engines expected to be reset
1136  *
1137  * This function is called when a vGPU is being destroyed.
1138  *
1139  */
1140 void intel_vgpu_reset_submission(struct intel_vgpu *vgpu,
1141                 unsigned long engine_mask)
1142 {
1143         struct intel_vgpu_submission *s = &vgpu->submission;
1144
1145         if (!s->active)
1146                 return;
1147
1148         intel_vgpu_clean_workloads(vgpu, engine_mask);
1149         s->ops->reset(vgpu, engine_mask);
1150 }
1151
1152 static void
1153 i915_context_ppgtt_root_save(struct intel_vgpu_submission *s)
1154 {
1155         struct i915_hw_ppgtt *i915_ppgtt = s->shadow_ctx->ppgtt;
1156         int i;
1157
1158         if (i915_vm_is_48bit(&i915_ppgtt->vm))
1159                 s->i915_context_pml4 = px_dma(&i915_ppgtt->pml4);
1160         else {
1161                 for (i = 0; i < GEN8_3LVL_PDPES; i++)
1162                         s->i915_context_pdps[i] =
1163                                 px_dma(i915_ppgtt->pdp.page_directory[i]);
1164         }
1165 }
1166
1167 /**
1168  * intel_vgpu_setup_submission - setup submission-related resource for vGPU
1169  * @vgpu: a vGPU
1170  *
1171  * This function is called when a vGPU is being created.
1172  *
1173  * Returns:
1174  * Zero on success, negative error code if failed.
1175  *
1176  */
1177 int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
1178 {
1179         struct intel_vgpu_submission *s = &vgpu->submission;
1180         enum intel_engine_id i;
1181         struct intel_engine_cs *engine;
1182         int ret;
1183
1184         s->shadow_ctx = i915_gem_context_create_gvt(
1185                         &vgpu->gvt->dev_priv->drm);
1186         if (IS_ERR(s->shadow_ctx))
1187                 return PTR_ERR(s->shadow_ctx);
1188
1189         i915_context_ppgtt_root_save(s);
1190
1191         bitmap_zero(s->shadow_ctx_desc_updated, I915_NUM_ENGINES);
1192
1193         s->workloads = kmem_cache_create_usercopy("gvt-g_vgpu_workload",
1194                                                   sizeof(struct intel_vgpu_workload), 0,
1195                                                   SLAB_HWCACHE_ALIGN,
1196                                                   offsetof(struct intel_vgpu_workload, rb_tail),
1197                                                   sizeof_field(struct intel_vgpu_workload, rb_tail),
1198                                                   NULL);
1199
1200         if (!s->workloads) {
1201                 ret = -ENOMEM;
1202                 goto out_shadow_ctx;
1203         }
1204
1205         for_each_engine(engine, vgpu->gvt->dev_priv, i)
1206                 INIT_LIST_HEAD(&s->workload_q_head[i]);
1207
1208         atomic_set(&s->running_workload_num, 0);
1209         bitmap_zero(s->tlb_handle_pending, I915_NUM_ENGINES);
1210
1211         return 0;
1212
1213 out_shadow_ctx:
1214         i915_gem_context_put(s->shadow_ctx);
1215         return ret;
1216 }
1217
1218 /**
1219  * intel_vgpu_select_submission_ops - select virtual submission interface
1220  * @vgpu: a vGPU
1221  * @engine_mask: either ALL_ENGINES or target engine mask
1222  * @interface: expected vGPU virtual submission interface
1223  *
1224  * This function is called when guest configures submission interface.
1225  *
1226  * Returns:
1227  * Zero on success, negative error code if failed.
1228  *
1229  */
1230 int intel_vgpu_select_submission_ops(struct intel_vgpu *vgpu,
1231                                      unsigned long engine_mask,
1232                                      unsigned int interface)
1233 {
1234         struct intel_vgpu_submission *s = &vgpu->submission;
1235         const struct intel_vgpu_submission_ops *ops[] = {
1236                 [INTEL_VGPU_EXECLIST_SUBMISSION] =
1237                         &intel_vgpu_execlist_submission_ops,
1238         };
1239         int ret;
1240
1241         if (WARN_ON(interface >= ARRAY_SIZE(ops)))
1242                 return -EINVAL;
1243
1244         if (WARN_ON(interface == 0 && engine_mask != ALL_ENGINES))
1245                 return -EINVAL;
1246
1247         if (s->active)
1248                 s->ops->clean(vgpu, engine_mask);
1249
1250         if (interface == 0) {
1251                 s->ops = NULL;
1252                 s->virtual_submission_interface = 0;
1253                 s->active = false;
1254                 gvt_dbg_core("vgpu%d: remove submission ops\n", vgpu->id);
1255                 return 0;
1256         }
1257
1258         ret = ops[interface]->init(vgpu, engine_mask);
1259         if (ret)
1260                 return ret;
1261
1262         s->ops = ops[interface];
1263         s->virtual_submission_interface = interface;
1264         s->active = true;
1265
1266         gvt_dbg_core("vgpu%d: activate ops [ %s ]\n",
1267                         vgpu->id, s->ops->name);
1268
1269         return 0;
1270 }
1271
1272 /**
1273  * intel_vgpu_destroy_workload - destroy a vGPU workload
1274  * @workload: workload to destroy
1275  *
1276  * This function is called when destroy a vGPU workload.
1277  *
1278  */
1279 void intel_vgpu_destroy_workload(struct intel_vgpu_workload *workload)
1280 {
1281         struct intel_vgpu_submission *s = &workload->vgpu->submission;
1282
1283         release_shadow_batch_buffer(workload);
1284         release_shadow_wa_ctx(&workload->wa_ctx);
1285
1286         if (workload->shadow_mm)
1287                 intel_vgpu_mm_put(workload->shadow_mm);
1288
1289         kmem_cache_free(s->workloads, workload);
1290 }
1291
1292 static struct intel_vgpu_workload *
1293 alloc_workload(struct intel_vgpu *vgpu)
1294 {
1295         struct intel_vgpu_submission *s = &vgpu->submission;
1296         struct intel_vgpu_workload *workload;
1297
1298         workload = kmem_cache_zalloc(s->workloads, GFP_KERNEL);
1299         if (!workload)
1300                 return ERR_PTR(-ENOMEM);
1301
1302         INIT_LIST_HEAD(&workload->list);
1303         INIT_LIST_HEAD(&workload->shadow_bb);
1304
1305         init_waitqueue_head(&workload->shadow_ctx_status_wq);
1306         atomic_set(&workload->shadow_ctx_active, 0);
1307
1308         workload->status = -EINPROGRESS;
1309         workload->vgpu = vgpu;
1310
1311         return workload;
1312 }
1313
1314 #define RING_CTX_OFF(x) \
1315         offsetof(struct execlist_ring_context, x)
1316
1317 static void read_guest_pdps(struct intel_vgpu *vgpu,
1318                 u64 ring_context_gpa, u32 pdp[8])
1319 {
1320         u64 gpa;
1321         int i;
1322
1323         gpa = ring_context_gpa + RING_CTX_OFF(pdps[0].val);
1324
1325         for (i = 0; i < 8; i++)
1326                 intel_gvt_hypervisor_read_gpa(vgpu,
1327                                 gpa + i * 8, &pdp[7 - i], 4);
1328 }
1329
1330 static int prepare_mm(struct intel_vgpu_workload *workload)
1331 {
1332         struct execlist_ctx_descriptor_format *desc = &workload->ctx_desc;
1333         struct intel_vgpu_mm *mm;
1334         struct intel_vgpu *vgpu = workload->vgpu;
1335         intel_gvt_gtt_type_t root_entry_type;
1336         u64 pdps[GVT_RING_CTX_NR_PDPS];
1337
1338         switch (desc->addressing_mode) {
1339         case 1: /* legacy 32-bit */
1340                 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY;
1341                 break;
1342         case 3: /* legacy 64-bit */
1343                 root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
1344                 break;
1345         default:
1346                 gvt_vgpu_err("Advanced Context mode(SVM) is not supported!\n");
1347                 return -EINVAL;
1348         }
1349
1350         read_guest_pdps(workload->vgpu, workload->ring_context_gpa, (void *)pdps);
1351
1352         mm = intel_vgpu_get_ppgtt_mm(workload->vgpu, root_entry_type, pdps);
1353         if (IS_ERR(mm))
1354                 return PTR_ERR(mm);
1355
1356         workload->shadow_mm = mm;
1357         return 0;
1358 }
1359
1360 #define same_context(a, b) (((a)->context_id == (b)->context_id) && \
1361                 ((a)->lrca == (b)->lrca))
1362
1363 #define get_last_workload(q) \
1364         (list_empty(q) ? NULL : container_of(q->prev, \
1365         struct intel_vgpu_workload, list))
1366 /**
1367  * intel_vgpu_create_workload - create a vGPU workload
1368  * @vgpu: a vGPU
1369  * @ring_id: ring index
1370  * @desc: a guest context descriptor
1371  *
1372  * This function is called when creating a vGPU workload.
1373  *
1374  * Returns:
1375  * struct intel_vgpu_workload * on success, negative error code in
1376  * pointer if failed.
1377  *
1378  */
1379 struct intel_vgpu_workload *
1380 intel_vgpu_create_workload(struct intel_vgpu *vgpu, int ring_id,
1381                            struct execlist_ctx_descriptor_format *desc)
1382 {
1383         struct intel_vgpu_submission *s = &vgpu->submission;
1384         struct list_head *q = workload_q_head(vgpu, ring_id);
1385         struct intel_vgpu_workload *last_workload = get_last_workload(q);
1386         struct intel_vgpu_workload *workload = NULL;
1387         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1388         u64 ring_context_gpa;
1389         u32 head, tail, start, ctl, ctx_ctl, per_ctx, indirect_ctx;
1390         int ret;
1391
1392         ring_context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
1393                         (u32)((desc->lrca + 1) << I915_GTT_PAGE_SHIFT));
1394         if (ring_context_gpa == INTEL_GVT_INVALID_ADDR) {
1395                 gvt_vgpu_err("invalid guest context LRCA: %x\n", desc->lrca);
1396                 return ERR_PTR(-EINVAL);
1397         }
1398
1399         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1400                         RING_CTX_OFF(ring_header.val), &head, 4);
1401
1402         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1403                         RING_CTX_OFF(ring_tail.val), &tail, 4);
1404
1405         head &= RB_HEAD_OFF_MASK;
1406         tail &= RB_TAIL_OFF_MASK;
1407
1408         if (last_workload && same_context(&last_workload->ctx_desc, desc)) {
1409                 gvt_dbg_el("ring id %d cur workload == last\n", ring_id);
1410                 gvt_dbg_el("ctx head %x real head %lx\n", head,
1411                                 last_workload->rb_tail);
1412                 /*
1413                  * cannot use guest context head pointer here,
1414                  * as it might not be updated at this time
1415                  */
1416                 head = last_workload->rb_tail;
1417         }
1418
1419         gvt_dbg_el("ring id %d begin a new workload\n", ring_id);
1420
1421         /* record some ring buffer register values for scan and shadow */
1422         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1423                         RING_CTX_OFF(rb_start.val), &start, 4);
1424         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1425                         RING_CTX_OFF(rb_ctrl.val), &ctl, 4);
1426         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1427                         RING_CTX_OFF(ctx_ctrl.val), &ctx_ctl, 4);
1428
1429         workload = alloc_workload(vgpu);
1430         if (IS_ERR(workload))
1431                 return workload;
1432
1433         workload->ring_id = ring_id;
1434         workload->ctx_desc = *desc;
1435         workload->ring_context_gpa = ring_context_gpa;
1436         workload->rb_head = head;
1437         workload->rb_tail = tail;
1438         workload->rb_start = start;
1439         workload->rb_ctl = ctl;
1440
1441         if (ring_id == RCS) {
1442                 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1443                         RING_CTX_OFF(bb_per_ctx_ptr.val), &per_ctx, 4);
1444                 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1445                         RING_CTX_OFF(rcs_indirect_ctx.val), &indirect_ctx, 4);
1446
1447                 workload->wa_ctx.indirect_ctx.guest_gma =
1448                         indirect_ctx & INDIRECT_CTX_ADDR_MASK;
1449                 workload->wa_ctx.indirect_ctx.size =
1450                         (indirect_ctx & INDIRECT_CTX_SIZE_MASK) *
1451                         CACHELINE_BYTES;
1452                 workload->wa_ctx.per_ctx.guest_gma =
1453                         per_ctx & PER_CTX_ADDR_MASK;
1454                 workload->wa_ctx.per_ctx.valid = per_ctx & 1;
1455         }
1456
1457         gvt_dbg_el("workload %p ring id %d head %x tail %x start %x ctl %x\n",
1458                         workload, ring_id, head, tail, start, ctl);
1459
1460         ret = prepare_mm(workload);
1461         if (ret) {
1462                 kmem_cache_free(s->workloads, workload);
1463                 return ERR_PTR(ret);
1464         }
1465
1466         /* Only scan and shadow the first workload in the queue
1467          * as there is only one pre-allocated buf-obj for shadow.
1468          */
1469         if (list_empty(workload_q_head(vgpu, ring_id))) {
1470                 intel_runtime_pm_get(dev_priv);
1471                 mutex_lock(&dev_priv->drm.struct_mutex);
1472                 ret = intel_gvt_scan_and_shadow_workload(workload);
1473                 mutex_unlock(&dev_priv->drm.struct_mutex);
1474                 intel_runtime_pm_put_unchecked(dev_priv);
1475         }
1476
1477         if (ret && (vgpu_is_vm_unhealthy(ret))) {
1478                 enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR);
1479                 intel_vgpu_destroy_workload(workload);
1480                 return ERR_PTR(ret);
1481         }
1482
1483         return workload;
1484 }
1485
1486 /**
1487  * intel_vgpu_queue_workload - Qeue a vGPU workload
1488  * @workload: the workload to queue in
1489  */
1490 void intel_vgpu_queue_workload(struct intel_vgpu_workload *workload)
1491 {
1492         list_add_tail(&workload->list,
1493                 workload_q_head(workload->vgpu, workload->ring_id));
1494         intel_gvt_kick_schedule(workload->vgpu->gvt);
1495         wake_up(&workload->vgpu->gvt->scheduler.waitq[workload->ring_id]);
1496 }