Merge airlied/drm-next into drm-intel-next-queued
[muen/linux.git] / drivers / gpu / drm / i915 / i915_drv.c
1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2  */
3 /*
4  *
5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6  * All Rights Reserved.
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a
9  * copy of this software and associated documentation files (the
10  * "Software"), to deal in the Software without restriction, including
11  * without limitation the rights to use, copy, modify, merge, publish,
12  * distribute, sub license, and/or sell copies of the Software, and to
13  * permit persons to whom the Software is furnished to do so, subject to
14  * the following conditions:
15  *
16  * The above copyright notice and this permission notice (including the
17  * next paragraph) shall be included in all copies or substantial portions
18  * of the Software.
19  *
20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27  *
28  */
29
30 #include <linux/acpi.h>
31 #include <linux/device.h>
32 #include <linux/oom.h>
33 #include <linux/module.h>
34 #include <linux/pci.h>
35 #include <linux/pm.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/pnp.h>
38 #include <linux/slab.h>
39 #include <linux/vgaarb.h>
40 #include <linux/vga_switcheroo.h>
41 #include <linux/vt.h>
42 #include <acpi/video.h>
43
44 #include <drm/drmP.h>
45 #include <drm/drm_crtc_helper.h>
46 #include <drm/drm_atomic_helper.h>
47 #include <drm/i915_drm.h>
48
49 #include "i915_drv.h"
50 #include "i915_trace.h"
51 #include "i915_vgpu.h"
52 #include "intel_drv.h"
53 #include "intel_uc.h"
54
55 static struct drm_driver driver;
56
57 static unsigned int i915_load_fail_count;
58
59 bool __i915_inject_load_failure(const char *func, int line)
60 {
61         if (i915_load_fail_count >= i915.inject_load_failure)
62                 return false;
63
64         if (++i915_load_fail_count == i915.inject_load_failure) {
65                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
66                          i915.inject_load_failure, func, line);
67                 return true;
68         }
69
70         return false;
71 }
72
73 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
74 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
75                     "providing the dmesg log by booting with drm.debug=0xf"
76
77 void
78 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
79               const char *fmt, ...)
80 {
81         static bool shown_bug_once;
82         struct device *kdev = dev_priv->drm.dev;
83         bool is_error = level[1] <= KERN_ERR[1];
84         bool is_debug = level[1] == KERN_DEBUG[1];
85         struct va_format vaf;
86         va_list args;
87
88         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
89                 return;
90
91         va_start(args, fmt);
92
93         vaf.fmt = fmt;
94         vaf.va = &args;
95
96         dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
97                    __builtin_return_address(0), &vaf);
98
99         if (is_error && !shown_bug_once) {
100                 dev_notice(kdev, "%s", FDO_BUG_MSG);
101                 shown_bug_once = true;
102         }
103
104         va_end(args);
105 }
106
107 static bool i915_error_injected(struct drm_i915_private *dev_priv)
108 {
109         return i915.inject_load_failure &&
110                i915_load_fail_count == i915.inject_load_failure;
111 }
112
113 #define i915_load_error(dev_priv, fmt, ...)                                  \
114         __i915_printk(dev_priv,                                              \
115                       i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
116                       fmt, ##__VA_ARGS__)
117
118
119 static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
120 {
121         enum intel_pch ret = PCH_NOP;
122
123         /*
124          * In a virtualized passthrough environment we can be in a
125          * setup where the ISA bridge is not able to be passed through.
126          * In this case, a south bridge can be emulated and we have to
127          * make an educated guess as to which PCH is really there.
128          */
129
130         if (IS_GEN5(dev_priv)) {
131                 ret = PCH_IBX;
132                 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
133         } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
134                 ret = PCH_CPT;
135                 DRM_DEBUG_KMS("Assuming CougarPoint PCH\n");
136         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
137                 ret = PCH_LPT;
138                 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
139                         dev_priv->pch_id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
140                 else
141                         dev_priv->pch_id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
142                 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
143         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
144                 ret = PCH_SPT;
145                 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
146         } else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
147                 ret = PCH_CNP;
148                 DRM_DEBUG_KMS("Assuming CannonPoint PCH\n");
149         }
150
151         return ret;
152 }
153
154 static void intel_detect_pch(struct drm_i915_private *dev_priv)
155 {
156         struct pci_dev *pch = NULL;
157
158         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
159          * (which really amounts to a PCH but no South Display).
160          */
161         if (INTEL_INFO(dev_priv)->num_pipes == 0) {
162                 dev_priv->pch_type = PCH_NOP;
163                 return;
164         }
165
166         /*
167          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
168          * make graphics device passthrough work easy for VMM, that only
169          * need to expose ISA bridge to let driver know the real hardware
170          * underneath. This is a requirement from virtualization team.
171          *
172          * In some virtualized environments (e.g. XEN), there is irrelevant
173          * ISA bridge in the system. To work reliably, we should scan trhough
174          * all the ISA bridge devices and check for the first match, instead
175          * of only checking the first one.
176          */
177         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
178                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
179                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
180
181                         dev_priv->pch_id = id;
182
183                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
184                                 dev_priv->pch_type = PCH_IBX;
185                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
186                                 WARN_ON(!IS_GEN5(dev_priv));
187                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
188                                 dev_priv->pch_type = PCH_CPT;
189                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
190                                 WARN_ON(!IS_GEN6(dev_priv) &&
191                                         !IS_IVYBRIDGE(dev_priv));
192                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
193                                 /* PantherPoint is CPT compatible */
194                                 dev_priv->pch_type = PCH_CPT;
195                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
196                                 WARN_ON(!IS_GEN6(dev_priv) &&
197                                         !IS_IVYBRIDGE(dev_priv));
198                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
199                                 dev_priv->pch_type = PCH_LPT;
200                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
201                                 WARN_ON(!IS_HASWELL(dev_priv) &&
202                                         !IS_BROADWELL(dev_priv));
203                                 WARN_ON(IS_HSW_ULT(dev_priv) ||
204                                         IS_BDW_ULT(dev_priv));
205                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
206                                 dev_priv->pch_type = PCH_LPT;
207                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
208                                 WARN_ON(!IS_HASWELL(dev_priv) &&
209                                         !IS_BROADWELL(dev_priv));
210                                 WARN_ON(!IS_HSW_ULT(dev_priv) &&
211                                         !IS_BDW_ULT(dev_priv));
212                         } else if (id == INTEL_PCH_WPT_DEVICE_ID_TYPE) {
213                                 /* WildcatPoint is LPT compatible */
214                                 dev_priv->pch_type = PCH_LPT;
215                                 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
216                                 WARN_ON(!IS_HASWELL(dev_priv) &&
217                                         !IS_BROADWELL(dev_priv));
218                                 WARN_ON(IS_HSW_ULT(dev_priv) ||
219                                         IS_BDW_ULT(dev_priv));
220                         } else if (id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE) {
221                                 /* WildcatPoint is LPT compatible */
222                                 dev_priv->pch_type = PCH_LPT;
223                                 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
224                                 WARN_ON(!IS_HASWELL(dev_priv) &&
225                                         !IS_BROADWELL(dev_priv));
226                                 WARN_ON(!IS_HSW_ULT(dev_priv) &&
227                                         !IS_BDW_ULT(dev_priv));
228                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
229                                 dev_priv->pch_type = PCH_SPT;
230                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
231                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
232                                         !IS_KABYLAKE(dev_priv));
233                         } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
234                                 dev_priv->pch_type = PCH_SPT;
235                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
236                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
237                                         !IS_KABYLAKE(dev_priv));
238                         } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
239                                 dev_priv->pch_type = PCH_KBP;
240                                 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
241                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
242                                         !IS_KABYLAKE(dev_priv));
243                         } else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
244                                 dev_priv->pch_type = PCH_CNP;
245                                 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
246                                 WARN_ON(!IS_CANNONLAKE(dev_priv) &&
247                                         !IS_COFFEELAKE(dev_priv));
248                         } else if (id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
249                                 dev_priv->pch_type = PCH_CNP;
250                                 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
251                                 WARN_ON(!IS_CANNONLAKE(dev_priv) &&
252                                         !IS_COFFEELAKE(dev_priv));
253                         } else if (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
254                                    id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
255                                    (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
256                                     pch->subsystem_vendor ==
257                                             PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
258                                     pch->subsystem_device ==
259                                             PCI_SUBDEVICE_ID_QEMU)) {
260                                 dev_priv->pch_type =
261                                         intel_virt_detect_pch(dev_priv);
262                         } else
263                                 continue;
264
265                         break;
266                 }
267         }
268         if (!pch)
269                 DRM_DEBUG_KMS("No PCH found.\n");
270
271         pci_dev_put(pch);
272 }
273
274 static int i915_getparam(struct drm_device *dev, void *data,
275                          struct drm_file *file_priv)
276 {
277         struct drm_i915_private *dev_priv = to_i915(dev);
278         struct pci_dev *pdev = dev_priv->drm.pdev;
279         drm_i915_getparam_t *param = data;
280         int value;
281
282         switch (param->param) {
283         case I915_PARAM_IRQ_ACTIVE:
284         case I915_PARAM_ALLOW_BATCHBUFFER:
285         case I915_PARAM_LAST_DISPATCH:
286         case I915_PARAM_HAS_EXEC_CONSTANTS:
287                 /* Reject all old ums/dri params. */
288                 return -ENODEV;
289         case I915_PARAM_CHIPSET_ID:
290                 value = pdev->device;
291                 break;
292         case I915_PARAM_REVISION:
293                 value = pdev->revision;
294                 break;
295         case I915_PARAM_NUM_FENCES_AVAIL:
296                 value = dev_priv->num_fence_regs;
297                 break;
298         case I915_PARAM_HAS_OVERLAY:
299                 value = dev_priv->overlay ? 1 : 0;
300                 break;
301         case I915_PARAM_HAS_BSD:
302                 value = !!dev_priv->engine[VCS];
303                 break;
304         case I915_PARAM_HAS_BLT:
305                 value = !!dev_priv->engine[BCS];
306                 break;
307         case I915_PARAM_HAS_VEBOX:
308                 value = !!dev_priv->engine[VECS];
309                 break;
310         case I915_PARAM_HAS_BSD2:
311                 value = !!dev_priv->engine[VCS2];
312                 break;
313         case I915_PARAM_HAS_LLC:
314                 value = HAS_LLC(dev_priv);
315                 break;
316         case I915_PARAM_HAS_WT:
317                 value = HAS_WT(dev_priv);
318                 break;
319         case I915_PARAM_HAS_ALIASING_PPGTT:
320                 value = USES_PPGTT(dev_priv);
321                 break;
322         case I915_PARAM_HAS_SEMAPHORES:
323                 value = i915.semaphores;
324                 break;
325         case I915_PARAM_HAS_SECURE_BATCHES:
326                 value = capable(CAP_SYS_ADMIN);
327                 break;
328         case I915_PARAM_CMD_PARSER_VERSION:
329                 value = i915_cmd_parser_get_version(dev_priv);
330                 break;
331         case I915_PARAM_SUBSLICE_TOTAL:
332                 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
333                 if (!value)
334                         return -ENODEV;
335                 break;
336         case I915_PARAM_EU_TOTAL:
337                 value = INTEL_INFO(dev_priv)->sseu.eu_total;
338                 if (!value)
339                         return -ENODEV;
340                 break;
341         case I915_PARAM_HAS_GPU_RESET:
342                 value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
343                 if (value && intel_has_reset_engine(dev_priv))
344                         value = 2;
345                 break;
346         case I915_PARAM_HAS_RESOURCE_STREAMER:
347                 value = HAS_RESOURCE_STREAMER(dev_priv);
348                 break;
349         case I915_PARAM_HAS_POOLED_EU:
350                 value = HAS_POOLED_EU(dev_priv);
351                 break;
352         case I915_PARAM_MIN_EU_IN_POOL:
353                 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
354                 break;
355         case I915_PARAM_HUC_STATUS:
356                 intel_runtime_pm_get(dev_priv);
357                 value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
358                 intel_runtime_pm_put(dev_priv);
359                 break;
360         case I915_PARAM_MMAP_GTT_VERSION:
361                 /* Though we've started our numbering from 1, and so class all
362                  * earlier versions as 0, in effect their value is undefined as
363                  * the ioctl will report EINVAL for the unknown param!
364                  */
365                 value = i915_gem_mmap_gtt_version();
366                 break;
367         case I915_PARAM_HAS_SCHEDULER:
368                 value = dev_priv->engine[RCS] &&
369                         dev_priv->engine[RCS]->schedule;
370                 break;
371         case I915_PARAM_MMAP_VERSION:
372                 /* Remember to bump this if the version changes! */
373         case I915_PARAM_HAS_GEM:
374         case I915_PARAM_HAS_PAGEFLIPPING:
375         case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
376         case I915_PARAM_HAS_RELAXED_FENCING:
377         case I915_PARAM_HAS_COHERENT_RINGS:
378         case I915_PARAM_HAS_RELAXED_DELTA:
379         case I915_PARAM_HAS_GEN7_SOL_RESET:
380         case I915_PARAM_HAS_WAIT_TIMEOUT:
381         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
382         case I915_PARAM_HAS_PINNED_BATCHES:
383         case I915_PARAM_HAS_EXEC_NO_RELOC:
384         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
385         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
386         case I915_PARAM_HAS_EXEC_SOFTPIN:
387         case I915_PARAM_HAS_EXEC_ASYNC:
388         case I915_PARAM_HAS_EXEC_FENCE:
389         case I915_PARAM_HAS_EXEC_CAPTURE:
390         case I915_PARAM_HAS_EXEC_BATCH_FIRST:
391                 /* For the time being all of these are always true;
392                  * if some supported hardware does not have one of these
393                  * features this value needs to be provided from
394                  * INTEL_INFO(), a feature macro, or similar.
395                  */
396                 value = 1;
397                 break;
398         case I915_PARAM_SLICE_MASK:
399                 value = INTEL_INFO(dev_priv)->sseu.slice_mask;
400                 if (!value)
401                         return -ENODEV;
402                 break;
403         case I915_PARAM_SUBSLICE_MASK:
404                 value = INTEL_INFO(dev_priv)->sseu.subslice_mask;
405                 if (!value)
406                         return -ENODEV;
407                 break;
408         default:
409                 DRM_DEBUG("Unknown parameter %d\n", param->param);
410                 return -EINVAL;
411         }
412
413         if (put_user(value, param->value))
414                 return -EFAULT;
415
416         return 0;
417 }
418
419 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
420 {
421         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
422         if (!dev_priv->bridge_dev) {
423                 DRM_ERROR("bridge device not found\n");
424                 return -1;
425         }
426         return 0;
427 }
428
429 /* Allocate space for the MCH regs if needed, return nonzero on error */
430 static int
431 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
432 {
433         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
434         u32 temp_lo, temp_hi = 0;
435         u64 mchbar_addr;
436         int ret;
437
438         if (INTEL_GEN(dev_priv) >= 4)
439                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
440         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
441         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
442
443         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
444 #ifdef CONFIG_PNP
445         if (mchbar_addr &&
446             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
447                 return 0;
448 #endif
449
450         /* Get some space for it */
451         dev_priv->mch_res.name = "i915 MCHBAR";
452         dev_priv->mch_res.flags = IORESOURCE_MEM;
453         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
454                                      &dev_priv->mch_res,
455                                      MCHBAR_SIZE, MCHBAR_SIZE,
456                                      PCIBIOS_MIN_MEM,
457                                      0, pcibios_align_resource,
458                                      dev_priv->bridge_dev);
459         if (ret) {
460                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
461                 dev_priv->mch_res.start = 0;
462                 return ret;
463         }
464
465         if (INTEL_GEN(dev_priv) >= 4)
466                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
467                                        upper_32_bits(dev_priv->mch_res.start));
468
469         pci_write_config_dword(dev_priv->bridge_dev, reg,
470                                lower_32_bits(dev_priv->mch_res.start));
471         return 0;
472 }
473
474 /* Setup MCHBAR if possible, return true if we should disable it again */
475 static void
476 intel_setup_mchbar(struct drm_i915_private *dev_priv)
477 {
478         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
479         u32 temp;
480         bool enabled;
481
482         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
483                 return;
484
485         dev_priv->mchbar_need_disable = false;
486
487         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
488                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
489                 enabled = !!(temp & DEVEN_MCHBAR_EN);
490         } else {
491                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
492                 enabled = temp & 1;
493         }
494
495         /* If it's already enabled, don't have to do anything */
496         if (enabled)
497                 return;
498
499         if (intel_alloc_mchbar_resource(dev_priv))
500                 return;
501
502         dev_priv->mchbar_need_disable = true;
503
504         /* Space is allocated or reserved, so enable it. */
505         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
506                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
507                                        temp | DEVEN_MCHBAR_EN);
508         } else {
509                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
510                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
511         }
512 }
513
514 static void
515 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
516 {
517         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
518
519         if (dev_priv->mchbar_need_disable) {
520                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
521                         u32 deven_val;
522
523                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
524                                               &deven_val);
525                         deven_val &= ~DEVEN_MCHBAR_EN;
526                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
527                                                deven_val);
528                 } else {
529                         u32 mchbar_val;
530
531                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
532                                               &mchbar_val);
533                         mchbar_val &= ~1;
534                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
535                                                mchbar_val);
536                 }
537         }
538
539         if (dev_priv->mch_res.start)
540                 release_resource(&dev_priv->mch_res);
541 }
542
543 /* true = enable decode, false = disable decoder */
544 static unsigned int i915_vga_set_decode(void *cookie, bool state)
545 {
546         struct drm_i915_private *dev_priv = cookie;
547
548         intel_modeset_vga_set_state(dev_priv, state);
549         if (state)
550                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
551                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
552         else
553                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
554 }
555
556 static int i915_resume_switcheroo(struct drm_device *dev);
557 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
558
559 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
560 {
561         struct drm_device *dev = pci_get_drvdata(pdev);
562         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
563
564         if (state == VGA_SWITCHEROO_ON) {
565                 pr_info("switched on\n");
566                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
567                 /* i915 resume handler doesn't set to D0 */
568                 pci_set_power_state(pdev, PCI_D0);
569                 i915_resume_switcheroo(dev);
570                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
571         } else {
572                 pr_info("switched off\n");
573                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
574                 i915_suspend_switcheroo(dev, pmm);
575                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
576         }
577 }
578
579 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
580 {
581         struct drm_device *dev = pci_get_drvdata(pdev);
582
583         /*
584          * FIXME: open_count is protected by drm_global_mutex but that would lead to
585          * locking inversion with the driver load path. And the access here is
586          * completely racy anyway. So don't bother with locking for now.
587          */
588         return dev->open_count == 0;
589 }
590
591 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
592         .set_gpu_state = i915_switcheroo_set_state,
593         .reprobe = NULL,
594         .can_switch = i915_switcheroo_can_switch,
595 };
596
597 static void i915_gem_fini(struct drm_i915_private *dev_priv)
598 {
599         /* Flush any outstanding unpin_work. */
600         i915_gem_drain_workqueue(dev_priv);
601
602         mutex_lock(&dev_priv->drm.struct_mutex);
603         intel_uc_fini_hw(dev_priv);
604         i915_gem_cleanup_engines(dev_priv);
605         i915_gem_contexts_fini(dev_priv);
606         i915_gem_cleanup_userptr(dev_priv);
607         mutex_unlock(&dev_priv->drm.struct_mutex);
608
609         i915_gem_drain_freed_objects(dev_priv);
610
611         WARN_ON(!list_empty(&dev_priv->contexts.list));
612 }
613
614 static int i915_load_modeset_init(struct drm_device *dev)
615 {
616         struct drm_i915_private *dev_priv = to_i915(dev);
617         struct pci_dev *pdev = dev_priv->drm.pdev;
618         int ret;
619
620         if (i915_inject_load_failure())
621                 return -ENODEV;
622
623         intel_bios_init(dev_priv);
624
625         /* If we have > 1 VGA cards, then we need to arbitrate access
626          * to the common VGA resources.
627          *
628          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
629          * then we do not take part in VGA arbitration and the
630          * vga_client_register() fails with -ENODEV.
631          */
632         ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
633         if (ret && ret != -ENODEV)
634                 goto out;
635
636         intel_register_dsm_handler();
637
638         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
639         if (ret)
640                 goto cleanup_vga_client;
641
642         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
643         intel_update_rawclk(dev_priv);
644
645         intel_power_domains_init_hw(dev_priv, false);
646
647         intel_csr_ucode_init(dev_priv);
648
649         ret = intel_irq_install(dev_priv);
650         if (ret)
651                 goto cleanup_csr;
652
653         intel_setup_gmbus(dev_priv);
654
655         /* Important: The output setup functions called by modeset_init need
656          * working irqs for e.g. gmbus and dp aux transfers. */
657         ret = intel_modeset_init(dev);
658         if (ret)
659                 goto cleanup_irq;
660
661         intel_uc_init_fw(dev_priv);
662
663         ret = i915_gem_init(dev_priv);
664         if (ret)
665                 goto cleanup_uc;
666
667         intel_modeset_gem_init(dev);
668
669         if (INTEL_INFO(dev_priv)->num_pipes == 0)
670                 return 0;
671
672         ret = intel_fbdev_init(dev);
673         if (ret)
674                 goto cleanup_gem;
675
676         /* Only enable hotplug handling once the fbdev is fully set up. */
677         intel_hpd_init(dev_priv);
678
679         drm_kms_helper_poll_init(dev);
680
681         return 0;
682
683 cleanup_gem:
684         if (i915_gem_suspend(dev_priv))
685                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
686         i915_gem_fini(dev_priv);
687 cleanup_uc:
688         intel_uc_fini_fw(dev_priv);
689 cleanup_irq:
690         drm_irq_uninstall(dev);
691         intel_teardown_gmbus(dev_priv);
692 cleanup_csr:
693         intel_csr_ucode_fini(dev_priv);
694         intel_power_domains_fini(dev_priv);
695         vga_switcheroo_unregister_client(pdev);
696 cleanup_vga_client:
697         vga_client_register(pdev, NULL, NULL, NULL);
698 out:
699         return ret;
700 }
701
702 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
703 {
704         struct apertures_struct *ap;
705         struct pci_dev *pdev = dev_priv->drm.pdev;
706         struct i915_ggtt *ggtt = &dev_priv->ggtt;
707         bool primary;
708         int ret;
709
710         ap = alloc_apertures(1);
711         if (!ap)
712                 return -ENOMEM;
713
714         ap->ranges[0].base = ggtt->mappable_base;
715         ap->ranges[0].size = ggtt->mappable_end;
716
717         primary =
718                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
719
720         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
721
722         kfree(ap);
723
724         return ret;
725 }
726
727 #if !defined(CONFIG_VGA_CONSOLE)
728 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
729 {
730         return 0;
731 }
732 #elif !defined(CONFIG_DUMMY_CONSOLE)
733 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
734 {
735         return -ENODEV;
736 }
737 #else
738 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
739 {
740         int ret = 0;
741
742         DRM_INFO("Replacing VGA console driver\n");
743
744         console_lock();
745         if (con_is_bound(&vga_con))
746                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
747         if (ret == 0) {
748                 ret = do_unregister_con_driver(&vga_con);
749
750                 /* Ignore "already unregistered". */
751                 if (ret == -ENODEV)
752                         ret = 0;
753         }
754         console_unlock();
755
756         return ret;
757 }
758 #endif
759
760 static void intel_init_dpio(struct drm_i915_private *dev_priv)
761 {
762         /*
763          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
764          * CHV x1 PHY (DP/HDMI D)
765          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
766          */
767         if (IS_CHERRYVIEW(dev_priv)) {
768                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
769                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
770         } else if (IS_VALLEYVIEW(dev_priv)) {
771                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
772         }
773 }
774
775 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
776 {
777         /*
778          * The i915 workqueue is primarily used for batched retirement of
779          * requests (and thus managing bo) once the task has been completed
780          * by the GPU. i915_gem_retire_requests() is called directly when we
781          * need high-priority retirement, such as waiting for an explicit
782          * bo.
783          *
784          * It is also used for periodic low-priority events, such as
785          * idle-timers and recording error state.
786          *
787          * All tasks on the workqueue are expected to acquire the dev mutex
788          * so there is no point in running more than one instance of the
789          * workqueue at any time.  Use an ordered one.
790          */
791         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
792         if (dev_priv->wq == NULL)
793                 goto out_err;
794
795         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
796         if (dev_priv->hotplug.dp_wq == NULL)
797                 goto out_free_wq;
798
799         return 0;
800
801 out_free_wq:
802         destroy_workqueue(dev_priv->wq);
803 out_err:
804         DRM_ERROR("Failed to allocate workqueues.\n");
805
806         return -ENOMEM;
807 }
808
809 static void i915_engines_cleanup(struct drm_i915_private *i915)
810 {
811         struct intel_engine_cs *engine;
812         enum intel_engine_id id;
813
814         for_each_engine(engine, i915, id)
815                 kfree(engine);
816 }
817
818 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
819 {
820         destroy_workqueue(dev_priv->hotplug.dp_wq);
821         destroy_workqueue(dev_priv->wq);
822 }
823
824 /*
825  * We don't keep the workarounds for pre-production hardware, so we expect our
826  * driver to fail on these machines in one way or another. A little warning on
827  * dmesg may help both the user and the bug triagers.
828  */
829 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
830 {
831         bool pre = false;
832
833         pre |= IS_HSW_EARLY_SDV(dev_priv);
834         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
835         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
836
837         if (pre) {
838                 DRM_ERROR("This is a pre-production stepping. "
839                           "It may not be fully functional.\n");
840                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
841         }
842 }
843
844 /**
845  * i915_driver_init_early - setup state not requiring device access
846  * @dev_priv: device private
847  *
848  * Initialize everything that is a "SW-only" state, that is state not
849  * requiring accessing the device or exposing the driver via kernel internal
850  * or userspace interfaces. Example steps belonging here: lock initialization,
851  * system memory allocation, setting up device specific attributes and
852  * function hooks not requiring accessing the device.
853  */
854 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
855                                   const struct pci_device_id *ent)
856 {
857         const struct intel_device_info *match_info =
858                 (struct intel_device_info *)ent->driver_data;
859         struct intel_device_info *device_info;
860         int ret = 0;
861
862         if (i915_inject_load_failure())
863                 return -ENODEV;
864
865         /* Setup the write-once "constant" device info */
866         device_info = mkwrite_device_info(dev_priv);
867         memcpy(device_info, match_info, sizeof(*device_info));
868         device_info->device_id = dev_priv->drm.pdev->device;
869
870         BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
871         device_info->gen_mask = BIT(device_info->gen - 1);
872
873         spin_lock_init(&dev_priv->irq_lock);
874         spin_lock_init(&dev_priv->gpu_error.lock);
875         mutex_init(&dev_priv->backlight_lock);
876         spin_lock_init(&dev_priv->uncore.lock);
877
878         spin_lock_init(&dev_priv->mm.object_stat_lock);
879         mutex_init(&dev_priv->sb_lock);
880         mutex_init(&dev_priv->modeset_restore_lock);
881         mutex_init(&dev_priv->av_mutex);
882         mutex_init(&dev_priv->wm.wm_mutex);
883         mutex_init(&dev_priv->pps_mutex);
884
885         intel_uc_init_early(dev_priv);
886         i915_memcpy_init_early(dev_priv);
887
888         ret = i915_workqueues_init(dev_priv);
889         if (ret < 0)
890                 goto err_engines;
891
892         /* This must be called before any calls to HAS_PCH_* */
893         intel_detect_pch(dev_priv);
894
895         intel_pm_setup(dev_priv);
896         intel_init_dpio(dev_priv);
897         intel_power_domains_init(dev_priv);
898         intel_irq_init(dev_priv);
899         intel_hangcheck_init(dev_priv);
900         intel_init_display_hooks(dev_priv);
901         intel_init_clock_gating_hooks(dev_priv);
902         intel_init_audio_hooks(dev_priv);
903         ret = i915_gem_load_init(dev_priv);
904         if (ret < 0)
905                 goto err_irq;
906
907         intel_display_crc_init(dev_priv);
908
909         intel_device_info_dump(dev_priv);
910
911         intel_detect_preproduction_hw(dev_priv);
912
913         i915_perf_init(dev_priv);
914
915         return 0;
916
917 err_irq:
918         intel_irq_fini(dev_priv);
919         i915_workqueues_cleanup(dev_priv);
920 err_engines:
921         i915_engines_cleanup(dev_priv);
922         return ret;
923 }
924
925 /**
926  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
927  * @dev_priv: device private
928  */
929 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
930 {
931         i915_perf_fini(dev_priv);
932         i915_gem_load_cleanup(dev_priv);
933         intel_irq_fini(dev_priv);
934         i915_workqueues_cleanup(dev_priv);
935         i915_engines_cleanup(dev_priv);
936 }
937
938 static int i915_mmio_setup(struct drm_i915_private *dev_priv)
939 {
940         struct pci_dev *pdev = dev_priv->drm.pdev;
941         int mmio_bar;
942         int mmio_size;
943
944         mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
945         /*
946          * Before gen4, the registers and the GTT are behind different BARs.
947          * However, from gen4 onwards, the registers and the GTT are shared
948          * in the same BAR, so we want to restrict this ioremap from
949          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
950          * the register BAR remains the same size for all the earlier
951          * generations up to Ironlake.
952          */
953         if (INTEL_GEN(dev_priv) < 5)
954                 mmio_size = 512 * 1024;
955         else
956                 mmio_size = 2 * 1024 * 1024;
957         dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
958         if (dev_priv->regs == NULL) {
959                 DRM_ERROR("failed to map registers\n");
960
961                 return -EIO;
962         }
963
964         /* Try to make sure MCHBAR is enabled before poking at it */
965         intel_setup_mchbar(dev_priv);
966
967         return 0;
968 }
969
970 static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
971 {
972         struct pci_dev *pdev = dev_priv->drm.pdev;
973
974         intel_teardown_mchbar(dev_priv);
975         pci_iounmap(pdev, dev_priv->regs);
976 }
977
978 /**
979  * i915_driver_init_mmio - setup device MMIO
980  * @dev_priv: device private
981  *
982  * Setup minimal device state necessary for MMIO accesses later in the
983  * initialization sequence. The setup here should avoid any other device-wide
984  * side effects or exposing the driver via kernel internal or user space
985  * interfaces.
986  */
987 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
988 {
989         int ret;
990
991         if (i915_inject_load_failure())
992                 return -ENODEV;
993
994         if (i915_get_bridge_dev(dev_priv))
995                 return -EIO;
996
997         ret = i915_mmio_setup(dev_priv);
998         if (ret < 0)
999                 goto err_bridge;
1000
1001         intel_uncore_init(dev_priv);
1002
1003         ret = intel_engines_init_mmio(dev_priv);
1004         if (ret)
1005                 goto err_uncore;
1006
1007         i915_gem_init_mmio(dev_priv);
1008
1009         return 0;
1010
1011 err_uncore:
1012         intel_uncore_fini(dev_priv);
1013 err_bridge:
1014         pci_dev_put(dev_priv->bridge_dev);
1015
1016         return ret;
1017 }
1018
1019 /**
1020  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1021  * @dev_priv: device private
1022  */
1023 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1024 {
1025         intel_uncore_fini(dev_priv);
1026         i915_mmio_cleanup(dev_priv);
1027         pci_dev_put(dev_priv->bridge_dev);
1028 }
1029
1030 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
1031 {
1032         i915.enable_execlists =
1033                 intel_sanitize_enable_execlists(dev_priv,
1034                                                 i915.enable_execlists);
1035
1036         /*
1037          * i915.enable_ppgtt is read-only, so do an early pass to validate the
1038          * user's requested state against the hardware/driver capabilities.  We
1039          * do this now so that we can print out any log messages once rather
1040          * than every time we check intel_enable_ppgtt().
1041          */
1042         i915.enable_ppgtt =
1043                 intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
1044         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
1045
1046         i915.semaphores = intel_sanitize_semaphores(dev_priv, i915.semaphores);
1047         DRM_DEBUG_DRIVER("use GPU semaphores? %s\n", yesno(i915.semaphores));
1048
1049         intel_uc_sanitize_options(dev_priv);
1050
1051         intel_gvt_sanitize_options(dev_priv);
1052 }
1053
1054 /**
1055  * i915_driver_init_hw - setup state requiring device access
1056  * @dev_priv: device private
1057  *
1058  * Setup state that requires accessing the device, but doesn't require
1059  * exposing the driver via kernel internal or userspace interfaces.
1060  */
1061 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1062 {
1063         struct pci_dev *pdev = dev_priv->drm.pdev;
1064         int ret;
1065
1066         if (i915_inject_load_failure())
1067                 return -ENODEV;
1068
1069         intel_device_info_runtime_init(dev_priv);
1070
1071         intel_sanitize_options(dev_priv);
1072
1073         ret = i915_ggtt_probe_hw(dev_priv);
1074         if (ret)
1075                 return ret;
1076
1077         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1078          * otherwise the vga fbdev driver falls over. */
1079         ret = i915_kick_out_firmware_fb(dev_priv);
1080         if (ret) {
1081                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1082                 goto out_ggtt;
1083         }
1084
1085         ret = i915_kick_out_vgacon(dev_priv);
1086         if (ret) {
1087                 DRM_ERROR("failed to remove conflicting VGA console\n");
1088                 goto out_ggtt;
1089         }
1090
1091         ret = i915_ggtt_init_hw(dev_priv);
1092         if (ret)
1093                 return ret;
1094
1095         ret = i915_ggtt_enable_hw(dev_priv);
1096         if (ret) {
1097                 DRM_ERROR("failed to enable GGTT\n");
1098                 goto out_ggtt;
1099         }
1100
1101         pci_set_master(pdev);
1102
1103         /* overlay on gen2 is broken and can't address above 1G */
1104         if (IS_GEN2(dev_priv)) {
1105                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1106                 if (ret) {
1107                         DRM_ERROR("failed to set DMA mask\n");
1108
1109                         goto out_ggtt;
1110                 }
1111         }
1112
1113         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1114          * using 32bit addressing, overwriting memory if HWS is located
1115          * above 4GB.
1116          *
1117          * The documentation also mentions an issue with undefined
1118          * behaviour if any general state is accessed within a page above 4GB,
1119          * which also needs to be handled carefully.
1120          */
1121         if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1122                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1123
1124                 if (ret) {
1125                         DRM_ERROR("failed to set DMA mask\n");
1126
1127                         goto out_ggtt;
1128                 }
1129         }
1130
1131         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1132                            PM_QOS_DEFAULT_VALUE);
1133
1134         intel_uncore_sanitize(dev_priv);
1135
1136         intel_opregion_setup(dev_priv);
1137
1138         i915_gem_load_init_fences(dev_priv);
1139
1140         /* On the 945G/GM, the chipset reports the MSI capability on the
1141          * integrated graphics even though the support isn't actually there
1142          * according to the published specs.  It doesn't appear to function
1143          * correctly in testing on 945G.
1144          * This may be a side effect of MSI having been made available for PEG
1145          * and the registers being closely associated.
1146          *
1147          * According to chipset errata, on the 965GM, MSI interrupts may
1148          * be lost or delayed, and was defeatured. MSI interrupts seem to
1149          * get lost on g4x as well, and interrupt delivery seems to stay
1150          * properly dead afterwards. So we'll just disable them for all
1151          * pre-gen5 chipsets.
1152          */
1153         if (INTEL_GEN(dev_priv) >= 5) {
1154                 if (pci_enable_msi(pdev) < 0)
1155                         DRM_DEBUG_DRIVER("can't enable MSI");
1156         }
1157
1158         ret = intel_gvt_init(dev_priv);
1159         if (ret)
1160                 goto out_ggtt;
1161
1162         return 0;
1163
1164 out_ggtt:
1165         i915_ggtt_cleanup_hw(dev_priv);
1166
1167         return ret;
1168 }
1169
1170 /**
1171  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1172  * @dev_priv: device private
1173  */
1174 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1175 {
1176         struct pci_dev *pdev = dev_priv->drm.pdev;
1177
1178         if (pdev->msi_enabled)
1179                 pci_disable_msi(pdev);
1180
1181         pm_qos_remove_request(&dev_priv->pm_qos);
1182         i915_ggtt_cleanup_hw(dev_priv);
1183 }
1184
1185 /**
1186  * i915_driver_register - register the driver with the rest of the system
1187  * @dev_priv: device private
1188  *
1189  * Perform any steps necessary to make the driver available via kernel
1190  * internal or userspace interfaces.
1191  */
1192 static void i915_driver_register(struct drm_i915_private *dev_priv)
1193 {
1194         struct drm_device *dev = &dev_priv->drm;
1195
1196         i915_gem_shrinker_init(dev_priv);
1197
1198         /*
1199          * Notify a valid surface after modesetting,
1200          * when running inside a VM.
1201          */
1202         if (intel_vgpu_active(dev_priv))
1203                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1204
1205         /* Reveal our presence to userspace */
1206         if (drm_dev_register(dev, 0) == 0) {
1207                 i915_debugfs_register(dev_priv);
1208                 i915_guc_log_register(dev_priv);
1209                 i915_setup_sysfs(dev_priv);
1210
1211                 /* Depends on sysfs having been initialized */
1212                 i915_perf_register(dev_priv);
1213         } else
1214                 DRM_ERROR("Failed to register driver for userspace access!\n");
1215
1216         if (INTEL_INFO(dev_priv)->num_pipes) {
1217                 /* Must be done after probing outputs */
1218                 intel_opregion_register(dev_priv);
1219                 acpi_video_register();
1220         }
1221
1222         if (IS_GEN5(dev_priv))
1223                 intel_gpu_ips_init(dev_priv);
1224
1225         intel_audio_init(dev_priv);
1226
1227         /*
1228          * Some ports require correctly set-up hpd registers for detection to
1229          * work properly (leading to ghost connected connector status), e.g. VGA
1230          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1231          * irqs are fully enabled. We do it last so that the async config
1232          * cannot run before the connectors are registered.
1233          */
1234         intel_fbdev_initial_config_async(dev);
1235 }
1236
1237 /**
1238  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1239  * @dev_priv: device private
1240  */
1241 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1242 {
1243         intel_fbdev_unregister(dev_priv);
1244         intel_audio_deinit(dev_priv);
1245
1246         intel_gpu_ips_teardown();
1247         acpi_video_unregister();
1248         intel_opregion_unregister(dev_priv);
1249
1250         i915_perf_unregister(dev_priv);
1251
1252         i915_teardown_sysfs(dev_priv);
1253         i915_guc_log_unregister(dev_priv);
1254         drm_dev_unregister(&dev_priv->drm);
1255
1256         i915_gem_shrinker_cleanup(dev_priv);
1257 }
1258
1259 /**
1260  * i915_driver_load - setup chip and create an initial config
1261  * @pdev: PCI device
1262  * @ent: matching PCI ID entry
1263  *
1264  * The driver load routine has to do several things:
1265  *   - drive output discovery via intel_modeset_init()
1266  *   - initialize the memory manager
1267  *   - allocate initial config memory
1268  *   - setup the DRM framebuffer with the allocated memory
1269  */
1270 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1271 {
1272         const struct intel_device_info *match_info =
1273                 (struct intel_device_info *)ent->driver_data;
1274         struct drm_i915_private *dev_priv;
1275         int ret;
1276
1277         /* Enable nuclear pageflip on ILK+ */
1278         if (!i915.nuclear_pageflip && match_info->gen < 5)
1279                 driver.driver_features &= ~DRIVER_ATOMIC;
1280
1281         ret = -ENOMEM;
1282         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1283         if (dev_priv)
1284                 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1285         if (ret) {
1286                 DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
1287                 goto out_free;
1288         }
1289
1290         dev_priv->drm.pdev = pdev;
1291         dev_priv->drm.dev_private = dev_priv;
1292
1293         ret = pci_enable_device(pdev);
1294         if (ret)
1295                 goto out_fini;
1296
1297         pci_set_drvdata(pdev, &dev_priv->drm);
1298         /*
1299          * Disable the system suspend direct complete optimization, which can
1300          * leave the device suspended skipping the driver's suspend handlers
1301          * if the device was already runtime suspended. This is needed due to
1302          * the difference in our runtime and system suspend sequence and
1303          * becaue the HDA driver may require us to enable the audio power
1304          * domain during system suspend.
1305          */
1306         pdev->dev_flags |= PCI_DEV_FLAGS_NEEDS_RESUME;
1307
1308         ret = i915_driver_init_early(dev_priv, ent);
1309         if (ret < 0)
1310                 goto out_pci_disable;
1311
1312         intel_runtime_pm_get(dev_priv);
1313
1314         ret = i915_driver_init_mmio(dev_priv);
1315         if (ret < 0)
1316                 goto out_runtime_pm_put;
1317
1318         ret = i915_driver_init_hw(dev_priv);
1319         if (ret < 0)
1320                 goto out_cleanup_mmio;
1321
1322         /*
1323          * TODO: move the vblank init and parts of modeset init steps into one
1324          * of the i915_driver_init_/i915_driver_register functions according
1325          * to the role/effect of the given init step.
1326          */
1327         if (INTEL_INFO(dev_priv)->num_pipes) {
1328                 ret = drm_vblank_init(&dev_priv->drm,
1329                                       INTEL_INFO(dev_priv)->num_pipes);
1330                 if (ret)
1331                         goto out_cleanup_hw;
1332         }
1333
1334         ret = i915_load_modeset_init(&dev_priv->drm);
1335         if (ret < 0)
1336                 goto out_cleanup_hw;
1337
1338         i915_driver_register(dev_priv);
1339
1340         intel_runtime_pm_enable(dev_priv);
1341
1342         dev_priv->ipc_enabled = false;
1343
1344         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1345                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1346         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1347                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1348
1349         intel_runtime_pm_put(dev_priv);
1350
1351         return 0;
1352
1353 out_cleanup_hw:
1354         i915_driver_cleanup_hw(dev_priv);
1355 out_cleanup_mmio:
1356         i915_driver_cleanup_mmio(dev_priv);
1357 out_runtime_pm_put:
1358         intel_runtime_pm_put(dev_priv);
1359         i915_driver_cleanup_early(dev_priv);
1360 out_pci_disable:
1361         pci_disable_device(pdev);
1362 out_fini:
1363         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1364         drm_dev_fini(&dev_priv->drm);
1365 out_free:
1366         kfree(dev_priv);
1367         return ret;
1368 }
1369
1370 void i915_driver_unload(struct drm_device *dev)
1371 {
1372         struct drm_i915_private *dev_priv = to_i915(dev);
1373         struct pci_dev *pdev = dev_priv->drm.pdev;
1374
1375         i915_driver_unregister(dev_priv);
1376
1377         if (i915_gem_suspend(dev_priv))
1378                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1379
1380         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1381
1382         drm_atomic_helper_shutdown(dev);
1383
1384         intel_gvt_cleanup(dev_priv);
1385
1386         intel_modeset_cleanup(dev);
1387
1388         /*
1389          * free the memory space allocated for the child device
1390          * config parsed from VBT
1391          */
1392         if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1393                 kfree(dev_priv->vbt.child_dev);
1394                 dev_priv->vbt.child_dev = NULL;
1395                 dev_priv->vbt.child_dev_num = 0;
1396         }
1397         kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1398         dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1399         kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1400         dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1401
1402         vga_switcheroo_unregister_client(pdev);
1403         vga_client_register(pdev, NULL, NULL, NULL);
1404
1405         intel_csr_ucode_fini(dev_priv);
1406
1407         /* Free error state after interrupts are fully disabled. */
1408         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1409         i915_reset_error_state(dev_priv);
1410
1411         i915_gem_fini(dev_priv);
1412         intel_uc_fini_fw(dev_priv);
1413         intel_fbc_cleanup_cfb(dev_priv);
1414
1415         intel_power_domains_fini(dev_priv);
1416
1417         i915_driver_cleanup_hw(dev_priv);
1418         i915_driver_cleanup_mmio(dev_priv);
1419
1420         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1421 }
1422
1423 static void i915_driver_release(struct drm_device *dev)
1424 {
1425         struct drm_i915_private *dev_priv = to_i915(dev);
1426
1427         i915_driver_cleanup_early(dev_priv);
1428         drm_dev_fini(&dev_priv->drm);
1429
1430         kfree(dev_priv);
1431 }
1432
1433 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1434 {
1435         struct drm_i915_private *i915 = to_i915(dev);
1436         int ret;
1437
1438         ret = i915_gem_open(i915, file);
1439         if (ret)
1440                 return ret;
1441
1442         return 0;
1443 }
1444
1445 /**
1446  * i915_driver_lastclose - clean up after all DRM clients have exited
1447  * @dev: DRM device
1448  *
1449  * Take care of cleaning up after all DRM clients have exited.  In the
1450  * mode setting case, we want to restore the kernel's initial mode (just
1451  * in case the last client left us in a bad state).
1452  *
1453  * Additionally, in the non-mode setting case, we'll tear down the GTT
1454  * and DMA structures, since the kernel won't be using them, and clea
1455  * up any GEM state.
1456  */
1457 static void i915_driver_lastclose(struct drm_device *dev)
1458 {
1459         intel_fbdev_restore_mode(dev);
1460         vga_switcheroo_process_delayed_switch();
1461 }
1462
1463 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1464 {
1465         struct drm_i915_file_private *file_priv = file->driver_priv;
1466
1467         mutex_lock(&dev->struct_mutex);
1468         i915_gem_context_close(file);
1469         i915_gem_release(dev, file);
1470         mutex_unlock(&dev->struct_mutex);
1471
1472         kfree(file_priv);
1473 }
1474
1475 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1476 {
1477         struct drm_device *dev = &dev_priv->drm;
1478         struct intel_encoder *encoder;
1479
1480         drm_modeset_lock_all(dev);
1481         for_each_intel_encoder(dev, encoder)
1482                 if (encoder->suspend)
1483                         encoder->suspend(encoder);
1484         drm_modeset_unlock_all(dev);
1485 }
1486
1487 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1488                               bool rpm_resume);
1489 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1490
1491 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1492 {
1493 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1494         if (acpi_target_system_state() < ACPI_STATE_S3)
1495                 return true;
1496 #endif
1497         return false;
1498 }
1499
1500 static int i915_drm_suspend(struct drm_device *dev)
1501 {
1502         struct drm_i915_private *dev_priv = to_i915(dev);
1503         struct pci_dev *pdev = dev_priv->drm.pdev;
1504         pci_power_t opregion_target_state;
1505         int error;
1506
1507         /* ignore lid events during suspend */
1508         mutex_lock(&dev_priv->modeset_restore_lock);
1509         dev_priv->modeset_restore = MODESET_SUSPENDED;
1510         mutex_unlock(&dev_priv->modeset_restore_lock);
1511
1512         disable_rpm_wakeref_asserts(dev_priv);
1513
1514         /* We do a lot of poking in a lot of registers, make sure they work
1515          * properly. */
1516         intel_display_set_init_power(dev_priv, true);
1517
1518         drm_kms_helper_poll_disable(dev);
1519
1520         pci_save_state(pdev);
1521
1522         error = i915_gem_suspend(dev_priv);
1523         if (error) {
1524                 dev_err(&pdev->dev,
1525                         "GEM idle failed, resume might fail\n");
1526                 goto out;
1527         }
1528
1529         intel_display_suspend(dev);
1530
1531         intel_dp_mst_suspend(dev);
1532
1533         intel_runtime_pm_disable_interrupts(dev_priv);
1534         intel_hpd_cancel_work(dev_priv);
1535
1536         intel_suspend_encoders(dev_priv);
1537
1538         intel_suspend_hw(dev_priv);
1539
1540         i915_gem_suspend_gtt_mappings(dev_priv);
1541
1542         i915_save_state(dev_priv);
1543
1544         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1545         intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1546
1547         intel_uncore_suspend(dev_priv);
1548         intel_opregion_unregister(dev_priv);
1549
1550         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1551
1552         dev_priv->suspend_count++;
1553
1554         intel_csr_ucode_suspend(dev_priv);
1555
1556 out:
1557         enable_rpm_wakeref_asserts(dev_priv);
1558
1559         return error;
1560 }
1561
1562 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1563 {
1564         struct drm_i915_private *dev_priv = to_i915(dev);
1565         struct pci_dev *pdev = dev_priv->drm.pdev;
1566         bool fw_csr;
1567         int ret;
1568
1569         disable_rpm_wakeref_asserts(dev_priv);
1570
1571         intel_display_set_init_power(dev_priv, false);
1572
1573         fw_csr = !IS_GEN9_LP(dev_priv) &&
1574                 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
1575         /*
1576          * In case of firmware assisted context save/restore don't manually
1577          * deinit the power domains. This also means the CSR/DMC firmware will
1578          * stay active, it will power down any HW resources as required and
1579          * also enable deeper system power states that would be blocked if the
1580          * firmware was inactive.
1581          */
1582         if (!fw_csr)
1583                 intel_power_domains_suspend(dev_priv);
1584
1585         ret = 0;
1586         if (IS_GEN9_LP(dev_priv))
1587                 bxt_enable_dc9(dev_priv);
1588         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1589                 hsw_enable_pc8(dev_priv);
1590         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1591                 ret = vlv_suspend_complete(dev_priv);
1592
1593         if (ret) {
1594                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1595                 if (!fw_csr)
1596                         intel_power_domains_init_hw(dev_priv, true);
1597
1598                 goto out;
1599         }
1600
1601         pci_disable_device(pdev);
1602         /*
1603          * During hibernation on some platforms the BIOS may try to access
1604          * the device even though it's already in D3 and hang the machine. So
1605          * leave the device in D0 on those platforms and hope the BIOS will
1606          * power down the device properly. The issue was seen on multiple old
1607          * GENs with different BIOS vendors, so having an explicit blacklist
1608          * is inpractical; apply the workaround on everything pre GEN6. The
1609          * platforms where the issue was seen:
1610          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1611          * Fujitsu FSC S7110
1612          * Acer Aspire 1830T
1613          */
1614         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1615                 pci_set_power_state(pdev, PCI_D3hot);
1616
1617         dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1618
1619 out:
1620         enable_rpm_wakeref_asserts(dev_priv);
1621
1622         return ret;
1623 }
1624
1625 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1626 {
1627         int error;
1628
1629         if (!dev) {
1630                 DRM_ERROR("dev: %p\n", dev);
1631                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1632                 return -ENODEV;
1633         }
1634
1635         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1636                          state.event != PM_EVENT_FREEZE))
1637                 return -EINVAL;
1638
1639         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1640                 return 0;
1641
1642         error = i915_drm_suspend(dev);
1643         if (error)
1644                 return error;
1645
1646         return i915_drm_suspend_late(dev, false);
1647 }
1648
1649 static int i915_drm_resume(struct drm_device *dev)
1650 {
1651         struct drm_i915_private *dev_priv = to_i915(dev);
1652         int ret;
1653
1654         disable_rpm_wakeref_asserts(dev_priv);
1655         intel_sanitize_gt_powersave(dev_priv);
1656
1657         ret = i915_ggtt_enable_hw(dev_priv);
1658         if (ret)
1659                 DRM_ERROR("failed to re-enable GGTT\n");
1660
1661         intel_csr_ucode_resume(dev_priv);
1662
1663         i915_gem_resume(dev_priv);
1664
1665         i915_restore_state(dev_priv);
1666         intel_pps_unlock_regs_wa(dev_priv);
1667         intel_opregion_setup(dev_priv);
1668
1669         intel_init_pch_refclk(dev_priv);
1670
1671         /*
1672          * Interrupts have to be enabled before any batches are run. If not the
1673          * GPU will hang. i915_gem_init_hw() will initiate batches to
1674          * update/restore the context.
1675          *
1676          * drm_mode_config_reset() needs AUX interrupts.
1677          *
1678          * Modeset enabling in intel_modeset_init_hw() also needs working
1679          * interrupts.
1680          */
1681         intel_runtime_pm_enable_interrupts(dev_priv);
1682
1683         drm_mode_config_reset(dev);
1684
1685         mutex_lock(&dev->struct_mutex);
1686         if (i915_gem_init_hw(dev_priv)) {
1687                 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
1688                 i915_gem_set_wedged(dev_priv);
1689         }
1690         mutex_unlock(&dev->struct_mutex);
1691
1692         intel_guc_resume(dev_priv);
1693
1694         intel_modeset_init_hw(dev);
1695
1696         spin_lock_irq(&dev_priv->irq_lock);
1697         if (dev_priv->display.hpd_irq_setup)
1698                 dev_priv->display.hpd_irq_setup(dev_priv);
1699         spin_unlock_irq(&dev_priv->irq_lock);
1700
1701         intel_dp_mst_resume(dev);
1702
1703         intel_display_resume(dev);
1704
1705         drm_kms_helper_poll_enable(dev);
1706
1707         /*
1708          * ... but also need to make sure that hotplug processing
1709          * doesn't cause havoc. Like in the driver load code we don't
1710          * bother with the tiny race here where we might loose hotplug
1711          * notifications.
1712          * */
1713         intel_hpd_init(dev_priv);
1714
1715         intel_opregion_register(dev_priv);
1716
1717         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1718
1719         mutex_lock(&dev_priv->modeset_restore_lock);
1720         dev_priv->modeset_restore = MODESET_DONE;
1721         mutex_unlock(&dev_priv->modeset_restore_lock);
1722
1723         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1724
1725         intel_autoenable_gt_powersave(dev_priv);
1726
1727         enable_rpm_wakeref_asserts(dev_priv);
1728
1729         return 0;
1730 }
1731
1732 static int i915_drm_resume_early(struct drm_device *dev)
1733 {
1734         struct drm_i915_private *dev_priv = to_i915(dev);
1735         struct pci_dev *pdev = dev_priv->drm.pdev;
1736         int ret;
1737
1738         /*
1739          * We have a resume ordering issue with the snd-hda driver also
1740          * requiring our device to be power up. Due to the lack of a
1741          * parent/child relationship we currently solve this with an early
1742          * resume hook.
1743          *
1744          * FIXME: This should be solved with a special hdmi sink device or
1745          * similar so that power domains can be employed.
1746          */
1747
1748         /*
1749          * Note that we need to set the power state explicitly, since we
1750          * powered off the device during freeze and the PCI core won't power
1751          * it back up for us during thaw. Powering off the device during
1752          * freeze is not a hard requirement though, and during the
1753          * suspend/resume phases the PCI core makes sure we get here with the
1754          * device powered on. So in case we change our freeze logic and keep
1755          * the device powered we can also remove the following set power state
1756          * call.
1757          */
1758         ret = pci_set_power_state(pdev, PCI_D0);
1759         if (ret) {
1760                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1761                 goto out;
1762         }
1763
1764         /*
1765          * Note that pci_enable_device() first enables any parent bridge
1766          * device and only then sets the power state for this device. The
1767          * bridge enabling is a nop though, since bridge devices are resumed
1768          * first. The order of enabling power and enabling the device is
1769          * imposed by the PCI core as described above, so here we preserve the
1770          * same order for the freeze/thaw phases.
1771          *
1772          * TODO: eventually we should remove pci_disable_device() /
1773          * pci_enable_enable_device() from suspend/resume. Due to how they
1774          * depend on the device enable refcount we can't anyway depend on them
1775          * disabling/enabling the device.
1776          */
1777         if (pci_enable_device(pdev)) {
1778                 ret = -EIO;
1779                 goto out;
1780         }
1781
1782         pci_set_master(pdev);
1783
1784         disable_rpm_wakeref_asserts(dev_priv);
1785
1786         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1787                 ret = vlv_resume_prepare(dev_priv, false);
1788         if (ret)
1789                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1790                           ret);
1791
1792         intel_uncore_resume_early(dev_priv);
1793
1794         if (IS_GEN9_LP(dev_priv)) {
1795                 if (!dev_priv->suspended_to_idle)
1796                         gen9_sanitize_dc_state(dev_priv);
1797                 bxt_disable_dc9(dev_priv);
1798         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1799                 hsw_disable_pc8(dev_priv);
1800         }
1801
1802         intel_uncore_sanitize(dev_priv);
1803
1804         if (IS_GEN9_LP(dev_priv) ||
1805             !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
1806                 intel_power_domains_init_hw(dev_priv, true);
1807
1808         i915_gem_sanitize(dev_priv);
1809
1810         enable_rpm_wakeref_asserts(dev_priv);
1811
1812 out:
1813         dev_priv->suspended_to_idle = false;
1814
1815         return ret;
1816 }
1817
1818 static int i915_resume_switcheroo(struct drm_device *dev)
1819 {
1820         int ret;
1821
1822         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1823                 return 0;
1824
1825         ret = i915_drm_resume_early(dev);
1826         if (ret)
1827                 return ret;
1828
1829         return i915_drm_resume(dev);
1830 }
1831
1832 /**
1833  * i915_reset - reset chip after a hang
1834  * @i915: #drm_i915_private to reset
1835  * @flags: Instructions
1836  *
1837  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
1838  * on failure.
1839  *
1840  * Caller must hold the struct_mutex.
1841  *
1842  * Procedure is fairly simple:
1843  *   - reset the chip using the reset reg
1844  *   - re-init context state
1845  *   - re-init hardware status page
1846  *   - re-init ring buffer
1847  *   - re-init interrupt state
1848  *   - re-init display
1849  */
1850 void i915_reset(struct drm_i915_private *i915, unsigned int flags)
1851 {
1852         struct i915_gpu_error *error = &i915->gpu_error;
1853         int ret;
1854
1855         lockdep_assert_held(&i915->drm.struct_mutex);
1856         GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
1857
1858         if (!test_bit(I915_RESET_HANDOFF, &error->flags))
1859                 return;
1860
1861         /* Clear any previous failed attempts at recovery. Time to try again. */
1862         if (!i915_gem_unset_wedged(i915))
1863                 goto wakeup;
1864
1865         if (!(flags & I915_RESET_QUIET))
1866                 dev_notice(i915->drm.dev, "Resetting chip after gpu hang\n");
1867         error->reset_count++;
1868
1869         disable_irq(i915->drm.irq);
1870         ret = i915_gem_reset_prepare(i915);
1871         if (ret) {
1872                 DRM_ERROR("GPU recovery failed\n");
1873                 intel_gpu_reset(i915, ALL_ENGINES);
1874                 goto error;
1875         }
1876
1877         ret = intel_gpu_reset(i915, ALL_ENGINES);
1878         if (ret) {
1879                 if (ret != -ENODEV)
1880                         DRM_ERROR("Failed to reset chip: %i\n", ret);
1881                 else
1882                         DRM_DEBUG_DRIVER("GPU reset disabled\n");
1883                 goto error;
1884         }
1885
1886         i915_gem_reset(i915);
1887         intel_overlay_reset(i915);
1888
1889         /* Ok, now get things going again... */
1890
1891         /*
1892          * Everything depends on having the GTT running, so we need to start
1893          * there.  Fortunately we don't need to do this unless we reset the
1894          * chip at a PCI level.
1895          *
1896          * Next we need to restore the context, but we don't use those
1897          * yet either...
1898          *
1899          * Ring buffer needs to be re-initialized in the KMS case, or if X
1900          * was running at the time of the reset (i.e. we weren't VT
1901          * switched away).
1902          */
1903         ret = i915_gem_init_hw(i915);
1904         if (ret) {
1905                 DRM_ERROR("Failed hw init on reset %d\n", ret);
1906                 goto error;
1907         }
1908
1909         i915_queue_hangcheck(i915);
1910
1911 finish:
1912         i915_gem_reset_finish(i915);
1913         enable_irq(i915->drm.irq);
1914
1915 wakeup:
1916         clear_bit(I915_RESET_HANDOFF, &error->flags);
1917         wake_up_bit(&error->flags, I915_RESET_HANDOFF);
1918         return;
1919
1920 error:
1921         i915_gem_set_wedged(i915);
1922         i915_gem_retire_requests(i915);
1923         goto finish;
1924 }
1925
1926 /**
1927  * i915_reset_engine - reset GPU engine to recover from a hang
1928  * @engine: engine to reset
1929  * @flags: options
1930  *
1931  * Reset a specific GPU engine. Useful if a hang is detected.
1932  * Returns zero on successful reset or otherwise an error code.
1933  *
1934  * Procedure is:
1935  *  - identifies the request that caused the hang and it is dropped
1936  *  - reset engine (which will force the engine to idle)
1937  *  - re-init/configure engine
1938  */
1939 int i915_reset_engine(struct intel_engine_cs *engine, unsigned int flags)
1940 {
1941         struct i915_gpu_error *error = &engine->i915->gpu_error;
1942         struct drm_i915_gem_request *active_request;
1943         int ret;
1944
1945         GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));
1946
1947         if (!(flags & I915_RESET_QUIET)) {
1948                 dev_notice(engine->i915->drm.dev,
1949                            "Resetting %s after gpu hang\n", engine->name);
1950         }
1951         error->reset_engine_count[engine->id]++;
1952
1953         active_request = i915_gem_reset_prepare_engine(engine);
1954         if (IS_ERR(active_request)) {
1955                 DRM_DEBUG_DRIVER("Previous reset failed, promote to full reset\n");
1956                 ret = PTR_ERR(active_request);
1957                 goto out;
1958         }
1959
1960         ret = intel_gpu_reset(engine->i915, intel_engine_flag(engine));
1961         if (ret) {
1962                 /* If we fail here, we expect to fallback to a global reset */
1963                 DRM_DEBUG_DRIVER("Failed to reset %s, ret=%d\n",
1964                                  engine->name, ret);
1965                 goto out;
1966         }
1967
1968         /*
1969          * The request that caused the hang is stuck on elsp, we know the
1970          * active request and can drop it, adjust head to skip the offending
1971          * request to resume executing remaining requests in the queue.
1972          */
1973         i915_gem_reset_engine(engine, active_request);
1974
1975         /*
1976          * The engine and its registers (and workarounds in case of render)
1977          * have been reset to their default values. Follow the init_ring
1978          * process to program RING_MODE, HWSP and re-enable submission.
1979          */
1980         ret = engine->init_hw(engine);
1981         if (ret)
1982                 goto out;
1983
1984 out:
1985         i915_gem_reset_finish_engine(engine);
1986         return ret;
1987 }
1988
1989 static int i915_pm_suspend(struct device *kdev)
1990 {
1991         struct pci_dev *pdev = to_pci_dev(kdev);
1992         struct drm_device *dev = pci_get_drvdata(pdev);
1993
1994         if (!dev) {
1995                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1996                 return -ENODEV;
1997         }
1998
1999         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2000                 return 0;
2001
2002         return i915_drm_suspend(dev);
2003 }
2004
2005 static int i915_pm_suspend_late(struct device *kdev)
2006 {
2007         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2008
2009         /*
2010          * We have a suspend ordering issue with the snd-hda driver also
2011          * requiring our device to be power up. Due to the lack of a
2012          * parent/child relationship we currently solve this with an late
2013          * suspend hook.
2014          *
2015          * FIXME: This should be solved with a special hdmi sink device or
2016          * similar so that power domains can be employed.
2017          */
2018         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2019                 return 0;
2020
2021         return i915_drm_suspend_late(dev, false);
2022 }
2023
2024 static int i915_pm_poweroff_late(struct device *kdev)
2025 {
2026         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2027
2028         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2029                 return 0;
2030
2031         return i915_drm_suspend_late(dev, true);
2032 }
2033
2034 static int i915_pm_resume_early(struct device *kdev)
2035 {
2036         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2037
2038         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2039                 return 0;
2040
2041         return i915_drm_resume_early(dev);
2042 }
2043
2044 static int i915_pm_resume(struct device *kdev)
2045 {
2046         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2047
2048         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2049                 return 0;
2050
2051         return i915_drm_resume(dev);
2052 }
2053
2054 /* freeze: before creating the hibernation_image */
2055 static int i915_pm_freeze(struct device *kdev)
2056 {
2057         int ret;
2058
2059         ret = i915_pm_suspend(kdev);
2060         if (ret)
2061                 return ret;
2062
2063         ret = i915_gem_freeze(kdev_to_i915(kdev));
2064         if (ret)
2065                 return ret;
2066
2067         return 0;
2068 }
2069
2070 static int i915_pm_freeze_late(struct device *kdev)
2071 {
2072         int ret;
2073
2074         ret = i915_pm_suspend_late(kdev);
2075         if (ret)
2076                 return ret;
2077
2078         ret = i915_gem_freeze_late(kdev_to_i915(kdev));
2079         if (ret)
2080                 return ret;
2081
2082         return 0;
2083 }
2084
2085 /* thaw: called after creating the hibernation image, but before turning off. */
2086 static int i915_pm_thaw_early(struct device *kdev)
2087 {
2088         return i915_pm_resume_early(kdev);
2089 }
2090
2091 static int i915_pm_thaw(struct device *kdev)
2092 {
2093         return i915_pm_resume(kdev);
2094 }
2095
2096 /* restore: called after loading the hibernation image. */
2097 static int i915_pm_restore_early(struct device *kdev)
2098 {
2099         return i915_pm_resume_early(kdev);
2100 }
2101
2102 static int i915_pm_restore(struct device *kdev)
2103 {
2104         return i915_pm_resume(kdev);
2105 }
2106
2107 /*
2108  * Save all Gunit registers that may be lost after a D3 and a subsequent
2109  * S0i[R123] transition. The list of registers needing a save/restore is
2110  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2111  * registers in the following way:
2112  * - Driver: saved/restored by the driver
2113  * - Punit : saved/restored by the Punit firmware
2114  * - No, w/o marking: no need to save/restore, since the register is R/O or
2115  *                    used internally by the HW in a way that doesn't depend
2116  *                    keeping the content across a suspend/resume.
2117  * - Debug : used for debugging
2118  *
2119  * We save/restore all registers marked with 'Driver', with the following
2120  * exceptions:
2121  * - Registers out of use, including also registers marked with 'Debug'.
2122  *   These have no effect on the driver's operation, so we don't save/restore
2123  *   them to reduce the overhead.
2124  * - Registers that are fully setup by an initialization function called from
2125  *   the resume path. For example many clock gating and RPS/RC6 registers.
2126  * - Registers that provide the right functionality with their reset defaults.
2127  *
2128  * TODO: Except for registers that based on the above 3 criteria can be safely
2129  * ignored, we save/restore all others, practically treating the HW context as
2130  * a black-box for the driver. Further investigation is needed to reduce the
2131  * saved/restored registers even further, by following the same 3 criteria.
2132  */
2133 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2134 {
2135         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2136         int i;
2137
2138         /* GAM 0x4000-0x4770 */
2139         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
2140         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
2141         s->arb_mode             = I915_READ(ARB_MODE);
2142         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
2143         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
2144
2145         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2146                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2147
2148         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2149         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2150
2151         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
2152         s->ecochk               = I915_READ(GAM_ECOCHK);
2153         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2154         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2155
2156         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2157
2158         /* MBC 0x9024-0x91D0, 0x8500 */
2159         s->g3dctl               = I915_READ(VLV_G3DCTL);
2160         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2161         s->mbctl                = I915_READ(GEN6_MBCTL);
2162
2163         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2164         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2165         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2166         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2167         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2168         s->rstctl               = I915_READ(GEN6_RSTCTL);
2169         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2170
2171         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2172         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2173         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2174         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2175         s->ecobus               = I915_READ(ECOBUS);
2176         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2177         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2178         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2179         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2180         s->rcedata              = I915_READ(VLV_RCEDATA);
2181         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2182
2183         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2184         s->gt_imr               = I915_READ(GTIMR);
2185         s->gt_ier               = I915_READ(GTIER);
2186         s->pm_imr               = I915_READ(GEN6_PMIMR);
2187         s->pm_ier               = I915_READ(GEN6_PMIER);
2188
2189         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2190                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2191
2192         /* GT SA CZ domain, 0x100000-0x138124 */
2193         s->tilectl              = I915_READ(TILECTL);
2194         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2195         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2196         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2197         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2198
2199         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2200         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2201         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2202         s->pcbr                 = I915_READ(VLV_PCBR);
2203         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2204
2205         /*
2206          * Not saving any of:
2207          * DFT,         0x9800-0x9EC0
2208          * SARB,        0xB000-0xB1FC
2209          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2210          * PCI CFG
2211          */
2212 }
2213
2214 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2215 {
2216         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2217         u32 val;
2218         int i;
2219
2220         /* GAM 0x4000-0x4770 */
2221         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2222         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2223         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2224         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2225         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2226
2227         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2228                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2229
2230         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2231         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2232
2233         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2234         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2235         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2236         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2237
2238         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2239
2240         /* MBC 0x9024-0x91D0, 0x8500 */
2241         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2242         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2243         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2244
2245         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2246         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2247         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2248         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2249         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2250         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2251         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2252
2253         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2254         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2255         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2256         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2257         I915_WRITE(ECOBUS,              s->ecobus);
2258         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2259         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2260         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2261         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2262         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2263         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2264
2265         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2266         I915_WRITE(GTIMR,               s->gt_imr);
2267         I915_WRITE(GTIER,               s->gt_ier);
2268         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2269         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2270
2271         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2272                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2273
2274         /* GT SA CZ domain, 0x100000-0x138124 */
2275         I915_WRITE(TILECTL,                     s->tilectl);
2276         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2277         /*
2278          * Preserve the GT allow wake and GFX force clock bit, they are not
2279          * be restored, as they are used to control the s0ix suspend/resume
2280          * sequence by the caller.
2281          */
2282         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2283         val &= VLV_GTLC_ALLOWWAKEREQ;
2284         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2285         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2286
2287         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2288         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2289         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2290         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2291
2292         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2293
2294         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2295         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2296         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2297         I915_WRITE(VLV_PCBR,                    s->pcbr);
2298         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2299 }
2300
2301 static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2302                                   u32 mask, u32 val)
2303 {
2304         /* The HW does not like us polling for PW_STATUS frequently, so
2305          * use the sleeping loop rather than risk the busy spin within
2306          * intel_wait_for_register().
2307          *
2308          * Transitioning between RC6 states should be at most 2ms (see
2309          * valleyview_enable_rps) so use a 3ms timeout.
2310          */
2311         return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val,
2312                         3);
2313 }
2314
2315 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2316 {
2317         u32 val;
2318         int err;
2319
2320         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2321         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2322         if (force_on)
2323                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2324         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2325
2326         if (!force_on)
2327                 return 0;
2328
2329         err = intel_wait_for_register(dev_priv,
2330                                       VLV_GTLC_SURVIVABILITY_REG,
2331                                       VLV_GFX_CLK_STATUS_BIT,
2332                                       VLV_GFX_CLK_STATUS_BIT,
2333                                       20);
2334         if (err)
2335                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2336                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2337
2338         return err;
2339 }
2340
2341 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2342 {
2343         u32 mask;
2344         u32 val;
2345         int err;
2346
2347         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2348         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2349         if (allow)
2350                 val |= VLV_GTLC_ALLOWWAKEREQ;
2351         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2352         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2353
2354         mask = VLV_GTLC_ALLOWWAKEACK;
2355         val = allow ? mask : 0;
2356
2357         err = vlv_wait_for_pw_status(dev_priv, mask, val);
2358         if (err)
2359                 DRM_ERROR("timeout disabling GT waking\n");
2360
2361         return err;
2362 }
2363
2364 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2365                                   bool wait_for_on)
2366 {
2367         u32 mask;
2368         u32 val;
2369
2370         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2371         val = wait_for_on ? mask : 0;
2372
2373         /*
2374          * RC6 transitioning can be delayed up to 2 msec (see
2375          * valleyview_enable_rps), use 3 msec for safety.
2376          */
2377         if (vlv_wait_for_pw_status(dev_priv, mask, val))
2378                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2379                           onoff(wait_for_on));
2380 }
2381
2382 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2383 {
2384         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2385                 return;
2386
2387         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2388         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2389 }
2390
2391 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2392 {
2393         u32 mask;
2394         int err;
2395
2396         /*
2397          * Bspec defines the following GT well on flags as debug only, so
2398          * don't treat them as hard failures.
2399          */
2400         vlv_wait_for_gt_wells(dev_priv, false);
2401
2402         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2403         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2404
2405         vlv_check_no_gt_access(dev_priv);
2406
2407         err = vlv_force_gfx_clock(dev_priv, true);
2408         if (err)
2409                 goto err1;
2410
2411         err = vlv_allow_gt_wake(dev_priv, false);
2412         if (err)
2413                 goto err2;
2414
2415         if (!IS_CHERRYVIEW(dev_priv))
2416                 vlv_save_gunit_s0ix_state(dev_priv);
2417
2418         err = vlv_force_gfx_clock(dev_priv, false);
2419         if (err)
2420                 goto err2;
2421
2422         return 0;
2423
2424 err2:
2425         /* For safety always re-enable waking and disable gfx clock forcing */
2426         vlv_allow_gt_wake(dev_priv, true);
2427 err1:
2428         vlv_force_gfx_clock(dev_priv, false);
2429
2430         return err;
2431 }
2432
2433 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2434                                 bool rpm_resume)
2435 {
2436         int err;
2437         int ret;
2438
2439         /*
2440          * If any of the steps fail just try to continue, that's the best we
2441          * can do at this point. Return the first error code (which will also
2442          * leave RPM permanently disabled).
2443          */
2444         ret = vlv_force_gfx_clock(dev_priv, true);
2445
2446         if (!IS_CHERRYVIEW(dev_priv))
2447                 vlv_restore_gunit_s0ix_state(dev_priv);
2448
2449         err = vlv_allow_gt_wake(dev_priv, true);
2450         if (!ret)
2451                 ret = err;
2452
2453         err = vlv_force_gfx_clock(dev_priv, false);
2454         if (!ret)
2455                 ret = err;
2456
2457         vlv_check_no_gt_access(dev_priv);
2458
2459         if (rpm_resume)
2460                 intel_init_clock_gating(dev_priv);
2461
2462         return ret;
2463 }
2464
2465 static int intel_runtime_suspend(struct device *kdev)
2466 {
2467         struct pci_dev *pdev = to_pci_dev(kdev);
2468         struct drm_device *dev = pci_get_drvdata(pdev);
2469         struct drm_i915_private *dev_priv = to_i915(dev);
2470         int ret;
2471
2472         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
2473                 return -ENODEV;
2474
2475         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2476                 return -ENODEV;
2477
2478         DRM_DEBUG_KMS("Suspending device\n");
2479
2480         disable_rpm_wakeref_asserts(dev_priv);
2481
2482         /*
2483          * We are safe here against re-faults, since the fault handler takes
2484          * an RPM reference.
2485          */
2486         i915_gem_runtime_suspend(dev_priv);
2487
2488         intel_guc_suspend(dev_priv);
2489
2490         intel_runtime_pm_disable_interrupts(dev_priv);
2491
2492         ret = 0;
2493         if (IS_GEN9_LP(dev_priv)) {
2494                 bxt_display_core_uninit(dev_priv);
2495                 bxt_enable_dc9(dev_priv);
2496         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2497                 hsw_enable_pc8(dev_priv);
2498         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2499                 ret = vlv_suspend_complete(dev_priv);
2500         }
2501
2502         if (ret) {
2503                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2504                 intel_runtime_pm_enable_interrupts(dev_priv);
2505
2506                 enable_rpm_wakeref_asserts(dev_priv);
2507
2508                 return ret;
2509         }
2510
2511         intel_uncore_suspend(dev_priv);
2512
2513         enable_rpm_wakeref_asserts(dev_priv);
2514         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2515
2516         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2517                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2518
2519         dev_priv->pm.suspended = true;
2520
2521         /*
2522          * FIXME: We really should find a document that references the arguments
2523          * used below!
2524          */
2525         if (IS_BROADWELL(dev_priv)) {
2526                 /*
2527                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2528                  * being detected, and the call we do at intel_runtime_resume()
2529                  * won't be able to restore them. Since PCI_D3hot matches the
2530                  * actual specification and appears to be working, use it.
2531                  */
2532                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2533         } else {
2534                 /*
2535                  * current versions of firmware which depend on this opregion
2536                  * notification have repurposed the D1 definition to mean
2537                  * "runtime suspended" vs. what you would normally expect (D3)
2538                  * to distinguish it from notifications that might be sent via
2539                  * the suspend path.
2540                  */
2541                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2542         }
2543
2544         assert_forcewakes_inactive(dev_priv);
2545
2546         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2547                 intel_hpd_poll_init(dev_priv);
2548
2549         DRM_DEBUG_KMS("Device suspended\n");
2550         return 0;
2551 }
2552
2553 static int intel_runtime_resume(struct device *kdev)
2554 {
2555         struct pci_dev *pdev = to_pci_dev(kdev);
2556         struct drm_device *dev = pci_get_drvdata(pdev);
2557         struct drm_i915_private *dev_priv = to_i915(dev);
2558         int ret = 0;
2559
2560         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2561                 return -ENODEV;
2562
2563         DRM_DEBUG_KMS("Resuming device\n");
2564
2565         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2566         disable_rpm_wakeref_asserts(dev_priv);
2567
2568         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2569         dev_priv->pm.suspended = false;
2570         if (intel_uncore_unclaimed_mmio(dev_priv))
2571                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2572
2573         intel_guc_resume(dev_priv);
2574
2575         if (IS_GEN9_LP(dev_priv)) {
2576                 bxt_disable_dc9(dev_priv);
2577                 bxt_display_core_init(dev_priv, true);
2578                 if (dev_priv->csr.dmc_payload &&
2579                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2580                         gen9_enable_dc5(dev_priv);
2581         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2582                 hsw_disable_pc8(dev_priv);
2583         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2584                 ret = vlv_resume_prepare(dev_priv, true);
2585         }
2586
2587         /*
2588          * No point of rolling back things in case of an error, as the best
2589          * we can do is to hope that things will still work (and disable RPM).
2590          */
2591         i915_gem_init_swizzling(dev_priv);
2592         i915_gem_restore_fences(dev_priv);
2593
2594         intel_runtime_pm_enable_interrupts(dev_priv);
2595
2596         /*
2597          * On VLV/CHV display interrupts are part of the display
2598          * power well, so hpd is reinitialized from there. For
2599          * everyone else do it here.
2600          */
2601         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2602                 intel_hpd_init(dev_priv);
2603
2604         enable_rpm_wakeref_asserts(dev_priv);
2605
2606         if (ret)
2607                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2608         else
2609                 DRM_DEBUG_KMS("Device resumed\n");
2610
2611         return ret;
2612 }
2613
2614 const struct dev_pm_ops i915_pm_ops = {
2615         /*
2616          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2617          * PMSG_RESUME]
2618          */
2619         .suspend = i915_pm_suspend,
2620         .suspend_late = i915_pm_suspend_late,
2621         .resume_early = i915_pm_resume_early,
2622         .resume = i915_pm_resume,
2623
2624         /*
2625          * S4 event handlers
2626          * @freeze, @freeze_late    : called (1) before creating the
2627          *                            hibernation image [PMSG_FREEZE] and
2628          *                            (2) after rebooting, before restoring
2629          *                            the image [PMSG_QUIESCE]
2630          * @thaw, @thaw_early       : called (1) after creating the hibernation
2631          *                            image, before writing it [PMSG_THAW]
2632          *                            and (2) after failing to create or
2633          *                            restore the image [PMSG_RECOVER]
2634          * @poweroff, @poweroff_late: called after writing the hibernation
2635          *                            image, before rebooting [PMSG_HIBERNATE]
2636          * @restore, @restore_early : called after rebooting and restoring the
2637          *                            hibernation image [PMSG_RESTORE]
2638          */
2639         .freeze = i915_pm_freeze,
2640         .freeze_late = i915_pm_freeze_late,
2641         .thaw_early = i915_pm_thaw_early,
2642         .thaw = i915_pm_thaw,
2643         .poweroff = i915_pm_suspend,
2644         .poweroff_late = i915_pm_poweroff_late,
2645         .restore_early = i915_pm_restore_early,
2646         .restore = i915_pm_restore,
2647
2648         /* S0ix (via runtime suspend) event handlers */
2649         .runtime_suspend = intel_runtime_suspend,
2650         .runtime_resume = intel_runtime_resume,
2651 };
2652
2653 static const struct vm_operations_struct i915_gem_vm_ops = {
2654         .fault = i915_gem_fault,
2655         .open = drm_gem_vm_open,
2656         .close = drm_gem_vm_close,
2657 };
2658
2659 static const struct file_operations i915_driver_fops = {
2660         .owner = THIS_MODULE,
2661         .open = drm_open,
2662         .release = drm_release,
2663         .unlocked_ioctl = drm_ioctl,
2664         .mmap = drm_gem_mmap,
2665         .poll = drm_poll,
2666         .read = drm_read,
2667         .compat_ioctl = i915_compat_ioctl,
2668         .llseek = noop_llseek,
2669 };
2670
2671 static int
2672 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2673                           struct drm_file *file)
2674 {
2675         return -ENODEV;
2676 }
2677
2678 static const struct drm_ioctl_desc i915_ioctls[] = {
2679         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2680         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2681         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2682         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2683         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2684         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2685         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2686         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2687         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2688         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2689         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2690         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2691         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2692         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2693         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2694         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2695         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2696         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2697         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2698         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2699         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2700         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2701         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2702         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2703         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2704         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2705         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2706         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2707         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2708         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2709         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2710         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2711         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2712         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2713         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2714         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2715         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2716         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2717         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2718         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2719         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2720         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2721         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2722         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2723         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2724         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2725         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2726         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2727         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2728         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2729         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2730         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2731         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2732         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2733         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2734 };
2735
2736 static struct drm_driver driver = {
2737         /* Don't use MTRRs here; the Xserver or userspace app should
2738          * deal with them for Intel hardware.
2739          */
2740         .driver_features =
2741             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2742             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC,
2743         .release = i915_driver_release,
2744         .open = i915_driver_open,
2745         .lastclose = i915_driver_lastclose,
2746         .postclose = i915_driver_postclose,
2747
2748         .gem_close_object = i915_gem_close_object,
2749         .gem_free_object_unlocked = i915_gem_free_object,
2750         .gem_vm_ops = &i915_gem_vm_ops,
2751
2752         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2753         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2754         .gem_prime_export = i915_gem_prime_export,
2755         .gem_prime_import = i915_gem_prime_import,
2756
2757         .dumb_create = i915_gem_dumb_create,
2758         .dumb_map_offset = i915_gem_mmap_gtt,
2759         .ioctls = i915_ioctls,
2760         .num_ioctls = ARRAY_SIZE(i915_ioctls),
2761         .fops = &i915_driver_fops,
2762         .name = DRIVER_NAME,
2763         .desc = DRIVER_DESC,
2764         .date = DRIVER_DATE,
2765         .major = DRIVER_MAJOR,
2766         .minor = DRIVER_MINOR,
2767         .patchlevel = DRIVER_PATCHLEVEL,
2768 };
2769
2770 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2771 #include "selftests/mock_drm.c"
2772 #endif