drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <linux/circ_buf.h>
  34 #include <drm/drmP.h>
  35 #include <drm/i915_drm.h>
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39
  40 /**
  41  * DOC: interrupt handling
  42  *
  43  * These functions provide the basic support for enabling and disabling the
  44  * interrupt handling support. There's a lot more functionality in i915_irq.c
  45  * and related files, but that will be described in separate chapters.
  46  */
  47
  48 static const u32 hpd_ilk[HPD_NUM_PINS] = {
  49         [HPD_PORT_A] = DE_DP_A_HOTPLUG,
  50 };
  51
  52 static const u32 hpd_ivb[HPD_NUM_PINS] = {
  53         [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
  54 };
  55
  56 static const u32 hpd_bdw[HPD_NUM_PINS] = {
  57         [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
  58 };
  59
  60 static const u32 hpd_ibx[HPD_NUM_PINS] = {
  61         [HPD_CRT] = SDE_CRT_HOTPLUG,
  62         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  63         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  64         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  65         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  66 };
  67
  68 static const u32 hpd_cpt[HPD_NUM_PINS] = {
  69         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  70         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  71         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  72         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  73         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  74 };
  75
  76 static const u32 hpd_spt[HPD_NUM_PINS] = {
  77         [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
  78         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  79         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  80         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
  81         [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
  82 };
  83
  84 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
  85         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  86         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  87         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  88         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  89         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  90         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  91 };
  92
  93 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
  94         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  95         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  96         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  97         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  98         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  99         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
 100 };
 101
 102 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
 103         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
 104         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
 105         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
 106         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
 107         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
 108         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
 109 };
 110
 111 /* BXT hpd list */
 112 static const u32 hpd_bxt[HPD_NUM_PINS] = {
 113         [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
 114         [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
 115         [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
 116 };
 117
 118 static const u32 hpd_gen11[HPD_NUM_PINS] = {
 119         [HPD_PORT_C] = GEN11_TC1_HOTPLUG | GEN11_TBT1_HOTPLUG,
 120         [HPD_PORT_D] = GEN11_TC2_HOTPLUG | GEN11_TBT2_HOTPLUG,
 121         [HPD_PORT_E] = GEN11_TC3_HOTPLUG | GEN11_TBT3_HOTPLUG,
 122         [HPD_PORT_F] = GEN11_TC4_HOTPLUG | GEN11_TBT4_HOTPLUG
 123 };
 124
 125 static const u32 hpd_icp[HPD_NUM_PINS] = {
 126         [HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP,
 127         [HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP,
 128         [HPD_PORT_C] = SDE_TC1_HOTPLUG_ICP,
 129         [HPD_PORT_D] = SDE_TC2_HOTPLUG_ICP,
 130         [HPD_PORT_E] = SDE_TC3_HOTPLUG_ICP,
 131         [HPD_PORT_F] = SDE_TC4_HOTPLUG_ICP
 132 };
 133
 134 /* IIR can theoretically queue up two events. Be paranoid. */
 135 #define GEN8_IRQ_RESET_NDX(type, which) do { \
 136         I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
 137         POSTING_READ(GEN8_##type##_IMR(which)); \
 138         I915_WRITE(GEN8_##type##_IER(which), 0); \
 139         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
 140         POSTING_READ(GEN8_##type##_IIR(which)); \
 141         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
 142         POSTING_READ(GEN8_##type##_IIR(which)); \
 143 } while (0)
 144
 145 #define GEN3_IRQ_RESET(type) do { \
 146         I915_WRITE(type##IMR, 0xffffffff); \
 147         POSTING_READ(type##IMR); \
 148         I915_WRITE(type##IER, 0); \
 149         I915_WRITE(type##IIR, 0xffffffff); \
 150         POSTING_READ(type##IIR); \
 151         I915_WRITE(type##IIR, 0xffffffff); \
 152         POSTING_READ(type##IIR); \
 153 } while (0)
 154
 155 #define GEN2_IRQ_RESET(type) do { \
 156         I915_WRITE16(type##IMR, 0xffff); \
 157         POSTING_READ16(type##IMR); \
 158         I915_WRITE16(type##IER, 0); \
 159         I915_WRITE16(type##IIR, 0xffff); \
 160         POSTING_READ16(type##IIR); \
 161         I915_WRITE16(type##IIR, 0xffff); \
 162         POSTING_READ16(type##IIR); \
 163 } while (0)
 164
 165 /*
 166  * We should clear IMR at preinstall/uninstall, and just check at postinstall.
 167  */
 168 static void gen3_assert_iir_is_zero(struct drm_i915_private *dev_priv,
 169                                     i915_reg_t reg)
 170 {
 171         u32 val = I915_READ(reg);
 172
 173         if (val == 0)
 174                 return;
 175
 176         WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
 177              i915_mmio_reg_offset(reg), val);
 178         I915_WRITE(reg, 0xffffffff);
 179         POSTING_READ(reg);
 180         I915_WRITE(reg, 0xffffffff);
 181         POSTING_READ(reg);
 182 }
 183
 184 static void gen2_assert_iir_is_zero(struct drm_i915_private *dev_priv,
 185                                     i915_reg_t reg)
 186 {
 187         u16 val = I915_READ16(reg);
 188
 189         if (val == 0)
 190                 return;
 191
 192         WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
 193              i915_mmio_reg_offset(reg), val);
 194         I915_WRITE16(reg, 0xffff);
 195         POSTING_READ16(reg);
 196         I915_WRITE16(reg, 0xffff);
 197         POSTING_READ16(reg);
 198 }
 199
 200 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
 201         gen3_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
 202         I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
 203         I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
 204         POSTING_READ(GEN8_##type##_IMR(which)); \
 205 } while (0)
 206
 207 #define GEN3_IRQ_INIT(type, imr_val, ier_val) do { \
 208         gen3_assert_iir_is_zero(dev_priv, type##IIR); \
 209         I915_WRITE(type##IER, (ier_val)); \
 210         I915_WRITE(type##IMR, (imr_val)); \
 211         POSTING_READ(type##IMR); \
 212 } while (0)
 213
 214 #define GEN2_IRQ_INIT(type, imr_val, ier_val) do { \
 215         gen2_assert_iir_is_zero(dev_priv, type##IIR); \
 216         I915_WRITE16(type##IER, (ier_val)); \
 217         I915_WRITE16(type##IMR, (imr_val)); \
 218         POSTING_READ16(type##IMR); \
 219 } while (0)
 220
 221 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
 222 static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
 223
 224 /* For display hotplug interrupt */
 225 static inline void
 226 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
 227                                      uint32_t mask,
 228                                      uint32_t bits)
 229 {
 230         uint32_t val;
 231
 232         lockdep_assert_held(&dev_priv->irq_lock);
 233         WARN_ON(bits & ~mask);
 234
 235         val = I915_READ(PORT_HOTPLUG_EN);
 236         val &= ~mask;
 237         val |= bits;
 238         I915_WRITE(PORT_HOTPLUG_EN, val);
 239 }
 240
 241 /**
 242  * i915_hotplug_interrupt_update - update hotplug interrupt enable
 243  * @dev_priv: driver private
 244  * @mask: bits to update
 245  * @bits: bits to enable
 246  * NOTE: the HPD enable bits are modified both inside and outside
 247  * of an interrupt context. To avoid that read-modify-write cycles
 248  * interfer, these bits are protected by a spinlock. Since this
 249  * function is usually not called from a context where the lock is
 250  * held already, this function acquires the lock itself. A non-locking
 251  * version is also available.
 252  */
 253 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
 254                                    uint32_t mask,
 255                                    uint32_t bits)
 256 {
 257         spin_lock_irq(&dev_priv->irq_lock);
 258         i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
 259         spin_unlock_irq(&dev_priv->irq_lock);
 260 }
 261
 262 static u32
 263 gen11_gt_engine_identity(struct drm_i915_private * const i915,
 264                          const unsigned int bank, const unsigned int bit);
 265
 266 bool gen11_reset_one_iir(struct drm_i915_private * const i915,
 267                          const unsigned int bank,
 268                          const unsigned int bit)
 269 {
 270         void __iomem * const regs = i915->regs;
 271         u32 dw;
 272
 273         lockdep_assert_held(&i915->irq_lock);
 274
 275         dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
 276         if (dw & BIT(bit)) {
 277                 /*
 278                  * According to the BSpec, DW_IIR bits cannot be cleared without
 279                  * first servicing the Selector & Shared IIR registers.
 280                  */
 281                 gen11_gt_engine_identity(i915, bank, bit);
 282
 283                 /*
 284                  * We locked GT INT DW by reading it. If we want to (try
 285                  * to) recover from this succesfully, we need to clear
 286                  * our bit, otherwise we are locking the register for
 287                  * everybody.
 288                  */
 289                 raw_reg_write(regs, GEN11_GT_INTR_DW(bank), BIT(bit));
 290
 291                 return true;
 292         }
 293
 294         return false;
 295 }
 296
 297 /**
 298  * ilk_update_display_irq - update DEIMR
 299  * @dev_priv: driver private
 300  * @interrupt_mask: mask of interrupt bits to update
 301  * @enabled_irq_mask: mask of interrupt bits to enable
 302  */
 303 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
 304                             uint32_t interrupt_mask,
 305                             uint32_t enabled_irq_mask)
 306 {
 307         uint32_t new_val;
 308
 309         lockdep_assert_held(&dev_priv->irq_lock);
 310
 311         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 312
 313         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 314                 return;
 315
 316         new_val = dev_priv->irq_mask;
 317         new_val &= ~interrupt_mask;
 318         new_val |= (~enabled_irq_mask & interrupt_mask);
 319
 320         if (new_val != dev_priv->irq_mask) {
 321                 dev_priv->irq_mask = new_val;
 322                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 323                 POSTING_READ(DEIMR);
 324         }
 325 }
 326
 327 /**
 328  * ilk_update_gt_irq - update GTIMR
 329  * @dev_priv: driver private
 330  * @interrupt_mask: mask of interrupt bits to update
 331  * @enabled_irq_mask: mask of interrupt bits to enable
 332  */
 333 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
 334                               uint32_t interrupt_mask,
 335                               uint32_t enabled_irq_mask)
 336 {
 337         lockdep_assert_held(&dev_priv->irq_lock);
 338
 339         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 340
 341         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 342                 return;
 343
 344         dev_priv->gt_irq_mask &= ~interrupt_mask;
 345         dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
 346         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 347 }
 348
 349 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 350 {
 351         ilk_update_gt_irq(dev_priv, mask, mask);
 352         POSTING_READ_FW(GTIMR);
 353 }
 354
 355 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 356 {
 357         ilk_update_gt_irq(dev_priv, mask, 0);
 358 }
 359
 360 static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
 361 {
 362         WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11);
 363
 364         return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
 365 }
 366
 367 static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
 368 {
 369         if (INTEL_GEN(dev_priv) >= 11)
 370                 return GEN11_GPM_WGBOXPERF_INTR_MASK;
 371         else if (INTEL_GEN(dev_priv) >= 8)
 372                 return GEN8_GT_IMR(2);
 373         else
 374                 return GEN6_PMIMR;
 375 }
 376
 377 static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
 378 {
 379         if (INTEL_GEN(dev_priv) >= 11)
 380                 return GEN11_GPM_WGBOXPERF_INTR_ENABLE;
 381         else if (INTEL_GEN(dev_priv) >= 8)
 382                 return GEN8_GT_IER(2);
 383         else
 384                 return GEN6_PMIER;
 385 }
 386
 387 /**
 388  * snb_update_pm_irq - update GEN6_PMIMR
 389  * @dev_priv: driver private
 390  * @interrupt_mask: mask of interrupt bits to update
 391  * @enabled_irq_mask: mask of interrupt bits to enable
 392  */
 393 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
 394                               uint32_t interrupt_mask,
 395                               uint32_t enabled_irq_mask)
 396 {
 397         uint32_t new_val;
 398
 399         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 400
 401         lockdep_assert_held(&dev_priv->irq_lock);
 402
 403         new_val = dev_priv->pm_imr;
 404         new_val &= ~interrupt_mask;
 405         new_val |= (~enabled_irq_mask & interrupt_mask);
 406
 407         if (new_val != dev_priv->pm_imr) {
 408                 dev_priv->pm_imr = new_val;
 409                 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_imr);
 410                 POSTING_READ(gen6_pm_imr(dev_priv));
 411         }
 412 }
 413
 414 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
 415 {
 416         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 417                 return;
 418
 419         snb_update_pm_irq(dev_priv, mask, mask);
 420 }
 421
 422 static void __gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
 423 {
 424         snb_update_pm_irq(dev_priv, mask, 0);
 425 }
 426
 427 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
 428 {
 429         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 430                 return;
 431
 432         __gen6_mask_pm_irq(dev_priv, mask);
 433 }
 434
 435 static void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
 436 {
 437         i915_reg_t reg = gen6_pm_iir(dev_priv);
 438
 439         lockdep_assert_held(&dev_priv->irq_lock);
 440
 441         I915_WRITE(reg, reset_mask);
 442         I915_WRITE(reg, reset_mask);
 443         POSTING_READ(reg);
 444 }
 445
 446 static void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
 447 {
 448         lockdep_assert_held(&dev_priv->irq_lock);
 449
 450         dev_priv->pm_ier |= enable_mask;
 451         I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
 452         gen6_unmask_pm_irq(dev_priv, enable_mask);
 453         /* unmask_pm_irq provides an implicit barrier (POSTING_READ) */
 454 }
 455
 456 static void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask)
 457 {
 458         lockdep_assert_held(&dev_priv->irq_lock);
 459
 460         dev_priv->pm_ier &= ~disable_mask;
 461         __gen6_mask_pm_irq(dev_priv, disable_mask);
 462         I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
 463         /* though a barrier is missing here, but don't really need a one */
 464 }
 465
 466 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv)
 467 {
 468         spin_lock_irq(&dev_priv->irq_lock);
 469
 470         while (gen11_reset_one_iir(dev_priv, 0, GEN11_GTPM))
 471                 ;
 472
 473         dev_priv->gt_pm.rps.pm_iir = 0;
 474
 475         spin_unlock_irq(&dev_priv->irq_lock);
 476 }
 477
 478 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
 479 {
 480         spin_lock_irq(&dev_priv->irq_lock);
 481         gen6_reset_pm_iir(dev_priv, dev_priv->pm_rps_events);
 482         dev_priv->gt_pm.rps.pm_iir = 0;
 483         spin_unlock_irq(&dev_priv->irq_lock);
 484 }
 485
 486 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
 487 {
 488         struct intel_rps *rps = &dev_priv->gt_pm.rps;
 489
 490         if (READ_ONCE(rps->interrupts_enabled))
 491                 return;
 492
 493         spin_lock_irq(&dev_priv->irq_lock);
 494         WARN_ON_ONCE(rps->pm_iir);
 495
 496         if (INTEL_GEN(dev_priv) >= 11)
 497                 WARN_ON_ONCE(gen11_reset_one_iir(dev_priv, 0, GEN11_GTPM));
 498         else
 499                 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
 500
 501         rps->interrupts_enabled = true;
 502         gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 503
 504         spin_unlock_irq(&dev_priv->irq_lock);
 505 }
 506
 507 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
 508 {
 509         struct intel_rps *rps = &dev_priv->gt_pm.rps;
 510
 511         if (!READ_ONCE(rps->interrupts_enabled))
 512                 return;
 513
 514         spin_lock_irq(&dev_priv->irq_lock);
 515         rps->interrupts_enabled = false;
 516
 517         I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u));
 518
 519         gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 520
 521         spin_unlock_irq(&dev_priv->irq_lock);
 522         synchronize_irq(dev_priv->drm.irq);
 523
 524         /* Now that we will not be generating any more work, flush any
 525          * outstanding tasks. As we are called on the RPS idle path,
 526          * we will reset the GPU to minimum frequencies, so the current
 527          * state of the worker can be discarded.
 528          */
 529         cancel_work_sync(&rps->work);
 530         if (INTEL_GEN(dev_priv) >= 11)
 531                 gen11_reset_rps_interrupts(dev_priv);
 532         else
 533                 gen6_reset_rps_interrupts(dev_priv);
 534 }
 535
 536 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
 537 {
 538         assert_rpm_wakelock_held(dev_priv);
 539
 540         spin_lock_irq(&dev_priv->irq_lock);
 541         gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
 542         spin_unlock_irq(&dev_priv->irq_lock);
 543 }
 544
 545 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
 546 {
 547         assert_rpm_wakelock_held(dev_priv);
 548
 549         spin_lock_irq(&dev_priv->irq_lock);
 550         if (!dev_priv->guc.interrupts_enabled) {
 551                 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
 552                                        dev_priv->pm_guc_events);
 553                 dev_priv->guc.interrupts_enabled = true;
 554                 gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
 555         }
 556         spin_unlock_irq(&dev_priv->irq_lock);
 557 }
 558
 559 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
 560 {
 561         assert_rpm_wakelock_held(dev_priv);
 562
 563         spin_lock_irq(&dev_priv->irq_lock);
 564         dev_priv->guc.interrupts_enabled = false;
 565
 566         gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events);
 567
 568         spin_unlock_irq(&dev_priv->irq_lock);
 569         synchronize_irq(dev_priv->drm.irq);
 570
 571         gen9_reset_guc_interrupts(dev_priv);
 572 }
 573
 574 /**
 575  * bdw_update_port_irq - update DE port interrupt
 576  * @dev_priv: driver private
 577  * @interrupt_mask: mask of interrupt bits to update
 578  * @enabled_irq_mask: mask of interrupt bits to enable
 579  */
 580 static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
 581                                 uint32_t interrupt_mask,
 582                                 uint32_t enabled_irq_mask)
 583 {
 584         uint32_t new_val;
 585         uint32_t old_val;
 586
 587         lockdep_assert_held(&dev_priv->irq_lock);
 588
 589         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 590
 591         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 592                 return;
 593
 594         old_val = I915_READ(GEN8_DE_PORT_IMR);
 595
 596         new_val = old_val;
 597         new_val &= ~interrupt_mask;
 598         new_val |= (~enabled_irq_mask & interrupt_mask);
 599
 600         if (new_val != old_val) {
 601                 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
 602                 POSTING_READ(GEN8_DE_PORT_IMR);
 603         }
 604 }
 605
 606 /**
 607  * bdw_update_pipe_irq - update DE pipe interrupt
 608  * @dev_priv: driver private
 609  * @pipe: pipe whose interrupt to update
 610  * @interrupt_mask: mask of interrupt bits to update
 611  * @enabled_irq_mask: mask of interrupt bits to enable
 612  */
 613 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
 614                          enum pipe pipe,
 615                          uint32_t interrupt_mask,
 616                          uint32_t enabled_irq_mask)
 617 {
 618         uint32_t new_val;
 619
 620         lockdep_assert_held(&dev_priv->irq_lock);
 621
 622         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 623
 624         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 625                 return;
 626
 627         new_val = dev_priv->de_irq_mask[pipe];
 628         new_val &= ~interrupt_mask;
 629         new_val |= (~enabled_irq_mask & interrupt_mask);
 630
 631         if (new_val != dev_priv->de_irq_mask[pipe]) {
 632                 dev_priv->de_irq_mask[pipe] = new_val;
 633                 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
 634                 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
 635         }
 636 }
 637
 638 /**
 639  * ibx_display_interrupt_update - update SDEIMR
 640  * @dev_priv: driver private
 641  * @interrupt_mask: mask of interrupt bits to update
 642  * @enabled_irq_mask: mask of interrupt bits to enable
 643  */
 644 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 645                                   uint32_t interrupt_mask,
 646                                   uint32_t enabled_irq_mask)
 647 {
 648         uint32_t sdeimr = I915_READ(SDEIMR);
 649         sdeimr &= ~interrupt_mask;
 650         sdeimr |= (~enabled_irq_mask & interrupt_mask);
 651
 652         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 653
 654         lockdep_assert_held(&dev_priv->irq_lock);
 655
 656         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 657                 return;
 658
 659         I915_WRITE(SDEIMR, sdeimr);
 660         POSTING_READ(SDEIMR);
 661 }
 662
 663 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
 664                               enum pipe pipe)
 665 {
 666         u32 status_mask = dev_priv->pipestat_irq_mask[pipe];
 667         u32 enable_mask = status_mask << 16;
 668
 669         lockdep_assert_held(&dev_priv->irq_lock);
 670
 671         if (INTEL_GEN(dev_priv) < 5)
 672                 goto out;
 673
 674         /*
 675          * On pipe A we don't support the PSR interrupt yet,
 676          * on pipe B and C the same bit MBZ.
 677          */
 678         if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
 679                 return 0;
 680         /*
 681          * On pipe B and C we don't support the PSR interrupt yet, on pipe
 682          * A the same bit is for perf counters which we don't use either.
 683          */
 684         if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
 685                 return 0;
 686
 687         enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
 688                          SPRITE0_FLIP_DONE_INT_EN_VLV |
 689                          SPRITE1_FLIP_DONE_INT_EN_VLV);
 690         if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
 691                 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
 692         if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
 693                 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
 694
 695 out:
 696         WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 697                   status_mask & ~PIPESTAT_INT_STATUS_MASK,
 698                   "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 699                   pipe_name(pipe), enable_mask, status_mask);
 700
 701         return enable_mask;
 702 }
 703
 704 void i915_enable_pipestat(struct drm_i915_private *dev_priv,
 705                           enum pipe pipe, u32 status_mask)
 706 {
 707         i915_reg_t reg = PIPESTAT(pipe);
 708         u32 enable_mask;
 709
 710         WARN_ONCE(status_mask & ~PIPESTAT_INT_STATUS_MASK,
 711                   "pipe %c: status_mask=0x%x\n",
 712                   pipe_name(pipe), status_mask);
 713
 714         lockdep_assert_held(&dev_priv->irq_lock);
 715         WARN_ON(!intel_irqs_enabled(dev_priv));
 716
 717         if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask)
 718                 return;
 719
 720         dev_priv->pipestat_irq_mask[pipe] |= status_mask;
 721         enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
 722
 723         I915_WRITE(reg, enable_mask | status_mask);
 724         POSTING_READ(reg);
 725 }
 726
 727 void i915_disable_pipestat(struct drm_i915_private *dev_priv,
 728                            enum pipe pipe, u32 status_mask)
 729 {
 730         i915_reg_t reg = PIPESTAT(pipe);
 731         u32 enable_mask;
 732
 733         WARN_ONCE(status_mask & ~PIPESTAT_INT_STATUS_MASK,
 734                   "pipe %c: status_mask=0x%x\n",
 735                   pipe_name(pipe), status_mask);
 736
 737         lockdep_assert_held(&dev_priv->irq_lock);
 738         WARN_ON(!intel_irqs_enabled(dev_priv));
 739
 740         if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0)
 741                 return;
 742
 743         dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
 744         enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
 745
 746         I915_WRITE(reg, enable_mask | status_mask);
 747         POSTING_READ(reg);
 748 }
 749
 750 /**
 751  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
 752  * @dev_priv: i915 device private
 753  */
 754 static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
 755 {
 756         if (!dev_priv->opregion.asle || !IS_MOBILE(dev_priv))
 757                 return;
 758
 759         spin_lock_irq(&dev_priv->irq_lock);
 760
 761         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
 762         if (INTEL_GEN(dev_priv) >= 4)
 763                 i915_enable_pipestat(dev_priv, PIPE_A,
 764                                      PIPE_LEGACY_BLC_EVENT_STATUS);
 765
 766         spin_unlock_irq(&dev_priv->irq_lock);
 767 }
 768
 769 /*
 770  * This timing diagram depicts the video signal in and
 771  * around the vertical blanking period.
 772  *
 773  * Assumptions about the fictitious mode used in this example:
 774  *  vblank_start >= 3
 775  *  vsync_start = vblank_start + 1
 776  *  vsync_end = vblank_start + 2
 777  *  vtotal = vblank_start + 3
 778  *
 779  *           start of vblank:
 780  *           latch double buffered registers
 781  *           increment frame counter (ctg+)
 782  *           generate start of vblank interrupt (gen4+)
 783  *           |
 784  *           |          frame start:
 785  *           |          generate frame start interrupt (aka. vblank interrupt) (gmch)
 786  *           |          may be shifted forward 1-3 extra lines via PIPECONF
 787  *           |          |
 788  *           |          |  start of vsync:
 789  *           |          |  generate vsync interrupt
 790  *           |          |  |
 791  * ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx
 792  *       .   \hs/   .      \hs/          \hs/          \hs/   .      \hs/
 793  * ----va---> <-----------------vb--------------------> <--------va-------------
 794  *       |          |       <----vs----->                     |
 795  * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
 796  * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
 797  * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
 798  *       |          |                                         |
 799  *       last visible pixel                                   first visible pixel
 800  *                  |                                         increment frame counter (gen3/4)
 801  *                  pixel counter = vblank_start * htotal     pixel counter = 0 (gen3/4)
 802  *
 803  * x  = horizontal active
 804  * _  = horizontal blanking
 805  * hs = horizontal sync
 806  * va = vertical active
 807  * vb = vertical blanking
 808  * vs = vertical sync
 809  * vbs = vblank_start (number)
 810  *
 811  * Summary:
 812  * - most events happen at the start of horizontal sync
 813  * - frame start happens at the start of horizontal blank, 1-4 lines
 814  *   (depending on PIPECONF settings) after the start of vblank
 815  * - gen3/4 pixel and frame counter are synchronized with the start
 816  *   of horizontal active on the first line of vertical active
 817  */
 818
 819 /* Called from drm generic code, passed a 'crtc', which
 820  * we use as a pipe index
 821  */
 822 static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 823 {
 824         struct drm_i915_private *dev_priv = to_i915(dev);
 825         i915_reg_t high_frame, low_frame;
 826         u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
 827         const struct drm_display_mode *mode = &dev->vblank[pipe].hwmode;
 828         unsigned long irqflags;
 829
 830         htotal = mode->crtc_htotal;
 831         hsync_start = mode->crtc_hsync_start;
 832         vbl_start = mode->crtc_vblank_start;
 833         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 834                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 835
 836         /* Convert to pixel count */
 837         vbl_start *= htotal;
 838
 839         /* Start of vblank event occurs at start of hsync */
 840         vbl_start -= htotal - hsync_start;
 841
 842         high_frame = PIPEFRAME(pipe);
 843         low_frame = PIPEFRAMEPIXEL(pipe);
 844
 845         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 846
 847         /*
 848          * High & low register fields aren't synchronized, so make sure
 849          * we get a low value that's stable across two reads of the high
 850          * register.
 851          */
 852         do {
 853                 high1 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK;
 854                 low   = I915_READ_FW(low_frame);
 855                 high2 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK;
 856         } while (high1 != high2);
 857
 858         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 859
 860         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 861         pixel = low & PIPE_PIXEL_MASK;
 862         low >>= PIPE_FRAME_LOW_SHIFT;
 863
 864         /*
 865          * The frame counter increments at beginning of active.
 866          * Cook up a vblank counter by also checking the pixel
 867          * counter against vblank start.
 868          */
 869         return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
 870 }
 871
 872 static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 873 {
 874         struct drm_i915_private *dev_priv = to_i915(dev);
 875
 876         return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
 877 }
 878
 879 /*
 880  * On certain encoders on certain platforms, pipe
 881  * scanline register will not work to get the scanline,
 882  * since the timings are driven from the PORT or issues
 883  * with scanline register updates.
 884  * This function will use Framestamp and current
 885  * timestamp registers to calculate the scanline.
 886  */
 887 static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
 888 {
 889         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 890         struct drm_vblank_crtc *vblank =
 891                 &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
 892         const struct drm_display_mode *mode = &vblank->hwmode;
 893         u32 vblank_start = mode->crtc_vblank_start;
 894         u32 vtotal = mode->crtc_vtotal;
 895         u32 htotal = mode->crtc_htotal;
 896         u32 clock = mode->crtc_clock;
 897         u32 scanline, scan_prev_time, scan_curr_time, scan_post_time;
 898
 899         /*
 900          * To avoid the race condition where we might cross into the
 901          * next vblank just between the PIPE_FRMTMSTMP and TIMESTAMP_CTR
 902          * reads. We make sure we read PIPE_FRMTMSTMP and TIMESTAMP_CTR
 903          * during the same frame.
 904          */
 905         do {
 906                 /*
 907                  * This field provides read back of the display
 908                  * pipe frame time stamp. The time stamp value
 909                  * is sampled at every start of vertical blank.
 910                  */
 911                 scan_prev_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe));
 912
 913                 /*
 914                  * The TIMESTAMP_CTR register has the current
 915                  * time stamp value.
 916                  */
 917                 scan_curr_time = I915_READ_FW(IVB_TIMESTAMP_CTR);
 918
 919                 scan_post_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe));
 920         } while (scan_post_time != scan_prev_time);
 921
 922         scanline = div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
 923                                         clock), 1000 * htotal);
 924         scanline = min(scanline, vtotal - 1);
 925         scanline = (scanline + vblank_start) % vtotal;
 926
 927         return scanline;
 928 }
 929
 930 /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
 931 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
 932 {
 933         struct drm_device *dev = crtc->base.dev;
 934         struct drm_i915_private *dev_priv = to_i915(dev);
 935         const struct drm_display_mode *mode;
 936         struct drm_vblank_crtc *vblank;
 937         enum pipe pipe = crtc->pipe;
 938         int position, vtotal;
 939
 940         if (!crtc->active)
 941                 return -1;
 942
 943         vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
 944         mode = &vblank->hwmode;
 945
 946         if (mode->private_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP)
 947                 return __intel_get_crtc_scanline_from_timestamp(crtc);
 948
 949         vtotal = mode->crtc_vtotal;
 950         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 951                 vtotal /= 2;
 952
 953         if (IS_GEN2(dev_priv))
 954                 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
 955         else
 956                 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 957
 958         /*
 959          * On HSW, the DSL reg (0x70000) appears to return 0 if we
 960          * read it just before the start of vblank.  So try it again
 961          * so we don't accidentally end up spanning a vblank frame
 962          * increment, causing the pipe_update_end() code to squak at us.
 963          *
 964          * The nature of this problem means we can't simply check the ISR
 965          * bit and return the vblank start value; nor can we use the scanline
 966          * debug register in the transcoder as it appears to have the same
 967          * problem.  We may need to extend this to include other platforms,
 968          * but so far testing only shows the problem on HSW.
 969          */
 970         if (HAS_DDI(dev_priv) && !position) {
 971                 int i, temp;
 972
 973                 for (i = 0; i < 100; i++) {
 974                         udelay(1);
 975                         temp = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 976                         if (temp != position) {
 977                                 position = temp;
 978                                 break;
 979                         }
 980                 }
 981         }
 982
 983         /*
 984          * See update_scanline_offset() for the details on the
 985          * scanline_offset adjustment.
 986          */
 987         return (position + crtc->scanline_offset) % vtotal;
 988 }
 989
 990 static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
 991                                      bool in_vblank_irq, int *vpos, int *hpos,
 992                                      ktime_t *stime, ktime_t *etime,
 993                                      const struct drm_display_mode *mode)
 994 {
 995         struct drm_i915_private *dev_priv = to_i915(dev);
 996         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
 997                                                                 pipe);
 998         int position;
 999         int vbl_start, vbl_end, hsync_start, htotal, vtotal;
1000         unsigned long irqflags;
1001
1002         if (WARN_ON(!mode->crtc_clock)) {
1003                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
1004                                  "pipe %c\n", pipe_name(pipe));
1005                 return false;
1006         }
1007
1008         htotal = mode->crtc_htotal;
1009         hsync_start = mode->crtc_hsync_start;
1010         vtotal = mode->crtc_vtotal;
1011         vbl_start = mode->crtc_vblank_start;
1012         vbl_end = mode->crtc_vblank_end;
1013
1014         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1015                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
1016                 vbl_end /= 2;
1017                 vtotal /= 2;
1018         }
1019
1020         /*
1021          * Lock uncore.lock, as we will do multiple timing critical raw
1022          * register reads, potentially with preemption disabled, so the
1023          * following code must not block on uncore.lock.
1024          */
1025         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1026
1027         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1028
1029         /* Get optional system timestamp before query. */
1030         if (stime)
1031                 *stime = ktime_get();
1032
1033         if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
1034                 /* No obvious pixelcount register. Only query vertical
1035                  * scanout position from Display scan line register.
1036                  */
1037                 position = __intel_get_crtc_scanline(intel_crtc);
1038         } else {
1039                 /* Have access to pixelcount since start of frame.
1040                  * We can split this into vertical and horizontal
1041                  * scanout position.
1042                  */
1043                 position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
1044
1045                 /* convert to pixel counts */
1046                 vbl_start *= htotal;
1047                 vbl_end *= htotal;
1048                 vtotal *= htotal;
1049
1050                 /*
1051                  * In interlaced modes, the pixel counter counts all pixels,
1052                  * so one field will have htotal more pixels. In order to avoid
1053                  * the reported position from jumping backwards when the pixel
1054                  * counter is beyond the length of the shorter field, just
1055                  * clamp the position the length of the shorter field. This
1056                  * matches how the scanline counter based position works since
1057                  * the scanline counter doesn't count the two half lines.
1058                  */
1059                 if (position >= vtotal)
1060                         position = vtotal - 1;
1061
1062                 /*
1063                  * Start of vblank interrupt is triggered at start of hsync,
1064                  * just prior to the first active line of vblank. However we
1065                  * consider lines to start at the leading edge of horizontal
1066                  * active. So, should we get here before we've crossed into
1067                  * the horizontal active of the first line in vblank, we would
1068                  * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
1069                  * always add htotal-hsync_start to the current pixel position.
1070                  */
1071                 position = (position + htotal - hsync_start) % vtotal;
1072         }
1073
1074         /* Get optional system timestamp after query. */
1075         if (etime)
1076                 *etime = ktime_get();
1077
1078         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1079
1080         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1081
1082         /*
1083          * While in vblank, position will be negative
1084          * counting up towards 0 at vbl_end. And outside
1085          * vblank, position will be positive counting
1086          * up since vbl_end.
1087          */
1088         if (position >= vbl_start)
1089                 position -= vbl_end;
1090         else
1091                 position += vtotal - vbl_end;
1092
1093         if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
1094                 *vpos = position;
1095                 *hpos = 0;
1096         } else {
1097                 *vpos = position / htotal;
1098                 *hpos = position - (*vpos * htotal);
1099         }
1100
1101         return true;
1102 }
1103
1104 int intel_get_crtc_scanline(struct intel_crtc *crtc)
1105 {
1106         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1107         unsigned long irqflags;
1108         int position;
1109
1110         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1111         position = __intel_get_crtc_scanline(crtc);
1112         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1113
1114         return position;
1115 }
1116
1117 static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv)
1118 {
1119         u32 busy_up, busy_down, max_avg, min_avg;
1120         u8 new_delay;
1121
1122         spin_lock(&mchdev_lock);
1123
1124         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
1125
1126         new_delay = dev_priv->ips.cur_delay;
1127
1128         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
1129         busy_up = I915_READ(RCPREVBSYTUPAVG);
1130         busy_down = I915_READ(RCPREVBSYTDNAVG);
1131         max_avg = I915_READ(RCBMAXAVG);
1132         min_avg = I915_READ(RCBMINAVG);
1133
1134         /* Handle RCS change request from hw */
1135         if (busy_up > max_avg) {
1136                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
1137                         new_delay = dev_priv->ips.cur_delay - 1;
1138                 if (new_delay < dev_priv->ips.max_delay)
1139                         new_delay = dev_priv->ips.max_delay;
1140         } else if (busy_down < min_avg) {
1141                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
1142                         new_delay = dev_priv->ips.cur_delay + 1;
1143                 if (new_delay > dev_priv->ips.min_delay)
1144                         new_delay = dev_priv->ips.min_delay;
1145         }
1146
1147         if (ironlake_set_drps(dev_priv, new_delay))
1148                 dev_priv->ips.cur_delay = new_delay;
1149
1150         spin_unlock(&mchdev_lock);
1151
1152         return;
1153 }
1154
1155 static void notify_ring(struct intel_engine_cs *engine)
1156 {
1157         const u32 seqno = intel_engine_get_seqno(engine);
1158         struct i915_request *rq = NULL;
1159         struct task_struct *tsk = NULL;
1160         struct intel_wait *wait;
1161
1162         if (unlikely(!engine->breadcrumbs.irq_armed))
1163                 return;
1164
1165         rcu_read_lock();
1166
1167         spin_lock(&engine->breadcrumbs.irq_lock);
1168         wait = engine->breadcrumbs.irq_wait;
1169         if (wait) {
1170                 /*
1171                  * We use a callback from the dma-fence to submit
1172                  * requests after waiting on our own requests. To
1173                  * ensure minimum delay in queuing the next request to
1174                  * hardware, signal the fence now rather than wait for
1175                  * the signaler to be woken up. We still wake up the
1176                  * waiter in order to handle the irq-seqno coherency
1177                  * issues (we may receive the interrupt before the
1178                  * seqno is written, see __i915_request_irq_complete())
1179                  * and to handle coalescing of multiple seqno updates
1180                  * and many waiters.
1181                  */
1182                 if (i915_seqno_passed(seqno, wait->seqno)) {
1183                         struct i915_request *waiter = wait->request;
1184
1185                         if (waiter &&
1186                             !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
1187                                       &waiter->fence.flags) &&
1188                             intel_wait_check_request(wait, waiter))
1189                                 rq = i915_request_get(waiter);
1190
1191                         tsk = wait->tsk;
1192                 } else {
1193                         if (engine->irq_seqno_barrier &&
1194                             i915_seqno_passed(seqno, wait->seqno - 1)) {
1195                                 set_bit(ENGINE_IRQ_BREADCRUMB,
1196                                         &engine->irq_posted);
1197                                 tsk = wait->tsk;
1198                         }
1199                 }
1200
1201                 engine->breadcrumbs.irq_count++;
1202         } else {
1203                 if (engine->breadcrumbs.irq_armed)
1204                         __intel_engine_disarm_breadcrumbs(engine);
1205         }
1206         spin_unlock(&engine->breadcrumbs.irq_lock);
1207
1208         if (rq) {
1209                 spin_lock(&rq->lock);
1210                 dma_fence_signal_locked(&rq->fence);
1211                 GEM_BUG_ON(!i915_request_completed(rq));
1212                 spin_unlock(&rq->lock);
1213
1214                 i915_request_put(rq);
1215         }
1216
1217         if (tsk && tsk->state & TASK_NORMAL)
1218                 wake_up_process(tsk);
1219
1220         rcu_read_unlock();
1221
1222         trace_intel_engine_notify(engine, wait);
1223 }
1224
1225 static void vlv_c0_read(struct drm_i915_private *dev_priv,
1226                         struct intel_rps_ei *ei)
1227 {
1228         ei->ktime = ktime_get_raw();
1229         ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
1230         ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
1231 }
1232
1233 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1234 {
1235         memset(&dev_priv->gt_pm.rps.ei, 0, sizeof(dev_priv->gt_pm.rps.ei));
1236 }
1237
1238 static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1239 {
1240         struct intel_rps *rps = &dev_priv->gt_pm.rps;
1241         const struct intel_rps_ei *prev = &rps->ei;
1242         struct intel_rps_ei now;
1243         u32 events = 0;
1244
1245         if ((pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) == 0)
1246                 return 0;
1247
1248         vlv_c0_read(dev_priv, &now);
1249
1250         if (prev->ktime) {
1251                 u64 time, c0;
1252                 u32 render, media;
1253
1254                 time = ktime_us_delta(now.ktime, prev->ktime);
1255
1256                 time *= dev_priv->czclk_freq;
1257
1258                 /* Workload can be split between render + media,
1259                  * e.g. SwapBuffers being blitted in X after being rendered in
1260                  * mesa. To account for this we need to combine both engines
1261                  * into our activity counter.
1262                  */
1263                 render = now.render_c0 - prev->render_c0;
1264                 media = now.media_c0 - prev->media_c0;
1265                 c0 = max(render, media);
1266                 c0 *= 1000 * 100 << 8; /* to usecs and scale to threshold% */
1267
1268                 if (c0 > time * rps->up_threshold)
1269                         events = GEN6_PM_RP_UP_THRESHOLD;
1270                 else if (c0 < time * rps->down_threshold)
1271                         events = GEN6_PM_RP_DOWN_THRESHOLD;
1272         }
1273
1274         rps->ei = now;
1275         return events;
1276 }
1277
1278 static void gen6_pm_rps_work(struct work_struct *work)
1279 {
1280         struct drm_i915_private *dev_priv =
1281                 container_of(work, struct drm_i915_private, gt_pm.rps.work);
1282         struct intel_rps *rps = &dev_priv->gt_pm.rps;
1283         bool client_boost = false;
1284         int new_delay, adj, min, max;
1285         u32 pm_iir = 0;
1286
1287         spin_lock_irq(&dev_priv->irq_lock);
1288         if (rps->interrupts_enabled) {
1289                 pm_iir = fetch_and_zero(&rps->pm_iir);
1290                 client_boost = atomic_read(&rps->num_waiters);
1291         }
1292         spin_unlock_irq(&dev_priv->irq_lock);
1293
1294         /* Make sure we didn't queue anything we're not going to process. */
1295         WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1296         if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1297                 goto out;
1298
1299         mutex_lock(&dev_priv->pcu_lock);
1300
1301         pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1302
1303         adj = rps->last_adj;
1304         new_delay = rps->cur_freq;
1305         min = rps->min_freq_softlimit;
1306         max = rps->max_freq_softlimit;
1307         if (client_boost)
1308                 max = rps->max_freq;
1309         if (client_boost && new_delay < rps->boost_freq) {
1310                 new_delay = rps->boost_freq;
1311                 adj = 0;
1312         } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1313                 if (adj > 0)
1314                         adj *= 2;
1315                 else /* CHV needs even encode values */
1316                         adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1317
1318                 if (new_delay >= rps->max_freq_softlimit)
1319                         adj = 0;
1320         } else if (client_boost) {
1321                 adj = 0;
1322         } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1323                 if (rps->cur_freq > rps->efficient_freq)
1324                         new_delay = rps->efficient_freq;
1325                 else if (rps->cur_freq > rps->min_freq_softlimit)
1326                         new_delay = rps->min_freq_softlimit;
1327                 adj = 0;
1328         } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1329                 if (adj < 0)
1330                         adj *= 2;
1331                 else /* CHV needs even encode values */
1332                         adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1333
1334                 if (new_delay <= rps->min_freq_softlimit)
1335                         adj = 0;
1336         } else { /* unknown event */
1337                 adj = 0;
1338         }
1339
1340         rps->last_adj = adj;
1341
1342         /* sysfs frequency interfaces may have snuck in while servicing the
1343          * interrupt
1344          */
1345         new_delay += adj;
1346         new_delay = clamp_t(int, new_delay, min, max);
1347
1348         if (intel_set_rps(dev_priv, new_delay)) {
1349                 DRM_DEBUG_DRIVER("Failed to set new GPU frequency\n");
1350                 rps->last_adj = 0;
1351         }
1352
1353         mutex_unlock(&dev_priv->pcu_lock);
1354
1355 out:
1356         /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1357         spin_lock_irq(&dev_priv->irq_lock);
1358         if (rps->interrupts_enabled)
1359                 gen6_unmask_pm_irq(dev_priv, dev_priv->pm_rps_events);
1360         spin_unlock_irq(&dev_priv->irq_lock);
1361 }
1362
1363
1364 /**
1365  * ivybridge_parity_work - Workqueue called when a parity error interrupt
1366  * occurred.
1367  * @work: workqueue struct
1368  *
1369  * Doesn't actually do anything except notify userspace. As a consequence of
1370  * this event, userspace should try to remap the bad rows since statistically
1371  * it is likely the same row is more likely to go bad again.
1372  */
1373 static void ivybridge_parity_work(struct work_struct *work)
1374 {
1375         struct drm_i915_private *dev_priv =
1376                 container_of(work, typeof(*dev_priv), l3_parity.error_work);
1377         u32 error_status, row, bank, subbank;
1378         char *parity_event[6];
1379         uint32_t misccpctl;
1380         uint8_t slice = 0;
1381
1382         /* We must turn off DOP level clock gating to access the L3 registers.
1383          * In order to prevent a get/put style interface, acquire struct mutex
1384          * any time we access those registers.
1385          */
1386         mutex_lock(&dev_priv->drm.struct_mutex);
1387
1388         /* If we've screwed up tracking, just let the interrupt fire again */
1389         if (WARN_ON(!dev_priv->l3_parity.which_slice))
1390                 goto out;
1391
1392         misccpctl = I915_READ(GEN7_MISCCPCTL);
1393         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1394         POSTING_READ(GEN7_MISCCPCTL);
1395
1396         while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1397                 i915_reg_t reg;
1398
1399                 slice--;
1400                 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv)))
1401                         break;
1402
1403                 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1404
1405                 reg = GEN7_L3CDERRST1(slice);
1406
1407                 error_status = I915_READ(reg);
1408                 row = GEN7_PARITY_ERROR_ROW(error_status);
1409                 bank = GEN7_PARITY_ERROR_BANK(error_status);
1410                 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1411
1412                 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1413                 POSTING_READ(reg);
1414
1415                 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1416                 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1417                 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1418                 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1419                 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1420                 parity_event[5] = NULL;
1421
1422                 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,
1423                                    KOBJ_CHANGE, parity_event);
1424
1425                 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1426                           slice, row, bank, subbank);
1427
1428                 kfree(parity_event[4]);
1429                 kfree(parity_event[3]);
1430                 kfree(parity_event[2]);
1431                 kfree(parity_event[1]);
1432         }
1433
1434         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1435
1436 out:
1437         WARN_ON(dev_priv->l3_parity.which_slice);
1438         spin_lock_irq(&dev_priv->irq_lock);
1439         gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1440         spin_unlock_irq(&dev_priv->irq_lock);
1441
1442         mutex_unlock(&dev_priv->drm.struct_mutex);
1443 }
1444
1445 static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv,
1446                                                u32 iir)
1447 {
1448         if (!HAS_L3_DPF(dev_priv))
1449                 return;
1450
1451         spin_lock(&dev_priv->irq_lock);
1452         gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1453         spin_unlock(&dev_priv->irq_lock);
1454
1455         iir &= GT_PARITY_ERROR(dev_priv);
1456         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1457                 dev_priv->l3_parity.which_slice |= 1 << 1;
1458
1459         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1460                 dev_priv->l3_parity.which_slice |= 1 << 0;
1461
1462         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1463 }
1464
1465 static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv,
1466                                u32 gt_iir)
1467 {
1468         if (gt_iir & GT_RENDER_USER_INTERRUPT)
1469                 notify_ring(dev_priv->engine[RCS]);
1470         if (gt_iir & ILK_BSD_USER_INTERRUPT)
1471                 notify_ring(dev_priv->engine[VCS]);
1472 }
1473
1474 static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
1475                                u32 gt_iir)
1476 {
1477         if (gt_iir & GT_RENDER_USER_INTERRUPT)
1478                 notify_ring(dev_priv->engine[RCS]);
1479         if (gt_iir & GT_BSD_USER_INTERRUPT)
1480                 notify_ring(dev_priv->engine[VCS]);
1481         if (gt_iir & GT_BLT_USER_INTERRUPT)
1482                 notify_ring(dev_priv->engine[BCS]);
1483
1484         if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1485                       GT_BSD_CS_ERROR_INTERRUPT |
1486                       GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1487                 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1488
1489         if (gt_iir & GT_PARITY_ERROR(dev_priv))
1490                 ivybridge_parity_error_irq_handler(dev_priv, gt_iir);
1491 }
1492
1493 static void
1494 gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
1495 {
1496         bool tasklet = false;
1497
1498         if (iir & GT_CONTEXT_SWITCH_INTERRUPT)
1499                 tasklet = true;
1500
1501         if (iir & GT_RENDER_USER_INTERRUPT) {
1502                 notify_ring(engine);
1503                 tasklet |= USES_GUC_SUBMISSION(engine->i915);
1504         }
1505
1506         if (tasklet)
1507                 tasklet_hi_schedule(&engine->execlists.tasklet);
1508 }
1509
1510 static void gen8_gt_irq_ack(struct drm_i915_private *i915,
1511                             u32 master_ctl, u32 gt_iir[4])
1512 {
1513         void __iomem * const regs = i915->regs;
1514
1515 #define GEN8_GT_IRQS (GEN8_GT_RCS_IRQ | \
1516                       GEN8_GT_BCS_IRQ | \
1517                       GEN8_GT_VCS1_IRQ | \
1518                       GEN8_GT_VCS2_IRQ | \
1519                       GEN8_GT_VECS_IRQ | \
1520                       GEN8_GT_PM_IRQ | \
1521                       GEN8_GT_GUC_IRQ)
1522
1523         if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1524                 gt_iir[0] = raw_reg_read(regs, GEN8_GT_IIR(0));
1525                 if (likely(gt_iir[0]))
1526                         raw_reg_write(regs, GEN8_GT_IIR(0), gt_iir[0]);
1527         }
1528
1529         if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1530                 gt_iir[1] = raw_reg_read(regs, GEN8_GT_IIR(1));
1531                 if (likely(gt_iir[1]))
1532                         raw_reg_write(regs, GEN8_GT_IIR(1), gt_iir[1]);
1533         }
1534
1535         if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
1536                 gt_iir[2] = raw_reg_read(regs, GEN8_GT_IIR(2));
1537                 if (likely(gt_iir[2] & (i915->pm_rps_events |
1538                                         i915->pm_guc_events)))
1539                         raw_reg_write(regs, GEN8_GT_IIR(2),
1540                                       gt_iir[2] & (i915->pm_rps_events |
1541                                                    i915->pm_guc_events));
1542         }
1543
1544         if (master_ctl & GEN8_GT_VECS_IRQ) {
1545                 gt_iir[3] = raw_reg_read(regs, GEN8_GT_IIR(3));
1546                 if (likely(gt_iir[3]))
1547                         raw_reg_write(regs, GEN8_GT_IIR(3), gt_iir[3]);
1548         }
1549 }
1550
1551 static void gen8_gt_irq_handler(struct drm_i915_private *i915,
1552                                 u32 master_ctl, u32 gt_iir[4])
1553 {
1554         if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1555                 gen8_cs_irq_handler(i915->engine[RCS],
1556                                     gt_iir[0] >> GEN8_RCS_IRQ_SHIFT);
1557                 gen8_cs_irq_handler(i915->engine[BCS],
1558                                     gt_iir[0] >> GEN8_BCS_IRQ_SHIFT);
1559         }
1560
1561         if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1562                 gen8_cs_irq_handler(i915->engine[VCS],
1563                                     gt_iir[1] >> GEN8_VCS1_IRQ_SHIFT);
1564                 gen8_cs_irq_handler(i915->engine[VCS2],
1565                                     gt_iir[1] >> GEN8_VCS2_IRQ_SHIFT);
1566         }
1567
1568         if (master_ctl & GEN8_GT_VECS_IRQ) {
1569                 gen8_cs_irq_handler(i915->engine[VECS],
1570                                     gt_iir[3] >> GEN8_VECS_IRQ_SHIFT);
1571         }
1572
1573         if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
1574                 gen6_rps_irq_handler(i915, gt_iir[2]);
1575                 gen9_guc_irq_handler(i915, gt_iir[2]);
1576         }
1577 }
1578
1579 static bool gen11_port_hotplug_long_detect(enum port port, u32 val)
1580 {
1581         switch (port) {
1582         case PORT_C:
1583                 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1);
1584         case PORT_D:
1585                 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2);
1586         case PORT_E:
1587                 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3);
1588         case PORT_F:
1589                 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4);
1590         default:
1591                 return false;
1592         }
1593 }
1594
1595 static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
1596 {
1597         switch (port) {
1598         case PORT_A:
1599                 return val & PORTA_HOTPLUG_LONG_DETECT;
1600         case PORT_B:
1601                 return val & PORTB_HOTPLUG_LONG_DETECT;
1602         case PORT_C:
1603                 return val & PORTC_HOTPLUG_LONG_DETECT;
1604         default:
1605                 return false;
1606         }
1607 }
1608
1609 static bool icp_ddi_port_hotplug_long_detect(enum port port, u32 val)
1610 {
1611         switch (port) {
1612         case PORT_A:
1613                 return val & ICP_DDIA_HPD_LONG_DETECT;
1614         case PORT_B:
1615                 return val & ICP_DDIB_HPD_LONG_DETECT;
1616         default:
1617                 return false;
1618         }
1619 }
1620
1621 static bool icp_tc_port_hotplug_long_detect(enum port port, u32 val)
1622 {
1623         switch (port) {
1624         case PORT_C:
1625                 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
1626         case PORT_D:
1627                 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
1628         case PORT_E:
1629                 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
1630         case PORT_F:
1631                 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
1632         default:
1633                 return false;
1634         }
1635 }
1636
1637 static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
1638 {
1639         switch (port) {
1640         case PORT_E:
1641                 return val & PORTE_HOTPLUG_LONG_DETECT;
1642         default:
1643                 return false;
1644         }
1645 }
1646
1647 static bool spt_port_hotplug_long_detect(enum port port, u32 val)
1648 {
1649         switch (port) {
1650         case PORT_A:
1651                 return val & PORTA_HOTPLUG_LONG_DETECT;
1652         case PORT_B:
1653                 return val & PORTB_HOTPLUG_LONG_DETECT;
1654         case PORT_C:
1655                 return val & PORTC_HOTPLUG_LONG_DETECT;
1656         case PORT_D:
1657                 return val & PORTD_HOTPLUG_LONG_DETECT;
1658         default:
1659                 return false;
1660         }
1661 }
1662
1663 static bool ilk_port_hotplug_long_detect(enum port port, u32 val)
1664 {
1665         switch (port) {
1666         case PORT_A:
1667                 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1668         default:
1669                 return false;
1670         }
1671 }
1672
1673 static bool pch_port_hotplug_long_detect(enum port port, u32 val)
1674 {
1675         switch (port) {
1676         case PORT_B:
1677                 return val & PORTB_HOTPLUG_LONG_DETECT;
1678         case PORT_C:
1679                 return val & PORTC_HOTPLUG_LONG_DETECT;
1680         case PORT_D:
1681                 return val & PORTD_HOTPLUG_LONG_DETECT;
1682         default:
1683                 return false;
1684         }
1685 }
1686
1687 static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
1688 {
1689         switch (port) {
1690         case PORT_B:
1691                 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1692         case PORT_C:
1693                 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1694         case PORT_D:
1695                 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1696         default:
1697                 return false;
1698         }
1699 }
1700
1701 /*
1702  * Get a bit mask of pins that have triggered, and which ones may be long.
1703  * This can be called multiple times with the same masks to accumulate
1704  * hotplug detection results from several registers.
1705  *
1706  * Note that the caller is expected to zero out the masks initially.
1707  */
1708 static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
1709                                u32 *pin_mask, u32 *long_mask,
1710                                u32 hotplug_trigger, u32 dig_hotplug_reg,
1711                                const u32 hpd[HPD_NUM_PINS],
1712                                bool long_pulse_detect(enum port port, u32 val))
1713 {
1714         enum port port;
1715         int i;
1716
1717         for_each_hpd_pin(i) {
1718                 if ((hpd[i] & hotplug_trigger) == 0)
1719                         continue;
1720
1721                 *pin_mask |= BIT(i);
1722
1723                 port = intel_hpd_pin_to_port(dev_priv, i);
1724                 if (port == PORT_NONE)
1725                         continue;
1726
1727                 if (long_pulse_detect(port, dig_hotplug_reg))
1728                         *long_mask |= BIT(i);
1729         }
1730
1731         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1732                          hotplug_trigger, dig_hotplug_reg, *pin_mask);
1733
1734 }
1735
1736 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1737 {
1738         wake_up_all(&dev_priv->gmbus_wait_queue);
1739 }
1740
1741 static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1742 {
1743         wake_up_all(&dev_priv->gmbus_wait_queue);
1744 }
1745
1746 #if defined(CONFIG_DEBUG_FS)
1747 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1748                                          enum pipe pipe,
1749                                          uint32_t crc0, uint32_t crc1,
1750                                          uint32_t crc2, uint32_t crc3,
1751                                          uint32_t crc4)
1752 {
1753         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1754         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1755         uint32_t crcs[5];
1756
1757         spin_lock(&pipe_crc->lock);
1758         /*
1759          * For some not yet identified reason, the first CRC is
1760          * bonkers. So let's just wait for the next vblank and read
1761          * out the buggy result.
1762          *
1763          * On GEN8+ sometimes the second CRC is bonkers as well, so
1764          * don't trust that one either.
1765          */
1766         if (pipe_crc->skipped <= 0 ||
1767             (INTEL_GEN(dev_priv) >= 8 && pipe_crc->skipped == 1)) {
1768                 pipe_crc->skipped++;
1769                 spin_unlock(&pipe_crc->lock);
1770                 return;
1771         }
1772         spin_unlock(&pipe_crc->lock);
1773
1774         crcs[0] = crc0;
1775         crcs[1] = crc1;
1776         crcs[2] = crc2;
1777         crcs[3] = crc3;
1778         crcs[4] = crc4;
1779         drm_crtc_add_crc_entry(&crtc->base, true,
1780                                 drm_crtc_accurate_vblank_count(&crtc->base),
1781                                 crcs);
1782 }
1783 #else
1784 static inline void
1785 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1786                              enum pipe pipe,
1787                              uint32_t crc0, uint32_t crc1,
1788                              uint32_t crc2, uint32_t crc3,
1789                              uint32_t crc4) {}
1790 #endif
1791
1792
1793 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1794                                      enum pipe pipe)
1795 {
1796         display_pipe_crc_irq_handler(dev_priv, pipe,
1797                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1798                                      0, 0, 0, 0);
1799 }
1800
1801 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1802                                      enum pipe pipe)
1803 {
1804         display_pipe_crc_irq_handler(dev_priv, pipe,
1805                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1806                                      I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1807                                      I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1808                                      I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1809                                      I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1810 }
1811
1812 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1813                                       enum pipe pipe)
1814 {
1815         uint32_t res1, res2;
1816
1817         if (INTEL_GEN(dev_priv) >= 3)
1818                 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1819         else
1820                 res1 = 0;
1821
1822         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1823                 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1824         else
1825                 res2 = 0;
1826
1827         display_pipe_crc_irq_handler(dev_priv, pipe,
1828                                      I915_READ(PIPE_CRC_RES_RED(pipe)),
1829                                      I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1830                                      I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1831                                      res1, res2);
1832 }
1833
1834 /* The RPS events need forcewake, so we add them to a work queue and mask their
1835  * IMR bits until the work is done. Other interrupts can be processed without
1836  * the work queue. */
1837 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1838 {
1839         struct intel_rps *rps = &dev_priv->gt_pm.rps;
1840
1841         if (pm_iir & dev_priv->pm_rps_events) {
1842                 spin_lock(&dev_priv->irq_lock);
1843                 gen6_mask_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1844                 if (rps->interrupts_enabled) {
1845                         rps->pm_iir |= pm_iir & dev_priv->pm_rps_events;
1846                         schedule_work(&rps->work);
1847                 }
1848                 spin_unlock(&dev_priv->irq_lock);
1849         }
1850
1851         if (INTEL_GEN(dev_priv) >= 8)
1852                 return;
1853
1854         if (HAS_VEBOX(dev_priv)) {
1855                 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1856                         notify_ring(dev_priv->engine[VECS]);
1857
1858                 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1859                         DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1860         }
1861 }
1862
1863 static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)
1864 {
1865         if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT)
1866                 intel_guc_to_host_event_handler(&dev_priv->guc);
1867 }
1868
1869 static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
1870 {
1871         enum pipe pipe;
1872
1873         for_each_pipe(dev_priv, pipe) {
1874                 I915_WRITE(PIPESTAT(pipe),
1875                            PIPESTAT_INT_STATUS_MASK |
1876                            PIPE_FIFO_UNDERRUN_STATUS);
1877
1878                 dev_priv->pipestat_irq_mask[pipe] = 0;
1879         }
1880 }
1881
1882 static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1883                                   u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1884 {
1885         int pipe;
1886
1887         spin_lock(&dev_priv->irq_lock);
1888
1889         if (!dev_priv->display_irqs_enabled) {
1890                 spin_unlock(&dev_priv->irq_lock);
1891                 return;
1892         }
1893
1894         for_each_pipe(dev_priv, pipe) {
1895                 i915_reg_t reg;
1896                 u32 status_mask, enable_mask, iir_bit = 0;
1897
1898                 /*
1899                  * PIPESTAT bits get signalled even when the interrupt is
1900                  * disabled with the mask bits, and some of the status bits do
1901                  * not generate interrupts at all (like the underrun bit). Hence
1902                  * we need to be careful that we only handle what we want to
1903                  * handle.
1904                  */
1905
1906                 /* fifo underruns are filterered in the underrun handler. */
1907                 status_mask = PIPE_FIFO_UNDERRUN_STATUS;
1908
1909                 switch (pipe) {
1910                 case PIPE_A:
1911                         iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1912                         break;
1913                 case PIPE_B:
1914                         iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1915                         break;
1916                 case PIPE_C:
1917                         iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1918                         break;
1919                 }
1920                 if (iir & iir_bit)
1921                         status_mask |= dev_priv->pipestat_irq_mask[pipe];
1922
1923                 if (!status_mask)
1924                         continue;
1925
1926                 reg = PIPESTAT(pipe);
1927                 pipe_stats[pipe] = I915_READ(reg) & status_mask;
1928                 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
1929
1930                 /*
1931                  * Clear the PIPE*STAT regs before the IIR
1932                  *
1933                  * Toggle the enable bits to make sure we get an
1934                  * edge in the ISR pipe event bit if we don't clear
1935                  * all the enabled status bits. Otherwise the edge
1936                  * triggered IIR on i965/g4x wouldn't notice that
1937                  * an interrupt is still pending.
1938                  */
1939                 if (pipe_stats[pipe]) {
1940                         I915_WRITE(reg, pipe_stats[pipe]);
1941                         I915_WRITE(reg, enable_mask);
1942                 }
1943         }
1944         spin_unlock(&dev_priv->irq_lock);
1945 }
1946
1947 static void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1948                                       u16 iir, u32 pipe_stats[I915_MAX_PIPES])
1949 {
1950         enum pipe pipe;
1951
1952         for_each_pipe(dev_priv, pipe) {
1953                 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1954                         drm_handle_vblank(&dev_priv->drm, pipe);
1955
1956                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1957                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1958
1959                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1960                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1961         }
1962 }
1963
1964 static void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1965                                       u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1966 {
1967         bool blc_event = false;
1968         enum pipe pipe;
1969
1970         for_each_pipe(dev_priv, pipe) {
1971                 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1972                         drm_handle_vblank(&dev_priv->drm, pipe);
1973
1974                 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1975                         blc_event = true;
1976
1977                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1978                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1979
1980                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1981                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1982         }
1983
1984         if (blc_event || (iir & I915_ASLE_INTERRUPT))
1985                 intel_opregion_asle_intr(dev_priv);
1986 }
1987
1988 static void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1989                                       u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1990 {
1991         bool blc_event = false;
1992         enum pipe pipe;
1993
1994         for_each_pipe(dev_priv, pipe) {
1995                 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1996                         drm_handle_vblank(&dev_priv->drm, pipe);
1997
1998                 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1999                         blc_event = true;
2000
2001                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
2002                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2003
2004                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2005                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2006         }
2007
2008         if (blc_event || (iir & I915_ASLE_INTERRUPT))
2009                 intel_opregion_asle_intr(dev_priv);
2010
2011         if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
2012                 gmbus_irq_handler(dev_priv);
2013 }
2014
2015 static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
2016                                             u32 pipe_stats[I915_MAX_PIPES])
2017 {
2018         enum pipe pipe;
2019
2020         for_each_pipe(dev_priv, pipe) {
2021                 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
2022                         drm_handle_vblank(&dev_priv->drm, pipe);
2023
2024                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
2025                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2026
2027                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2028                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2029         }
2030
2031         if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
2032                 gmbus_irq_handler(dev_priv);
2033 }
2034
2035 static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
2036 {
2037         u32 hotplug_status = 0, hotplug_status_mask;
2038         int i;
2039
2040         if (IS_G4X(dev_priv) ||
2041             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2042                 hotplug_status_mask = HOTPLUG_INT_STATUS_G4X |
2043                         DP_AUX_CHANNEL_MASK_INT_STATUS_G4X;
2044         else
2045                 hotplug_status_mask = HOTPLUG_INT_STATUS_I915;
2046
2047         /*
2048          * We absolutely have to clear all the pending interrupt
2049          * bits in PORT_HOTPLUG_STAT. Otherwise the ISR port
2050          * interrupt bit won't have an edge, and the i965/g4x
2051          * edge triggered IIR will not notice that an interrupt
2052          * is still pending. We can't use PORT_HOTPLUG_EN to
2053          * guarantee the edge as the act of toggling the enable
2054          * bits can itself generate a new hotplug interrupt :(
2055          */
2056         for (i = 0; i < 10; i++) {
2057                 u32 tmp = I915_READ(PORT_HOTPLUG_STAT) & hotplug_status_mask;
2058
2059                 if (tmp == 0)
2060                         return hotplug_status;
2061
2062                 hotplug_status |= tmp;
2063                 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2064         }
2065
2066         WARN_ONCE(1,
2067                   "PORT_HOTPLUG_STAT did not clear (0x%08x)\n",
2068                   I915_READ(PORT_HOTPLUG_STAT));
2069
2070         return hotplug_status;
2071 }
2072
2073 static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
2074                                  u32 hotplug_status)
2075 {
2076         u32 pin_mask = 0, long_mask = 0;
2077
2078         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
2079             IS_CHERRYVIEW(dev_priv)) {
2080                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
2081
2082                 if (hotplug_trigger) {
2083                         intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2084                                            hotplug_trigger, hotplug_trigger,
2085                                            hpd_status_g4x,
2086                                            i9xx_port_hotplug_long_detect);
2087
2088                         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2089                 }
2090
2091                 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
2092                         dp_aux_irq_handler(dev_priv);
2093         } else {
2094                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
2095
2096                 if (hotplug_trigger) {
2097                         intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2098                                            hotplug_trigger, hotplug_trigger,
2099                                            hpd_status_i915,
2100                                            i9xx_port_hotplug_long_detect);
2101                         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2102                 }
2103         }
2104 }
2105
2106 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
2107 {
2108         struct drm_device *dev = arg;
2109         struct drm_i915_private *dev_priv = to_i915(dev);
2110         irqreturn_t ret = IRQ_NONE;
2111
2112         if (!intel_irqs_enabled(dev_priv))
2113                 return IRQ_NONE;
2114
2115         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2116         disable_rpm_wakeref_asserts(dev_priv);
2117
2118         do {
2119                 u32 iir, gt_iir, pm_iir;
2120                 u32 pipe_stats[I915_MAX_PIPES] = {};
2121                 u32 hotplug_status = 0;
2122                 u32 ier = 0;
2123
2124                 gt_iir = I915_READ(GTIIR);
2125                 pm_iir = I915_READ(GEN6_PMIIR);
2126                 iir = I915_READ(VLV_IIR);
2127
2128                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
2129                         break;
2130
2131                 ret = IRQ_HANDLED;
2132
2133                 /*
2134                  * Theory on interrupt generation, based on empirical evidence:
2135                  *
2136                  * x = ((VLV_IIR & VLV_IER) ||
2137                  *      (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
2138                  *       (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
2139                  *
2140                  * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
2141                  * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
2142                  * guarantee the CPU interrupt will be raised again even if we
2143                  * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
2144                  * bits this time around.
2145                  */
2146                 I915_WRITE(VLV_MASTER_IER, 0);
2147                 ier = I915_READ(VLV_IER);
2148                 I915_WRITE(VLV_IER, 0);
2149
2150                 if (gt_iir)
2151                         I915_WRITE(GTIIR, gt_iir);
2152                 if (pm_iir)
2153                         I915_WRITE(GEN6_PMIIR, pm_iir);
2154
2155                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
2156                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
2157
2158                 /* Call regardless, as some status bits might not be
2159                  * signalled in iir */
2160                 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
2161
2162                 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
2163                            I915_LPE_PIPE_B_INTERRUPT))
2164                         intel_lpe_audio_irq_handler(dev_priv);
2165
2166                 /*
2167                  * VLV_IIR is single buffered, and reflects the level
2168                  * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
2169                  */
2170                 if (iir)
2171                         I915_WRITE(VLV_IIR, iir);
2172
2173                 I915_WRITE(VLV_IER, ier);
2174                 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2175
2176                 if (gt_iir)
2177                         snb_gt_irq_handler(dev_priv, gt_iir);
2178                 if (pm_iir)
2179                         gen6_rps_irq_handler(dev_priv, pm_iir);
2180
2181                 if (hotplug_status)
2182                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
2183
2184                 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
2185         } while (0);
2186
2187         enable_rpm_wakeref_asserts(dev_priv);
2188
2189         return ret;
2190 }
2191
2192 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
2193 {
2194         struct drm_device *dev = arg;
2195         struct drm_i915_private *dev_priv = to_i915(dev);
2196         irqreturn_t ret = IRQ_NONE;
2197
2198         if (!intel_irqs_enabled(dev_priv))
2199                 return IRQ_NONE;
2200
2201         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2202         disable_rpm_wakeref_asserts(dev_priv);
2203
2204         do {
2205                 u32 master_ctl, iir;
2206                 u32 pipe_stats[I915_MAX_PIPES] = {};
2207                 u32 hotplug_status = 0;
2208                 u32 gt_iir[4];
2209                 u32 ier = 0;
2210
2211                 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
2212                 iir = I915_READ(VLV_IIR);
2213
2214                 if (master_ctl == 0 && iir == 0)
2215                         break;
2216
2217                 ret = IRQ_HANDLED;
2218
2219                 /*
2220                  * Theory on interrupt generation, based on empirical evidence:
2221                  *
2222                  * x = ((VLV_IIR & VLV_IER) ||
2223                  *      ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
2224                  *       (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
2225                  *
2226                  * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
2227                  * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
2228                  * guarantee the CPU interrupt will be raised again even if we
2229                  * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
2230                  * bits this time around.
2231                  */
2232                 I915_WRITE(GEN8_MASTER_IRQ, 0);
2233                 ier = I915_READ(VLV_IER);
2234                 I915_WRITE(VLV_IER, 0);
2235
2236                 gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
2237
2238                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
2239                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
2240
2241                 /* Call regardless, as some status bits might not be
2242                  * signalled in iir */
2243                 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
2244
2245                 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
2246                            I915_LPE_PIPE_B_INTERRUPT |
2247                            I915_LPE_PIPE_C_INTERRUPT))
2248                         intel_lpe_audio_irq_handler(dev_priv);
2249
2250                 /*
2251                  * VLV_IIR is single buffered, and reflects the level
2252                  * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
2253                  */
2254                 if (iir)
2255                         I915_WRITE(VLV_IIR, iir);
2256
2257                 I915_WRITE(VLV_IER, ier);
2258                 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2259
2260                 gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
2261
2262                 if (hotplug_status)
2263                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
2264
2265                 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
2266         } while (0);
2267
2268         enable_rpm_wakeref_asserts(dev_priv);
2269
2270         return ret;
2271 }
2272
2273 static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
2274                                 u32 hotplug_trigger,
2275                                 const u32 hpd[HPD_NUM_PINS])
2276 {
2277         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2278
2279         /*
2280          * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
2281          * unless we touch the hotplug register, even if hotplug_trigger is
2282          * zero. Not acking leads to "The master control interrupt lied (SDE)!"
2283          * errors.
2284          */
2285         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2286         if (!hotplug_trigger) {
2287                 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
2288                         PORTD_HOTPLUG_STATUS_MASK |
2289                         PORTC_HOTPLUG_STATUS_MASK |
2290                         PORTB_HOTPLUG_STATUS_MASK;
2291                 dig_hotplug_reg &= ~mask;
2292         }
2293
2294         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2295         if (!hotplug_trigger)
2296                 return;
2297
2298         intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
2299                            dig_hotplug_reg, hpd,
2300                            pch_port_hotplug_long_detect);
2301
2302         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2303 }
2304
2305 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2306 {
2307         int pipe;
2308         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
2309
2310         ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx);
2311
2312         if (pch_iir & SDE_AUDIO_POWER_MASK) {
2313                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
2314                                SDE_AUDIO_POWER_SHIFT);
2315                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
2316                                  port_name(port));
2317         }
2318
2319         if (pch_iir & SDE_AUX_MASK)
2320                 dp_aux_irq_handler(dev_priv);
2321
2322         if (pch_iir & SDE_GMBUS)
2323                 gmbus_irq_handler(dev_priv);
2324
2325         if (pch_iir & SDE_AUDIO_HDCP_MASK)
2326                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
2327
2328         if (pch_iir & SDE_AUDIO_TRANS_MASK)
2329                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
2330
2331         if (pch_iir & SDE_POISON)
2332                 DRM_ERROR("PCH poison interrupt\n");
2333
2334         if (pch_iir & SDE_FDI_MASK)
2335                 for_each_pipe(dev_priv, pipe)
2336                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
2337                                          pipe_name(pipe),
2338                                          I915_READ(FDI_RX_IIR(pipe)));
2339
2340         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
2341                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
2342
2343         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
2344                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
2345
2346         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
2347                 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
2348
2349         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
2350                 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);
2351 }
2352
2353 static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
2354 {
2355         u32 err_int = I915_READ(GEN7_ERR_INT);
2356         enum pipe pipe;
2357
2358         if (err_int & ERR_INT_POISON)
2359                 DRM_ERROR("Poison interrupt\n");
2360
2361         for_each_pipe(dev_priv, pipe) {
2362                 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
2363                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2364
2365                 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
2366                         if (IS_IVYBRIDGE(dev_priv))
2367                                 ivb_pipe_crc_irq_handler(dev_priv, pipe);
2368                         else
2369                                 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2370                 }
2371         }
2372
2373         I915_WRITE(GEN7_ERR_INT, err_int);
2374 }
2375
2376 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
2377 {
2378         u32 serr_int = I915_READ(SERR_INT);
2379         enum pipe pipe;
2380
2381         if (serr_int & SERR_INT_POISON)
2382                 DRM_ERROR("PCH poison interrupt\n");
2383
2384         for_each_pipe(dev_priv, pipe)
2385                 if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe))
2386                         intel_pch_fifo_underrun_irq_handler(dev_priv, pipe);
2387
2388         I915_WRITE(SERR_INT, serr_int);
2389 }
2390
2391 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2392 {
2393         int pipe;
2394         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2395
2396         ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt);
2397
2398         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2399                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2400                                SDE_AUDIO_POWER_SHIFT_CPT);
2401                 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2402                                  port_name(port));
2403         }
2404
2405         if (pch_iir & SDE_AUX_MASK_CPT)
2406                 dp_aux_irq_handler(dev_priv);
2407
2408         if (pch_iir & SDE_GMBUS_CPT)
2409                 gmbus_irq_handler(dev_priv);
2410
2411         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2412                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2413
2414         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2415                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2416
2417         if (pch_iir & SDE_FDI_MASK_CPT)
2418                 for_each_pipe(dev_priv, pipe)
2419                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
2420                                          pipe_name(pipe),
2421                                          I915_READ(FDI_RX_IIR(pipe)));
2422
2423         if (pch_iir & SDE_ERROR_CPT)
2424                 cpt_serr_int_handler(dev_priv);
2425 }
2426
2427 static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2428 {
2429         u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
2430         u32 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
2431         u32 pin_mask = 0, long_mask = 0;
2432
2433         if (ddi_hotplug_trigger) {
2434                 u32 dig_hotplug_reg;
2435
2436                 dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
2437                 I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
2438
2439                 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2440                                    ddi_hotplug_trigger,
2441                                    dig_hotplug_reg, hpd_icp,
2442                                    icp_ddi_port_hotplug_long_detect);
2443         }
2444
2445         if (tc_hotplug_trigger) {
2446                 u32 dig_hotplug_reg;
2447
2448                 dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
2449                 I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
2450
2451                 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2452                                    tc_hotplug_trigger,
2453                                    dig_hotplug_reg, hpd_icp,
2454                                    icp_tc_port_hotplug_long_detect);
2455         }
2456
2457         if (pin_mask)
2458                 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2459
2460         if (pch_iir & SDE_GMBUS_ICP)
2461                 gmbus_irq_handler(dev_priv);
2462 }
2463
2464 static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2465 {
2466         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
2467                 ~SDE_PORTE_HOTPLUG_SPT;
2468         u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
2469         u32 pin_mask = 0, long_mask = 0;
2470
2471         if (hotplug_trigger) {
2472                 u32 dig_hotplug_reg;
2473
2474                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2475                 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2476
2477                 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2478                                    hotplug_trigger, dig_hotplug_reg, hpd_spt,
2479                                    spt_port_hotplug_long_detect);
2480         }
2481
2482         if (hotplug2_trigger) {
2483                 u32 dig_hotplug_reg;
2484
2485                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
2486                 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
2487
2488                 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2489                                    hotplug2_trigger, dig_hotplug_reg, hpd_spt,
2490                                    spt_port_hotplug2_long_detect);
2491         }
2492
2493         if (pin_mask)
2494                 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2495
2496         if (pch_iir & SDE_GMBUS_CPT)
2497                 gmbus_irq_handler(dev_priv);
2498 }
2499
2500 static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
2501                                 u32 hotplug_trigger,
2502                                 const u32 hpd[HPD_NUM_PINS])
2503 {
2504         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2505
2506         dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
2507         I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2508
2509         intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
2510                            dig_hotplug_reg, hpd,
2511                            ilk_port_hotplug_long_detect);
2512
2513         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2514 }
2515
2516 static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
2517                                     u32 de_iir)
2518 {
2519         enum pipe pipe;
2520         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2521
2522         if (hotplug_trigger)
2523                 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk);
2524
2525         if (de_iir & DE_AUX_CHANNEL_A)
2526                 dp_aux_irq_handler(dev_priv);
2527
2528         if (de_iir & DE_GSE)
2529                 intel_opregion_asle_intr(dev_priv);
2530
2531         if (de_iir & DE_POISON)
2532                 DRM_ERROR("Poison interrupt\n");
2533
2534         for_each_pipe(dev_priv, pipe) {
2535                 if (de_iir & DE_PIPE_VBLANK(pipe))
2536                         drm_handle_vblank(&dev_priv->drm, pipe);
2537
2538                 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2539                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2540
2541                 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2542                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2543         }
2544
2545         /* check event from PCH */
2546         if (de_iir & DE_PCH_EVENT) {
2547                 u32 pch_iir = I915_READ(SDEIIR);
2548
2549                 if (HAS_PCH_CPT(dev_priv))
2550                         cpt_irq_handler(dev_priv, pch_iir);
2551                 else
2552                         ibx_irq_handler(dev_priv, pch_iir);
2553
2554                 /* should clear PCH hotplug event before clear CPU irq */
2555                 I915_WRITE(SDEIIR, pch_iir);
2556         }
2557
2558         if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT)
2559                 ironlake_rps_change_irq_handler(dev_priv);
2560 }
2561
2562 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2563                                     u32 de_iir)
2564 {
2565         enum pipe pipe;
2566         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2567
2568         if (hotplug_trigger)
2569                 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb);
2570
2571         if (de_iir & DE_ERR_INT_IVB)
2572                 ivb_err_int_handler(dev_priv);
2573
2574         if (de_iir & DE_EDP_PSR_INT_HSW) {
2575                 u32 psr_iir = I915_READ(EDP_PSR_IIR);
2576
2577                 intel_psr_irq_handler(dev_priv, psr_iir);
2578                 I915_WRITE(EDP_PSR_IIR, psr_iir);
2579         }
2580
2581         if (de_iir & DE_AUX_CHANNEL_A_IVB)
2582                 dp_aux_irq_handler(dev_priv);
2583
2584         if (de_iir & DE_GSE_IVB)
2585                 intel_opregion_asle_intr(dev_priv);
2586
2587         for_each_pipe(dev_priv, pipe) {
2588                 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
2589                         drm_handle_vblank(&dev_priv->drm, pipe);
2590         }
2591
2592         /* check event from PCH */
2593         if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2594                 u32 pch_iir = I915_READ(SDEIIR);
2595
2596                 cpt_irq_handler(dev_priv, pch_iir);
2597
2598                 /* clear PCH hotplug event before clear CPU irq */
2599                 I915_WRITE(SDEIIR, pch_iir);
2600         }
2601 }
2602
2603 /*
2604  * To handle irqs with the minimum potential races with fresh interrupts, we:
2605  * 1 - Disable Master Interrupt Control.
2606  * 2 - Find the source(s) of the interrupt.
2607  * 3 - Clear the Interrupt Identity bits (IIR).
2608  * 4 - Process the interrupt(s) that had bits set in the IIRs.
2609  * 5 - Re-enable Master Interrupt Control.
2610  */
2611 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2612 {
2613         struct drm_device *dev = arg;
2614         struct drm_i915_private *dev_priv = to_i915(dev);
2615         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2616         irqreturn_t ret = IRQ_NONE;
2617
2618         if (!intel_irqs_enabled(dev_priv))
2619                 return IRQ_NONE;
2620
2621         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2622         disable_rpm_wakeref_asserts(dev_priv);
2623
2624         /* disable master interrupt before clearing iir  */
2625         de_ier = I915_READ(DEIER);
2626         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2627
2628         /* Disable south interrupts. We'll only write to SDEIIR once, so further
2629          * interrupts will will be stored on its back queue, and then we'll be
2630          * able to process them after we restore SDEIER (as soon as we restore
2631          * it, we'll get an interrupt if SDEIIR still has something to process
2632          * due to its back queue). */
2633         if (!HAS_PCH_NOP(dev_priv)) {
2634                 sde_ier = I915_READ(SDEIER);
2635                 I915_WRITE(SDEIER, 0);
2636         }
2637
2638         /* Find, clear, then process each source of interrupt */
2639
2640         gt_iir = I915_READ(GTIIR);
2641         if (gt_iir) {
2642                 I915_WRITE(GTIIR, gt_iir);
2643                 ret = IRQ_HANDLED;
2644                 if (INTEL_GEN(dev_priv) >= 6)
2645                         snb_gt_irq_handler(dev_priv, gt_iir);
2646                 else
2647                         ilk_gt_irq_handler(dev_priv, gt_iir);
2648         }
2649
2650         de_iir = I915_READ(DEIIR);
2651         if (de_iir) {
2652                 I915_WRITE(DEIIR, de_iir);
2653                 ret = IRQ_HANDLED;
2654                 if (INTEL_GEN(dev_priv) >= 7)
2655                         ivb_display_irq_handler(dev_priv, de_iir);
2656                 else
2657                         ilk_display_irq_handler(dev_priv, de_iir);
2658         }
2659
2660         if (INTEL_GEN(dev_priv) >= 6) {
2661                 u32 pm_iir = I915_READ(GEN6_PMIIR);
2662                 if (pm_iir) {
2663                         I915_WRITE(GEN6_PMIIR, pm_iir);
2664                         ret = IRQ_HANDLED;
2665                         gen6_rps_irq_handler(dev_priv, pm_iir);
2666                 }
2667         }
2668
2669         I915_WRITE(DEIER, de_ier);
2670         if (!HAS_PCH_NOP(dev_priv))
2671                 I915_WRITE(SDEIER, sde_ier);
2672
2673         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2674         enable_rpm_wakeref_asserts(dev_priv);
2675
2676         return ret;
2677 }
2678
2679 static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2680                                 u32 hotplug_trigger,
2681                                 const u32 hpd[HPD_NUM_PINS])
2682 {
2683         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2684
2685         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2686         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2687
2688         intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
2689                            dig_hotplug_reg, hpd,
2690                            bxt_port_hotplug_long_detect);
2691
2692         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2693 }
2694
2695 static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
2696 {
2697         u32 pin_mask = 0, long_mask = 0;
2698         u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
2699         u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK;
2700
2701         if (trigger_tc) {
2702                 u32 dig_hotplug_reg;
2703
2704                 dig_hotplug_reg = I915_READ(GEN11_TC_HOTPLUG_CTL);
2705                 I915_WRITE(GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg);
2706
2707                 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tc,
2708                                    dig_hotplug_reg, hpd_gen11,
2709                                    gen11_port_hotplug_long_detect);
2710         }
2711
2712         if (trigger_tbt) {
2713                 u32 dig_hotplug_reg;
2714
2715                 dig_hotplug_reg = I915_READ(GEN11_TBT_HOTPLUG_CTL);
2716                 I915_WRITE(GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg);
2717
2718                 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tbt,
2719                                    dig_hotplug_reg, hpd_gen11,
2720                                    gen11_port_hotplug_long_detect);
2721         }
2722
2723         if (pin_mask)
2724                 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2725         else
2726                 DRM_ERROR("Unexpected DE HPD interrupt 0x%08x\n", iir);
2727 }
2728
2729 static irqreturn_t
2730 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2731 {
2732         irqreturn_t ret = IRQ_NONE;
2733         u32 iir;
2734         enum pipe pipe;
2735
2736         if (master_ctl & GEN8_DE_MISC_IRQ) {
2737                 iir = I915_READ(GEN8_DE_MISC_IIR);
2738                 if (iir) {
2739                         bool found = false;
2740
2741                         I915_WRITE(GEN8_DE_MISC_IIR, iir);
2742                         ret = IRQ_HANDLED;
2743
2744                         if (iir & GEN8_DE_MISC_GSE) {
2745                                 intel_opregion_asle_intr(dev_priv);
2746                                 found = true;
2747                         }
2748
2749                         if (iir & GEN8_DE_EDP_PSR) {
2750                                 u32 psr_iir = I915_READ(EDP_PSR_IIR);
2751
2752                                 intel_psr_irq_handler(dev_priv, psr_iir);
2753                                 I915_WRITE(EDP_PSR_IIR, psr_iir);
2754                                 found = true;
2755                         }
2756
2757                         if (!found)
2758                                 DRM_ERROR("Unexpected DE Misc interrupt\n");
2759                 }
2760                 else
2761                         DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2762         }
2763
2764         if (INTEL_GEN(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {
2765                 iir = I915_READ(GEN11_DE_HPD_IIR);
2766                 if (iir) {
2767                         I915_WRITE(GEN11_DE_HPD_IIR, iir);
2768                         ret = IRQ_HANDLED;
2769                         gen11_hpd_irq_handler(dev_priv, iir);
2770                 } else {
2771                         DRM_ERROR("The master control interrupt lied, (DE HPD)!\n");
2772                 }
2773         }
2774
2775         if (master_ctl & GEN8_DE_PORT_IRQ) {
2776                 iir = I915_READ(GEN8_DE_PORT_IIR);
2777                 if (iir) {
2778                         u32 tmp_mask;
2779                         bool found = false;
2780
2781                         I915_WRITE(GEN8_DE_PORT_IIR, iir);
2782                         ret = IRQ_HANDLED;
2783
2784                         tmp_mask = GEN8_AUX_CHANNEL_A;
2785                         if (INTEL_GEN(dev_priv) >= 9)
2786                                 tmp_mask |= GEN9_AUX_CHANNEL_B |
2787                                             GEN9_AUX_CHANNEL_C |
2788                                             GEN9_AUX_CHANNEL_D;
2789
2790                         if (INTEL_GEN(dev_priv) >= 11)
2791                                 tmp_mask |= ICL_AUX_CHANNEL_E;
2792
2793                         if (IS_CNL_WITH_PORT_F(dev_priv) ||
2794                             INTEL_GEN(dev_priv) >= 11)
2795                                 tmp_mask |= CNL_AUX_CHANNEL_F;
2796
2797                         if (iir & tmp_mask) {
2798                                 dp_aux_irq_handler(dev_priv);
2799                                 found = true;
2800                         }
2801
2802                         if (IS_GEN9_LP(dev_priv)) {
2803                                 tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2804                                 if (tmp_mask) {
2805                                         bxt_hpd_irq_handler(dev_priv, tmp_mask,
2806                                                             hpd_bxt);
2807                                         found = true;
2808                                 }
2809                         } else if (IS_BROADWELL(dev_priv)) {
2810                                 tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2811                                 if (tmp_mask) {
2812                                         ilk_hpd_irq_handler(dev_priv,
2813                                                             tmp_mask, hpd_bdw);
2814                                         found = true;
2815                                 }
2816                         }
2817
2818                         if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
2819                                 gmbus_irq_handler(dev_priv);
2820                                 found = true;
2821                         }
2822
2823                         if (!found)
2824                                 DRM_ERROR("Unexpected DE Port interrupt\n");
2825                 }
2826                 else
2827                         DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2828         }
2829
2830         for_each_pipe(dev_priv, pipe) {
2831                 u32 fault_errors;
2832
2833                 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2834                         continue;
2835
2836                 iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2837                 if (!iir) {
2838                         DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2839                         continue;
2840                 }
2841
2842                 ret = IRQ_HANDLED;
2843                 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2844
2845                 if (iir & GEN8_PIPE_VBLANK)
2846                         drm_handle_vblank(&dev_priv->drm, pipe);
2847
2848                 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2849                         hsw_pipe_crc_irq_handler(dev_priv, pipe);
2850
2851                 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2852                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2853
2854                 fault_errors = iir;
2855                 if (INTEL_GEN(dev_priv) >= 9)
2856                         fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2857                 else
2858                         fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2859
2860                 if (fault_errors)
2861                         DRM_ERROR("Fault errors on pipe %c: 0x%08x\n",
2862                                   pipe_name(pipe),
2863                                   fault_errors);
2864         }
2865
2866         if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2867             master_ctl & GEN8_DE_PCH_IRQ) {
2868                 /*
2869                  * FIXME(BDW): Assume for now that the new interrupt handling
2870                  * scheme also closed the SDE interrupt handling race we've seen
2871                  * on older pch-split platforms. But this needs testing.
2872                  */
2873                 iir = I915_READ(SDEIIR);
2874                 if (iir) {
2875                         I915_WRITE(SDEIIR, iir);
2876                         ret = IRQ_HANDLED;
2877
2878                         if (HAS_PCH_ICP(dev_priv))
2879                                 icp_irq_handler(dev_priv, iir);
2880                         else if (HAS_PCH_SPT(dev_priv) ||
2881                                  HAS_PCH_KBP(dev_priv) ||
2882                                  HAS_PCH_CNP(dev_priv))
2883                                 spt_irq_handler(dev_priv, iir);
2884                         else
2885                                 cpt_irq_handler(dev_priv, iir);
2886                 } else {
2887                         /*
2888                          * Like on previous PCH there seems to be something
2889                          * fishy going on with forwarding PCH interrupts.
2890                          */
2891                         DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2892                 }
2893         }
2894
2895         return ret;
2896 }
2897
2898 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2899 {
2900         struct drm_i915_private *dev_priv = to_i915(arg);
2901         u32 master_ctl;
2902         u32 gt_iir[4];
2903
2904         if (!intel_irqs_enabled(dev_priv))
2905                 return IRQ_NONE;
2906
2907         master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
2908         master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2909         if (!master_ctl)
2910                 return IRQ_NONE;
2911
2912         I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
2913
2914         /* Find, clear, then process each source of interrupt */
2915         gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
2916
2917         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2918         if (master_ctl & ~GEN8_GT_IRQS) {
2919                 disable_rpm_wakeref_asserts(dev_priv);
2920                 gen8_de_irq_handler(dev_priv, master_ctl);
2921                 enable_rpm_wakeref_asserts(dev_priv);
2922         }
2923
2924         I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2925
2926         gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
2927
2928         return IRQ_HANDLED;
2929 }
2930
2931 struct wedge_me {
2932         struct delayed_work work;
2933         struct drm_i915_private *i915;
2934         const char *name;
2935 };
2936
2937 static void wedge_me(struct work_struct *work)
2938 {
2939         struct wedge_me *w = container_of(work, typeof(*w), work.work);
2940
2941         dev_err(w->i915->drm.dev,
2942                 "%s timed out, cancelling all in-flight rendering.\n",
2943                 w->name);
2944         i915_gem_set_wedged(w->i915);
2945 }
2946
2947 static void __init_wedge(struct wedge_me *w,
2948                          struct drm_i915_private *i915,
2949                          long timeout,
2950                          const char *name)
2951 {
2952         w->i915 = i915;
2953         w->name = name;
2954
2955         INIT_DELAYED_WORK_ONSTACK(&w->work, wedge_me);
2956         schedule_delayed_work(&w->work, timeout);
2957 }
2958
2959 static void __fini_wedge(struct wedge_me *w)
2960 {
2961         cancel_delayed_work_sync(&w->work);
2962         destroy_delayed_work_on_stack(&w->work);
2963         w->i915 = NULL;
2964 }
2965
2966 #define i915_wedge_on_timeout(W, DEV, TIMEOUT)                          \
2967         for (__init_wedge((W), (DEV), (TIMEOUT), __func__);             \
2968              (W)->i915;                                                 \
2969              __fini_wedge((W)))
2970
2971 static u32
2972 gen11_gt_engine_identity(struct drm_i915_private * const i915,
2973                          const unsigned int bank, const unsigned int bit)
2974 {
2975         void __iomem * const regs = i915->regs;
2976         u32 timeout_ts;
2977         u32 ident;
2978
2979         lockdep_assert_held(&i915->irq_lock);
2980
2981         raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank), BIT(bit));
2982
2983         /*
2984          * NB: Specs do not specify how long to spin wait,
2985          * so we do ~100us as an educated guess.
2986          */
2987         timeout_ts = (local_clock() >> 10) + 100;
2988         do {
2989                 ident = raw_reg_read(regs, GEN11_INTR_IDENTITY_REG(bank));
2990         } while (!(ident & GEN11_INTR_DATA_VALID) &&
2991                  !time_after32(local_clock() >> 10, timeout_ts));
2992
2993         if (unlikely(!(ident & GEN11_INTR_DATA_VALID))) {
2994                 DRM_ERROR("INTR_IDENTITY_REG%u:%u 0x%08x not valid!\n",
2995                           bank, bit, ident);
2996                 return 0;
2997         }
2998
2999         raw_reg_write(regs, GEN11_INTR_IDENTITY_REG(bank),
3000                       GEN11_INTR_DATA_VALID);
3001
3002         return ident;
3003 }
3004
3005 static void
3006 gen11_other_irq_handler(struct drm_i915_private * const i915,
3007                         const u8 instance, const u16 iir)
3008 {
3009         if (instance == OTHER_GTPM_INSTANCE)
3010                 return gen6_rps_irq_handler(i915, iir);
3011
3012         WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
3013                   instance, iir);
3014 }
3015
3016 static void
3017 gen11_engine_irq_handler(struct drm_i915_private * const i915,
3018                          const u8 class, const u8 instance, const u16 iir)
3019 {
3020         struct intel_engine_cs *engine;
3021
3022         if (instance <= MAX_ENGINE_INSTANCE)
3023                 engine = i915->engine_class[class][instance];
3024         else
3025                 engine = NULL;
3026
3027         if (likely(engine))
3028                 return gen8_cs_irq_handler(engine, iir);
3029
3030         WARN_ONCE(1, "unhandled engine interrupt class=0x%x, instance=0x%x\n",
3031                   class, instance);
3032 }
3033
3034 static void
3035 gen11_gt_identity_handler(struct drm_i915_private * const i915,
3036                           const u32 identity)
3037 {
3038         const u8 class = GEN11_INTR_ENGINE_CLASS(identity);
3039         const u8 instance = GEN11_INTR_ENGINE_INSTANCE(identity);
3040         const u16 intr = GEN11_INTR_ENGINE_INTR(identity);
3041
3042         if (unlikely(!intr))
3043                 return;
3044
3045         if (class <= COPY_ENGINE_CLASS)
3046                 return gen11_engine_irq_handler(i915, class, instance, intr);
3047
3048         if (class == OTHER_CLASS)
3049                 return gen11_other_irq_handler(i915, instance, intr);
3050
3051         WARN_ONCE(1, "unknown interrupt class=0x%x, instance=0x%x, intr=0x%x\n",
3052                   class, instance, intr);
3053 }
3054
3055 static void
3056 gen11_gt_bank_handler(struct drm_i915_private * const i915,
3057                       const unsigned int bank)
3058 {
3059         void __iomem * const regs = i915->regs;
3060         unsigned long intr_dw;
3061         unsigned int bit;
3062
3063         lockdep_assert_held(&i915->irq_lock);
3064
3065         intr_dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
3066
3067         if (unlikely(!intr_dw)) {
3068                 DRM_ERROR("GT_INTR_DW%u blank!\n", bank);
3069                 return;
3070         }
3071
3072         for_each_set_bit(bit, &intr_dw, 32) {
3073                 const u32 ident = gen11_gt_engine_identity(i915,
3074                                                            bank, bit);
3075
3076                 gen11_gt_identity_handler(i915, ident);
3077         }
3078
3079         /* Clear must be after shared has been served for engine */
3080         raw_reg_write(regs, GEN11_GT_INTR_DW(bank), intr_dw);
3081 }
3082
3083 static void
3084 gen11_gt_irq_handler(struct drm_i915_private * const i915,
3085                      const u32 master_ctl)
3086 {
3087         unsigned int bank;
3088
3089         spin_lock(&i915->irq_lock);
3090
3091         for (bank = 0; bank < 2; bank++) {
3092                 if (master_ctl & GEN11_GT_DW_IRQ(bank))
3093                         gen11_gt_bank_handler(i915, bank);
3094         }
3095
3096         spin_unlock(&i915->irq_lock);
3097 }
3098
3099 static void
3100 gen11_gu_misc_irq_ack(struct drm_i915_private *dev_priv, const u32 master_ctl,
3101                       u32 *iir)
3102 {
3103         void __iomem * const regs = dev_priv->regs;
3104
3105         if (!(master_ctl & GEN11_GU_MISC_IRQ))
3106                 return;
3107
3108         *iir = raw_reg_read(regs, GEN11_GU_MISC_IIR);
3109         if (likely(*iir))
3110                 raw_reg_write(regs, GEN11_GU_MISC_IIR, *iir);
3111 }
3112
3113 static void
3114 gen11_gu_misc_irq_handler(struct drm_i915_private *dev_priv,
3115                           const u32 master_ctl, const u32 iir)
3116 {
3117         if (!(master_ctl & GEN11_GU_MISC_IRQ))
3118                 return;
3119
3120         if (unlikely(!iir)) {
3121                 DRM_ERROR("GU_MISC iir blank!\n");
3122                 return;
3123         }
3124
3125         if (iir & GEN11_GU_MISC_GSE)
3126                 intel_opregion_asle_intr(dev_priv);
3127         else
3128                 DRM_ERROR("Unexpected GU_MISC interrupt 0x%x\n", iir);
3129 }
3130
3131 static irqreturn_t gen11_irq_handler(int irq, void *arg)
3132 {
3133         struct drm_i915_private * const i915 = to_i915(arg);
3134         void __iomem * const regs = i915->regs;
3135         u32 master_ctl;
3136         u32 gu_misc_iir;
3137
3138         if (!intel_irqs_enabled(i915))
3139                 return IRQ_NONE;
3140
3141         master_ctl = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
3142         master_ctl &= ~GEN11_MASTER_IRQ;
3143         if (!master_ctl)
3144                 return IRQ_NONE;
3145
3146         /* Disable interrupts. */
3147         raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0);
3148
3149         /* Find, clear, then process each source of interrupt. */
3150         gen11_gt_irq_handler(i915, master_ctl);
3151
3152         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3153         if (master_ctl & GEN11_DISPLAY_IRQ) {
3154                 const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
3155
3156                 disable_rpm_wakeref_asserts(i915);
3157                 /*
3158                  * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ
3159                  * for the display related bits.
3160                  */
3161                 gen8_de_irq_handler(i915, disp_ctl);
3162                 enable_rpm_wakeref_asserts(i915);
3163         }
3164
3165         gen11_gu_misc_irq_ack(i915, master_ctl, &gu_misc_iir);
3166
3167         /* Acknowledge and enable interrupts. */
3168         raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ | master_ctl);
3169
3170         gen11_gu_misc_irq_handler(i915, master_ctl, gu_misc_iir);
3171
3172         return IRQ_HANDLED;
3173 }
3174
3175 static void i915_reset_device(struct drm_i915_private *dev_priv,
3176                               u32 engine_mask,
3177                               const char *reason)
3178 {
3179         struct i915_gpu_error *error = &dev_priv->gpu_error;
3180         struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
3181         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
3182         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
3183         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
3184         struct wedge_me w;
3185
3186         kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
3187
3188         DRM_DEBUG_DRIVER("resetting chip\n");
3189         kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
3190
3191         /* Use a watchdog to ensure that our reset completes */
3192         i915_wedge_on_timeout(&w, dev_priv, 5*HZ) {
3193                 intel_prepare_reset(dev_priv);
3194
3195                 error->reason = reason;
3196                 error->stalled_mask = engine_mask;
3197
3198                 /* Signal that locked waiters should reset the GPU */
3199                 smp_mb__before_atomic();
3200                 set_bit(I915_RESET_HANDOFF, &error->flags);
3201                 wake_up_all(&error->wait_queue);
3202
3203                 /* Wait for anyone holding the lock to wakeup, without
3204                  * blocking indefinitely on struct_mutex.
3205                  */
3206                 do {
3207                         if (mutex_trylock(&dev_priv->drm.struct_mutex)) {
3208                                 i915_reset(dev_priv, engine_mask, reason);
3209                                 mutex_unlock(&dev_priv->drm.struct_mutex);
3210                         }
3211                 } while (wait_on_bit_timeout(&error->flags,
3212                                              I915_RESET_HANDOFF,
3213                                              TASK_UNINTERRUPTIBLE,
3214                                              1));
3215
3216                 error->stalled_mask = 0;
3217                 error->reason = NULL;
3218
3219                 intel_finish_reset(dev_priv);
3220         }
3221
3222         if (!test_bit(I915_WEDGED, &error->flags))
3223                 kobject_uevent_env(kobj, KOBJ_CHANGE, reset_done_event);
3224 }
3225
3226 static void i915_clear_error_registers(struct drm_i915_private *dev_priv)
3227 {
3228         u32 eir;
3229
3230         if (!IS_GEN2(dev_priv))
3231                 I915_WRITE(PGTBL_ER, I915_READ(PGTBL_ER));
3232
3233         if (INTEL_GEN(dev_priv) < 4)
3234                 I915_WRITE(IPEIR, I915_READ(IPEIR));
3235         else
3236                 I915_WRITE(IPEIR_I965, I915_READ(IPEIR_I965));
3237
3238         I915_WRITE(EIR, I915_READ(EIR));
3239         eir = I915_READ(EIR);
3240         if (eir) {
3241                 /*
3242                  * some errors might have become stuck,
3243                  * mask them.
3244                  */
3245                 DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
3246                 I915_WRITE(EMR, I915_READ(EMR) | eir);
3247                 I915_WRITE(IIR, I915_MASTER_ERROR_INTERRUPT);
3248         }
3249 }
3250
3251 /**
3252  * i915_handle_error - handle a gpu error
3253  * @dev_priv: i915 device private
3254  * @engine_mask: mask representing engines that are hung
3255  * @flags: control flags
3256  * @fmt: Error message format string
3257  *
3258  * Do some basic checking of register state at error time and
3259  * dump it to the syslog.  Also call i915_capture_error_state() to make
3260  * sure we get a record and make it available in debugfs.  Fire a uevent
3261  * so userspace knows something bad happened (should trigger collection
3262  * of a ring dump etc.).
3263  */
3264 void i915_handle_error(struct drm_i915_private *dev_priv,
3265                        u32 engine_mask,
3266                        unsigned long flags,
3267                        const char *fmt, ...)
3268 {
3269         struct intel_engine_cs *engine;
3270         unsigned int tmp;
3271         char error_msg[80];
3272         char *msg = NULL;
3273
3274         if (fmt) {
3275                 va_list args;
3276
3277                 va_start(args, fmt);
3278                 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
3279                 va_end(args);
3280
3281                 msg = error_msg;
3282         }
3283
3284         /*
3285          * In most cases it's guaranteed that we get here with an RPM
3286          * reference held, for example because there is a pending GPU
3287          * request that won't finish until the reset is done. This
3288          * isn't the case at least when we get here by doing a
3289          * simulated reset via debugfs, so get an RPM reference.
3290          */
3291         intel_runtime_pm_get(dev_priv);
3292
3293         engine_mask &= INTEL_INFO(dev_priv)->ring_mask;
3294
3295         if (flags & I915_ERROR_CAPTURE) {
3296                 i915_capture_error_state(dev_priv, engine_mask, msg);
3297                 i915_clear_error_registers(dev_priv);
3298         }
3299
3300         /*
3301          * Try engine reset when available. We fall back to full reset if
3302          * single reset fails.
3303          */
3304         if (intel_has_reset_engine(dev_priv)) {
3305                 for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
3306                         BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE);
3307                         if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
3308                                              &dev_priv->gpu_error.flags))
3309                                 continue;
3310
3311                         if (i915_reset_engine(engine, msg) == 0)
3312                                 engine_mask &= ~intel_engine_flag(engine);
3313
3314                         clear_bit(I915_RESET_ENGINE + engine->id,
3315                                   &dev_priv->gpu_error.flags);
3316                         wake_up_bit(&dev_priv->gpu_error.flags,
3317                                     I915_RESET_ENGINE + engine->id);
3318                 }
3319         }