5291e08f34369a2d0528a026441da75154a24b76
[muen/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2  * Copyright © 2006-2007 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *      Eric Anholt <eric@anholt.net>
25  */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40 #include "i915_gem_clflush.h"
41 #include "intel_dsi.h"
42 #include "i915_trace.h"
43 #include <drm/drm_atomic.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_dp_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_plane_helper.h>
48 #include <drm/drm_rect.h>
49 #include <linux/dma_remapping.h>
50 #include <linux/reservation.h>
51
52 /* Primary plane formats for gen <= 3 */
53 static const uint32_t i8xx_primary_formats[] = {
54         DRM_FORMAT_C8,
55         DRM_FORMAT_RGB565,
56         DRM_FORMAT_XRGB1555,
57         DRM_FORMAT_XRGB8888,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t i965_primary_formats[] = {
62         DRM_FORMAT_C8,
63         DRM_FORMAT_RGB565,
64         DRM_FORMAT_XRGB8888,
65         DRM_FORMAT_XBGR8888,
66         DRM_FORMAT_XRGB2101010,
67         DRM_FORMAT_XBGR2101010,
68 };
69
70 static const uint64_t i9xx_format_modifiers[] = {
71         I915_FORMAT_MOD_X_TILED,
72         DRM_FORMAT_MOD_LINEAR,
73         DRM_FORMAT_MOD_INVALID
74 };
75
76 static const uint32_t skl_primary_formats[] = {
77         DRM_FORMAT_C8,
78         DRM_FORMAT_RGB565,
79         DRM_FORMAT_XRGB8888,
80         DRM_FORMAT_XBGR8888,
81         DRM_FORMAT_ARGB8888,
82         DRM_FORMAT_ABGR8888,
83         DRM_FORMAT_XRGB2101010,
84         DRM_FORMAT_XBGR2101010,
85         DRM_FORMAT_YUYV,
86         DRM_FORMAT_YVYU,
87         DRM_FORMAT_UYVY,
88         DRM_FORMAT_VYUY,
89 };
90
91 static const uint64_t skl_format_modifiers_noccs[] = {
92         I915_FORMAT_MOD_Yf_TILED,
93         I915_FORMAT_MOD_Y_TILED,
94         I915_FORMAT_MOD_X_TILED,
95         DRM_FORMAT_MOD_LINEAR,
96         DRM_FORMAT_MOD_INVALID
97 };
98
99 static const uint64_t skl_format_modifiers_ccs[] = {
100         I915_FORMAT_MOD_Yf_TILED_CCS,
101         I915_FORMAT_MOD_Y_TILED_CCS,
102         I915_FORMAT_MOD_Yf_TILED,
103         I915_FORMAT_MOD_Y_TILED,
104         I915_FORMAT_MOD_X_TILED,
105         DRM_FORMAT_MOD_LINEAR,
106         DRM_FORMAT_MOD_INVALID
107 };
108
109 /* Cursor formats */
110 static const uint32_t intel_cursor_formats[] = {
111         DRM_FORMAT_ARGB8888,
112 };
113
114 static const uint64_t cursor_format_modifiers[] = {
115         DRM_FORMAT_MOD_LINEAR,
116         DRM_FORMAT_MOD_INVALID
117 };
118
119 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
120                                 struct intel_crtc_state *pipe_config);
121 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
122                                    struct intel_crtc_state *pipe_config);
123
124 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
125                                   struct drm_i915_gem_object *obj,
126                                   struct drm_mode_fb_cmd2 *mode_cmd);
127 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
128 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
129 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
130 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
131                                          struct intel_link_m_n *m_n,
132                                          struct intel_link_m_n *m2_n2);
133 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
134 static void haswell_set_pipeconf(struct drm_crtc *crtc);
135 static void haswell_set_pipemisc(struct drm_crtc *crtc);
136 static void vlv_prepare_pll(struct intel_crtc *crtc,
137                             const struct intel_crtc_state *pipe_config);
138 static void chv_prepare_pll(struct intel_crtc *crtc,
139                             const struct intel_crtc_state *pipe_config);
140 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
141 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
142 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
143                                     struct intel_crtc_state *crtc_state);
144 static void skylake_pfit_enable(struct intel_crtc *crtc);
145 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
146 static void ironlake_pfit_enable(struct intel_crtc *crtc);
147 static void intel_modeset_setup_hw_state(struct drm_device *dev,
148                                          struct drm_modeset_acquire_ctx *ctx);
149 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
150
151 struct intel_limit {
152         struct {
153                 int min, max;
154         } dot, vco, n, m, m1, m2, p, p1;
155
156         struct {
157                 int dot_limit;
158                 int p2_slow, p2_fast;
159         } p2;
160 };
161
162 /* returns HPLL frequency in kHz */
163 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
164 {
165         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
166
167         /* Obtain SKU information */
168         mutex_lock(&dev_priv->sb_lock);
169         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
170                 CCK_FUSE_HPLL_FREQ_MASK;
171         mutex_unlock(&dev_priv->sb_lock);
172
173         return vco_freq[hpll_freq] * 1000;
174 }
175
176 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
177                       const char *name, u32 reg, int ref_freq)
178 {
179         u32 val;
180         int divider;
181
182         mutex_lock(&dev_priv->sb_lock);
183         val = vlv_cck_read(dev_priv, reg);
184         mutex_unlock(&dev_priv->sb_lock);
185
186         divider = val & CCK_FREQUENCY_VALUES;
187
188         WARN((val & CCK_FREQUENCY_STATUS) !=
189              (divider << CCK_FREQUENCY_STATUS_SHIFT),
190              "%s change in progress\n", name);
191
192         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
193 }
194
195 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
196                            const char *name, u32 reg)
197 {
198         if (dev_priv->hpll_freq == 0)
199                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
200
201         return vlv_get_cck_clock(dev_priv, name, reg,
202                                  dev_priv->hpll_freq);
203 }
204
205 static void intel_update_czclk(struct drm_i915_private *dev_priv)
206 {
207         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
208                 return;
209
210         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
211                                                       CCK_CZ_CLOCK_CONTROL);
212
213         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
214 }
215
216 static inline u32 /* units of 100MHz */
217 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
218                     const struct intel_crtc_state *pipe_config)
219 {
220         if (HAS_DDI(dev_priv))
221                 return pipe_config->port_clock; /* SPLL */
222         else if (IS_GEN5(dev_priv))
223                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
224         else
225                 return 270000;
226 }
227
228 static const struct intel_limit intel_limits_i8xx_dac = {
229         .dot = { .min = 25000, .max = 350000 },
230         .vco = { .min = 908000, .max = 1512000 },
231         .n = { .min = 2, .max = 16 },
232         .m = { .min = 96, .max = 140 },
233         .m1 = { .min = 18, .max = 26 },
234         .m2 = { .min = 6, .max = 16 },
235         .p = { .min = 4, .max = 128 },
236         .p1 = { .min = 2, .max = 33 },
237         .p2 = { .dot_limit = 165000,
238                 .p2_slow = 4, .p2_fast = 2 },
239 };
240
241 static const struct intel_limit intel_limits_i8xx_dvo = {
242         .dot = { .min = 25000, .max = 350000 },
243         .vco = { .min = 908000, .max = 1512000 },
244         .n = { .min = 2, .max = 16 },
245         .m = { .min = 96, .max = 140 },
246         .m1 = { .min = 18, .max = 26 },
247         .m2 = { .min = 6, .max = 16 },
248         .p = { .min = 4, .max = 128 },
249         .p1 = { .min = 2, .max = 33 },
250         .p2 = { .dot_limit = 165000,
251                 .p2_slow = 4, .p2_fast = 4 },
252 };
253
254 static const struct intel_limit intel_limits_i8xx_lvds = {
255         .dot = { .min = 25000, .max = 350000 },
256         .vco = { .min = 908000, .max = 1512000 },
257         .n = { .min = 2, .max = 16 },
258         .m = { .min = 96, .max = 140 },
259         .m1 = { .min = 18, .max = 26 },
260         .m2 = { .min = 6, .max = 16 },
261         .p = { .min = 4, .max = 128 },
262         .p1 = { .min = 1, .max = 6 },
263         .p2 = { .dot_limit = 165000,
264                 .p2_slow = 14, .p2_fast = 7 },
265 };
266
267 static const struct intel_limit intel_limits_i9xx_sdvo = {
268         .dot = { .min = 20000, .max = 400000 },
269         .vco = { .min = 1400000, .max = 2800000 },
270         .n = { .min = 1, .max = 6 },
271         .m = { .min = 70, .max = 120 },
272         .m1 = { .min = 8, .max = 18 },
273         .m2 = { .min = 3, .max = 7 },
274         .p = { .min = 5, .max = 80 },
275         .p1 = { .min = 1, .max = 8 },
276         .p2 = { .dot_limit = 200000,
277                 .p2_slow = 10, .p2_fast = 5 },
278 };
279
280 static const struct intel_limit intel_limits_i9xx_lvds = {
281         .dot = { .min = 20000, .max = 400000 },
282         .vco = { .min = 1400000, .max = 2800000 },
283         .n = { .min = 1, .max = 6 },
284         .m = { .min = 70, .max = 120 },
285         .m1 = { .min = 8, .max = 18 },
286         .m2 = { .min = 3, .max = 7 },
287         .p = { .min = 7, .max = 98 },
288         .p1 = { .min = 1, .max = 8 },
289         .p2 = { .dot_limit = 112000,
290                 .p2_slow = 14, .p2_fast = 7 },
291 };
292
293
294 static const struct intel_limit intel_limits_g4x_sdvo = {
295         .dot = { .min = 25000, .max = 270000 },
296         .vco = { .min = 1750000, .max = 3500000},
297         .n = { .min = 1, .max = 4 },
298         .m = { .min = 104, .max = 138 },
299         .m1 = { .min = 17, .max = 23 },
300         .m2 = { .min = 5, .max = 11 },
301         .p = { .min = 10, .max = 30 },
302         .p1 = { .min = 1, .max = 3},
303         .p2 = { .dot_limit = 270000,
304                 .p2_slow = 10,
305                 .p2_fast = 10
306         },
307 };
308
309 static const struct intel_limit intel_limits_g4x_hdmi = {
310         .dot = { .min = 22000, .max = 400000 },
311         .vco = { .min = 1750000, .max = 3500000},
312         .n = { .min = 1, .max = 4 },
313         .m = { .min = 104, .max = 138 },
314         .m1 = { .min = 16, .max = 23 },
315         .m2 = { .min = 5, .max = 11 },
316         .p = { .min = 5, .max = 80 },
317         .p1 = { .min = 1, .max = 8},
318         .p2 = { .dot_limit = 165000,
319                 .p2_slow = 10, .p2_fast = 5 },
320 };
321
322 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
323         .dot = { .min = 20000, .max = 115000 },
324         .vco = { .min = 1750000, .max = 3500000 },
325         .n = { .min = 1, .max = 3 },
326         .m = { .min = 104, .max = 138 },
327         .m1 = { .min = 17, .max = 23 },
328         .m2 = { .min = 5, .max = 11 },
329         .p = { .min = 28, .max = 112 },
330         .p1 = { .min = 2, .max = 8 },
331         .p2 = { .dot_limit = 0,
332                 .p2_slow = 14, .p2_fast = 14
333         },
334 };
335
336 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
337         .dot = { .min = 80000, .max = 224000 },
338         .vco = { .min = 1750000, .max = 3500000 },
339         .n = { .min = 1, .max = 3 },
340         .m = { .min = 104, .max = 138 },
341         .m1 = { .min = 17, .max = 23 },
342         .m2 = { .min = 5, .max = 11 },
343         .p = { .min = 14, .max = 42 },
344         .p1 = { .min = 2, .max = 6 },
345         .p2 = { .dot_limit = 0,
346                 .p2_slow = 7, .p2_fast = 7
347         },
348 };
349
350 static const struct intel_limit intel_limits_pineview_sdvo = {
351         .dot = { .min = 20000, .max = 400000},
352         .vco = { .min = 1700000, .max = 3500000 },
353         /* Pineview's Ncounter is a ring counter */
354         .n = { .min = 3, .max = 6 },
355         .m = { .min = 2, .max = 256 },
356         /* Pineview only has one combined m divider, which we treat as m2. */
357         .m1 = { .min = 0, .max = 0 },
358         .m2 = { .min = 0, .max = 254 },
359         .p = { .min = 5, .max = 80 },
360         .p1 = { .min = 1, .max = 8 },
361         .p2 = { .dot_limit = 200000,
362                 .p2_slow = 10, .p2_fast = 5 },
363 };
364
365 static const struct intel_limit intel_limits_pineview_lvds = {
366         .dot = { .min = 20000, .max = 400000 },
367         .vco = { .min = 1700000, .max = 3500000 },
368         .n = { .min = 3, .max = 6 },
369         .m = { .min = 2, .max = 256 },
370         .m1 = { .min = 0, .max = 0 },
371         .m2 = { .min = 0, .max = 254 },
372         .p = { .min = 7, .max = 112 },
373         .p1 = { .min = 1, .max = 8 },
374         .p2 = { .dot_limit = 112000,
375                 .p2_slow = 14, .p2_fast = 14 },
376 };
377
378 /* Ironlake / Sandybridge
379  *
380  * We calculate clock using (register_value + 2) for N/M1/M2, so here
381  * the range value for them is (actual_value - 2).
382  */
383 static const struct intel_limit intel_limits_ironlake_dac = {
384         .dot = { .min = 25000, .max = 350000 },
385         .vco = { .min = 1760000, .max = 3510000 },
386         .n = { .min = 1, .max = 5 },
387         .m = { .min = 79, .max = 127 },
388         .m1 = { .min = 12, .max = 22 },
389         .m2 = { .min = 5, .max = 9 },
390         .p = { .min = 5, .max = 80 },
391         .p1 = { .min = 1, .max = 8 },
392         .p2 = { .dot_limit = 225000,
393                 .p2_slow = 10, .p2_fast = 5 },
394 };
395
396 static const struct intel_limit intel_limits_ironlake_single_lvds = {
397         .dot = { .min = 25000, .max = 350000 },
398         .vco = { .min = 1760000, .max = 3510000 },
399         .n = { .min = 1, .max = 3 },
400         .m = { .min = 79, .max = 118 },
401         .m1 = { .min = 12, .max = 22 },
402         .m2 = { .min = 5, .max = 9 },
403         .p = { .min = 28, .max = 112 },
404         .p1 = { .min = 2, .max = 8 },
405         .p2 = { .dot_limit = 225000,
406                 .p2_slow = 14, .p2_fast = 14 },
407 };
408
409 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
410         .dot = { .min = 25000, .max = 350000 },
411         .vco = { .min = 1760000, .max = 3510000 },
412         .n = { .min = 1, .max = 3 },
413         .m = { .min = 79, .max = 127 },
414         .m1 = { .min = 12, .max = 22 },
415         .m2 = { .min = 5, .max = 9 },
416         .p = { .min = 14, .max = 56 },
417         .p1 = { .min = 2, .max = 8 },
418         .p2 = { .dot_limit = 225000,
419                 .p2_slow = 7, .p2_fast = 7 },
420 };
421
422 /* LVDS 100mhz refclk limits. */
423 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
424         .dot = { .min = 25000, .max = 350000 },
425         .vco = { .min = 1760000, .max = 3510000 },
426         .n = { .min = 1, .max = 2 },
427         .m = { .min = 79, .max = 126 },
428         .m1 = { .min = 12, .max = 22 },
429         .m2 = { .min = 5, .max = 9 },
430         .p = { .min = 28, .max = 112 },
431         .p1 = { .min = 2, .max = 8 },
432         .p2 = { .dot_limit = 225000,
433                 .p2_slow = 14, .p2_fast = 14 },
434 };
435
436 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
437         .dot = { .min = 25000, .max = 350000 },
438         .vco = { .min = 1760000, .max = 3510000 },
439         .n = { .min = 1, .max = 3 },
440         .m = { .min = 79, .max = 126 },
441         .m1 = { .min = 12, .max = 22 },
442         .m2 = { .min = 5, .max = 9 },
443         .p = { .min = 14, .max = 42 },
444         .p1 = { .min = 2, .max = 6 },
445         .p2 = { .dot_limit = 225000,
446                 .p2_slow = 7, .p2_fast = 7 },
447 };
448
449 static const struct intel_limit intel_limits_vlv = {
450          /*
451           * These are the data rate limits (measured in fast clocks)
452           * since those are the strictest limits we have. The fast
453           * clock and actual rate limits are more relaxed, so checking
454           * them would make no difference.
455           */
456         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
457         .vco = { .min = 4000000, .max = 6000000 },
458         .n = { .min = 1, .max = 7 },
459         .m1 = { .min = 2, .max = 3 },
460         .m2 = { .min = 11, .max = 156 },
461         .p1 = { .min = 2, .max = 3 },
462         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
463 };
464
465 static const struct intel_limit intel_limits_chv = {
466         /*
467          * These are the data rate limits (measured in fast clocks)
468          * since those are the strictest limits we have.  The fast
469          * clock and actual rate limits are more relaxed, so checking
470          * them would make no difference.
471          */
472         .dot = { .min = 25000 * 5, .max = 540000 * 5},
473         .vco = { .min = 4800000, .max = 6480000 },
474         .n = { .min = 1, .max = 1 },
475         .m1 = { .min = 2, .max = 2 },
476         .m2 = { .min = 24 << 22, .max = 175 << 22 },
477         .p1 = { .min = 2, .max = 4 },
478         .p2 = { .p2_slow = 1, .p2_fast = 14 },
479 };
480
481 static const struct intel_limit intel_limits_bxt = {
482         /* FIXME: find real dot limits */
483         .dot = { .min = 0, .max = INT_MAX },
484         .vco = { .min = 4800000, .max = 6700000 },
485         .n = { .min = 1, .max = 1 },
486         .m1 = { .min = 2, .max = 2 },
487         /* FIXME: find real m2 limits */
488         .m2 = { .min = 2 << 22, .max = 255 << 22 },
489         .p1 = { .min = 2, .max = 4 },
490         .p2 = { .p2_slow = 1, .p2_fast = 20 },
491 };
492
493 static bool
494 needs_modeset(struct drm_crtc_state *state)
495 {
496         return drm_atomic_crtc_needs_modeset(state);
497 }
498
499 /*
500  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
501  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
502  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
503  * The helpers' return value is the rate of the clock that is fed to the
504  * display engine's pipe which can be the above fast dot clock rate or a
505  * divided-down version of it.
506  */
507 /* m1 is reserved as 0 in Pineview, n is a ring counter */
508 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
509 {
510         clock->m = clock->m2 + 2;
511         clock->p = clock->p1 * clock->p2;
512         if (WARN_ON(clock->n == 0 || clock->p == 0))
513                 return 0;
514         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
515         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
516
517         return clock->dot;
518 }
519
520 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
521 {
522         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
523 }
524
525 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
526 {
527         clock->m = i9xx_dpll_compute_m(clock);
528         clock->p = clock->p1 * clock->p2;
529         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
530                 return 0;
531         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
532         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
533
534         return clock->dot;
535 }
536
537 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
538 {
539         clock->m = clock->m1 * clock->m2;
540         clock->p = clock->p1 * clock->p2;
541         if (WARN_ON(clock->n == 0 || clock->p == 0))
542                 return 0;
543         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
544         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
545
546         return clock->dot / 5;
547 }
548
549 int chv_calc_dpll_params(int refclk, struct dpll *clock)
550 {
551         clock->m = clock->m1 * clock->m2;
552         clock->p = clock->p1 * clock->p2;
553         if (WARN_ON(clock->n == 0 || clock->p == 0))
554                 return 0;
555         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
556                         clock->n << 22);
557         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
558
559         return clock->dot / 5;
560 }
561
562 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
563 /**
564  * Returns whether the given set of divisors are valid for a given refclk with
565  * the given connectors.
566  */
567
568 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
569                                const struct intel_limit *limit,
570                                const struct dpll *clock)
571 {
572         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
573                 INTELPllInvalid("n out of range\n");
574         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
575                 INTELPllInvalid("p1 out of range\n");
576         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
577                 INTELPllInvalid("m2 out of range\n");
578         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
579                 INTELPllInvalid("m1 out of range\n");
580
581         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
582             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
583                 if (clock->m1 <= clock->m2)
584                         INTELPllInvalid("m1 <= m2\n");
585
586         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
587             !IS_GEN9_LP(dev_priv)) {
588                 if (clock->p < limit->p.min || limit->p.max < clock->p)
589                         INTELPllInvalid("p out of range\n");
590                 if (clock->m < limit->m.min || limit->m.max < clock->m)
591                         INTELPllInvalid("m out of range\n");
592         }
593
594         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
595                 INTELPllInvalid("vco out of range\n");
596         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
597          * connector, etc., rather than just a single range.
598          */
599         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
600                 INTELPllInvalid("dot out of range\n");
601
602         return true;
603 }
604
605 static int
606 i9xx_select_p2_div(const struct intel_limit *limit,
607                    const struct intel_crtc_state *crtc_state,
608                    int target)
609 {
610         struct drm_device *dev = crtc_state->base.crtc->dev;
611
612         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
613                 /*
614                  * For LVDS just rely on its current settings for dual-channel.
615                  * We haven't figured out how to reliably set up different
616                  * single/dual channel state, if we even can.
617                  */
618                 if (intel_is_dual_link_lvds(dev))
619                         return limit->p2.p2_fast;
620                 else
621                         return limit->p2.p2_slow;
622         } else {
623                 if (target < limit->p2.dot_limit)
624                         return limit->p2.p2_slow;
625                 else
626                         return limit->p2.p2_fast;
627         }
628 }
629
630 /*
631  * Returns a set of divisors for the desired target clock with the given
632  * refclk, or FALSE.  The returned values represent the clock equation:
633  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
634  *
635  * Target and reference clocks are specified in kHz.
636  *
637  * If match_clock is provided, then best_clock P divider must match the P
638  * divider from @match_clock used for LVDS downclocking.
639  */
640 static bool
641 i9xx_find_best_dpll(const struct intel_limit *limit,
642                     struct intel_crtc_state *crtc_state,
643                     int target, int refclk, struct dpll *match_clock,
644                     struct dpll *best_clock)
645 {
646         struct drm_device *dev = crtc_state->base.crtc->dev;
647         struct dpll clock;
648         int err = target;
649
650         memset(best_clock, 0, sizeof(*best_clock));
651
652         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
653
654         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
655              clock.m1++) {
656                 for (clock.m2 = limit->m2.min;
657                      clock.m2 <= limit->m2.max; clock.m2++) {
658                         if (clock.m2 >= clock.m1)
659                                 break;
660                         for (clock.n = limit->n.min;
661                              clock.n <= limit->n.max; clock.n++) {
662                                 for (clock.p1 = limit->p1.min;
663                                         clock.p1 <= limit->p1.max; clock.p1++) {
664                                         int this_err;
665
666                                         i9xx_calc_dpll_params(refclk, &clock);
667                                         if (!intel_PLL_is_valid(to_i915(dev),
668                                                                 limit,
669                                                                 &clock))
670                                                 continue;
671                                         if (match_clock &&
672                                             clock.p != match_clock->p)
673                                                 continue;
674
675                                         this_err = abs(clock.dot - target);
676                                         if (this_err < err) {
677                                                 *best_clock = clock;
678                                                 err = this_err;
679                                         }
680                                 }
681                         }
682                 }
683         }
684
685         return (err != target);
686 }
687
688 /*
689  * Returns a set of divisors for the desired target clock with the given
690  * refclk, or FALSE.  The returned values represent the clock equation:
691  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
692  *
693  * Target and reference clocks are specified in kHz.
694  *
695  * If match_clock is provided, then best_clock P divider must match the P
696  * divider from @match_clock used for LVDS downclocking.
697  */
698 static bool
699 pnv_find_best_dpll(const struct intel_limit *limit,
700                    struct intel_crtc_state *crtc_state,
701                    int target, int refclk, struct dpll *match_clock,
702                    struct dpll *best_clock)
703 {
704         struct drm_device *dev = crtc_state->base.crtc->dev;
705         struct dpll clock;
706         int err = target;
707
708         memset(best_clock, 0, sizeof(*best_clock));
709
710         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
711
712         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
713              clock.m1++) {
714                 for (clock.m2 = limit->m2.min;
715                      clock.m2 <= limit->m2.max; clock.m2++) {
716                         for (clock.n = limit->n.min;
717                              clock.n <= limit->n.max; clock.n++) {
718                                 for (clock.p1 = limit->p1.min;
719                                         clock.p1 <= limit->p1.max; clock.p1++) {
720                                         int this_err;
721
722                                         pnv_calc_dpll_params(refclk, &clock);
723                                         if (!intel_PLL_is_valid(to_i915(dev),
724                                                                 limit,
725                                                                 &clock))
726                                                 continue;
727                                         if (match_clock &&
728                                             clock.p != match_clock->p)
729                                                 continue;
730
731                                         this_err = abs(clock.dot - target);
732                                         if (this_err < err) {
733                                                 *best_clock = clock;
734                                                 err = this_err;
735                                         }
736                                 }
737                         }
738                 }
739         }
740
741         return (err != target);
742 }
743
744 /*
745  * Returns a set of divisors for the desired target clock with the given
746  * refclk, or FALSE.  The returned values represent the clock equation:
747  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
748  *
749  * Target and reference clocks are specified in kHz.
750  *
751  * If match_clock is provided, then best_clock P divider must match the P
752  * divider from @match_clock used for LVDS downclocking.
753  */
754 static bool
755 g4x_find_best_dpll(const struct intel_limit *limit,
756                    struct intel_crtc_state *crtc_state,
757                    int target, int refclk, struct dpll *match_clock,
758                    struct dpll *best_clock)
759 {
760         struct drm_device *dev = crtc_state->base.crtc->dev;
761         struct dpll clock;
762         int max_n;
763         bool found = false;
764         /* approximately equals target * 0.00585 */
765         int err_most = (target >> 8) + (target >> 9);
766
767         memset(best_clock, 0, sizeof(*best_clock));
768
769         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
770
771         max_n = limit->n.max;
772         /* based on hardware requirement, prefer smaller n to precision */
773         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
774                 /* based on hardware requirement, prefere larger m1,m2 */
775                 for (clock.m1 = limit->m1.max;
776                      clock.m1 >= limit->m1.min; clock.m1--) {
777                         for (clock.m2 = limit->m2.max;
778                              clock.m2 >= limit->m2.min; clock.m2--) {
779                                 for (clock.p1 = limit->p1.max;
780                                      clock.p1 >= limit->p1.min; clock.p1--) {
781                                         int this_err;
782
783                                         i9xx_calc_dpll_params(refclk, &clock);
784                                         if (!intel_PLL_is_valid(to_i915(dev),
785                                                                 limit,
786                                                                 &clock))
787                                                 continue;
788
789                                         this_err = abs(clock.dot - target);
790                                         if (this_err < err_most) {
791                                                 *best_clock = clock;
792                                                 err_most = this_err;
793                                                 max_n = clock.n;
794                                                 found = true;
795                                         }
796                                 }
797                         }
798                 }
799         }
800         return found;
801 }
802
803 /*
804  * Check if the calculated PLL configuration is more optimal compared to the
805  * best configuration and error found so far. Return the calculated error.
806  */
807 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
808                                const struct dpll *calculated_clock,
809                                const struct dpll *best_clock,
810                                unsigned int best_error_ppm,
811                                unsigned int *error_ppm)
812 {
813         /*
814          * For CHV ignore the error and consider only the P value.
815          * Prefer a bigger P value based on HW requirements.
816          */
817         if (IS_CHERRYVIEW(to_i915(dev))) {
818                 *error_ppm = 0;
819
820                 return calculated_clock->p > best_clock->p;
821         }
822
823         if (WARN_ON_ONCE(!target_freq))
824                 return false;
825
826         *error_ppm = div_u64(1000000ULL *
827                                 abs(target_freq - calculated_clock->dot),
828                              target_freq);
829         /*
830          * Prefer a better P value over a better (smaller) error if the error
831          * is small. Ensure this preference for future configurations too by
832          * setting the error to 0.
833          */
834         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
835                 *error_ppm = 0;
836
837                 return true;
838         }
839
840         return *error_ppm + 10 < best_error_ppm;
841 }
842
843 /*
844  * Returns a set of divisors for the desired target clock with the given
845  * refclk, or FALSE.  The returned values represent the clock equation:
846  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
847  */
848 static bool
849 vlv_find_best_dpll(const struct intel_limit *limit,
850                    struct intel_crtc_state *crtc_state,
851                    int target, int refclk, struct dpll *match_clock,
852                    struct dpll *best_clock)
853 {
854         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
855         struct drm_device *dev = crtc->base.dev;
856         struct dpll clock;
857         unsigned int bestppm = 1000000;
858         /* min update 19.2 MHz */
859         int max_n = min(limit->n.max, refclk / 19200);
860         bool found = false;
861
862         target *= 5; /* fast clock */
863
864         memset(best_clock, 0, sizeof(*best_clock));
865
866         /* based on hardware requirement, prefer smaller n to precision */
867         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
868                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
869                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
870                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
871                                 clock.p = clock.p1 * clock.p2;
872                                 /* based on hardware requirement, prefer bigger m1,m2 values */
873                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
874                                         unsigned int ppm;
875
876                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
877                                                                      refclk * clock.m1);
878
879                                         vlv_calc_dpll_params(refclk, &clock);
880
881                                         if (!intel_PLL_is_valid(to_i915(dev),
882                                                                 limit,
883                                                                 &clock))
884                                                 continue;
885
886                                         if (!vlv_PLL_is_optimal(dev, target,
887                                                                 &clock,
888                                                                 best_clock,
889                                                                 bestppm, &ppm))
890                                                 continue;
891
892                                         *best_clock = clock;
893                                         bestppm = ppm;
894                                         found = true;
895                                 }
896                         }
897                 }
898         }
899
900         return found;
901 }
902
903 /*
904  * Returns a set of divisors for the desired target clock with the given
905  * refclk, or FALSE.  The returned values represent the clock equation:
906  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
907  */
908 static bool
909 chv_find_best_dpll(const struct intel_limit *limit,
910                    struct intel_crtc_state *crtc_state,
911                    int target, int refclk, struct dpll *match_clock,
912                    struct dpll *best_clock)
913 {
914         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
915         struct drm_device *dev = crtc->base.dev;
916         unsigned int best_error_ppm;
917         struct dpll clock;
918         uint64_t m2;
919         int found = false;
920
921         memset(best_clock, 0, sizeof(*best_clock));
922         best_error_ppm = 1000000;
923
924         /*
925          * Based on hardware doc, the n always set to 1, and m1 always
926          * set to 2.  If requires to support 200Mhz refclk, we need to
927          * revisit this because n may not 1 anymore.
928          */
929         clock.n = 1, clock.m1 = 2;
930         target *= 5;    /* fast clock */
931
932         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
933                 for (clock.p2 = limit->p2.p2_fast;
934                                 clock.p2 >= limit->p2.p2_slow;
935                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
936                         unsigned int error_ppm;
937
938                         clock.p = clock.p1 * clock.p2;
939
940                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
941                                         clock.n) << 22, refclk * clock.m1);
942
943                         if (m2 > INT_MAX/clock.m1)
944                                 continue;
945
946                         clock.m2 = m2;
947
948                         chv_calc_dpll_params(refclk, &clock);
949
950                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
951                                 continue;
952
953                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
954                                                 best_error_ppm, &error_ppm))
955                                 continue;
956
957                         *best_clock = clock;
958                         best_error_ppm = error_ppm;
959                         found = true;
960                 }
961         }
962
963         return found;
964 }
965
966 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
967                         struct dpll *best_clock)
968 {
969         int refclk = 100000;
970         const struct intel_limit *limit = &intel_limits_bxt;
971
972         return chv_find_best_dpll(limit, crtc_state,
973                                   target_clock, refclk, NULL, best_clock);
974 }
975
976 bool intel_crtc_active(struct intel_crtc *crtc)
977 {
978         /* Be paranoid as we can arrive here with only partial
979          * state retrieved from the hardware during setup.
980          *
981          * We can ditch the adjusted_mode.crtc_clock check as soon
982          * as Haswell has gained clock readout/fastboot support.
983          *
984          * We can ditch the crtc->primary->fb check as soon as we can
985          * properly reconstruct framebuffers.
986          *
987          * FIXME: The intel_crtc->active here should be switched to
988          * crtc->state->active once we have proper CRTC states wired up
989          * for atomic.
990          */
991         return crtc->active && crtc->base.primary->state->fb &&
992                 crtc->config->base.adjusted_mode.crtc_clock;
993 }
994
995 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
996                                              enum pipe pipe)
997 {
998         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
999
1000         return crtc->config->cpu_transcoder;
1001 }
1002
1003 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
1004 {
1005         i915_reg_t reg = PIPEDSL(pipe);
1006         u32 line1, line2;
1007         u32 line_mask;
1008
1009         if (IS_GEN2(dev_priv))
1010                 line_mask = DSL_LINEMASK_GEN2;
1011         else
1012                 line_mask = DSL_LINEMASK_GEN3;
1013
1014         line1 = I915_READ(reg) & line_mask;
1015         msleep(5);
1016         line2 = I915_READ(reg) & line_mask;
1017
1018         return line1 == line2;
1019 }
1020
1021 /*
1022  * intel_wait_for_pipe_off - wait for pipe to turn off
1023  * @crtc: crtc whose pipe to wait for
1024  *
1025  * After disabling a pipe, we can't wait for vblank in the usual way,
1026  * spinning on the vblank interrupt status bit, since we won't actually
1027  * see an interrupt when the pipe is disabled.
1028  *
1029  * On Gen4 and above:
1030  *   wait for the pipe register state bit to turn off
1031  *
1032  * Otherwise:
1033  *   wait for the display line value to settle (it usually
1034  *   ends up stopping at the start of the next frame).
1035  *
1036  */
1037 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1038 {
1039         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1040         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1041         enum pipe pipe = crtc->pipe;
1042
1043         if (INTEL_GEN(dev_priv) >= 4) {
1044                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1045
1046                 /* Wait for the Pipe State to go off */
1047                 if (intel_wait_for_register(dev_priv,
1048                                             reg, I965_PIPECONF_ACTIVE, 0,
1049                                             100))
1050                         WARN(1, "pipe_off wait timed out\n");
1051         } else {
1052                 /* Wait for the display line to settle */
1053                 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1054                         WARN(1, "pipe_off wait timed out\n");
1055         }
1056 }
1057
1058 /* Only for pre-ILK configs */
1059 void assert_pll(struct drm_i915_private *dev_priv,
1060                 enum pipe pipe, bool state)
1061 {
1062         u32 val;
1063         bool cur_state;
1064
1065         val = I915_READ(DPLL(pipe));
1066         cur_state = !!(val & DPLL_VCO_ENABLE);
1067         I915_STATE_WARN(cur_state != state,
1068              "PLL state assertion failure (expected %s, current %s)\n",
1069                         onoff(state), onoff(cur_state));
1070 }
1071
1072 /* XXX: the dsi pll is shared between MIPI DSI ports */
1073 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1074 {
1075         u32 val;
1076         bool cur_state;
1077
1078         mutex_lock(&dev_priv->sb_lock);
1079         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1080         mutex_unlock(&dev_priv->sb_lock);
1081
1082         cur_state = val & DSI_PLL_VCO_EN;
1083         I915_STATE_WARN(cur_state != state,
1084              "DSI PLL state assertion failure (expected %s, current %s)\n",
1085                         onoff(state), onoff(cur_state));
1086 }
1087
1088 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1089                           enum pipe pipe, bool state)
1090 {
1091         bool cur_state;
1092         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1093                                                                       pipe);
1094
1095         if (HAS_DDI(dev_priv)) {
1096                 /* DDI does not have a specific FDI_TX register */
1097                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1098                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1099         } else {
1100                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1101                 cur_state = !!(val & FDI_TX_ENABLE);
1102         }
1103         I915_STATE_WARN(cur_state != state,
1104              "FDI TX state assertion failure (expected %s, current %s)\n",
1105                         onoff(state), onoff(cur_state));
1106 }
1107 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1108 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1109
1110 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1111                           enum pipe pipe, bool state)
1112 {
1113         u32 val;
1114         bool cur_state;
1115
1116         val = I915_READ(FDI_RX_CTL(pipe));
1117         cur_state = !!(val & FDI_RX_ENABLE);
1118         I915_STATE_WARN(cur_state != state,
1119              "FDI RX state assertion failure (expected %s, current %s)\n",
1120                         onoff(state), onoff(cur_state));
1121 }
1122 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1123 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1124
1125 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1126                                       enum pipe pipe)
1127 {
1128         u32 val;
1129
1130         /* ILK FDI PLL is always enabled */
1131         if (IS_GEN5(dev_priv))
1132                 return;
1133
1134         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1135         if (HAS_DDI(dev_priv))
1136                 return;
1137
1138         val = I915_READ(FDI_TX_CTL(pipe));
1139         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1140 }
1141
1142 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1143                        enum pipe pipe, bool state)
1144 {
1145         u32 val;
1146         bool cur_state;
1147
1148         val = I915_READ(FDI_RX_CTL(pipe));
1149         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1150         I915_STATE_WARN(cur_state != state,
1151              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1152                         onoff(state), onoff(cur_state));
1153 }
1154
1155 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1156 {
1157         i915_reg_t pp_reg;
1158         u32 val;
1159         enum pipe panel_pipe = PIPE_A;
1160         bool locked = true;
1161
1162         if (WARN_ON(HAS_DDI(dev_priv)))
1163                 return;
1164
1165         if (HAS_PCH_SPLIT(dev_priv)) {
1166                 u32 port_sel;
1167
1168                 pp_reg = PP_CONTROL(0);
1169                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1170
1171                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1172                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1173                         panel_pipe = PIPE_B;
1174                 /* XXX: else fix for eDP */
1175         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1176                 /* presumably write lock depends on pipe, not port select */
1177                 pp_reg = PP_CONTROL(pipe);
1178                 panel_pipe = pipe;
1179         } else {
1180                 pp_reg = PP_CONTROL(0);
1181                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1182                         panel_pipe = PIPE_B;
1183         }
1184
1185         val = I915_READ(pp_reg);
1186         if (!(val & PANEL_POWER_ON) ||
1187             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1188                 locked = false;
1189
1190         I915_STATE_WARN(panel_pipe == pipe && locked,
1191              "panel assertion failure, pipe %c regs locked\n",
1192              pipe_name(pipe));
1193 }
1194
1195 static void assert_cursor(struct drm_i915_private *dev_priv,
1196                           enum pipe pipe, bool state)
1197 {
1198         bool cur_state;
1199
1200         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1201                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1202         else
1203                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1204
1205         I915_STATE_WARN(cur_state != state,
1206              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1207                         pipe_name(pipe), onoff(state), onoff(cur_state));
1208 }
1209 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1210 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1211
1212 void assert_pipe(struct drm_i915_private *dev_priv,
1213                  enum pipe pipe, bool state)
1214 {
1215         bool cur_state;
1216         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1217                                                                       pipe);
1218         enum intel_display_power_domain power_domain;
1219
1220         /* we keep both pipes enabled on 830 */
1221         if (IS_I830(dev_priv))
1222                 state = true;
1223
1224         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1225         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1226                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1227                 cur_state = !!(val & PIPECONF_ENABLE);
1228
1229                 intel_display_power_put(dev_priv, power_domain);
1230         } else {
1231                 cur_state = false;
1232         }
1233
1234         I915_STATE_WARN(cur_state != state,
1235              "pipe %c assertion failure (expected %s, current %s)\n",
1236                         pipe_name(pipe), onoff(state), onoff(cur_state));
1237 }
1238
1239 static void assert_plane(struct drm_i915_private *dev_priv,
1240                          enum plane plane, bool state)
1241 {
1242         u32 val;
1243         bool cur_state;
1244
1245         val = I915_READ(DSPCNTR(plane));
1246         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1247         I915_STATE_WARN(cur_state != state,
1248              "plane %c assertion failure (expected %s, current %s)\n",
1249                         plane_name(plane), onoff(state), onoff(cur_state));
1250 }
1251
1252 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1253 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1254
1255 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1256                                    enum pipe pipe)
1257 {
1258         int i;
1259
1260         /* Primary planes are fixed to pipes on gen4+ */
1261         if (INTEL_GEN(dev_priv) >= 4) {
1262                 u32 val = I915_READ(DSPCNTR(pipe));
1263                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1264                      "plane %c assertion failure, should be disabled but not\n",
1265                      plane_name(pipe));
1266                 return;
1267         }
1268
1269         /* Need to check both planes against the pipe */
1270         for_each_pipe(dev_priv, i) {
1271                 u32 val = I915_READ(DSPCNTR(i));
1272                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1273                         DISPPLANE_SEL_PIPE_SHIFT;
1274                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1275                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1276                      plane_name(i), pipe_name(pipe));
1277         }
1278 }
1279
1280 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1281                                     enum pipe pipe)
1282 {
1283         int sprite;
1284
1285         if (INTEL_GEN(dev_priv) >= 9) {
1286                 for_each_sprite(dev_priv, pipe, sprite) {
1287                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1288                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1289                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1290                              sprite, pipe_name(pipe));
1291                 }
1292         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1293                 for_each_sprite(dev_priv, pipe, sprite) {
1294                         u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
1295                         I915_STATE_WARN(val & SP_ENABLE,
1296                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1297                              sprite_name(pipe, sprite), pipe_name(pipe));
1298                 }
1299         } else if (INTEL_GEN(dev_priv) >= 7) {
1300                 u32 val = I915_READ(SPRCTL(pipe));
1301                 I915_STATE_WARN(val & SPRITE_ENABLE,
1302                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1303                      plane_name(pipe), pipe_name(pipe));
1304         } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
1305                 u32 val = I915_READ(DVSCNTR(pipe));
1306                 I915_STATE_WARN(val & DVS_ENABLE,
1307                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1308                      plane_name(pipe), pipe_name(pipe));
1309         }
1310 }
1311
1312 static void assert_vblank_disabled(struct drm_crtc *crtc)
1313 {
1314         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1315                 drm_crtc_vblank_put(crtc);
1316 }
1317
1318 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1319                                     enum pipe pipe)
1320 {
1321         u32 val;
1322         bool enabled;
1323
1324         val = I915_READ(PCH_TRANSCONF(pipe));
1325         enabled = !!(val & TRANS_ENABLE);
1326         I915_STATE_WARN(enabled,
1327              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1328              pipe_name(pipe));
1329 }
1330
1331 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1332                             enum pipe pipe, u32 port_sel, u32 val)
1333 {
1334         if ((val & DP_PORT_EN) == 0)
1335                 return false;
1336
1337         if (HAS_PCH_CPT(dev_priv)) {
1338                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1339                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1340                         return false;
1341         } else if (IS_CHERRYVIEW(dev_priv)) {
1342                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1343                         return false;
1344         } else {
1345                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1346                         return false;
1347         }
1348         return true;
1349 }
1350
1351 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1352                               enum pipe pipe, u32 val)
1353 {
1354         if ((val & SDVO_ENABLE) == 0)
1355                 return false;
1356
1357         if (HAS_PCH_CPT(dev_priv)) {
1358                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1359                         return false;
1360         } else if (IS_CHERRYVIEW(dev_priv)) {
1361                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1362                         return false;
1363         } else {
1364                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1365                         return false;
1366         }
1367         return true;
1368 }
1369
1370 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1371                               enum pipe pipe, u32 val)
1372 {
1373         if ((val & LVDS_PORT_EN) == 0)
1374                 return false;
1375
1376         if (HAS_PCH_CPT(dev_priv)) {
1377                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1378                         return false;
1379         } else {
1380                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1381                         return false;
1382         }
1383         return true;
1384 }
1385
1386 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1387                               enum pipe pipe, u32 val)
1388 {
1389         if ((val & ADPA_DAC_ENABLE) == 0)
1390                 return false;
1391         if (HAS_PCH_CPT(dev_priv)) {
1392                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1393                         return false;
1394         } else {
1395                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1396                         return false;
1397         }
1398         return true;
1399 }
1400
1401 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1402                                    enum pipe pipe, i915_reg_t reg,
1403                                    u32 port_sel)
1404 {
1405         u32 val = I915_READ(reg);
1406         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1407              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1408              i915_mmio_reg_offset(reg), pipe_name(pipe));
1409
1410         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1411              && (val & DP_PIPEB_SELECT),
1412              "IBX PCH dp port still using transcoder B\n");
1413 }
1414
1415 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1416                                      enum pipe pipe, i915_reg_t reg)
1417 {
1418         u32 val = I915_READ(reg);
1419         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1420              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1421              i915_mmio_reg_offset(reg), pipe_name(pipe));
1422
1423         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1424              && (val & SDVO_PIPE_B_SELECT),
1425              "IBX PCH hdmi port still using transcoder B\n");
1426 }
1427
1428 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1429                                       enum pipe pipe)
1430 {
1431         u32 val;
1432
1433         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1434         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1435         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1436
1437         val = I915_READ(PCH_ADPA);
1438         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1439              "PCH VGA enabled on transcoder %c, should be disabled\n",
1440              pipe_name(pipe));
1441
1442         val = I915_READ(PCH_LVDS);
1443         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1444              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1445              pipe_name(pipe));
1446
1447         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1448         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1449         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1450 }
1451
1452 static void _vlv_enable_pll(struct intel_crtc *crtc,
1453                             const struct intel_crtc_state *pipe_config)
1454 {
1455         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1456         enum pipe pipe = crtc->pipe;
1457
1458         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1459         POSTING_READ(DPLL(pipe));
1460         udelay(150);
1461
1462         if (intel_wait_for_register(dev_priv,
1463                                     DPLL(pipe),
1464                                     DPLL_LOCK_VLV,
1465                                     DPLL_LOCK_VLV,
1466                                     1))
1467                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1468 }
1469
1470 static void vlv_enable_pll(struct intel_crtc *crtc,
1471                            const struct intel_crtc_state *pipe_config)
1472 {
1473         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1474         enum pipe pipe = crtc->pipe;
1475
1476         assert_pipe_disabled(dev_priv, pipe);
1477
1478         /* PLL is protected by panel, make sure we can write it */
1479         assert_panel_unlocked(dev_priv, pipe);
1480
1481         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1482                 _vlv_enable_pll(crtc, pipe_config);
1483
1484         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1485         POSTING_READ(DPLL_MD(pipe));
1486 }
1487
1488
1489 static void _chv_enable_pll(struct intel_crtc *crtc,
1490                             const struct intel_crtc_state *pipe_config)
1491 {
1492         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1493         enum pipe pipe = crtc->pipe;
1494         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1495         u32 tmp;
1496
1497         mutex_lock(&dev_priv->sb_lock);
1498
1499         /* Enable back the 10bit clock to display controller */
1500         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1501         tmp |= DPIO_DCLKP_EN;
1502         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1503
1504         mutex_unlock(&dev_priv->sb_lock);
1505
1506         /*
1507          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1508          */
1509         udelay(1);
1510
1511         /* Enable PLL */
1512         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1513
1514         /* Check PLL is locked */
1515         if (intel_wait_for_register(dev_priv,
1516                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1517                                     1))
1518                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1519 }
1520
1521 static void chv_enable_pll(struct intel_crtc *crtc,
1522                            const struct intel_crtc_state *pipe_config)
1523 {
1524         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1525         enum pipe pipe = crtc->pipe;
1526
1527         assert_pipe_disabled(dev_priv, pipe);
1528
1529         /* PLL is protected by panel, make sure we can write it */
1530         assert_panel_unlocked(dev_priv, pipe);
1531
1532         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1533                 _chv_enable_pll(crtc, pipe_config);
1534
1535         if (pipe != PIPE_A) {
1536                 /*
1537                  * WaPixelRepeatModeFixForC0:chv
1538                  *
1539                  * DPLLCMD is AWOL. Use chicken bits to propagate
1540                  * the value from DPLLBMD to either pipe B or C.
1541                  */
1542                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1543                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1544                 I915_WRITE(CBR4_VLV, 0);
1545                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1546
1547                 /*
1548                  * DPLLB VGA mode also seems to cause problems.
1549                  * We should always have it disabled.
1550                  */
1551                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1552         } else {
1553                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1554                 POSTING_READ(DPLL_MD(pipe));
1555         }
1556 }
1557
1558 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1559 {
1560         struct intel_crtc *crtc;
1561         int count = 0;
1562
1563         for_each_intel_crtc(&dev_priv->drm, crtc) {
1564                 count += crtc->base.state->active &&
1565                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1566         }
1567
1568         return count;
1569 }
1570
1571 static void i9xx_enable_pll(struct intel_crtc *crtc)
1572 {
1573         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1574         i915_reg_t reg = DPLL(crtc->pipe);
1575         u32 dpll = crtc->config->dpll_hw_state.dpll;
1576         int i;
1577
1578         assert_pipe_disabled(dev_priv, crtc->pipe);
1579
1580         /* PLL is protected by panel, make sure we can write it */
1581         if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1582                 assert_panel_unlocked(dev_priv, crtc->pipe);
1583
1584         /* Enable DVO 2x clock on both PLLs if necessary */
1585         if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1586                 /*
1587                  * It appears to be important that we don't enable this
1588                  * for the current pipe before otherwise configuring the
1589                  * PLL. No idea how this should be handled if multiple
1590                  * DVO outputs are enabled simultaneosly.
1591                  */
1592                 dpll |= DPLL_DVO_2X_MODE;
1593                 I915_WRITE(DPLL(!crtc->pipe),
1594                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1595         }
1596
1597         /*
1598          * Apparently we need to have VGA mode enabled prior to changing
1599          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1600          * dividers, even though the register value does change.
1601          */
1602         I915_WRITE(reg, 0);
1603
1604         I915_WRITE(reg, dpll);
1605
1606         /* Wait for the clocks to stabilize. */
1607         POSTING_READ(reg);
1608         udelay(150);
1609
1610         if (INTEL_GEN(dev_priv) >= 4) {
1611                 I915_WRITE(DPLL_MD(crtc->pipe),
1612                            crtc->config->dpll_hw_state.dpll_md);
1613         } else {
1614                 /* The pixel multiplier can only be updated once the
1615                  * DPLL is enabled and the clocks are stable.
1616                  *
1617                  * So write it again.
1618                  */
1619                 I915_WRITE(reg, dpll);
1620         }
1621
1622         /* We do this three times for luck */
1623         for (i = 0; i < 3; i++) {
1624                 I915_WRITE(reg, dpll);
1625                 POSTING_READ(reg);
1626                 udelay(150); /* wait for warmup */
1627         }
1628 }
1629
1630 /**
1631  * i9xx_disable_pll - disable a PLL
1632  * @dev_priv: i915 private structure
1633  * @pipe: pipe PLL to disable
1634  *
1635  * Disable the PLL for @pipe, making sure the pipe is off first.
1636  *
1637  * Note!  This is for pre-ILK only.
1638  */
1639 static void i9xx_disable_pll(struct intel_crtc *crtc)
1640 {
1641         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1642         enum pipe pipe = crtc->pipe;
1643
1644         /* Disable DVO 2x clock on both PLLs if necessary */
1645         if (IS_I830(dev_priv) &&
1646             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1647             !intel_num_dvo_pipes(dev_priv)) {
1648                 I915_WRITE(DPLL(PIPE_B),
1649                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1650                 I915_WRITE(DPLL(PIPE_A),
1651                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1652         }
1653
1654         /* Don't disable pipe or pipe PLLs if needed */
1655         if (IS_I830(dev_priv))
1656                 return;
1657
1658         /* Make sure the pipe isn't still relying on us */
1659         assert_pipe_disabled(dev_priv, pipe);
1660
1661         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1662         POSTING_READ(DPLL(pipe));
1663 }
1664
1665 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1666 {
1667         u32 val;
1668
1669         /* Make sure the pipe isn't still relying on us */
1670         assert_pipe_disabled(dev_priv, pipe);
1671
1672         val = DPLL_INTEGRATED_REF_CLK_VLV |
1673                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1674         if (pipe != PIPE_A)
1675                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1676
1677         I915_WRITE(DPLL(pipe), val);
1678         POSTING_READ(DPLL(pipe));
1679 }
1680
1681 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1682 {
1683         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1684         u32 val;
1685
1686         /* Make sure the pipe isn't still relying on us */
1687         assert_pipe_disabled(dev_priv, pipe);
1688
1689         val = DPLL_SSC_REF_CLK_CHV |
1690                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1691         if (pipe != PIPE_A)
1692                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1693
1694         I915_WRITE(DPLL(pipe), val);
1695         POSTING_READ(DPLL(pipe));
1696
1697         mutex_lock(&dev_priv->sb_lock);
1698
1699         /* Disable 10bit clock to display controller */
1700         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1701         val &= ~DPIO_DCLKP_EN;
1702         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1703
1704         mutex_unlock(&dev_priv->sb_lock);
1705 }
1706
1707 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1708                          struct intel_digital_port *dport,
1709                          unsigned int expected_mask)
1710 {
1711         u32 port_mask;
1712         i915_reg_t dpll_reg;
1713
1714         switch (dport->port) {
1715         case PORT_B:
1716                 port_mask = DPLL_PORTB_READY_MASK;
1717                 dpll_reg = DPLL(0);
1718                 break;
1719         case PORT_C:
1720                 port_mask = DPLL_PORTC_READY_MASK;
1721                 dpll_reg = DPLL(0);
1722                 expected_mask <<= 4;
1723                 break;
1724         case PORT_D:
1725                 port_mask = DPLL_PORTD_READY_MASK;
1726                 dpll_reg = DPIO_PHY_STATUS;
1727                 break;
1728         default:
1729                 BUG();
1730         }
1731
1732         if (intel_wait_for_register(dev_priv,
1733                                     dpll_reg, port_mask, expected_mask,
1734                                     1000))
1735                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1736                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1737 }
1738
1739 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1740                                            enum pipe pipe)
1741 {
1742         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1743                                                                 pipe);
1744         i915_reg_t reg;
1745         uint32_t val, pipeconf_val;
1746
1747         /* Make sure PCH DPLL is enabled */
1748         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1749
1750         /* FDI must be feeding us bits for PCH ports */
1751         assert_fdi_tx_enabled(dev_priv, pipe);
1752         assert_fdi_rx_enabled(dev_priv, pipe);
1753
1754         if (HAS_PCH_CPT(dev_priv)) {
1755                 /* Workaround: Set the timing override bit before enabling the
1756                  * pch transcoder. */
1757                 reg = TRANS_CHICKEN2(pipe);
1758                 val = I915_READ(reg);
1759                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1760                 I915_WRITE(reg, val);
1761         }
1762
1763         reg = PCH_TRANSCONF(pipe);
1764         val = I915_READ(reg);
1765         pipeconf_val = I915_READ(PIPECONF(pipe));
1766
1767         if (HAS_PCH_IBX(dev_priv)) {
1768                 /*
1769                  * Make the BPC in transcoder be consistent with
1770                  * that in pipeconf reg. For HDMI we must use 8bpc
1771                  * here for both 8bpc and 12bpc.
1772                  */
1773                 val &= ~PIPECONF_BPC_MASK;
1774                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1775                         val |= PIPECONF_8BPC;
1776                 else
1777                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1778         }
1779
1780         val &= ~TRANS_INTERLACE_MASK;
1781         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1782                 if (HAS_PCH_IBX(dev_priv) &&
1783                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1784                         val |= TRANS_LEGACY_INTERLACED_ILK;
1785                 else
1786                         val |= TRANS_INTERLACED;
1787         else
1788                 val |= TRANS_PROGRESSIVE;
1789
1790         I915_WRITE(reg, val | TRANS_ENABLE);
1791         if (intel_wait_for_register(dev_priv,
1792                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1793                                     100))
1794                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1795 }
1796
1797 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1798                                       enum transcoder cpu_transcoder)
1799 {
1800         u32 val, pipeconf_val;
1801
1802         /* FDI must be feeding us bits for PCH ports */
1803         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1804         assert_fdi_rx_enabled(dev_priv, PIPE_A);
1805
1806         /* Workaround: set timing override bit. */
1807         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1808         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1809         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1810
1811         val = TRANS_ENABLE;
1812         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1813
1814         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1815             PIPECONF_INTERLACED_ILK)
1816                 val |= TRANS_INTERLACED;
1817         else
1818                 val |= TRANS_PROGRESSIVE;
1819
1820         I915_WRITE(LPT_TRANSCONF, val);
1821         if (intel_wait_for_register(dev_priv,
1822                                     LPT_TRANSCONF,
1823                                     TRANS_STATE_ENABLE,
1824                                     TRANS_STATE_ENABLE,
1825                                     100))
1826                 DRM_ERROR("Failed to enable PCH transcoder\n");
1827 }
1828
1829 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1830                                             enum pipe pipe)
1831 {
1832         i915_reg_t reg;
1833         uint32_t val;
1834
1835         /* FDI relies on the transcoder */
1836         assert_fdi_tx_disabled(dev_priv, pipe);
1837         assert_fdi_rx_disabled(dev_priv, pipe);
1838
1839         /* Ports must be off as well */
1840         assert_pch_ports_disabled(dev_priv, pipe);
1841
1842         reg = PCH_TRANSCONF(pipe);
1843         val = I915_READ(reg);
1844         val &= ~TRANS_ENABLE;
1845         I915_WRITE(reg, val);
1846         /* wait for PCH transcoder off, transcoder state */
1847         if (intel_wait_for_register(dev_priv,
1848                                     reg, TRANS_STATE_ENABLE, 0,
1849                                     50))
1850                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1851
1852         if (HAS_PCH_CPT(dev_priv)) {
1853                 /* Workaround: Clear the timing override chicken bit again. */
1854                 reg = TRANS_CHICKEN2(pipe);
1855                 val = I915_READ(reg);
1856                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1857                 I915_WRITE(reg, val);
1858         }
1859 }
1860
1861 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1862 {
1863         u32 val;
1864
1865         val = I915_READ(LPT_TRANSCONF);
1866         val &= ~TRANS_ENABLE;
1867         I915_WRITE(LPT_TRANSCONF, val);
1868         /* wait for PCH transcoder off, transcoder state */
1869         if (intel_wait_for_register(dev_priv,
1870                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1871                                     50))
1872                 DRM_ERROR("Failed to disable PCH transcoder\n");
1873
1874         /* Workaround: clear timing override bit. */
1875         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1876         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1877         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1878 }
1879
1880 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1881 {
1882         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1883
1884         WARN_ON(!crtc->config->has_pch_encoder);
1885
1886         if (HAS_PCH_LPT(dev_priv))
1887                 return PIPE_A;
1888         else
1889                 return crtc->pipe;
1890 }
1891
1892 /**
1893  * intel_enable_pipe - enable a pipe, asserting requirements
1894  * @crtc: crtc responsible for the pipe
1895  *
1896  * Enable @crtc's pipe, making sure that various hardware specific requirements
1897  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1898  */
1899 static void intel_enable_pipe(struct intel_crtc *crtc)
1900 {
1901         struct drm_device *dev = crtc->base.dev;
1902         struct drm_i915_private *dev_priv = to_i915(dev);
1903         enum pipe pipe = crtc->pipe;
1904         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1905         i915_reg_t reg;
1906         u32 val;
1907
1908         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1909
1910         assert_planes_disabled(dev_priv, pipe);
1911         assert_cursor_disabled(dev_priv, pipe);
1912         assert_sprites_disabled(dev_priv, pipe);
1913
1914         /*
1915          * A pipe without a PLL won't actually be able to drive bits from
1916          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1917          * need the check.
1918          */
1919         if (HAS_GMCH_DISPLAY(dev_priv)) {
1920                 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1921                         assert_dsi_pll_enabled(dev_priv);
1922                 else
1923                         assert_pll_enabled(dev_priv, pipe);
1924         } else {
1925                 if (crtc->config->has_pch_encoder) {
1926                         /* if driving the PCH, we need FDI enabled */
1927                         assert_fdi_rx_pll_enabled(dev_priv,
1928                                                   intel_crtc_pch_transcoder(crtc));
1929                         assert_fdi_tx_pll_enabled(dev_priv,
1930                                                   (enum pipe) cpu_transcoder);
1931                 }
1932                 /* FIXME: assert CPU port conditions for SNB+ */
1933         }
1934
1935         reg = PIPECONF(cpu_transcoder);
1936         val = I915_READ(reg);
1937         if (val & PIPECONF_ENABLE) {
1938                 /* we keep both pipes enabled on 830 */
1939                 WARN_ON(!IS_I830(dev_priv));
1940                 return;
1941         }
1942
1943         I915_WRITE(reg, val | PIPECONF_ENABLE);
1944         POSTING_READ(reg);
1945
1946         /*
1947          * Until the pipe starts DSL will read as 0, which would cause
1948          * an apparent vblank timestamp jump, which messes up also the
1949          * frame count when it's derived from the timestamps. So let's
1950          * wait for the pipe to start properly before we call
1951          * drm_crtc_vblank_on()
1952          */
1953         if (dev->max_vblank_count == 0 &&
1954             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1955                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1956 }
1957
1958 /**
1959  * intel_disable_pipe - disable a pipe, asserting requirements
1960  * @crtc: crtc whose pipes is to be disabled
1961  *
1962  * Disable the pipe of @crtc, making sure that various hardware
1963  * specific requirements are met, if applicable, e.g. plane
1964  * disabled, panel fitter off, etc.
1965  *
1966  * Will wait until the pipe has shut down before returning.
1967  */
1968 static void intel_disable_pipe(struct intel_crtc *crtc)
1969 {
1970         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1971         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1972         enum pipe pipe = crtc->pipe;
1973         i915_reg_t reg;
1974         u32 val;
1975
1976         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1977
1978         /*
1979          * Make sure planes won't keep trying to pump pixels to us,
1980          * or we might hang the display.
1981          */
1982         assert_planes_disabled(dev_priv, pipe);
1983         assert_cursor_disabled(dev_priv, pipe);
1984         assert_sprites_disabled(dev_priv, pipe);
1985
1986         reg = PIPECONF(cpu_transcoder);
1987         val = I915_READ(reg);
1988         if ((val & PIPECONF_ENABLE) == 0)
1989                 return;
1990
1991         /*
1992          * Double wide has implications for planes
1993          * so best keep it disabled when not needed.
1994          */
1995         if (crtc->config->double_wide)
1996                 val &= ~PIPECONF_DOUBLE_WIDE;
1997
1998         /* Don't disable pipe or pipe PLLs if needed */
1999         if (!IS_I830(dev_priv))
2000                 val &= ~PIPECONF_ENABLE;
2001
2002         I915_WRITE(reg, val);
2003         if ((val & PIPECONF_ENABLE) == 0)
2004                 intel_wait_for_pipe_off(crtc);
2005 }
2006
2007 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2008 {
2009         return IS_GEN2(dev_priv) ? 2048 : 4096;
2010 }
2011
2012 static unsigned int
2013 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
2014 {
2015         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2016         unsigned int cpp = fb->format->cpp[plane];
2017
2018         switch (fb->modifier) {
2019         case DRM_FORMAT_MOD_LINEAR:
2020                 return cpp;
2021         case I915_FORMAT_MOD_X_TILED:
2022                 if (IS_GEN2(dev_priv))
2023                         return 128;
2024                 else
2025                         return 512;
2026         case I915_FORMAT_MOD_Y_TILED_CCS:
2027                 if (plane == 1)
2028                         return 128;
2029                 /* fall through */
2030         case I915_FORMAT_MOD_Y_TILED:
2031                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2032                         return 128;
2033                 else
2034                         return 512;
2035         case I915_FORMAT_MOD_Yf_TILED_CCS:
2036                 if (plane == 1)
2037                         return 128;
2038                 /* fall through */
2039         case I915_FORMAT_MOD_Yf_TILED:
2040                 switch (cpp) {
2041                 case 1:
2042                         return 64;
2043                 case 2:
2044                 case 4:
2045                         return 128;
2046                 case 8:
2047                 case 16:
2048                         return 256;
2049                 default:
2050                         MISSING_CASE(cpp);
2051                         return cpp;
2052                 }
2053                 break;
2054         default:
2055                 MISSING_CASE(fb->modifier);
2056                 return cpp;
2057         }
2058 }
2059
2060 static unsigned int
2061 intel_tile_height(const struct drm_framebuffer *fb, int plane)
2062 {
2063         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
2064                 return 1;
2065         else
2066                 return intel_tile_size(to_i915(fb->dev)) /
2067                         intel_tile_width_bytes(fb, plane);
2068 }
2069
2070 /* Return the tile dimensions in pixel units */
2071 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
2072                             unsigned int *tile_width,
2073                             unsigned int *tile_height)
2074 {
2075         unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
2076         unsigned int cpp = fb->format->cpp[plane];
2077
2078         *tile_width = tile_width_bytes / cpp;
2079         *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
2080 }
2081
2082 unsigned int
2083 intel_fb_align_height(const struct drm_framebuffer *fb,
2084                       int plane, unsigned int height)
2085 {
2086         unsigned int tile_height = intel_tile_height(fb, plane);
2087
2088         return ALIGN(height, tile_height);
2089 }
2090
2091 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2092 {
2093         unsigned int size = 0;
2094         int i;
2095
2096         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2097                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2098
2099         return size;
2100 }
2101
2102 static void
2103 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2104                         const struct drm_framebuffer *fb,
2105                         unsigned int rotation)
2106 {
2107         view->type = I915_GGTT_VIEW_NORMAL;
2108         if (drm_rotation_90_or_270(rotation)) {
2109                 view->type = I915_GGTT_VIEW_ROTATED;
2110                 view->rotated = to_intel_framebuffer(fb)->rot_info;
2111         }
2112 }
2113
2114 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2115 {
2116         if (IS_I830(dev_priv))
2117                 return 16 * 1024;
2118         else if (IS_I85X(dev_priv))
2119                 return 256;
2120         else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2121                 return 32;
2122         else
2123                 return 4 * 1024;
2124 }
2125
2126 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2127 {
2128         if (INTEL_INFO(dev_priv)->gen >= 9)
2129                 return 256 * 1024;
2130         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2131                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2132                 return 128 * 1024;
2133         else if (INTEL_INFO(dev_priv)->gen >= 4)
2134                 return 4 * 1024;
2135         else
2136                 return 0;
2137 }
2138
2139 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2140                                          int plane)
2141 {
2142         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2143
2144         /* AUX_DIST needs only 4K alignment */
2145         if (plane == 1)
2146                 return 4096;
2147
2148         switch (fb->modifier) {
2149         case DRM_FORMAT_MOD_LINEAR:
2150                 return intel_linear_alignment(dev_priv);
2151         case I915_FORMAT_MOD_X_TILED:
2152                 if (INTEL_GEN(dev_priv) >= 9)
2153                         return 256 * 1024;
2154                 return 0;
2155         case I915_FORMAT_MOD_Y_TILED_CCS:
2156         case I915_FORMAT_MOD_Yf_TILED_CCS:
2157         case I915_FORMAT_MOD_Y_TILED:
2158         case I915_FORMAT_MOD_Yf_TILED:
2159                 return 1 * 1024 * 1024;
2160         default:
2161                 MISSING_CASE(fb->modifier);
2162                 return 0;
2163         }
2164 }
2165
2166 struct i915_vma *
2167 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2168 {
2169         struct drm_device *dev = fb->dev;
2170         struct drm_i915_private *dev_priv = to_i915(dev);
2171         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2172         struct i915_ggtt_view view;
2173         struct i915_vma *vma;
2174         u32 alignment;
2175
2176         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2177
2178         alignment = intel_surf_alignment(fb, 0);
2179
2180         intel_fill_fb_ggtt_view(&view, fb, rotation);
2181
2182         /* Note that the w/a also requires 64 PTE of padding following the
2183          * bo. We currently fill all unused PTE with the shadow page and so
2184          * we should always have valid PTE following the scanout preventing
2185          * the VT-d warning.
2186          */
2187         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2188                 alignment = 256 * 1024;
2189
2190         /*
2191          * Global gtt pte registers are special registers which actually forward
2192          * writes to a chunk of system memory. Which means that there is no risk
2193          * that the register values disappear as soon as we call
2194          * intel_runtime_pm_put(), so it is correct to wrap only the
2195          * pin/unpin/fence and not more.
2196          */
2197         intel_runtime_pm_get(dev_priv);
2198
2199         atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2200
2201         vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2202         if (IS_ERR(vma))
2203                 goto err;
2204
2205         if (i915_vma_is_map_and_fenceable(vma)) {
2206                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2207                  * fence, whereas 965+ only requires a fence if using
2208                  * framebuffer compression.  For simplicity, we always, when
2209                  * possible, install a fence as the cost is not that onerous.
2210                  *
2211                  * If we fail to fence the tiled scanout, then either the
2212                  * modeset will reject the change (which is highly unlikely as
2213                  * the affected systems, all but one, do not have unmappable
2214                  * space) or we will not be able to enable full powersaving
2215                  * techniques (also likely not to apply due to various limits
2216                  * FBC and the like impose on the size of the buffer, which
2217                  * presumably we violated anyway with this unmappable buffer).
2218                  * Anyway, it is presumably better to stumble onwards with
2219                  * something and try to run the system in a "less than optimal"
2220                  * mode that matches the user configuration.
2221                  */
2222                 if (i915_vma_get_fence(vma) == 0)
2223                         i915_vma_pin_fence(vma);
2224         }
2225
2226         i915_vma_get(vma);
2227 err:
2228         atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2229
2230         intel_runtime_pm_put(dev_priv);
2231         return vma;
2232 }
2233
2234 void intel_unpin_fb_vma(struct i915_vma *vma)
2235 {
2236         lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2237
2238         i915_vma_unpin_fence(vma);
2239         i915_gem_object_unpin_from_display_plane(vma);
2240         i915_vma_put(vma);
2241 }
2242
2243 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2244                           unsigned int rotation)
2245 {
2246         if (drm_rotation_90_or_270(rotation))
2247                 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2248         else
2249                 return fb->pitches[plane];
2250 }
2251
2252 /*
2253  * Convert the x/y offsets into a linear offset.
2254  * Only valid with 0/180 degree rotation, which is fine since linear
2255  * offset is only used with linear buffers on pre-hsw and tiled buffers
2256  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2257  */
2258 u32 intel_fb_xy_to_linear(int x, int y,
2259                           const struct intel_plane_state *state,
2260                           int plane)
2261 {
2262         const struct drm_framebuffer *fb = state->base.fb;
2263         unsigned int cpp = fb->format->cpp[plane];
2264         unsigned int pitch = fb->pitches[plane];
2265
2266         return y * pitch + x * cpp;
2267 }
2268
2269 /*
2270  * Add the x/y offsets derived from fb->offsets[] to the user
2271  * specified plane src x/y offsets. The resulting x/y offsets
2272  * specify the start of scanout from the beginning of the gtt mapping.
2273  */
2274 void intel_add_fb_offsets(int *x, int *y,
2275                           const struct intel_plane_state *state,
2276                           int plane)
2277
2278 {
2279         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2280         unsigned int rotation = state->base.rotation;
2281
2282         if (drm_rotation_90_or_270(rotation)) {
2283                 *x += intel_fb->rotated[plane].x;
2284                 *y += intel_fb->rotated[plane].y;
2285         } else {
2286                 *x += intel_fb->normal[plane].x;
2287                 *y += intel_fb->normal[plane].y;
2288         }
2289 }
2290
2291 static u32 __intel_adjust_tile_offset(int *x, int *y,
2292                                       unsigned int tile_width,
2293                                       unsigned int tile_height,
2294                                       unsigned int tile_size,
2295                                       unsigned int pitch_tiles,
2296                                       u32 old_offset,
2297                                       u32 new_offset)
2298 {
2299         unsigned int pitch_pixels = pitch_tiles * tile_width;
2300         unsigned int tiles;
2301
2302         WARN_ON(old_offset & (tile_size - 1));
2303         WARN_ON(new_offset & (tile_size - 1));
2304         WARN_ON(new_offset > old_offset);
2305
2306         tiles = (old_offset - new_offset) / tile_size;
2307
2308         *y += tiles / pitch_tiles * tile_height;
2309         *x += tiles % pitch_tiles * tile_width;
2310
2311         /* minimize x in case it got needlessly big */
2312         *y += *x / pitch_pixels * tile_height;
2313         *x %= pitch_pixels;
2314
2315         return new_offset;
2316 }
2317
2318 static u32 _intel_adjust_tile_offset(int *x, int *y,
2319                                      const struct drm_framebuffer *fb, int plane,
2320                                      unsigned int rotation,
2321                                      u32 old_offset, u32 new_offset)
2322 {
2323         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2324         unsigned int cpp = fb->format->cpp[plane];
2325         unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2326
2327         WARN_ON(new_offset > old_offset);
2328
2329         if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2330                 unsigned int tile_size, tile_width, tile_height;
2331                 unsigned int pitch_tiles;
2332
2333                 tile_size = intel_tile_size(dev_priv);
2334                 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2335
2336                 if (drm_rotation_90_or_270(rotation)) {
2337                         pitch_tiles = pitch / tile_height;
2338                         swap(tile_width, tile_height);
2339                 } else {
2340                         pitch_tiles = pitch / (tile_width * cpp);
2341                 }
2342
2343                 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2344                                            tile_size, pitch_tiles,
2345                                            old_offset, new_offset);
2346         } else {
2347                 old_offset += *y * pitch + *x * cpp;
2348
2349                 *y = (old_offset - new_offset) / pitch;
2350                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2351         }
2352
2353         return new_offset;
2354 }
2355
2356 /*
2357  * Adjust the tile offset by moving the difference into
2358  * the x/y offsets.
2359  */
2360 static u32 intel_adjust_tile_offset(int *x, int *y,
2361                                     const struct intel_plane_state *state, int plane,
2362                                     u32 old_offset, u32 new_offset)
2363 {
2364         return _intel_adjust_tile_offset(x, y, state->base.fb, plane,
2365                                          state->base.rotation,
2366                                          old_offset, new_offset);
2367 }
2368
2369 /*
2370  * Computes the linear offset to the base tile and adjusts
2371  * x, y. bytes per pixel is assumed to be a power-of-two.
2372  *
2373  * In the 90/270 rotated case, x and y are assumed
2374  * to be already rotated to match the rotated GTT view, and
2375  * pitch is the tile_height aligned framebuffer height.
2376  *
2377  * This function is used when computing the derived information
2378  * under intel_framebuffer, so using any of that information
2379  * here is not allowed. Anything under drm_framebuffer can be
2380  * used. This is why the user has to pass in the pitch since it
2381  * is specified in the rotated orientation.
2382  */
2383 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2384                                       int *x, int *y,
2385                                       const struct drm_framebuffer *fb, int plane,
2386                                       unsigned int pitch,
2387                                       unsigned int rotation,
2388                                       u32 alignment)
2389 {
2390         uint64_t fb_modifier = fb->modifier;
2391         unsigned int cpp = fb->format->cpp[plane];
2392         u32 offset, offset_aligned;
2393
2394         if (alignment)
2395                 alignment--;
2396
2397         if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
2398                 unsigned int tile_size, tile_width, tile_height;
2399                 unsigned int tile_rows, tiles, pitch_tiles;
2400
2401                 tile_size = intel_tile_size(dev_priv);
2402                 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2403
2404                 if (drm_rotation_90_or_270(rotation)) {
2405                         pitch_tiles = pitch / tile_height;
2406                         swap(tile_width, tile_height);
2407                 } else {
2408                         pitch_tiles = pitch / (tile_width * cpp);
2409                 }
2410
2411                 tile_rows = *y / tile_height;
2412                 *y %= tile_height;
2413
2414                 tiles = *x / tile_width;
2415                 *x %= tile_width;
2416
2417                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2418                 offset_aligned = offset & ~alignment;
2419
2420                 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2421                                            tile_size, pitch_tiles,
2422                                            offset, offset_aligned);
2423         } else {
2424                 offset = *y * pitch + *x * cpp;
2425                 offset_aligned = offset & ~alignment;
2426
2427                 *y = (offset & alignment) / pitch;
2428                 *x = ((offset & alignment) - *y * pitch) / cpp;
2429         }
2430
2431         return offset_aligned;
2432 }
2433
2434 u32 intel_compute_tile_offset(int *x, int *y,
2435                               const struct intel_plane_state *state,
2436                               int plane)
2437 {
2438         struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2439         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2440         const struct drm_framebuffer *fb = state->base.fb;
2441         unsigned int rotation = state->base.rotation;
2442         int pitch = intel_fb_pitch(fb, plane, rotation);
2443         u32 alignment;
2444
2445         if (intel_plane->id == PLANE_CURSOR)
2446                 alignment = intel_cursor_alignment(dev_priv);
2447         else
2448                 alignment = intel_surf_alignment(fb, plane);
2449
2450         return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2451                                           rotation, alignment);
2452 }
2453
2454 /* Convert the fb->offset[] into x/y offsets */
2455 static int intel_fb_offset_to_xy(int *x, int *y,
2456                                  const struct drm_framebuffer *fb, int plane)
2457 {
2458         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2459
2460         if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
2461             fb->offsets[plane] % intel_tile_size(dev_priv))
2462                 return -EINVAL;
2463
2464         *x = 0;
2465         *y = 0;
2466
2467         _intel_adjust_tile_offset(x, y,
2468                                   fb, plane, DRM_MODE_ROTATE_0,
2469                                   fb->offsets[plane], 0);
2470
2471         return 0;
2472 }
2473
2474 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2475 {
2476         switch (fb_modifier) {
2477         case I915_FORMAT_MOD_X_TILED:
2478                 return I915_TILING_X;
2479         case I915_FORMAT_MOD_Y_TILED:
2480         case I915_FORMAT_MOD_Y_TILED_CCS:
2481                 return I915_TILING_Y;
2482         default:
2483                 return I915_TILING_NONE;
2484         }
2485 }
2486
2487 static const struct drm_format_info ccs_formats[] = {
2488         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2489         { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2490         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2491         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2492 };
2493
2494 static const struct drm_format_info *
2495 lookup_format_info(const struct drm_format_info formats[],
2496                    int num_formats, u32 format)
2497 {
2498         int i;
2499
2500         for (i = 0; i < num_formats; i++) {
2501                 if (formats[i].format == format)
2502                         return &formats[i];
2503         }
2504
2505         return NULL;
2506 }
2507
2508 static const struct drm_format_info *
2509 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2510 {
2511         switch (cmd->modifier[0]) {
2512         case I915_FORMAT_MOD_Y_TILED_CCS:
2513         case I915_FORMAT_MOD_Yf_TILED_CCS:
2514                 return lookup_format_info(ccs_formats,
2515                                           ARRAY_SIZE(ccs_formats),
2516                                           cmd->pixel_format);
2517         default:
2518                 return NULL;
2519         }
2520 }
2521
2522 static int
2523 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2524                    struct drm_framebuffer *fb)
2525 {
2526         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2527         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2528         u32 gtt_offset_rotated = 0;
2529         unsigned int max_size = 0;
2530         int i, num_planes = fb->format->num_planes;
2531         unsigned int tile_size = intel_tile_size(dev_priv);
2532
2533         for (i = 0; i < num_planes; i++) {
2534                 unsigned int width, height;
2535                 unsigned int cpp, size;
2536                 u32 offset;
2537                 int x, y;
2538                 int ret;
2539
2540                 cpp = fb->format->cpp[i];
2541                 width = drm_framebuffer_plane_width(fb->width, fb, i);
2542                 height = drm_framebuffer_plane_height(fb->height, fb, i);
2543
2544                 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
2545                 if (ret) {
2546                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2547                                       i, fb->offsets[i]);
2548                         return ret;
2549                 }
2550
2551                 if ((fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2552                      fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) && i == 1) {
2553                         int hsub = fb->format->hsub;
2554                         int vsub = fb->format->vsub;
2555                         int tile_width, tile_height;
2556                         int main_x, main_y;
2557                         int ccs_x, ccs_y;
2558
2559                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2560                         tile_width *= hsub;
2561                         tile_height *= vsub;
2562
2563                         ccs_x = (x * hsub) % tile_width;
2564                         ccs_y = (y * vsub) % tile_height;
2565                         main_x = intel_fb->normal[0].x % tile_width;
2566                         main_y = intel_fb->normal[0].y % tile_height;
2567
2568                         /*
2569                          * CCS doesn't have its own x/y offset register, so the intra CCS tile
2570                          * x/y offsets must match between CCS and the main surface.
2571                          */
2572                         if (main_x != ccs_x || main_y != ccs_y) {
2573                                 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2574                                               main_x, main_y,
2575                                               ccs_x, ccs_y,
2576                                               intel_fb->normal[0].x,
2577                                               intel_fb->normal[0].y,
2578                                               x, y);
2579                                 return -EINVAL;
2580                         }
2581                 }
2582
2583                 /*
2584                  * The fence (if used) is aligned to the start of the object
2585                  * so having the framebuffer wrap around across the edge of the
2586                  * fenced region doesn't really work. We have no API to configure
2587                  * the fence start offset within the object (nor could we probably
2588                  * on gen2/3). So it's just easier if we just require that the
2589                  * fb layout agrees with the fence layout. We already check that the
2590                  * fb stride matches the fence stride elsewhere.
2591                  */
2592                 if (i == 0 && i915_gem_object_is_tiled(intel_fb->obj) &&
2593                     (x + width) * cpp > fb->pitches[i]) {
2594                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2595                                       i, fb->offsets[i]);
2596                         return -EINVAL;
2597                 }
2598
2599                 /*
2600                  * First pixel of the framebuffer from
2601                  * the start of the normal gtt mapping.
2602                  */
2603                 intel_fb->normal[i].x = x;
2604                 intel_fb->normal[i].y = y;
2605
2606                 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2607                                                     fb, i, fb->pitches[i],
2608                                                     DRM_MODE_ROTATE_0, tile_size);
2609                 offset /= tile_size;
2610
2611                 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2612                         unsigned int tile_width, tile_height;
2613                         unsigned int pitch_tiles;
2614                         struct drm_rect r;
2615
2616                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2617
2618                         rot_info->plane[i].offset = offset;
2619                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2620                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2621                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2622
2623                         intel_fb->rotated[i].pitch =
2624                                 rot_info->plane[i].height * tile_height;
2625
2626                         /* how many tiles does this plane need */
2627                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2628                         /*
2629                          * If the plane isn't horizontally tile aligned,
2630                          * we need one more tile.
2631                          */
2632                         if (x != 0)
2633                                 size++;
2634
2635                         /* rotate the x/y offsets to match the GTT view */
2636                         r.x1 = x;
2637                         r.y1 = y;
2638                         r.x2 = x + width;
2639                         r.y2 = y + height;
2640                         drm_rect_rotate(&r,
2641                                         rot_info->plane[i].width * tile_width,
2642                                         rot_info->plane[i].height * tile_height,
2643                                         DRM_MODE_ROTATE_270);
2644                         x = r.x1;
2645                         y = r.y1;
2646
2647                         /* rotate the tile dimensions to match the GTT view */
2648                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2649                         swap(tile_width, tile_height);
2650
2651                         /*
2652                          * We only keep the x/y offsets, so push all of the
2653                          * gtt offset into the x/y offsets.
2654                          */
2655                         __intel_adjust_tile_offset(&x, &y,
2656                                                    tile_width, tile_height,
2657                                                    tile_size, pitch_tiles,
2658                                                    gtt_offset_rotated * tile_size, 0);
2659
2660                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2661
2662                         /*
2663                          * First pixel of the framebuffer from
2664                          * the start of the rotated gtt mapping.
2665                          */
2666                         intel_fb->rotated[i].x = x;
2667                         intel_fb->rotated[i].y = y;
2668                 } else {
2669                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2670                                             x * cpp, tile_size);
2671                 }
2672
2673                 /* how many tiles in total needed in the bo */
2674                 max_size = max(max_size, offset + size);
2675         }
2676
2677         if (max_size * tile_size > intel_fb->obj->base.size) {
2678                 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2679                               max_size * tile_size, intel_fb->obj->base.size);
2680                 return -EINVAL;
2681         }
2682
2683         return 0;
2684 }
2685
2686 static int i9xx_format_to_fourcc(int format)
2687 {
2688         switch (format) {
2689         case DISPPLANE_8BPP:
2690                 return DRM_FORMAT_C8;
2691         case DISPPLANE_BGRX555:
2692                 return DRM_FORMAT_XRGB1555;
2693         case DISPPLANE_BGRX565:
2694                 return DRM_FORMAT_RGB565;
2695         default:
2696         case DISPPLANE_BGRX888:
2697                 return DRM_FORMAT_XRGB8888;
2698         case DISPPLANE_RGBX888:
2699                 return DRM_FORMAT_XBGR8888;
2700         case DISPPLANE_BGRX101010:
2701                 return DRM_FORMAT_XRGB2101010;
2702         case DISPPLANE_RGBX101010:
2703                 return DRM_FORMAT_XBGR2101010;
2704         }
2705 }
2706
2707 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2708 {
2709         switch (format) {
2710         case PLANE_CTL_FORMAT_RGB_565:
2711                 return DRM_FORMAT_RGB565;
2712         default:
2713         case PLANE_CTL_FORMAT_XRGB_8888:
2714                 if (rgb_order) {
2715                         if (alpha)
2716                                 return DRM_FORMAT_ABGR8888;
2717                         else
2718                                 return DRM_FORMAT_XBGR8888;
2719                 } else {
2720                         if (alpha)
2721                                 return DRM_FORMAT_ARGB8888;
2722                         else
2723                                 return DRM_FORMAT_XRGB8888;
2724                 }
2725         case PLANE_CTL_FORMAT_XRGB_2101010:
2726                 if (rgb_order)
2727                         return DRM_FORMAT_XBGR2101010;
2728                 else
2729                         return DRM_FORMAT_XRGB2101010;
2730         }
2731 }
2732
2733 static bool
2734 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2735                               struct intel_initial_plane_config *plane_config)
2736 {
2737         struct drm_device *dev = crtc->base.dev;
2738         struct drm_i915_private *dev_priv = to_i915(dev);
2739         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2740         struct drm_i915_gem_object *obj = NULL;
2741         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2742         struct drm_framebuffer *fb = &plane_config->fb->base;
2743         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2744         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2745                                     PAGE_SIZE);
2746
2747         size_aligned -= base_aligned;
2748
2749         if (plane_config->size == 0)
2750                 return false;
2751
2752         /* If the FB is too big, just don't use it since fbdev is not very
2753          * important and we should probably use that space with FBC or other
2754          * features. */
2755         if (size_aligned * 2 > ggtt->stolen_usable_size)
2756                 return false;
2757
2758         mutex_lock(&dev->struct_mutex);
2759         obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2760                                                              base_aligned,
2761                                                              base_aligned,
2762                                                              size_aligned);
2763         mutex_unlock(&dev->struct_mutex);
2764         if (!obj)
2765                 return false;
2766
2767         if (plane_config->tiling == I915_TILING_X)
2768                 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2769
2770         mode_cmd.pixel_format = fb->format->format;
2771         mode_cmd.width = fb->width;
2772         mode_cmd.height = fb->height;
2773         mode_cmd.pitches[0] = fb->pitches[0];
2774         mode_cmd.modifier[0] = fb->modifier;
2775         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2776
2777         if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2778                 DRM_DEBUG_KMS("intel fb init failed\n");
2779                 goto out_unref_obj;
2780         }
2781
2782
2783         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2784         return true;
2785
2786 out_unref_obj:
2787         i915_gem_object_put(obj);
2788         return false;
2789 }
2790
2791 static void
2792 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2793                         struct intel_plane_state *plane_state,
2794                         bool visible)
2795 {
2796         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2797
2798         plane_state->base.visible = visible;
2799
2800         /* FIXME pre-g4x don't work like this */
2801         if (visible) {
2802                 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
2803                 crtc_state->active_planes |= BIT(plane->id);
2804         } else {
2805                 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
2806                 crtc_state->active_planes &= ~BIT(plane->id);
2807         }
2808
2809         DRM_DEBUG_KMS("%s active planes 0x%x\n",
2810                       crtc_state->base.crtc->name,
2811                       crtc_state->active_planes);
2812 }
2813
2814 static void
2815 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2816                              struct intel_initial_plane_config *plane_config)
2817 {
2818         struct drm_device *dev = intel_crtc->base.dev;
2819         struct drm_i915_private *dev_priv = to_i915(dev);
2820         struct drm_crtc *c;
2821         struct drm_i915_gem_object *obj;
2822         struct drm_plane *primary = intel_crtc->base.primary;
2823         struct drm_plane_state *plane_state = primary->state;
2824         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2825         struct intel_plane *intel_plane = to_intel_plane(primary);
2826         struct intel_plane_state *intel_state =
2827                 to_intel_plane_state(plane_state);
2828         struct drm_framebuffer *fb;
2829
2830         if (!plane_config->fb)
2831                 return;
2832
2833         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2834                 fb = &plane_config->fb->base;
2835                 goto valid_fb;
2836         }
2837
2838         kfree(plane_config->fb);
2839
2840         /*
2841          * Failed to alloc the obj, check to see if we should share
2842          * an fb with another CRTC instead
2843          */
2844         for_each_crtc(dev, c) {
2845                 struct intel_plane_state *state;
2846
2847                 if (c == &intel_crtc->base)
2848                         continue;
2849
2850                 if (!to_intel_crtc(c)->active)
2851                         continue;
2852
2853                 state = to_intel_plane_state(c->primary->state);
2854                 if (!state->vma)
2855                         continue;
2856
2857                 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2858                         fb = c->primary->fb;
2859                         drm_framebuffer_reference(fb);
2860                         goto valid_fb;
2861                 }
2862         }
2863
2864         /*
2865          * We've failed to reconstruct the BIOS FB.  Current display state
2866          * indicates that the primary plane is visible, but has a NULL FB,
2867          * which will lead to problems later if we don't fix it up.  The
2868          * simplest solution is to just disable the primary plane now and
2869          * pretend the BIOS never had it enabled.
2870          */
2871         intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2872                                 to_intel_plane_state(plane_state),
2873                                 false);
2874         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2875         trace_intel_disable_plane(primary, intel_crtc);
2876         intel_plane->disable_plane(intel_plane, intel_crtc);
2877
2878         return;
2879
2880 valid_fb:
2881         mutex_lock(&dev->struct_mutex);
2882         intel_state->vma =
2883                 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2884         mutex_unlock(&dev->struct_mutex);
2885         if (IS_ERR(intel_state->vma)) {
2886                 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2887                           intel_crtc->pipe, PTR_ERR(intel_state->vma));
2888
2889                 intel_state->vma = NULL;
2890                 drm_framebuffer_unreference(fb);
2891                 return;
2892         }
2893
2894         plane_state->src_x = 0;
2895         plane_state->src_y = 0;
2896         plane_state->src_w = fb->width << 16;
2897         plane_state->src_h = fb->height << 16;
2898
2899         plane_state->crtc_x = 0;
2900         plane_state->crtc_y = 0;
2901         plane_state->crtc_w = fb->width;
2902         plane_state->crtc_h = fb->height;
2903
2904         intel_state->base.src = drm_plane_state_src(plane_state);
2905         intel_state->base.dst = drm_plane_state_dest(plane_state);
2906
2907         obj = intel_fb_obj(fb);
2908         if (i915_gem_object_is_tiled(obj))
2909                 dev_priv->preserve_bios_swizzle = true;
2910
2911         drm_framebuffer_reference(fb);
2912         primary->fb = primary->state->fb = fb;
2913         primary->crtc = primary->state->crtc = &intel_crtc->base;
2914
2915         intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2916                                 to_intel_plane_state(plane_state),
2917                                 true);
2918
2919         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2920                   &obj->frontbuffer_bits);
2921 }
2922
2923 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2924                                unsigned int rotation)
2925 {
2926         int cpp = fb->format->cpp[plane];
2927
2928         switch (fb->modifier) {
2929         case DRM_FORMAT_MOD_LINEAR:
2930         case I915_FORMAT_MOD_X_TILED:
2931                 switch (cpp) {
2932                 case 8:
2933                         return 4096;
2934                 case 4:
2935                 case 2:
2936                 case 1:
2937                         return 8192;
2938                 default:
2939                         MISSING_CASE(cpp);
2940                         break;
2941                 }
2942                 break;
2943         case I915_FORMAT_MOD_Y_TILED_CCS:
2944         case I915_FORMAT_MOD_Yf_TILED_CCS:
2945                 /* FIXME AUX plane? */
2946         case I915_FORMAT_MOD_Y_TILED:
2947         case I915_FORMAT_MOD_Yf_TILED:
2948                 switch (cpp) {
2949                 case 8:
2950                         return 2048;
2951                 case 4:
2952                         return 4096;
2953                 case 2:
2954                 case 1:
2955                         return 8192;
2956                 default:
2957                         MISSING_CASE(cpp);
2958                         break;
2959                 }
2960                 break;
2961         default:
2962                 MISSING_CASE(fb->modifier);
2963         }
2964
2965         return 2048;
2966 }
2967
2968 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
2969                                            int main_x, int main_y, u32 main_offset)
2970 {
2971         const struct drm_framebuffer *fb = plane_state->base.fb;
2972         int hsub = fb->format->hsub;
2973         int vsub = fb->format->vsub;
2974         int aux_x = plane_state->aux.x;
2975         int aux_y = plane_state->aux.y;
2976         u32 aux_offset = plane_state->aux.offset;
2977         u32 alignment = intel_surf_alignment(fb, 1);
2978
2979         while (aux_offset >= main_offset && aux_y <= main_y) {
2980                 int x, y;
2981
2982                 if (aux_x == main_x && aux_y == main_y)
2983                         break;
2984
2985                 if (aux_offset == 0)
2986                         break;
2987
2988                 x = aux_x / hsub;
2989                 y = aux_y / vsub;
2990                 aux_offset = intel_adjust_tile_offset(&x, &y, plane_state, 1,
2991                                                       aux_offset, aux_offset - alignment);
2992                 aux_x = x * hsub + aux_x % hsub;
2993                 aux_y = y * vsub + aux_y % vsub;
2994         }
2995
2996         if (aux_x != main_x || aux_y != main_y)
2997                 return false;
2998
2999         plane_state->aux.offset = aux_offset;
3000         plane_state->aux.x = aux_x;
3001         plane_state->aux.y = aux_y;
3002
3003         return true;
3004 }
3005
3006 static int skl_check_main_surface(struct intel_plane_state *plane_state)
3007 {
3008         const struct drm_framebuffer *fb = plane_state->base.fb;
3009         unsigned int rotation = plane_state->base.rotation;
3010         int x = plane_state->base.src.x1 >> 16;
3011         int y = plane_state->base.src.y1 >> 16;
3012         int w = drm_rect_width(&plane_state->base.src) >> 16;
3013         int h = drm_rect_height(&plane_state->base.src) >> 16;
3014         int max_width = skl_max_plane_width(fb, 0, rotation);
3015         int max_height = 4096;
3016         u32 alignment, offset, aux_offset = plane_state->aux.offset;
3017
3018         if (w > max_width || h > max_height) {
3019                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3020                               w, h, max_width, max_height);
3021                 return -EINVAL;
3022         }
3023
3024         intel_add_fb_offsets(&x, &y, plane_state, 0);
3025         offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
3026         alignment = intel_surf_alignment(fb, 0);
3027
3028         /*
3029          * AUX surface offset is specified as the distance from the
3030          * main surface offset, and it must be non-negative. Make
3031          * sure that is what we will get.
3032          */
3033         if (offset > aux_offset)
3034                 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3035                                                   offset, aux_offset & ~(alignment - 1));
3036
3037         /*
3038          * When using an X-tiled surface, the plane blows up
3039          * if the x offset + width exceed the stride.
3040          *
3041          * TODO: linear and Y-tiled seem fine, Yf untested,
3042          */
3043         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3044                 int cpp = fb->format->cpp[0];
3045
3046                 while ((x + w) * cpp > fb->pitches[0]) {
3047                         if (offset == 0) {
3048                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3049                                 return -EINVAL;
3050                         }
3051
3052                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3053                                                           offset, offset - alignment);
3054                 }
3055         }
3056
3057         /*
3058          * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3059          * they match with the main surface x/y offsets.
3060          */
3061         if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3062             fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3063                 while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
3064                         if (offset == 0)
3065                                 break;
3066
3067                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3068                                                           offset, offset - alignment);
3069                 }
3070
3071                 if (x != plane_state->aux.x || y != plane_state->aux.y) {
3072                         DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3073                         return -EINVAL;
3074                 }
3075         }
3076
3077         plane_state->main.offset = offset;
3078         plane_state->main.x = x;
3079         plane_state->main.y = y;
3080
3081         return 0;
3082 }
3083
3084 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3085 {
3086         const struct drm_framebuffer *fb = plane_state->base.fb;
3087         unsigned int rotation = plane_state->base.rotation;
3088         int max_width = skl_max_plane_width(fb, 1, rotation);
3089         int max_height = 4096;
3090         int x = plane_state->base.src.x1 >> 17;
3091         int y = plane_state->base.src.y1 >> 17;
3092         int w = drm_rect_width(&plane_state->base.src) >> 17;
3093         int h = drm_rect_height(&plane_state->base.src) >> 17;
3094         u32 offset;
3095
3096         intel_add_fb_offsets(&x, &y, plane_state, 1);
3097         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3098
3099         /* FIXME not quite sure how/if these apply to the chroma plane */
3100         if (w > max_width || h > max_height) {
3101                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3102                               w, h, max_width, max_height);
3103                 return -EINVAL;
3104         }
3105
3106         plane_state->aux.offset = offset;
3107         plane_state->aux.x = x;
3108         plane_state->aux.y = y;
3109
3110         return 0;
3111 }
3112
3113 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3114 {
3115         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
3116         struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc);
3117         const struct drm_framebuffer *fb = plane_state->base.fb;
3118         int src_x = plane_state->base.src.x1 >> 16;
3119         int src_y = plane_state->base.src.y1 >> 16;
3120         int hsub = fb->format->hsub;
3121         int vsub = fb->format->vsub;
3122         int x = src_x / hsub;
3123         int y = src_y / vsub;
3124         u32 offset;
3125
3126         switch (plane->id) {
3127         case PLANE_PRIMARY:
3128         case PLANE_SPRITE0:
3129                 break;
3130         default:
3131                 DRM_DEBUG_KMS("RC support only on plane 1 and 2\n");
3132                 return -EINVAL;
3133         }
3134
3135         if (crtc->pipe == PIPE_C) {
3136                 DRM_DEBUG_KMS("No RC support on pipe C\n");
3137                 return -EINVAL;
3138         }
3139
3140         if (plane_state->base.rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180)) {
3141                 DRM_DEBUG_KMS("RC support only with 0/180 degree rotation %x\n",
3142                               plane_state->base.rotation);
3143                 return -EINVAL;
3144         }
3145
3146         intel_add_fb_offsets(&x, &y, plane_state, 1);
3147         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3148
3149         plane_state->aux.offset = offset;
3150         plane_state->aux.x = x * hsub + src_x % hsub;
3151         plane_state->aux.y = y * vsub + src_y % vsub;
3152
3153         return 0;
3154 }
3155
3156 int skl_check_plane_surface(struct intel_plane_state *plane_state)
3157 {
3158         const struct drm_framebuffer *fb = plane_state->base.fb;
3159         unsigned int rotation = plane_state->base.rotation;
3160         int ret;
3161
3162         if (!plane_state->base.visible)
3163                 return 0;
3164
3165         /* Rotate src coordinates to match rotated GTT view */
3166         if (drm_rotation_90_or_270(rotation))
3167                 drm_rect_rotate(&plane_state->base.src,
3168                                 fb->width << 16, fb->height << 16,
3169                                 DRM_MODE_ROTATE_270);
3170
3171         /*
3172          * Handle the AUX surface first since
3173          * the main surface setup depends on it.
3174          */
3175         if (fb->format->format == DRM_FORMAT_NV12) {
3176                 ret = skl_check_nv12_aux_surface(plane_state);