drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/types.h>
  32 #include <linux/notifier.h>
  33 #include <linux/reboot.h>
  34 #include <asm/byteorder.h>
  35 #include <drm/drmP.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_crtc_helper.h>
  39 #include <drm/drm_dp_helper.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/drm_hdcp.h>
  42 #include "intel_drv.h"
  43 #include <drm/i915_drm.h>
  44 #include "i915_drv.h"
  45
  46 #define DP_DPRX_ESI_LEN 14
  47
  48 /* Compliance test status bits  */
  49 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  50 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  51 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  52 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  53
  54 struct dp_link_dpll {
  55         int clock;
  56         struct dpll dpll;
  57 };
  58
  59 static const struct dp_link_dpll g4x_dpll[] = {
  60         { 162000,
  61                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  62         { 270000,
  63                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  64 };
  65
  66 static const struct dp_link_dpll pch_dpll[] = {
  67         { 162000,
  68                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  69         { 270000,
  70                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  71 };
  72
  73 static const struct dp_link_dpll vlv_dpll[] = {
  74         { 162000,
  75                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  76         { 270000,
  77                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  78 };
  79
  80 /*
  81  * CHV supports eDP 1.4 that have  more link rates.
  82  * Below only provides the fixed rate but exclude variable rate.
  83  */
  84 static const struct dp_link_dpll chv_dpll[] = {
  85         /*
  86          * CHV requires to program fractional division for m2.
  87          * m2 is stored in fixed point format using formula below
  88          * (m2_int << 22) | m2_fraction
  89          */
  90         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
  91                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  92         { 270000,       /* m2_int = 27, m2_fraction = 0 */
  93                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  94 };
  95
  96 /**
  97  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  98  * @intel_dp: DP struct
  99  *
 100  * If a CPU or PCH DP output is attached to an eDP panel, this function
 101  * will return true, and false otherwise.
 102  */
 103 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 104 {
 105         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 106
 107         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 108 }
 109
 110 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 111 {
 112         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 113 }
 114
 115 static void intel_dp_link_down(struct intel_encoder *encoder,
 116                                const struct intel_crtc_state *old_crtc_state);
 117 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 118 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 119 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
 120                                            const struct intel_crtc_state *crtc_state);
 121 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 122                                       enum pipe pipe);
 123 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 124
 125 /* update sink rates from dpcd */
 126 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 127 {
 128         static const int dp_rates[] = {
 129                 162000, 270000, 540000, 810000
 130         };
 131         int i, max_rate;
 132
 133         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 134
 135         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 136                 if (dp_rates[i] > max_rate)
 137                         break;
 138                 intel_dp->sink_rates[i] = dp_rates[i];
 139         }
 140
 141         intel_dp->num_sink_rates = i;
 142 }
 143
 144 /* Get length of rates array potentially limited by max_rate. */
 145 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 146 {
 147         int i;
 148
 149         /* Limit results by potentially reduced max rate */
 150         for (i = 0; i < len; i++) {
 151                 if (rates[len - i - 1] <= max_rate)
 152                         return len - i;
 153         }
 154
 155         return 0;
 156 }
 157
 158 /* Get length of common rates array potentially limited by max_rate. */
 159 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 160                                           int max_rate)
 161 {
 162         return intel_dp_rate_limit_len(intel_dp->common_rates,
 163                                        intel_dp->num_common_rates, max_rate);
 164 }
 165
 166 /* Theoretical max between source and sink */
 167 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 168 {
 169         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 170 }
 171
 172 static int intel_dp_get_fia_supported_lane_count(struct intel_dp *intel_dp)
 173 {
 174         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 175         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 176         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
 177         u32 lane_info;
 178
 179         if (tc_port == PORT_TC_NONE || dig_port->tc_type != TC_PORT_TYPEC)
 180                 return 4;
 181
 182         lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
 183                      DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
 184                     DP_LANE_ASSIGNMENT_SHIFT(tc_port);
 185
 186         switch (lane_info) {
 187         default:
 188                 MISSING_CASE(lane_info);
 189         case 1:
 190         case 2:
 191         case 4:
 192         case 8:
 193                 return 1;
 194         case 3:
 195         case 12:
 196                 return 2;
 197         case 15:
 198                 return 4;
 199         }
 200 }
 201
 202 /* Theoretical max between source and sink */
 203 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 204 {
 205         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 206         int source_max = intel_dig_port->max_lanes;
 207         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 208         int fia_max = intel_dp_get_fia_supported_lane_count(intel_dp);
 209
 210         return min3(source_max, sink_max, fia_max);
 211 }
 212
 213 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 214 {
 215         return intel_dp->max_link_lane_count;
 216 }
 217
 218 int
 219 intel_dp_link_required(int pixel_clock, int bpp)
 220 {
 221         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 222         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 223 }
 224
 225 void icl_program_mg_dp_mode(struct intel_dp *intel_dp)
 226 {
 227         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 228         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 229         enum port port = intel_dig_port->base.port;
 230         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
 231         u32 ln0, ln1, lane_info;
 232
 233         if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type == TC_PORT_TBT)
 234                 return;
 235
 236         ln0 = I915_READ(MG_DP_MODE(port, 0));
 237         ln1 = I915_READ(MG_DP_MODE(port, 1));
 238
 239         switch (intel_dig_port->tc_type) {
 240         case TC_PORT_TYPEC:
 241                 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
 242                 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
 243
 244                 lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
 245                              DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
 246                             DP_LANE_ASSIGNMENT_SHIFT(tc_port);
 247
 248                 switch (lane_info) {
 249                 case 0x1:
 250                 case 0x4:
 251                         break;
 252                 case 0x2:
 253                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
 254                         break;
 255                 case 0x3:
 256                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
 257                                MG_DP_MODE_CFG_DP_X2_MODE;
 258                         break;
 259                 case 0x8:
 260                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
 261                         break;
 262                 case 0xC:
 263                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
 264                                MG_DP_MODE_CFG_DP_X2_MODE;
 265                         break;
 266                 case 0xF:
 267                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
 268                                MG_DP_MODE_CFG_DP_X2_MODE;
 269                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
 270                                MG_DP_MODE_CFG_DP_X2_MODE;
 271                         break;
 272                 default:
 273                         MISSING_CASE(lane_info);
 274                 }
 275                 break;
 276
 277         case TC_PORT_LEGACY:
 278                 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
 279                 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
 280                 break;
 281
 282         default:
 283                 MISSING_CASE(intel_dig_port->tc_type);
 284                 return;
 285         }
 286
 287         I915_WRITE(MG_DP_MODE(port, 0), ln0);
 288         I915_WRITE(MG_DP_MODE(port, 1), ln1);
 289 }
 290
 291 void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
 292 {
 293         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 294         enum port port = dig_port->base.port;
 295         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
 296         i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
 297         u32 val;
 298         int i;
 299
 300         if (tc_port == PORT_TC_NONE)
 301                 return;
 302
 303         for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
 304                 val = I915_READ(mg_regs[i]);
 305                 val |= MG_DP_MODE_CFG_TR2PWR_GATING |
 306                        MG_DP_MODE_CFG_TRPWR_GATING |
 307                        MG_DP_MODE_CFG_CLNPWR_GATING |
 308                        MG_DP_MODE_CFG_DIGPWR_GATING |
 309                        MG_DP_MODE_CFG_GAONPWR_GATING;
 310                 I915_WRITE(mg_regs[i], val);
 311         }
 312
 313         val = I915_READ(MG_MISC_SUS0(tc_port));
 314         val |= MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3) |
 315                MG_MISC_SUS0_CFG_TR2PWR_GATING |
 316                MG_MISC_SUS0_CFG_CL2PWR_GATING |
 317                MG_MISC_SUS0_CFG_GAONPWR_GATING |
 318                MG_MISC_SUS0_CFG_TRPWR_GATING |
 319                MG_MISC_SUS0_CFG_CL1PWR_GATING |
 320                MG_MISC_SUS0_CFG_DGPWR_GATING;
 321         I915_WRITE(MG_MISC_SUS0(tc_port), val);
 322 }
 323
 324 void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
 325 {
 326         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 327         enum port port = dig_port->base.port;
 328         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
 329         i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
 330         u32 val;
 331         int i;
 332
 333         if (tc_port == PORT_TC_NONE)
 334                 return;
 335
 336         for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
 337                 val = I915_READ(mg_regs[i]);
 338                 val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
 339                          MG_DP_MODE_CFG_TRPWR_GATING |
 340                          MG_DP_MODE_CFG_CLNPWR_GATING |
 341                          MG_DP_MODE_CFG_DIGPWR_GATING |
 342                          MG_DP_MODE_CFG_GAONPWR_GATING);
 343                 I915_WRITE(mg_regs[i], val);
 344         }
 345
 346         val = I915_READ(MG_MISC_SUS0(tc_port));
 347         val &= ~(MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK |
 348                  MG_MISC_SUS0_CFG_TR2PWR_GATING |
 349                  MG_MISC_SUS0_CFG_CL2PWR_GATING |
 350                  MG_MISC_SUS0_CFG_GAONPWR_GATING |
 351                  MG_MISC_SUS0_CFG_TRPWR_GATING |
 352                  MG_MISC_SUS0_CFG_CL1PWR_GATING |
 353                  MG_MISC_SUS0_CFG_DGPWR_GATING);
 354         I915_WRITE(MG_MISC_SUS0(tc_port), val);
 355 }
 356
 357 int
 358 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 359 {
 360         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 361          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 362          * is transmitted every LS_Clk per lane, there is no need to account for
 363          * the channel encoding that is done in the PHY layer here.
 364          */
 365
 366         return max_link_clock * max_lanes;
 367 }
 368
 369 static int
 370 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 371 {
 372         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 373         struct intel_encoder *encoder = &intel_dig_port->base;
 374         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 375         int max_dotclk = dev_priv->max_dotclk_freq;
 376         int ds_max_dotclk;
 377
 378         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
 379
 380         if (type != DP_DS_PORT_TYPE_VGA)
 381                 return max_dotclk;
 382
 383         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
 384                                                     intel_dp->downstream_ports);
 385
 386         if (ds_max_dotclk != 0)
 387                 max_dotclk = min(max_dotclk, ds_max_dotclk);
 388
 389         return max_dotclk;
 390 }
 391
 392 static int cnl_max_source_rate(struct intel_dp *intel_dp)
 393 {
 394         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 395         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 396         enum port port = dig_port->base.port;
 397
 398         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 399
 400         /* Low voltage SKUs are limited to max of 5.4G */
 401         if (voltage == VOLTAGE_INFO_0_85V)
 402                 return 540000;
 403
 404         /* For this SKU 8.1G is supported in all ports */
 405         if (IS_CNL_WITH_PORT_F(dev_priv))
 406                 return 810000;
 407
 408         /* For other SKUs, max rate on ports A and D is 5.4G */
 409         if (port == PORT_A || port == PORT_D)
 410                 return 540000;
 411
 412         return 810000;
 413 }
 414
 415 static int icl_max_source_rate(struct intel_dp *intel_dp)
 416 {
 417         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 418         enum port port = dig_port->base.port;
 419
 420         if (port == PORT_B)
 421                 return 540000;
 422
 423         return 810000;
 424 }
 425
 426 static void
 427 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 428 {
 429         /* The values must be in increasing order */
 430         static const int cnl_rates[] = {
 431                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
 432         };
 433         static const int bxt_rates[] = {
 434                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 435         };
 436         static const int skl_rates[] = {
 437                 162000, 216000, 270000, 324000, 432000, 540000
 438         };
 439         static const int hsw_rates[] = {
 440                 162000, 270000, 540000
 441         };
 442         static const int g4x_rates[] = {
 443                 162000, 270000
 444         };
 445         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 446         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 447         const struct ddi_vbt_port_info *info =
 448                 &dev_priv->vbt.ddi_port_info[dig_port->base.port];
 449         const int *source_rates;
 450         int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
 451
 452         /* This should only be done once */
 453         WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
 454
 455         if (INTEL_GEN(dev_priv) >= 10) {
 456                 source_rates = cnl_rates;
 457                 size = ARRAY_SIZE(cnl_rates);
 458                 if (INTEL_GEN(dev_priv) == 10)
 459                         max_rate = cnl_max_source_rate(intel_dp);
 460                 else
 461                         max_rate = icl_max_source_rate(intel_dp);
 462         } else if (IS_GEN9_LP(dev_priv)) {
 463                 source_rates = bxt_rates;
 464                 size = ARRAY_SIZE(bxt_rates);
 465         } else if (IS_GEN9_BC(dev_priv)) {
 466                 source_rates = skl_rates;
 467                 size = ARRAY_SIZE(skl_rates);
 468         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 469                    IS_BROADWELL(dev_priv)) {
 470                 source_rates = hsw_rates;
 471                 size = ARRAY_SIZE(hsw_rates);
 472         } else {
 473                 source_rates = g4x_rates;
 474                 size = ARRAY_SIZE(g4x_rates);
 475         }
 476
 477         if (max_rate && vbt_max_rate)
 478                 max_rate = min(max_rate, vbt_max_rate);
 479         else if (vbt_max_rate)
 480                 max_rate = vbt_max_rate;
 481
 482         if (max_rate)
 483                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 484
 485         intel_dp->source_rates = source_rates;
 486         intel_dp->num_source_rates = size;
 487 }
 488
 489 static int intersect_rates(const int *source_rates, int source_len,
 490                            const int *sink_rates, int sink_len,
 491                            int *common_rates)
 492 {
 493         int i = 0, j = 0, k = 0;
 494
 495         while (i < source_len && j < sink_len) {
 496                 if (source_rates[i] == sink_rates[j]) {
 497                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 498                                 return k;
 499                         common_rates[k] = source_rates[i];
 500                         ++k;
 501                         ++i;
 502                         ++j;
 503                 } else if (source_rates[i] < sink_rates[j]) {
 504                         ++i;
 505                 } else {
 506                         ++j;
 507                 }
 508         }
 509         return k;
 510 }
 511
 512 /* return index of rate in rates array, or -1 if not found */
 513 static int intel_dp_rate_index(const int *rates, int len, int rate)
 514 {
 515         int i;
 516
 517         for (i = 0; i < len; i++)
 518                 if (rate == rates[i])
 519                         return i;
 520
 521         return -1;
 522 }
 523
 524 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 525 {
 526         WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 527
 528         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 529                                                      intel_dp->num_source_rates,
 530                                                      intel_dp->sink_rates,
 531                                                      intel_dp->num_sink_rates,
 532                                                      intel_dp->common_rates);
 533
 534         /* Paranoia, there should always be something in common. */
 535         if (WARN_ON(intel_dp->num_common_rates == 0)) {
 536                 intel_dp->common_rates[0] = 162000;
 537                 intel_dp->num_common_rates = 1;
 538         }
 539 }
 540
 541 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 542                                        uint8_t lane_count)
 543 {
 544         /*
 545          * FIXME: we need to synchronize the current link parameters with
 546          * hardware readout. Currently fast link training doesn't work on
 547          * boot-up.
 548          */
 549         if (link_rate == 0 ||
 550             link_rate > intel_dp->max_link_rate)
 551                 return false;
 552
 553         if (lane_count == 0 ||
 554             lane_count > intel_dp_max_lane_count(intel_dp))
 555                 return false;
 556
 557         return true;
 558 }
 559
 560 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 561                                                      int link_rate,
 562                                                      uint8_t lane_count)
 563 {
 564         const struct drm_display_mode *fixed_mode =
 565                 intel_dp->attached_connector->panel.fixed_mode;
 566         int mode_rate, max_rate;
 567
 568         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 569         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 570         if (mode_rate > max_rate)
 571                 return false;
 572
 573         return true;
 574 }
 575
 576 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 577                                             int link_rate, uint8_t lane_count)
 578 {
 579         int index;
 580
 581         index = intel_dp_rate_index(intel_dp->common_rates,
 582                                     intel_dp->num_common_rates,
 583                                     link_rate);
 584         if (index > 0) {
 585                 if (intel_dp_is_edp(intel_dp) &&
 586                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 587                                                               intel_dp->common_rates[index - 1],
 588                                                               lane_count)) {
 589                         DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
 590                         return 0;
 591                 }
 592                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 593                 intel_dp->max_link_lane_count = lane_count;
 594         } else if (lane_count > 1) {
 595                 if (intel_dp_is_edp(intel_dp) &&
 596                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 597                                                               intel_dp_max_common_rate(intel_dp),
 598                                                               lane_count >> 1)) {
 599                         DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
 600                         return 0;
 601                 }
 602                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 603                 intel_dp->max_link_lane_count = lane_count >> 1;
 604         } else {
 605                 DRM_ERROR("Link Training Unsuccessful\n");
 606                 return -1;
 607         }
 608
 609         return 0;
 610 }
 611
 612 static enum drm_mode_status
 613 intel_dp_mode_valid(struct drm_connector *connector,
 614                     struct drm_display_mode *mode)
 615 {
 616         struct intel_dp *intel_dp = intel_attached_dp(connector);
 617         struct intel_connector *intel_connector = to_intel_connector(connector);
 618         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 619         int target_clock = mode->clock;
 620         int max_rate, mode_rate, max_lanes, max_link_clock;
 621         int max_dotclk;
 622
 623         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 624                 return MODE_NO_DBLESCAN;
 625
 626         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 627
 628         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 629                 if (mode->hdisplay > fixed_mode->hdisplay)
 630                         return MODE_PANEL;
 631
 632                 if (mode->vdisplay > fixed_mode->vdisplay)
 633                         return MODE_PANEL;
 634
 635                 target_clock = fixed_mode->clock;
 636         }
 637
 638         max_link_clock = intel_dp_max_link_rate(intel_dp);
 639         max_lanes = intel_dp_max_lane_count(intel_dp);
 640
 641         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 642         mode_rate = intel_dp_link_required(target_clock, 18);
 643
 644         if (mode_rate > max_rate || target_clock > max_dotclk)
 645                 return MODE_CLOCK_HIGH;
 646
 647         if (mode->clock < 10000)
 648                 return MODE_CLOCK_LOW;
 649
 650         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 651                 return MODE_H_ILLEGAL;
 652
 653         return MODE_OK;
 654 }
 655
 656 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 657 {
 658         int     i;
 659         uint32_t v = 0;
 660
 661         if (src_bytes > 4)
 662                 src_bytes = 4;
 663         for (i = 0; i < src_bytes; i++)
 664                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 665         return v;
 666 }
 667
 668 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 669 {
 670         int i;
 671         if (dst_bytes > 4)
 672                 dst_bytes = 4;
 673         for (i = 0; i < dst_bytes; i++)
 674                 dst[i] = src >> ((3-i) * 8);
 675 }
 676
 677 static void
 678 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
 679 static void
 680 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
 681                                               bool force_disable_vdd);
 682 static void
 683 intel_dp_pps_init(struct intel_dp *intel_dp);
 684
 685 static void pps_lock(struct intel_dp *intel_dp)
 686 {
 687         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 688
 689         /*
 690          * See intel_power_sequencer_reset() why we need
 691          * a power domain reference here.
 692          */
 693         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
 694
 695         mutex_lock(&dev_priv->pps_mutex);
 696 }
 697
 698 static void pps_unlock(struct intel_dp *intel_dp)
 699 {
 700         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 701
 702         mutex_unlock(&dev_priv->pps_mutex);
 703
 704         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
 705 }
 706
 707 static void
 708 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 709 {
 710         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 711         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 712         enum pipe pipe = intel_dp->pps_pipe;
 713         bool pll_enabled, release_cl_override = false;
 714         enum dpio_phy phy = DPIO_PHY(pipe);
 715         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 716         uint32_t DP;
 717
 718         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 719                  "skipping pipe %c power sequencer kick due to port %c being active\n",
 720                  pipe_name(pipe), port_name(intel_dig_port->base.port)))
 721                 return;
 722
 723         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 724                       pipe_name(pipe), port_name(intel_dig_port->base.port));
 725
 726         /* Preserve the BIOS-computed detected bit. This is
 727          * supposed to be read-only.
 728          */
 729         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 730         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 731         DP |= DP_PORT_WIDTH(1);
 732         DP |= DP_LINK_TRAIN_PAT_1;
 733
 734         if (IS_CHERRYVIEW(dev_priv))
 735                 DP |= DP_PIPE_SEL_CHV(pipe);
 736         else
 737                 DP |= DP_PIPE_SEL(pipe);
 738
 739         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 740
 741         /*
 742          * The DPLL for the pipe must be enabled for this to work.
 743          * So enable temporarily it if it's not already enabled.
 744          */
 745         if (!pll_enabled) {
 746                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 747                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 748
 749                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 750                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 751                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 752                                   pipe_name(pipe));
 753                         return;
 754                 }
 755         }
 756
 757         /*
 758          * Similar magic as in intel_dp_enable_port().
 759          * We _must_ do this port enable + disable trick
 760          * to make this power sequencer lock onto the port.
 761          * Otherwise even VDD force bit won't work.
 762          */
 763         I915_WRITE(intel_dp->output_reg, DP);
 764         POSTING_READ(intel_dp->output_reg);
 765
 766         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 767         POSTING_READ(intel_dp->output_reg);
 768
 769         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 770         POSTING_READ(intel_dp->output_reg);
 771
 772         if (!pll_enabled) {
 773                 vlv_force_pll_off(dev_priv, pipe);
 774
 775                 if (release_cl_override)
 776                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 777         }
 778 }
 779
 780 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 781 {
 782         struct intel_encoder *encoder;
 783         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 784
 785         /*
 786          * We don't have power sequencer currently.
 787          * Pick one that's not used by other ports.
 788          */
 789         for_each_intel_dp(&dev_priv->drm, encoder) {
 790                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 791
 792                 if (encoder->type == INTEL_OUTPUT_EDP) {
 793                         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 794                                 intel_dp->active_pipe != intel_dp->pps_pipe);
 795
 796                         if (intel_dp->pps_pipe != INVALID_PIPE)
 797                                 pipes &= ~(1 << intel_dp->pps_pipe);
 798                 } else {
 799                         WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
 800
 801                         if (intel_dp->active_pipe != INVALID_PIPE)
 802                                 pipes &= ~(1 << intel_dp->active_pipe);
 803                 }
 804         }
 805
 806         if (pipes == 0)
 807                 return INVALID_PIPE;
 808
 809         return ffs(pipes) - 1;
 810 }
 811
 812 static enum pipe
 813 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 814 {
 815         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 816         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 817         enum pipe pipe;
 818
 819         lockdep_assert_held(&dev_priv->pps_mutex);
 820
 821         /* We should never land here with regular DP ports */
 822         WARN_ON(!intel_dp_is_edp(intel_dp));
 823
 824         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 825                 intel_dp->active_pipe != intel_dp->pps_pipe);
 826
 827         if (intel_dp->pps_pipe != INVALID_PIPE)
 828                 return intel_dp->pps_pipe;
 829
 830         pipe = vlv_find_free_pps(dev_priv);
 831
 832         /*
 833          * Didn't find one. This should not happen since there
 834          * are two power sequencers and up to two eDP ports.
 835          */
 836         if (WARN_ON(pipe == INVALID_PIPE))
 837                 pipe = PIPE_A;
 838
 839         vlv_steal_power_sequencer(dev_priv, pipe);
 840         intel_dp->pps_pipe = pipe;
 841
 842         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 843                       pipe_name(intel_dp->pps_pipe),
 844                       port_name(intel_dig_port->base.port));
 845
 846         /* init power sequencer on this pipe and port */
 847         intel_dp_init_panel_power_sequencer(intel_dp);
 848         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
 849
 850         /*
 851          * Even vdd force doesn't work until we've made
 852          * the power sequencer lock in on the port.
 853          */
 854         vlv_power_sequencer_kick(intel_dp);
 855
 856         return intel_dp->pps_pipe;
 857 }
 858
 859 static int
 860 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 861 {
 862         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 863         int backlight_controller = dev_priv->vbt.backlight.controller;
 864
 865         lockdep_assert_held(&dev_priv->pps_mutex);
 866
 867         /* We should never land here with regular DP ports */
 868         WARN_ON(!intel_dp_is_edp(intel_dp));
 869
 870         if (!intel_dp->pps_reset)
 871                 return backlight_controller;
 872
 873         intel_dp->pps_reset = false;
 874
 875         /*
 876          * Only the HW needs to be reprogrammed, the SW state is fixed and
 877          * has been setup during connector init.
 878          */
 879         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 880
 881         return backlight_controller;
 882 }
 883
 884 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 885                                enum pipe pipe);
 886
 887 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 888                                enum pipe pipe)
 889 {
 890         return I915_READ(PP_STATUS(pipe)) & PP_ON;
 891 }
 892
 893 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 894                                 enum pipe pipe)
 895 {
 896         return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 897 }
 898
 899 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 900                          enum pipe pipe)
 901 {
 902         return true;
 903 }
 904
 905 static enum pipe
 906 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 907                      enum port port,
 908                      vlv_pipe_check pipe_check)
 909 {
 910         enum pipe pipe;
 911
 912         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 913                 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
 914                         PANEL_PORT_SELECT_MASK;
 915
 916                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 917                         continue;
 918
 919                 if (!pipe_check(dev_priv, pipe))
 920                         continue;
 921
 922                 return pipe;
 923         }
 924
 925         return INVALID_PIPE;
 926 }
 927
 928 static void
 929 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 930 {
 931         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 932         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 933         enum port port = intel_dig_port->base.port;
 934
 935         lockdep_assert_held(&dev_priv->pps_mutex);
 936
 937         /* try to find a pipe with this port selected */
 938         /* first pick one where the panel is on */
 939         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 940                                                   vlv_pipe_has_pp_on);
 941         /* didn't find one? pick one where vdd is on */
 942         if (intel_dp->pps_pipe == INVALID_PIPE)
 943                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 944                                                           vlv_pipe_has_vdd_on);
 945         /* didn't find one? pick one with just the correct port */
 946         if (intel_dp->pps_pipe == INVALID_PIPE)
 947                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 948                                                           vlv_pipe_any);
 949
 950         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 951         if (intel_dp->pps_pipe == INVALID_PIPE) {
 952                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 953                               port_name(port));
 954                 return;
 955         }
 956
 957         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 958                       port_name(port), pipe_name(intel_dp->pps_pipe));
 959
 960         intel_dp_init_panel_power_sequencer(intel_dp);
 961         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 962 }
 963
 964 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
 965 {
 966         struct intel_encoder *encoder;
 967
 968         if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 969                     !IS_GEN9_LP(dev_priv)))
 970                 return;
 971
 972         /*
 973          * We can't grab pps_mutex here due to deadlock with power_domain
 974          * mutex when power_domain functions are called while holding pps_mutex.
 975          * That also means that in order to use pps_pipe the code needs to
 976          * hold both a power domain reference and pps_mutex, and the power domain
 977          * reference get/put must be done while _not_ holding pps_mutex.
 978          * pps_{lock,unlock}() do these steps in the correct order, so one
 979          * should use them always.
 980          */
 981
 982         for_each_intel_dp(&dev_priv->drm, encoder) {
 983                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 984
 985                 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
 986
 987                 if (encoder->type != INTEL_OUTPUT_EDP)
 988                         continue;
 989
 990                 if (IS_GEN9_LP(dev_priv))
 991                         intel_dp->pps_reset = true;
 992                 else
 993                         intel_dp->pps_pipe = INVALID_PIPE;
 994         }
 995 }
 996
 997 struct pps_registers {
 998         i915_reg_t pp_ctrl;
 999         i915_reg_t pp_stat;
1000         i915_reg_t pp_on;
1001         i915_reg_t pp_off;
1002         i915_reg_t pp_div;
1003 };
1004
1005 static void intel_pps_get_registers(struct intel_dp *intel_dp,
1006                                     struct pps_registers *regs)
1007 {
1008         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1009         int pps_idx = 0;
1010
1011         memset(regs, 0, sizeof(*regs));
1012
1013         if (IS_GEN9_LP(dev_priv))
1014                 pps_idx = bxt_power_sequencer_idx(intel_dp);
1015         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1016                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
1017
1018         regs->pp_ctrl = PP_CONTROL(pps_idx);
1019         regs->pp_stat = PP_STATUS(pps_idx);
1020         regs->pp_on = PP_ON_DELAYS(pps_idx);
1021         regs->pp_off = PP_OFF_DELAYS(pps_idx);
1022         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
1023             !HAS_PCH_ICP(dev_priv))
1024                 regs->pp_div = PP_DIVISOR(pps_idx);
1025 }
1026
1027 static i915_reg_t
1028 _pp_ctrl_reg(struct intel_dp *intel_dp)
1029 {
1030         struct pps_registers regs;
1031
1032         intel_pps_get_registers(intel_dp, &regs);
1033
1034         return regs.pp_ctrl;
1035 }
1036
1037 static i915_reg_t
1038 _pp_stat_reg(struct intel_dp *intel_dp)
1039 {
1040         struct pps_registers regs;
1041
1042         intel_pps_get_registers(intel_dp, &regs);
1043
1044         return regs.pp_stat;
1045 }
1046
1047 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
1048    This function only applicable when panel PM state is not to be tracked */
1049 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
1050                               void *unused)
1051 {
1052         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
1053                                                  edp_notifier);
1054         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1055
1056         if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
1057                 return 0;
1058
1059         pps_lock(intel_dp);
1060
1061         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1062                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
1063                 i915_reg_t pp_ctrl_reg, pp_div_reg;
1064                 u32 pp_div;
1065
1066                 pp_ctrl_reg = PP_CONTROL(pipe);
1067                 pp_div_reg  = PP_DIVISOR(pipe);
1068                 pp_div = I915_READ(pp_div_reg);
1069                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
1070
1071                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
1072                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
1073                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
1074                 msleep(intel_dp->panel_power_cycle_delay);
1075         }
1076
1077         pps_unlock(intel_dp);
1078
1079         return 0;
1080 }
1081
1082 static bool edp_have_panel_power(struct intel_dp *intel_dp)
1083 {
1084         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1085
1086         lockdep_assert_held(&dev_priv->pps_mutex);
1087
1088         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1089             intel_dp->pps_pipe == INVALID_PIPE)
1090                 return false;
1091
1092         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
1093 }
1094
1095 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
1096 {
1097         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1098
1099         lockdep_assert_held(&dev_priv->pps_mutex);
1100
1101         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1102             intel_dp->pps_pipe == INVALID_PIPE)
1103                 return false;
1104
1105         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
1106 }
1107
1108 static void
1109 intel_dp_check_edp(struct intel_dp *intel_dp)
1110 {
1111         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1112
1113         if (!intel_dp_is_edp(intel_dp))
1114                 return;
1115
1116         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
1117                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
1118                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
1119                               I915_READ(_pp_stat_reg(intel_dp)),
1120                               I915_READ(_pp_ctrl_reg(intel_dp)));
1121         }
1122 }
1123
1124 static uint32_t
1125 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
1126 {
1127         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1128         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1129         uint32_t status;
1130         bool done;
1131
1132 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1133         done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
1134                                   msecs_to_jiffies_timeout(10));
1135         if (!done)
1136                 DRM_ERROR("dp aux hw did not signal timeout!\n");
1137 #undef C
1138
1139         return status;
1140 }
1141
1142 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1143 {
1144         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1145
1146         if (index)
1147                 return 0;
1148
1149         /*
1150          * The clock divider is based off the hrawclk, and would like to run at
1151          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
1152          */
1153         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1154 }
1155
1156 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1157 {
1158         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1159
1160         if (index)
1161                 return 0;
1162
1163         /*
1164          * The clock divider is based off the cdclk or PCH rawclk, and would
1165          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
1166          * divide by 2000 and use that
1167          */
1168         if (intel_dp->aux_ch == AUX_CH_A)
1169                 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
1170         else
1171                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1172 }
1173
1174 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1175 {
1176         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1177
1178         if (intel_dp->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1179                 /* Workaround for non-ULT HSW */
1180                 switch (index) {
1181                 case 0: return 63;
1182                 case 1: return 72;
1183                 default: return 0;
1184                 }
1185         }
1186
1187         return ilk_get_aux_clock_divider(intel_dp, index);
1188 }
1189
1190 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1191 {
1192         /*
1193          * SKL doesn't need us to program the AUX clock divider (Hardware will
1194          * derive the clock from CDCLK automatically). We still implement the
1195          * get_aux_clock_divider vfunc to plug-in into the existing code.
1196          */
1197         return index ? 0 : 1;
1198 }
1199
1200 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1201                                      int send_bytes,
1202                                      uint32_t aux_clock_divider)
1203 {
1204         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1205         struct drm_i915_private *dev_priv =
1206                         to_i915(intel_dig_port->base.base.dev);
1207         uint32_t precharge, timeout;
1208
1209         if (IS_GEN6(dev_priv))
1210                 precharge = 3;
1211         else
1212                 precharge = 5;
1213
1214         if (IS_BROADWELL(dev_priv))
1215                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1216         else
1217                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1218
1219         return DP_AUX_CH_CTL_SEND_BUSY |
1220                DP_AUX_CH_CTL_DONE |
1221                DP_AUX_CH_CTL_INTERRUPT |
1222                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1223                timeout |
1224                DP_AUX_CH_CTL_RECEIVE_ERROR |
1225                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1226                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1227                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1228 }
1229
1230 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1231                                       int send_bytes,
1232                                       uint32_t unused)
1233 {
1234         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1235         uint32_t ret;
1236
1237         ret = DP_AUX_CH_CTL_SEND_BUSY |
1238               DP_AUX_CH_CTL_DONE |
1239               DP_AUX_CH_CTL_INTERRUPT |
1240               DP_AUX_CH_CTL_TIME_OUT_ERROR |
1241               DP_AUX_CH_CTL_TIME_OUT_MAX |
1242               DP_AUX_CH_CTL_RECEIVE_ERROR |
1243               (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1244               DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1245               DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1246
1247         if (intel_dig_port->tc_type == TC_PORT_TBT)
1248                 ret |= DP_AUX_CH_CTL_TBT_IO;
1249
1250         return ret;
1251 }
1252
1253 static int
1254 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1255                   const uint8_t *send, int send_bytes,
1256                   uint8_t *recv, int recv_size,
1257                   u32 aux_send_ctl_flags)
1258 {
1259         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1260         struct drm_i915_private *dev_priv =
1261                         to_i915(intel_dig_port->base.base.dev);
1262         i915_reg_t ch_ctl, ch_data[5];
1263         uint32_t aux_clock_divider;
1264         int i, ret, recv_bytes;
1265         uint32_t status;
1266         int try, clock = 0;
1267         bool vdd;
1268
1269         ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1270         for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1271                 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1272
1273         pps_lock(intel_dp);
1274
1275         /*
1276          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1277          * In such cases we want to leave VDD enabled and it's up to upper layers
1278          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1279          * ourselves.
1280          */
1281         vdd = edp_panel_vdd_on(intel_dp);
1282
1283         /* dp aux is extremely sensitive to irq latency, hence request the
1284          * lowest possible wakeup latency and so prevent the cpu from going into
1285          * deep sleep states.
1286          */
1287         pm_qos_update_request(&dev_priv->pm_qos, 0);
1288
1289         intel_dp_check_edp(intel_dp);
1290
1291         /* Try to wait for any previous AUX channel activity */
1292         for (try = 0; try < 3; try++) {
1293                 status = I915_READ_NOTRACE(ch_ctl);
1294                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1295                         break;
1296                 msleep(1);
1297         }
1298
1299         if (try == 3) {
1300                 static u32 last_status = -1;
1301                 const u32 status = I915_READ(ch_ctl);
1302
1303                 if (status != last_status) {
1304                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
1305                              status);
1306                         last_status = status;
1307                 }
1308
1309                 ret = -EBUSY;
1310                 goto out;
1311         }
1312
1313         /* Only 5 data registers! */
1314         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1315                 ret = -E2BIG;
1316                 goto out;
1317         }
1318
1319         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1320                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1321                                                           send_bytes,
1322                                                           aux_clock_divider);
1323
1324                 send_ctl |= aux_send_ctl_flags;
1325
1326                 /* Must try at least 3 times according to DP spec */
1327                 for (try = 0; try < 5; try++) {
1328                         /* Load the send data into the aux channel data registers */
1329                         for (i = 0; i < send_bytes; i += 4)
1330                                 I915_WRITE(ch_data[i >> 2],
1331                                            intel_dp_pack_aux(send + i,
1332                                                              send_bytes - i));
1333
1334                         /* Send the command and wait for it to complete */
1335                         I915_WRITE(ch_ctl, send_ctl);
1336
1337                         status = intel_dp_aux_wait_done(intel_dp);
1338
1339                         /* Clear done status and any errors */
1340                         I915_WRITE(ch_ctl,
1341                                    status |
1342                                    DP_AUX_CH_CTL_DONE |
1343                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
1344                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
1345
1346                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1347                          *   400us delay required for errors and timeouts
1348                          *   Timeout errors from the HW already meet this
1349                          *   requirement so skip to next iteration
1350                          */
1351                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1352                                 continue;
1353
1354                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1355                                 usleep_range(400, 500);
1356                                 continue;
1357                         }
1358                         if (status & DP_AUX_CH_CTL_DONE)
1359                                 goto done;
1360                 }
1361         }
1362
1363         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1364                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1365                 ret = -EBUSY;
1366                 goto out;
1367         }
1368
1369 done:
1370         /* Check for timeout or receive error.
1371          * Timeouts occur when the sink is not connected
1372          */
1373         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1374                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1375                 ret = -EIO;
1376                 goto out;
1377         }
1378
1379         /* Timeouts occur when the device isn't connected, so they're
1380          * "normal" -- don't fill the kernel log with these */
1381         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1382                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1383                 ret = -ETIMEDOUT;
1384                 goto out;
1385         }
1386
1387         /* Unload any bytes sent back from the other side */
1388         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1389                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1390
1391         /*
1392          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1393          * We have no idea of what happened so we return -EBUSY so
1394          * drm layer takes care for the necessary retries.
1395          */
1396         if (recv_bytes == 0 || recv_bytes > 20) {
1397                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1398                               recv_bytes);
1399                 ret = -EBUSY;
1400                 goto out;
1401         }
1402
1403         if (recv_bytes > recv_size)
1404                 recv_bytes = recv_size;
1405
1406         for (i = 0; i < recv_bytes; i += 4)
1407                 intel_dp_unpack_aux(I915_READ(ch_data[i >> 2]),
1408                                     recv + i, recv_bytes - i);
1409
1410         ret = recv_bytes;
1411 out:
1412         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1413
1414         if (vdd)
1415                 edp_panel_vdd_off(intel_dp, false);
1416
1417         pps_unlock(intel_dp);
1418
1419         return ret;
1420 }
1421
1422 #define BARE_ADDRESS_SIZE       3
1423 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1424
1425 static void
1426 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1427                     const struct drm_dp_aux_msg *msg)
1428 {
1429         txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1430         txbuf[1] = (msg->address >> 8) & 0xff;
1431         txbuf[2] = msg->address & 0xff;
1432         txbuf[3] = msg->size - 1;
1433 }
1434
1435 static ssize_t
1436 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1437 {
1438         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1439         uint8_t txbuf[20], rxbuf[20];
1440         size_t txsize, rxsize;
1441         int ret;
1442
1443         intel_dp_aux_header(txbuf, msg);
1444
1445         switch (msg->request & ~DP_AUX_I2C_MOT) {
1446         case DP_AUX_NATIVE_WRITE:
1447         case DP_AUX_I2C_WRITE:
1448         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1449                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1450                 rxsize = 2; /* 0 or 1 data bytes */
1451
1452                 if (WARN_ON(txsize > 20))
1453                         return -E2BIG;
1454
1455                 WARN_ON(!msg->buffer != !msg->size);
1456
1457                 if (msg->buffer)
1458                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1459
1460                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1461                                         rxbuf, rxsize, 0);
1462                 if (ret > 0) {
1463                         msg->reply = rxbuf[0] >> 4;
1464
1465                         if (ret > 1) {
1466                                 /* Number of bytes written in a short write. */
1467                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1468                         } else {
1469                                 /* Return payload size. */
1470                                 ret = msg->size;
1471                         }
1472                 }
1473                 break;
1474
1475         case DP_AUX_NATIVE_READ:
1476         case DP_AUX_I2C_READ:
1477                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1478                 rxsize = msg->size + 1;
1479
1480                 if (WARN_ON(rxsize > 20))
1481                         return -E2BIG;
1482
1483                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1484                                         rxbuf, rxsize, 0);
1485                 if (ret > 0) {
1486                         msg->reply = rxbuf[0] >> 4;
1487                         /*
1488                          * Assume happy day, and copy the data. The caller is
1489                          * expected to check msg->reply before touching it.
1490                          *
1491                          * Return payload size.
1492                          */
1493                         ret--;
1494                         memcpy(msg->buffer, rxbuf + 1, ret);
1495                 }
1496                 break;
1497
1498         default:
1499                 ret = -EINVAL;
1500                 break;
1501         }
1502
1503         return ret;
1504 }
1505
1506 static enum aux_ch intel_aux_ch(struct intel_dp *intel_dp)
1507 {
1508         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1509         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1510         enum port port = encoder->port;
1511         const struct ddi_vbt_port_info *info =
1512                 &dev_priv->vbt.ddi_port_info[port];
1513         enum aux_ch aux_ch;
1514
1515         if (!info->alternate_aux_channel) {
1516                 aux_ch = (enum aux_ch) port;
1517
1518                 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1519                               aux_ch_name(aux_ch), port_name(port));
1520                 return aux_ch;
1521         }
1522
1523         switch (info->alternate_aux_channel) {
1524         case DP_AUX_A:
1525                 aux_ch = AUX_CH_A;
1526                 break;
1527         case DP_AUX_B:
1528                 aux_ch = AUX_CH_B;
1529                 break;
1530         case DP_AUX_C:
1531                 aux_ch = AUX_CH_C;
1532                 break;
1533         case DP_AUX_D:
1534                 aux_ch = AUX_CH_D;
1535                 break;
1536         case DP_AUX_E:
1537                 aux_ch = AUX_CH_E;
1538                 break;
1539         case DP_AUX_F:
1540                 aux_ch = AUX_CH_F;
1541                 break;
1542         default:
1543                 MISSING_CASE(info->alternate_aux_channel);
1544                 aux_ch = AUX_CH_A;
1545                 break;
1546         }
1547
1548         DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1549                       aux_ch_name(aux_ch), port_name(port));
1550
1551         return aux_ch;
1552 }
1553
1554 static enum intel_display_power_domain
1555 intel_aux_power_domain(struct intel_dp *intel_dp)
1556 {
1557         switch (intel_dp->aux_ch) {
1558         case AUX_CH_A:
1559                 return POWER_DOMAIN_AUX_A;
1560         case AUX_CH_B:
1561                 return POWER_DOMAIN_AUX_B;
1562         case AUX_CH_C:
1563                 return POWER_DOMAIN_AUX_C;
1564         case AUX_CH_D:
1565                 return POWER_DOMAIN_AUX_D;
1566         case AUX_CH_E:
1567                 return POWER_DOMAIN_AUX_E;
1568         case AUX_CH_F:
1569                 return POWER_DOMAIN_AUX_F;
1570         default:
1571                 MISSING_CASE(intel_dp->aux_ch);
1572                 return POWER_DOMAIN_AUX_A;
1573         }
1574 }
1575
1576 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1577 {
1578         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1579         enum aux_ch aux_ch = intel_dp->aux_ch;
1580
1581         switch (aux_ch) {
1582         case AUX_CH_B:
1583         case AUX_CH_C:
1584         case AUX_CH_D:
1585                 return DP_AUX_CH_CTL(aux_ch);
1586         default:
1587                 MISSING_CASE(aux_ch);
1588                 return DP_AUX_CH_CTL(AUX_CH_B);
1589         }
1590 }
1591
1592 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1593 {
1594         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1595         enum aux_ch aux_ch = intel_dp->aux_ch;
1596
1597         switch (aux_ch) {
1598         case AUX_CH_B:
1599         case AUX_CH_C:
1600         case AUX_CH_D:
1601                 return DP_AUX_CH_DATA(aux_ch, index);
1602         default:
1603                 MISSING_CASE(aux_ch);
1604                 return DP_AUX_CH_DATA(AUX_CH_B, index);
1605         }
1606 }
1607
1608 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1609 {
1610         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1611         enum aux_ch aux_ch = intel_dp->aux_ch;
1612
1613         switch (aux_ch) {
1614         case AUX_CH_A:
1615                 return DP_AUX_CH_CTL(aux_ch);
1616         case AUX_CH_B:
1617         case AUX_CH_C:
1618         case AUX_CH_D:
1619                 return PCH_DP_AUX_CH_CTL(aux_ch);
1620         default:
1621                 MISSING_CASE(aux_ch);
1622                 return DP_AUX_CH_CTL(AUX_CH_A);
1623         }
1624 }
1625
1626 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1627 {
1628         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1629         enum aux_ch aux_ch = intel_dp->aux_ch;
1630
1631         switch (aux_ch) {
1632         case AUX_CH_A:
1633                 return DP_AUX_CH_DATA(aux_ch, index);
1634         case AUX_CH_B:
1635         case AUX_CH_C:
1636         case AUX_CH_D:
1637                 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1638         default:
1639                 MISSING_CASE(aux_ch);
1640                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1641         }
1642 }
1643
1644 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1645 {
1646         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1647         enum aux_ch aux_ch = intel_dp->aux_ch;
1648
1649         switch (aux_ch) {
1650         case AUX_CH_A:
1651         case AUX_CH_B:
1652         case AUX_CH_C:
1653         case AUX_CH_D:
1654         case AUX_CH_E:
1655         case AUX_CH_F:
1656                 return DP_AUX_CH_CTL(aux_ch);
1657         default:
1658                 MISSING_CASE(aux_ch);
1659                 return DP_AUX_CH_CTL(AUX_CH_A);
1660         }
1661 }
1662
1663 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1664 {
1665         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1666         enum aux_ch aux_ch = intel_dp->aux_ch;
1667
1668         switch (aux_ch) {
1669         case AUX_CH_A:
1670         case AUX_CH_B:
1671         case AUX_CH_C:
1672         case AUX_CH_D:
1673         case AUX_CH_E:
1674         case AUX_CH_F:
1675                 return DP_AUX_CH_DATA(aux_ch, index);
1676         default:
1677                 MISSING_CASE(aux_ch);
1678                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1679         }
1680 }
1681
1682 static void
1683 intel_dp_aux_fini(struct intel_dp *intel_dp)
1684 {
1685         kfree(intel_dp->aux.name);
1686 }
1687
1688 static void
1689 intel_dp_aux_init(struct intel_dp *intel_dp)
1690 {
1691         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1692         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1693
1694         intel_dp->aux_ch = intel_aux_ch(intel_dp);
1695         intel_dp->aux_power_domain = intel_aux_power_domain(intel_dp);
1696
1697         if (INTEL_GEN(dev_priv) >= 9) {
1698                 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1699                 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1700         } else if (HAS_PCH_SPLIT(dev_priv)) {
1701                 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1702                 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1703         } else {
1704                 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1705                 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1706         }
1707
1708         if (INTEL_GEN(dev_priv) >= 9)
1709                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1710         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1711                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1712         else if (HAS_PCH_SPLIT(dev_priv))
1713                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1714         else
1715                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1716
1717         if (INTEL_GEN(dev_priv) >= 9)
1718                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1719         else
1720                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1721
1722         drm_dp_aux_init(&intel_dp->aux);
1723
1724         /* Failure to allocate our preferred name is not critical */
1725         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c",
1726                                        port_name(encoder->port));
1727         intel_dp->aux.transfer = intel_dp_aux_transfer;
1728 }
1729
1730 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1731 {
1732         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1733
1734         return max_rate >= 540000;
1735 }
1736
1737 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1738 {
1739         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1740
1741         return max_rate >= 810000;
1742 }
1743
1744 static void
1745 intel_dp_set_clock(struct intel_encoder *encoder,
1746                    struct intel_crtc_state *pipe_config)
1747 {
1748         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1749         const struct dp_link_dpll *divisor = NULL;
1750         int i, count = 0;
1751
1752         if (IS_G4X(dev_priv)) {
1753                 divisor = g4x_dpll;
1754                 count = ARRAY_SIZE(g4x_dpll);
1755         } else if (HAS_PCH_SPLIT(dev_priv)) {
1756                 divisor = pch_dpll;
1757                 count = ARRAY_SIZE(pch_dpll);
1758         } else if (IS_CHERRYVIEW(dev_priv)) {
1759                 divisor = chv_dpll;
1760                 count = ARRAY_SIZE(chv_dpll);
1761         } else if (IS_VALLEYVIEW(dev_priv)) {
1762                 divisor = vlv_dpll;
1763                 count = ARRAY_SIZE(vlv_dpll);
1764         }
1765
1766         if (divisor && count) {
1767                 for (i = 0; i < count; i++) {
1768                         if (pipe_config->port_clock == divisor[i].clock) {
1769                                 pipe_config->dpll = divisor[i].dpll;
1770                                 pipe_config->clock_set = true;
1771                                 break;
1772                         }
1773                 }
1774         }
1775 }
1776
1777 static void snprintf_int_array(char *str, size_t len,
1778                                const int *array, int nelem)
1779 {
1780         int i;
1781
1782         str[0] = '\0';
1783
1784         for (i = 0; i < nelem; i++) {
1785                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1786                 if (r >= len)
1787                         return;
1788                 str += r;
1789                 len -= r;
1790         }
1791 }
1792
1793 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1794 {
1795         char str[128]; /* FIXME: too big for stack? */
1796
1797         if ((drm_debug & DRM_UT_KMS) == 0)
1798                 return;
1799
1800         snprintf_int_array(str, sizeof(str),
1801                            intel_dp->source_rates, intel_dp->num_source_rates);
1802         DRM_DEBUG_KMS("source rates: %s\n", str);
1803
1804         snprintf_int_array(str, sizeof(str),
1805                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1806         DRM_DEBUG_KMS("sink rates: %s\n", str);
1807
1808         snprintf_int_array(str, sizeof(str),
1809                            intel_dp->common_rates, intel_dp->num_common_rates);
1810         DRM_DEBUG_KMS("common rates: %s\n", str);
1811 }
1812
1813 int
1814 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1815 {
1816         int len;
1817
1818         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1819         if (WARN_ON(len <= 0))
1820                 return 162000;
1821
1822         return intel_dp->common_rates[len - 1];
1823 }
1824
1825 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1826 {
1827         int i = intel_dp_rate_index(intel_dp->sink_rates,
1828                                     intel_dp->num_sink_rates, rate);
1829
1830         if (WARN_ON(i < 0))
1831                 i = 0;
1832
1833         return i;
1834 }
1835
1836 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1837                            uint8_t *link_bw, uint8_t *rate_select)
1838 {
1839         /* eDP 1.4 rate select method. */
1840         if (intel_dp->use_rate_select) {
1841                 *link_bw = 0;
1842                 *rate_select =
1843                         intel_dp_rate_select(intel_dp, port_clock);
1844         } else {
1845                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1846                 *rate_select = 0;
1847         }
1848 }
1849
1850 struct link_config_limits {
1851         int min_clock, max_clock;
1852         int min_lane_count, max_lane_count;
1853         int min_bpp, max_bpp;
1854 };
1855
1856 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1857                                 struct intel_crtc_state *pipe_config)
1858 {
1859         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1860         struct intel_connector *intel_connector = intel_dp->attached_connector;
1861         int bpp, bpc;
1862
1863         bpp = pipe_config->pipe_bpp;
1864         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1865
1866         if (bpc > 0)
1867                 bpp = min(bpp, 3*bpc);
1868
1869         if (intel_dp_is_edp(intel_dp)) {
1870                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1871                 if (intel_connector->base.display_info.bpc == 0 &&
1872                     dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1873                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1874                                       dev_priv->vbt.edp.bpp);
1875                         bpp = dev_priv->vbt.edp.bpp;
1876                 }
1877         }
1878
1879         return bpp;
1880 }
1881
1882 /* Adjust link config limits based on compliance test requests. */
1883 static void
1884 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1885                                   struct intel_crtc_state *pipe_config,
1886                                   struct link_config_limits *limits)
1887 {
1888         /* For DP Compliance we override the computed bpp for the pipe */
1889         if (intel_dp->compliance.test_data.bpc != 0) {
1890                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1891
1892                 limits->min_bpp = limits->max_bpp = bpp;
1893                 pipe_config->dither_force_disable = bpp == 6 * 3;
1894
1895                 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
1896         }
1897
1898         /* Use values requested by Compliance Test Request */
1899         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1900                 int index;
1901
1902                 /* Validate the compliance test data since max values
1903                  * might have changed due to link train fallback.
1904                  */
1905                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1906                                                intel_dp->compliance.test_lane_count)) {
1907                         index = intel_dp_rate_index(intel_dp->common_rates,
1908                                                     intel_dp->num_common_rates,
1909                                                     intel_dp->compliance.test_link_rate);
1910                         if (index >= 0)
1911                                 limits->min_clock = limits->max_clock = index;
1912                         limits->min_lane_count = limits->max_lane_count =
1913                                 intel_dp->compliance.test_lane_count;
1914                 }
1915         }
1916 }
1917
1918 /* Optimize link config in order: max bpp, min clock, min lanes */
1919 static bool
1920 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1921                                   struct intel_crtc_state *pipe_config,
1922                                   const struct link_config_limits *limits)
1923 {
1924         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1925         int bpp, clock, lane_count;
1926         int mode_rate, link_clock, link_avail;
1927
1928         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1929                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1930                                                    bpp);
1931
1932                 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1933                         for (lane_count = limits->min_lane_count;
1934                              lane_count <= limits->max_lane_count;
1935                              lane_count <<= 1) {
1936                                 link_clock = intel_dp->common_rates[clock];
1937                                 link_avail = intel_dp_max_data_rate(link_clock,
1938                                                                     lane_count);
1939
1940                                 if (mode_rate <= link_avail) {
1941                                         pipe_config->lane_count = lane_count;
1942                                         pipe_config->pipe_bpp = bpp;
1943                                         pipe_config->port_clock = link_clock;
1944
1945                                         return true;
1946                                 }
1947                         }
1948                 }
1949         }
1950
1951         return false;
1952 }
1953
1954 static bool
1955 intel_dp_compute_link_config(struct intel_encoder *encoder,
1956                              struct intel_crtc_state *pipe_config)
1957 {
1958         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1959         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1960         struct link_config_limits limits;
1961         int common_len;
1962
1963         common_len = intel_dp_common_len_rate_limit(intel_dp,
1964                                                     intel_dp->max_link_rate);
1965
1966         /* No common link rates between source and sink */
1967         WARN_ON(common_len <= 0);
1968
1969         limits.min_clock = 0;
1970         limits.max_clock = common_len - 1;
1971
1972         limits.min_lane_count = 1;
1973         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
1974
1975         limits.min_bpp = 6 * 3;
1976         limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
1977
1978         if (intel_dp_is_edp(intel_dp)) {
1979                 /*
1980                  * Use the maximum clock and number of lanes the eDP panel
1981                  * advertizes being capable of. The panels are generally
1982                  * designed to support only a single clock and lane
1983                  * configuration, and typically these values correspond to the
1984                  * native resolution of the panel.
1985                  */
1986                 limits.min_lane_count = limits.max_lane_count;
1987                 limits.min_clock = limits.max_clock;
1988         }
1989
1990         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
1991
1992         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1993                       "max rate %d max bpp %d pixel clock %iKHz\n",
1994                       limits.max_lane_count,
1995                       intel_dp->common_rates[limits.max_clock],
1996                       limits.max_bpp, adjusted_mode->crtc_clock);
1997
1998         /*
1999          * Optimize for slow and wide. This is the place to add alternative
2000          * optimization policy.
2001          */
2002         if (!intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits))
2003                 return false;
2004
2005         DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
2006                       pipe_config->lane_count, pipe_config->port_clock,
2007                       pipe_config->pipe_bpp);
2008
2009         DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2010                       intel_dp_link_required(adjusted_mode->crtc_clock,
2011                                              pipe_config->pipe_bpp),
2012                       intel_dp_max_data_rate(pipe_config->port_clock,
2013                                              pipe_config->lane_count));
2014
2015         return true;
2016 }
2017
2018 bool
2019 intel_dp_compute_config(struct intel_encoder *encoder,
2020                         struct intel_crtc_state *pipe_config,
2021                         struct drm_connector_state *conn_state)
2022 {
2023         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2024         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2025         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2026         enum port port = encoder->port;
2027         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
2028         struct intel_connector *intel_connector = intel_dp->attached_connector;
2029         struct intel_digital_connector_state *intel_conn_state =
2030                 to_intel_digital_connector_state(conn_state);
2031         bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
2032                                            DP_DPCD_QUIRK_CONSTANT_N);
2033
2034         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
2035                 pipe_config->has_pch_encoder = true;
2036
2037         pipe_config->has_drrs = false;
2038         if (IS_G4X(dev_priv) || port == PORT_A)
2039                 pipe_config->has_audio = false;
2040         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2041                 pipe_config->has_audio = intel_dp->has_audio;
2042         else
2043                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
2044
2045         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2046                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
2047                                        adjusted_mode);
2048
2049                 if (INTEL_GEN(dev_priv) >= 9) {
2050                         int ret;
2051
2052                         ret = skl_update_scaler_crtc(pipe_config);
2053                         if (ret)
2054                                 return ret;
2055                 }
2056
2057                 if (HAS_GMCH_DISPLAY(dev_priv))
2058                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
2059                                                  conn_state->scaling_mode);
2060                 else
2061                         intel_pch_panel_fitting(intel_crtc, pipe_config,
2062                                                 conn_state->scaling_mode);
2063         }
2064
2065         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2066                 return false;
2067
2068         if (HAS_GMCH_DISPLAY(dev_priv) &&
2069             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2070                 return false;
2071
2072         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2073                 return false;
2074
2075         if (!intel_dp_compute_link_config(encoder, pipe_config))
2076                 return false;
2077
2078         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2079                 /*
2080                  * See:
2081                  * CEA-861-E - 5.1 Default Encoding Parameters
2082                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2083                  */
2084                 pipe_config->limited_color_range =
2085                         pipe_config->pipe_bpp != 18 &&
2086                         drm_default_rgb_quant_range(adjusted_mode) ==
2087                         HDMI_QUANTIZATION_RANGE_LIMITED;
2088         } else {
2089                 pipe_config->limited_color_range =
2090                         intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2091         }
2092
2093         intel_link_compute_m_n(pipe_config->pipe_bpp, pipe_config->lane_count,
2094                                adjusted_mode->crtc_clock,
2095                                pipe_config->port_clock,
2096                                &pipe_config->dp_m_n,
2097                                constant_n);
2098
2099         if (intel_connector->panel.downclock_mode != NULL &&
2100                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
2101                         pipe_config->has_drrs = true;
2102                         intel_link_compute_m_n(pipe_config->pipe_bpp,
2103                                                pipe_config->lane_count,
2104                                                intel_connector->panel.downclock_mode->clock,
2105                                                pipe_config->port_clock,
2106                                                &pipe_config->dp_m2_n2,
2107                                                constant_n);
2108         }
2109
2110         if (!HAS_DDI(dev_priv))
2111                 intel_dp_set_clock(encoder, pipe_config);
2112
2113         intel_psr_compute_config(intel_dp, pipe_config);
2114
2115         return true;
2116 }
2117
2118 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2119                               int link_rate, uint8_t lane_count,
2120                               bool link_mst)
2121 {
2122         intel_dp->link_trained = false;
2123         intel_dp->link_rate = link_rate;
2124         intel_dp->lane_count = lane_count;
2125         intel_dp->link_mst = link_mst;
2126 }
2127
2128 static void intel_dp_prepare(struct intel_encoder *encoder,
2129                              const struct intel_crtc_state *pipe_config)
2130 {
2131         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2132         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2133         enum port port = encoder->port;
2134         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2135         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2136
2137         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
2138                                  pipe_config->lane_count,
2139                                  intel_crtc_has_type(pipe_config,
2140                                                      INTEL_OUTPUT_DP_MST));
2141
2142         /*
2143          * There are four kinds of DP registers:
2144          *
2145          *      IBX PCH
2146          *      SNB CPU
2147          *      IVB CPU
2148          *      CPT PCH
2149          *
2150          * IBX PCH and CPU are the same for almost everything,
2151          * except that the CPU DP PLL is configured in this
2152          * register
2153          *
2154          * CPT PCH is quite different, having many bits moved
2155          * to the TRANS_DP_CTL register instead. That
2156          * configuration happens (oddly) in ironlake_pch_enable
2157          */
2158
2159         /* Preserve the BIOS-computed detected bit. This is
2160          * supposed to be read-only.
2161          */
2162         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
2163
2164         /* Handle DP bits in common between all three register formats */
2165         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
2166         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
2167
2168         /* Split out the IBX/CPU vs CPT settings */
2169
2170         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
2171                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2172                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2173                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2174                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2175                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2176
2177                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2178                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2179
2180                 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
2181         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2182                 u32 trans_dp;
2183
2184                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2185
2186                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2187                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2188                         trans_dp |= TRANS_DP_ENH_FRAMING;
2189                 else
2190                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
2191                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
2192         } else {
2193                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2194                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
2195
2196                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2197                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2198                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2199                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2200                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2201
2202                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2203                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2204
2205                 if (IS_CHERRYVIEW(dev_priv))
2206                         intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2207                 else
2208                         intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2209         }
2210 }
2211
2212 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
2213 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
2214
2215 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
2216 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
2217
2218 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2219 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
2220
2221 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2222
2223 static void wait_panel_status(struct intel_dp *intel_dp,
2224                                        u32 mask,
2225                                        u32 value)
2226 {
2227         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2228         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2229
2230         lockdep_assert_held(&dev_priv->pps_mutex);
2231
2232         intel_pps_verify_state(intel_dp);
2233
2234         pp_stat_reg = _pp_stat_reg(intel_dp);
2235         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2236
2237         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
2238                         mask, value,
2239                         I915_READ(pp_stat_reg),
2240                         I915_READ(pp_ctrl_reg));
2241
2242         if (intel_wait_for_register(dev_priv,
2243                                     pp_stat_reg, mask, value,
2244                                     5000))
2245                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
2246                                 I915_READ(pp_stat_reg),
2247                                 I915_READ(pp_ctrl_reg));
2248
2249         DRM_DEBUG_KMS("Wait complete\n");
2250 }
2251
2252 static void wait_panel_on(struct intel_dp *intel_dp)
2253 {
2254         DRM_DEBUG_KMS("Wait for panel power on\n");
2255         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2256 }
2257
2258 static void wait_panel_off(struct intel_dp *intel_dp)
2259 {
2260         DRM_DEBUG_KMS("Wait for panel power off time\n");
2261         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2262 }
2263
2264 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2265 {
2266         ktime_t panel_power_on_time;
2267         s64 panel_power_off_duration;
2268
2269         DRM_DEBUG_KMS("Wait for panel power cycle\n");
2270
2271         /* take the difference of currrent time and panel power off time
2272          * and then make panel wait for t11_t12 if needed. */
2273         panel_power_on_time = ktime_get_boottime();
2274         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2275
2276         /* When we disable the VDD override bit last we have to do the manual
2277          * wait. */
2278         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2279                 wait_remaining_ms_from_jiffies(jiffies,
2280                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2281
2282         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2283 }
2284
2285 static void wait_backlight_on(struct intel_dp *intel_dp)
2286 {
2287         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2288                                        intel_dp->backlight_on_delay);
2289 }
2290
2291 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2292 {
2293         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2294                                        intel_dp->backlight_off_delay);
2295 }
2296
2297 /* Read the current pp_control value, unlocking the register if it
2298  * is locked
2299  */
2300
2301 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2302 {
2303         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2304         u32 control;
2305
2306         lockdep_assert_held(&dev_priv->pps_mutex);
2307
2308         control = I915_READ(_pp_ctrl_reg(intel_dp));
2309         if (WARN_ON(!HAS_DDI(dev_priv) &&
2310                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2311                 control &= ~PANEL_UNLOCK_MASK;
2312                 control |= PANEL_UNLOCK_REGS;
2313         }
2314         return control;
2315 }
2316
2317 /*
2318  * Must be paired with edp_panel_vdd_off().
2319  * Must hold pps_mutex around the whole on/off sequence.
2320  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2321  */
2322 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2323 {
2324         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2325         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2326         u32 pp;
2327         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2328         bool need_to_disable = !intel_dp->want_panel_vdd;
2329
2330         lockdep_assert_held(&dev_priv->pps_mutex);
2331
2332         if (!intel_dp_is_edp(intel_dp))
2333                 return false;
2334
2335         cancel_delayed_work(&intel_dp->panel_vdd_work);
2336         intel_dp->want_panel_vdd = true;
2337
2338         if (edp_have_panel_vdd(intel_dp))
2339                 return need_to_disable;
2340
2341         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
2342
2343         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2344                       port_name(intel_dig_port->base.port));
2345
2346         if (!edp_have_panel_power(intel_dp))
2347                 wait_panel_power_cycle(intel_dp);
2348
2349         pp = ironlake_get_pp_control(intel_dp);
2350         pp |= EDP_FORCE_VDD;
2351
2352         pp_stat_reg = _pp_stat_reg(intel_dp);
2353         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2354
2355         I915_WRITE(pp_ctrl_reg, pp);
2356         POSTING_READ(pp_ctrl_reg);
2357         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2358                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2359         /*
2360          * If the panel wasn't on, delay before accessing aux channel
2361          */
2362         if (!edp_have_panel_power(intel_dp)) {
2363                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2364                               port_name(intel_dig_port->base.port));
2365                 msleep(intel_dp->panel_power_up_delay);
2366         }
2367
2368         return need_to_disable;
2369 }
2370
2371 /*
2372  * Must be paired with intel_edp_panel_vdd_off() or
2373  * intel_edp_panel_off().
2374  * Nested calls to these functions are not allowed since
2375  * we drop the lock. Caller must use some higher level
2376  * locking to prevent nested calls from other threads.
2377  */
2378 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2379 {
2380         bool vdd;
2381
2382         if (!intel_dp_is_edp(intel_dp))
2383                 return;
2384
2385         pps_lock(intel_dp);
2386         vdd = edp_panel_vdd_on(intel_dp);
2387         pps_unlock(intel_dp);
2388
2389         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2390              port_name(dp_to_dig_port(intel_dp)->base.port));
2391 }
2392
2393 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2394 {
2395         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2396         struct intel_digital_port *intel_dig_port =
2397                 dp_to_dig_port(intel_dp);
2398         u32 pp;
2399         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2400
2401         lockdep_assert_held(&dev_priv->pps_mutex);
2402
2403         WARN_ON(intel_dp->want_panel_vdd);
2404
2405         if (!edp_have_panel_vdd(intel_dp))
2406                 return;
2407
2408         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2409                       port_name(intel_dig_port->base.port));
2410
2411         pp = ironlake_get_pp_control(intel_dp);
2412         pp &= ~EDP_FORCE_VDD;
2413
2414         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2415         pp_stat_reg = _pp_stat_reg(intel_dp);
2416
2417         I915_WRITE(pp_ctrl_reg, pp);
2418         POSTING_READ(pp_ctrl_reg);
2419
2420         /* Make sure sequencer is idle before allowing subsequent activity */
2421         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2422         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2423
2424         if ((pp & PANEL_POWER_ON) == 0)
2425                 intel_dp->panel_power_off_time = ktime_get_boottime();
2426
2427         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2428 }
2429
2430 static void edp_panel_vdd_work(struct work_struct *__work)
2431 {
2432         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2433                                                  struct intel_dp, panel_vdd_work);
2434
2435         pps_lock(intel_dp);
2436         if (!intel_dp->want_panel_vdd)
2437                 edp_panel_vdd_off_sync(intel_dp);
2438         pps_unlock(intel_dp);
2439 }
2440
2441 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2442 {
2443         unsigned long delay;
2444
2445         /*
2446          * Queue the timer to fire a long time from now (relative to the power
2447          * down delay) to keep the panel power up across a sequence of
2448          * operations.
2449          */
2450         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2451         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2452 }
2453
2454 /*
2455  * Must be paired with edp_panel_vdd_on().
2456  * Must hold pps_mutex around the whole on/off sequence.
2457  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2458  */
2459 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2460 {
2461         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2462
2463         lockdep_assert_held(&dev_priv->pps_mutex);
2464
2465         if (!intel_dp_is_edp(intel_dp))
2466                 return;
2467
2468         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2469              port_name(dp_to_dig_port(intel_dp)->base.port));
2470
2471         intel_dp->want_panel_vdd = false;
2472
2473         if (sync)
2474                 edp_panel_vdd_off_sync(intel_dp);
2475         else
2476                 edp_panel_vdd_schedule_off(intel_dp);
2477 }
2478
2479 static void edp_panel_on(struct intel_dp *intel_dp)
2480 {
2481         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2482         u32 pp;
2483         i915_reg_t pp_ctrl_reg;
2484
2485         lockdep_assert_held(&dev_priv->pps_mutex);
2486
2487         if (!intel_dp_is_edp(intel_dp))
2488                 return;
2489
2490         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2491                       port_name(dp_to_dig_port(intel_dp)->base.port));
2492
2493         if (WARN(edp_have_panel_power(intel_dp),
2494                  "eDP port %c panel power already on\n",
2495                  port_name(dp_to_dig_port(intel_dp)->base.port)))
2496                 return;
2497
2498         wait_panel_power_cycle(intel_dp);
2499
2500         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2501         pp = ironlake_get_pp_control(intel_dp);
2502         if (IS_GEN5(dev_priv)) {
2503                 /* ILK workaround: disable reset around power sequence */
2504                 pp &= ~PANEL_POWER_RESET;
2505                 I915_WRITE(pp_ctrl_reg, pp);
2506                 POSTING_READ(pp_ctrl_reg);
2507         }
2508
2509         pp |= PANEL_POWER_ON;
2510         if (!IS_GEN5(dev_priv))
2511                 pp |= PANEL_POWER_RESET;
2512
2513         I915_WRITE(pp_ctrl_reg, pp);
2514         POSTING_READ(pp_ctrl_reg);
2515
2516         wait_panel_on(intel_dp);
2517         intel_dp->last_power_on = jiffies;
2518
2519         if (IS_GEN5(dev_priv)) {
2520                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2521                 I915_WRITE(pp_ctrl_reg, pp);
2522                 POSTING_READ(pp_ctrl_reg);
2523         }
2524 }
2525
2526 void intel_edp_panel_on(struct intel_dp *intel_dp)
2527 {
2528         if (!intel_dp_is_edp(intel_dp))
2529                 return;
2530
2531         pps_lock(intel_dp);
2532         edp_panel_on(intel_dp);
2533         pps_unlock(intel_dp);
2534 }
2535
2536
2537 static void edp_panel_off(struct intel_dp *intel_dp)
2538 {
2539         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2540         u32 pp;
2541         i915_reg_t pp_ctrl_reg;
2542
2543         lockdep_assert_held(&dev_priv->pps_mutex);
2544
2545         if (!intel_dp_is_edp(intel_dp))
2546                 return;
2547
2548         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2549                       port_name(dp_to_dig_port(intel_dp)->base.port));
2550
2551         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2552              port_name(dp_to_dig_port(intel_dp)->base.port));
2553
2554         pp = ironlake_get_pp_control(intel_dp);
2555         /* We need to switch off panel power _and_ force vdd, for otherwise some
2556          * panels get very unhappy and cease to work. */
2557         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2558                 EDP_BLC_ENABLE);
2559
2560         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2561
2562         intel_dp->want_panel_vdd = false;
2563
2564         I915_WRITE(pp_ctrl_reg, pp);
2565         POSTING_READ(pp_ctrl_reg);
2566
2567         wait_panel_off(intel_dp);
2568         intel_dp->panel_power_off_time = ktime_get_boottime();
2569
2570         /* We got a reference when we enabled the VDD. */
2571         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2572 }
2573
2574 void intel_edp_panel_off(struct intel_dp *intel_dp)
2575 {
2576         if (!intel_dp_is_edp(intel_dp))
2577                 return;
2578
2579         pps_lock(intel_dp);
2580         edp_panel_off(intel_dp);
2581         pps_unlock(intel_dp);
2582 }
2583
2584 /* Enable backlight in the panel power control. */
2585 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2586 {
2587         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2588         u32 pp;
2589         i915_reg_t pp_ctrl_reg;
2590
2591         /*
2592          * If we enable the backlight right away following a panel power
2593          * on, we may see slight flicker as the panel syncs with the eDP
2594          * link.  So delay a bit to make sure the image is solid before
2595          * allowing it to appear.
2596          */
2597         wait_backlight_on(intel_dp);
2598
2599         pps_lock(intel_dp);
2600
2601         pp = ironlake_get_pp_control(intel_dp);
2602         pp |= EDP_BLC_ENABLE;
2603
2604         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2605
2606         I915_WRITE(pp_ctrl_reg, pp);
2607         POSTING_READ(pp_ctrl_reg);
2608
2609         pps_unlock(intel_dp);
2610 }
2611
2612 /* Enable backlight PWM and backlight PP control. */
2613 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2614                             const struct drm_connector_state *conn_state)
2615 {
2616         struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2617
2618         if (!intel_dp_is_edp(intel_dp))
2619                 return;
2620
2621         DRM_DEBUG_KMS("\n");
2622
2623         intel_panel_enable_backlight(crtc_state, conn_state);
2624         _intel_edp_backlight_on(intel_dp);
2625 }
2626
2627 /* Disable backlight in the panel power control. */
2628 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2629 {
2630         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2631         u32 pp;
2632         i915_reg_t pp_ctrl_reg;
2633
2634         if (!intel_dp_is_edp(intel_dp))
2635                 return;
2636
2637         pps_lock(intel_dp);
2638
2639         pp = ironlake_get_pp_control(intel_dp);
2640         pp &= ~EDP_BLC_ENABLE;
2641
2642         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2643
2644         I915_WRITE(pp_ctrl_reg, pp);
2645         POSTING_READ(pp_ctrl_reg);
2646
2647         pps_unlock(intel_dp);
2648
2649         intel_dp->last_backlight_off = jiffies;
2650         edp_wait_backlight_off(intel_dp);
2651 }
2652
2653 /* Disable backlight PP control and backlight PWM. */
2654 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2655 {
2656         struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2657
2658         if (!intel_dp_is_edp(intel_dp))
2659                 return;
2660
2661         DRM_DEBUG_KMS("\n");
2662
2663         _intel_edp_backlight_off(intel_dp);
2664         intel_panel_disable_backlight(old_conn_state);
2665 }
2666
2667 /*
2668  * Hook for controlling the panel power control backlight through the bl_power
2669  * sysfs attribute. Take care to handle multiple calls.
2670  */
2671 static void intel_edp_backlight_power(struct intel_connector *connector,
2672                                       bool enable)
2673 {
2674         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2675         bool is_enabled;
2676
2677         pps_lock(intel_dp);
2678         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2679         pps_unlock(intel_dp);
2680
2681         if (is_enabled == enable)
2682                 return;
2683
2684         DRM_DEBUG_KMS("panel power control backlight %s\n",
2685                       enable ? "enable" : "disable");
2686
2687         if (enable)
2688                 _intel_edp_backlight_on(intel_dp);
2689         else
2690                 _intel_edp_backlight_off(intel_dp);
2691 }
2692
2693 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2694 {
2695         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2696         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2697         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2698
2699         I915_STATE_WARN(cur_state != state,
2700                         "DP port %c state assertion failure (expected %s, current %s)\n",
2701                         port_name(dig_port->base.port),
2702                         onoff(state), onoff(cur_state));
2703 }
2704 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2705
2706 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2707 {
2708         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2709
2710         I915_STATE_WARN(cur_state != state,
2711                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2712                         onoff(state), onoff(cur_state));
2713 }
2714 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2715 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2716
2717 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2718                                 const struct intel_crtc_state *pipe_config)
2719 {
2720         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2721         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2722
2723         assert_pipe_disabled(dev_priv, crtc->pipe);
2724         assert_dp_port_disabled(intel_dp);
2725         assert_edp_pll_disabled(dev_priv);
2726
2727         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2728                       pipe_config->port_clock);
2729
2730         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2731
2732         if (pipe_config->port_clock == 162000)
2733                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2734         else
2735                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2736
2737         I915_WRITE(DP_A, intel_dp->DP);
2738         POSTING_READ(DP_A);
2739         udelay(500);
2740
2741         /*
2742          * [DevILK] Work around required when enabling DP PLL
2743          * while a pipe is enabled going to FDI:
2744          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2745          * 2. Program DP PLL enable
2746          */
2747         if (IS_GEN5(dev_priv))
2748                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2749
2750         intel_dp->DP |= DP_PLL_ENABLE;
2751
2752         I915_WRITE(DP_A, intel_dp->DP);
2753         POSTING_READ(DP_A);
2754         udelay(200);
2755 }
2756
2757 static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
2758                                  const struct intel_crtc_state *old_crtc_state)
2759 {
2760         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
2761         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2762
2763         assert_pipe_disabled(dev_priv, crtc->pipe);
2764         assert_dp_port_disabled(intel_dp);
2765         assert_edp_pll_enabled(dev_priv);
2766
2767         DRM_DEBUG_KMS("disabling eDP PLL\n");
2768
2769         intel_dp->DP &= ~DP_PLL_ENABLE;
2770
2771         I915_WRITE(DP_A, intel_dp->DP);
2772         POSTING_READ(DP_A);
2773         udelay(200);
2774 }
2775
2776 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2777 {
2778         /*
2779          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2780          * be capable of signalling downstream hpd with a long pulse.
2781          * Whether or not that means D3 is safe to use is not clear,
2782          * but let's assume so until proven otherwise.
2783          *
2784          * FIXME should really check all downstream ports...
2785          */
2786         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2787                 intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
2788                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2789 }
2790
2791 /* If the sink supports it, try to set the power state appropriately */
2792 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2793 {
2794         int ret, i;
2795
2796         /* Should have a valid DPCD by this point */
2797         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2798                 return;
2799
2800         if (mode != DRM_MODE_DPMS_ON) {
2801                 if (downstream_hpd_needs_d0(intel_dp))
2802                         return;
2803
2804                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2805                                          DP_SET_POWER_D3);
2806         } else {
2807                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2808
2809                 /*
2810                  * When turning on, we need to retry for 1ms to give the sink
2811                  * time to wake up.
2812                  */
2813                 for (i = 0; i < 3; i++) {
2814                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2815                                                  DP_SET_POWER_D0);
2816                         if (ret == 1)
2817                                 break;
2818                         msleep(1);
2819                 }
2820
2821                 if (ret == 1 && lspcon->active)
2822                         lspcon_wait_pcon_mode(lspcon);
2823         }
2824
2825         if (ret != 1)
2826                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2827                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2828 }
2829
2830 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
2831                                  enum port port, enum pipe *pipe)
2832 {
2833         enum pipe p;
2834
2835         for_each_pipe(dev_priv, p) {
2836                 u32 val = I915_READ(TRANS_DP_CTL(p));
2837
2838                 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
2839                         *pipe = p;
2840                         return true;
2841                 }
2842         }
2843
2844         DRM_DEBUG_KMS("No pipe for DP port %c found\n", port_name(port));
2845
2846         /* must initialize pipe to something for the asserts */
2847         *pipe = PIPE_A;
2848
2849         return false;
2850 }
2851
2852 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
2853                            i915_reg_t dp_reg, enum port port,
2854                            enum pipe *pipe)
2855 {
2856         bool ret;
2857         u32 val;
2858
2859         val = I915_READ(dp_reg);
2860
2861         ret = val & DP_PORT_EN;
2862
2863         /* asserts want to know the pipe even if the port is disabled */
2864         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
2865                 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
2866         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
2867                 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
2868         else if (IS_CHERRYVIEW(dev_priv))
2869                 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
2870         else
2871                 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
2872
2873         return ret;
2874 }
2875
2876 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2877                                   enum pipe *pipe)
2878 {
2879         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2880         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2881         bool ret;
2882
2883         if (!intel_display_power_get_if_enabled(dev_priv,
2884                                                 encoder->power_domain))
2885                 return false;
2886
2887         ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
2888                                     encoder->port, pipe);
2889
2890         intel_display_power_put(dev_priv, encoder->power_domain);
2891
2892         return ret;
2893 }
2894
2895 static void intel_dp_get_config(struct intel_encoder *encoder,
2896                                 struct intel_crtc_state *pipe_config)
2897 {
2898         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2899         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2900         u32 tmp, flags = 0;
2901         enum port port = encoder->port;
2902         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2903
2904         if (encoder->type == INTEL_OUTPUT_EDP)
2905                 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
2906         else
2907                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
2908
2909         tmp = I915_READ(intel_dp->output_reg);
2910
2911         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2912
2913         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2914                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2915
2916                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2917                         flags |= DRM_MODE_FLAG_PHSYNC;
2918                 else
2919                         flags |= DRM_MODE_FLAG_NHSYNC;
2920
2921                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2922                         flags |= DRM_MODE_FLAG_PVSYNC;
2923                 else
2924                         flags |= DRM_MODE_FLAG_NVSYNC;
2925         } else {
2926                 if (tmp & DP_SYNC_HS_HIGH)
2927                         flags |= DRM_MODE_FLAG_PHSYNC;
2928                 else
2929                         flags |= DRM_MODE_FLAG_NHSYNC;
2930
2931                 if (tmp & DP_SYNC_VS_HIGH)
2932                         flags |= DRM_MODE_FLAG_PVSYNC;
2933                 else
2934                         flags |= DRM_MODE_FLAG_NVSYNC;
2935         }
2936
2937         pipe_config->base.adjusted_mode.flags |= flags;
2938
2939         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
2940                 pipe_config->limited_color_range = true;
2941
2942         pipe_config->lane_count =
2943                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2944
2945         intel_dp_get_m_n(crtc, pipe_config);
2946
2947         if (port == PORT_A) {
2948                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2949                         pipe_config->port_clock = 162000;
2950                 else
2951                         pipe_config->port_clock = 270000;
2952         }
2953
2954         pipe_config->base.adjusted_mode.crtc_clock =
2955                 intel_dotclock_calculate(pipe_config->port_clock,
2956                                          &pipe_config->dp_m_n);
2957
2958         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2959             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2960                 /*
2961                  * This is a big fat ugly hack.
2962                  *
2963                  * Some machines in UEFI boot mode provide us a VBT that has 18
2964                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2965                  * unknown we fail to light up. Yet the same BIOS boots up with
2966                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2967                  * max, not what it tells us to use.
2968                  *
2969                  * Note: This will still be broken if the eDP panel is not lit
2970                  * up by the BIOS, and thus we can't get the mode at module
2971                  * load.
2972                  */
2973                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2974                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2975                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2976         }
2977 }
2978
2979 static void intel_disable_dp(struct intel_encoder *encoder,
2980                              const struct intel_crtc_state *old_crtc_state,
2981                              const struct drm_connector_state *old_conn_state)
2982 {
2983         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2984
2985         intel_dp->link_trained = false;
2986
2987         if (old_crtc_state->has_audio)
2988                 intel_audio_codec_disable(encoder,
2989                                           old_crtc_state, old_conn_state);
2990
2991         /* Make sure the panel is off before trying to change the mode. But also
2992          * ensure that we have vdd while we switch off the panel. */
2993         intel_edp_panel_vdd_on(intel_dp);
2994         intel_edp_backlight_off(old_conn_state);
2995         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2996         intel_edp_panel_off(intel_dp);
2997 }
2998
2999 static void g4x_disable_dp(struct intel_encoder *encoder,
3000                            const struct intel_crtc_state *old_crtc_state,
3001                            const struct drm_connector_state *old_conn_state)
3002 {
3003         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3004 }
3005
3006 static void vlv_disable_dp(struct intel_encoder *encoder,
3007                            const struct intel_crtc_state *old_crtc_state,
3008                            const struct drm_connector_state *old_conn_state)
3009 {
3010         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3011 }
3012
3013 static void g4x_post_disable_dp(struct intel_encoder *encoder,
3014                                 const struct intel_crtc_state *old_crtc_state,
3015                                 const struct drm_connector_state *old_conn_state)
3016 {
3017         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3018         enum port port = encoder->port;
3019
3020         /*
3021          * Bspec does not list a specific disable sequence for g4x DP.
3022          * Follow the ilk+ sequence (disable pipe before the port) for
3023          * g4x DP as it does not suffer from underruns like the normal
3024          * g4x modeset sequence (disable pipe after the port).
3025          */
3026         intel_dp_link_down(encoder, old_crtc_state);
3027
3028         /* Only ilk+ has port A */
3029         if (port == PORT_A)
3030                 ironlake_edp_pll_off(intel_dp, old_crtc_state);
3031 }
3032
3033 static void vlv_post_disable_dp(struct intel_encoder *encoder,
3034                                 const struct intel_crtc_state *old_crtc_state,
3035                                 const struct drm_connector_state *old_conn_state)
3036 {
3037         intel_dp_link_down(encoder, old_crtc_state);
3038 }
3039
3040 static void chv_post_disable_dp(struct intel_encoder *encoder,
3041                                 const struct intel_crtc_state *old_crtc_state,
3042                                 const struct drm_connector_state *old_conn_state)
3043 {
3044         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3045
3046         intel_dp_link_down(encoder, old_crtc_state);
3047
3048         mutex_lock(&dev_priv->sb_lock);
3049
3050         /* Assert data lane reset */
3051         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
3052
3053         mutex_unlock(&dev_priv->sb_lock);
3054 }
3055
3056 static void
3057 _intel_dp_set_link_train(struct intel_dp *intel_dp,
3058                          uint32_t *DP,
3059                          uint8_t dp_train_pat)
3060 {
3061         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3062         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3063         enum port port = intel_dig_port->base.port;
3064         uint8_t train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
3065
3066         if (dp_train_pat & train_pat_mask)
3067                 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
3068                               dp_train_pat & train_pat_mask);
3069
3070         if (HAS_DDI(dev_priv)) {
3071                 uint32_t temp = I915_READ(DP_TP_CTL(port));
3072
3073                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
3074                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
3075                 else
3076                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
3077
3078                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3079                 switch (dp_train_pat & train_pat_mask) {
3080                 case DP_TRAINING_PATTERN_DISABLE:
3081                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3082
3083                         break;
3084                 case DP_TRAINING_PATTERN_1:
3085                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3086                         break;
3087                 case DP_TRAINING_PATTERN_2:
3088                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3089                         break;
3090                 case DP_TRAINING_PATTERN_3:
3091                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3092                         break;
3093                 case DP_TRAINING_PATTERN_4:
3094                         temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3095                         break;
3096                 }
3097                 I915_WRITE(DP_TP_CTL(port), temp);
3098
3099         } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3100                    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3101                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
3102
3103                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3104                 case DP_TRAINING_PATTERN_DISABLE:
3105                         *DP |= DP_LINK_TRAIN_OFF_CPT;
3106                         break;
3107                 case DP_TRAINING_PATTERN_1:
3108                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
3109                         break;
3110                 case DP_TRAINING_PATTERN_2:
3111                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3112                         break;
3113                 case DP_TRAINING_PATTERN_3:
3114                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3115                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3116                         break;
3117                 }
3118
3119         } else {
3120                 *DP &= ~DP_LINK_TRAIN_MASK;
3121
3122                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3123                 case DP_TRAINING_PATTERN_DISABLE:
3124                         *DP |= DP_LINK_TRAIN_OFF;
3125                         break;
3126                 case DP_TRAINING_PATTERN_1:
3127                         *DP |= DP_LINK_TRAIN_PAT_1;
3128                         break;
3129                 case DP_TRAINING_PATTERN_2:
3130                         *DP |= DP_LINK_TRAIN_PAT_2;
3131                         break;
3132                 case DP_TRAINING_PATTERN_3:
3133                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3134                         *DP |= DP_LINK_TRAIN_PAT_2;
3135                         break;
3136                 }
3137         }
3138 }
3139
3140 static void intel_dp_enable_port(struct intel_dp *intel_dp,
3141                                  const struct intel_crtc_state *old_crtc_state)
3142 {
3143         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3144
3145         /* enable with pattern 1 (as per spec) */
3146
3147         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
3148
3149         /*
3150          * Magic for VLV/CHV. We _must_ first set up the register
3151          * without actually enabling the port, and then do another
3152          * write to enable the port. Otherwise link training will
3153          * fail when the power sequencer is freshly used for this port.
3154          */
3155         intel_dp->DP |= DP_PORT_EN;
3156         if (old_crtc_state->has_audio)
3157                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
3158
3159         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3160         POSTING_READ(intel_dp->output_reg);
3161 }
3162
3163 static void intel_enable_dp(struct intel_encoder *encoder,
3164                             const struct intel_crtc_state *pipe_config,
3165                             const struct drm_connector_state *conn_state)
3166 {
3167         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3168         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3169         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3170         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
3171         enum pipe pipe = crtc->pipe;
3172
3173         if (WARN_ON(dp_reg & DP_PORT_EN))
3174                 return;
3175
3176         pps_lock(intel_dp);
3177
3178         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3179                 vlv_init_panel_power_sequencer(encoder, pipe_config);
3180
3181         intel_dp_enable_port(intel_dp, pipe_config);
3182
3183         edp_panel_vdd_on(intel_dp);
3184         edp_panel_on(intel_dp);
3185         edp_panel_vdd_off(intel_dp, true);
3186
3187         pps_unlock(intel_dp);
3188
3189         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3190                 unsigned int lane_mask = 0x0;
3191
3192                 if (IS_CHERRYVIEW(dev_priv))
3193                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
3194
3195                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
3196                                     lane_mask);
3197         }
3198
3199         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3200         intel_dp_start_link_train(intel_dp);
3201         intel_dp_stop_link_train(intel_dp);
3202
3203         if (pipe_config->has_audio) {
3204                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
3205                                  pipe_name(pipe));
3206                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
3207         }
3208 }
3209
3210 static void g4x_enable_dp(struct intel_encoder *encoder,
3211                           const struct intel_crtc_state *pipe_config,
3212                           const struct drm_connector_state *conn_state)
3213 {
3214         intel_enable_dp(encoder, pipe_config, conn_state);
3215         intel_edp_backlight_on(pipe_config, conn_state);
3216 }
3217
3218 static void vlv_enable_dp(struct intel_encoder *encoder,
3219                           const struct intel_crtc_state *pipe_config,
3220                           const struct drm_connector_state *conn_state)
3221 {
3222         intel_edp_backlight_on(pipe_config, conn_state);
3223 }
3224
3225 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
3226                               const struct intel_crtc_state *pipe_config,
3227                               const struct drm_connector_state *conn_state)
3228 {
3229         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3230         enum port port = encoder->port;
3231
3232         intel_dp_prepare(encoder, pipe_config);
3233
3234         /* Only ilk+ has port A */
3235         if (port == PORT_A)
3236                 ironlake_edp_pll_on(intel_dp, pipe_config);
3237 }
3238
3239 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
3240 {
3241         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3242         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3243         enum pipe pipe = intel_dp->pps_pipe;
3244         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
3245
3246         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3247
3248         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
3249                 return;
3250
3251         edp_panel_vdd_off_sync(intel_dp);
3252
3253         /*
3254          * VLV seems to get confused when multiple power sequencers
3255          * have the same port selected (even if only one has power/vdd
3256          * enabled). The failure manifests as vlv_wait_port_ready() failing
3257          * CHV on the other hand doesn't seem to mind having the same port
3258          * selected in multiple power sequencers, but let's clear the
3259          * port select always when logically disconnecting a power sequencer
3260          * from a port.
3261          */
3262         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
3263                       pipe_name(pipe), port_name(intel_dig_port->base.port));
3264         I915_WRITE(pp_on_reg, 0);
3265         POSTING_READ(pp_on_reg);
3266
3267         intel_dp->pps_pipe = INVALID_PIPE;
3268 }
3269
3270 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
3271                                       enum pipe pipe)
3272 {
3273         struct intel_encoder *encoder;
3274
3275         lockdep_assert_held(&dev_priv->pps_mutex);
3276
3277         for_each_intel_dp(&dev_priv->drm, encoder) {
3278                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3279                 enum port port = encoder->port;
3280
3281                 WARN(intel_dp->active_pipe == pipe,
3282                      "stealing pipe %c power sequencer from active (e)DP port %c\n",
3283                      pipe_name(pipe), port_name(port));
3284
3285                 if (intel_dp->pps_pipe != pipe)
3286                         continue;
3287
3288                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
3289                               pipe_name(pipe), port_name(port));
3290
3291                 /* make sure vdd is off before we steal it */
3292                 vlv_detach_power_sequencer(intel_dp);
3293         }
3294 }
3295
3296 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3297                                            const struct intel_crtc_state *crtc_state)
3298 {
3299         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3300         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3301         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3302
3303         lockdep_assert_held(&dev_priv->pps_mutex);
3304
3305         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3306
3307         if (intel_dp->pps_pipe != INVALID_PIPE &&
3308             intel_dp->pps_pipe != crtc->pipe) {
3309                 /*
3310                  * If another power sequencer was being used on this
3311                  * port previously make sure to turn off vdd there while
3312                  * we still have control of it.
3313                  */
3314                 vlv_detach_power_sequencer(intel_dp);
3315         }
3316
3317         /*
3318          * We may be stealing the power
3319          * sequencer from another port.
3320          */
3321         vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3322
3323         intel_dp->active_pipe = crtc->pipe;