drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <linux/sched/clock.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_encoder.h>
  37 #include <drm/drm_fb_helper.h>
  38 #include <drm/drm_dp_dual_mode_helper.h>
  39 #include <drm/drm_dp_mst_helper.h>
  40 #include <drm/drm_rect.h>
  41 #include <drm/drm_atomic.h>
  42
  43 /**
  44  * __wait_for - magic wait macro
  45  *
  46  * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
  47  * important that we check the condition again after having timed out, since the
  48  * timeout could be due to preemption or similar and we've never had a chance to
  49  * check the condition before the timeout.
  50  */
  51 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
  52         const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
  53         long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
  54         int ret__;                                                      \
  55         might_sleep();                                                  \
  56         for (;;) {                                                      \
  57                 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
  58                 OP;                                                     \
  59                 /* Guarantee COND check prior to timeout */             \
  60                 barrier();                                              \
  61                 if (COND) {                                             \
  62                         ret__ = 0;                                      \
  63                         break;                                          \
  64                 }                                                       \
  65                 if (expired__) {                                        \
  66                         ret__ = -ETIMEDOUT;                             \
  67                         break;                                          \
  68                 }                                                       \
  69                 usleep_range(wait__, wait__ * 2);                       \
  70                 if (wait__ < (Wmax))                                    \
  71                         wait__ <<= 1;                                   \
  72         }                                                               \
  73         ret__;                                                          \
  74 })
  75
  76 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
  77                                                    (Wmax))
  78 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 10, 1000)
  79
  80 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  81 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  82 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  83 #else
  84 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  85 #endif
  86
  87 #define _wait_for_atomic(COND, US, ATOMIC) \
  88 ({ \
  89         int cpu, ret, timeout = (US) * 1000; \
  90         u64 base; \
  91         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  92         if (!(ATOMIC)) { \
  93                 preempt_disable(); \
  94                 cpu = smp_processor_id(); \
  95         } \
  96         base = local_clock(); \
  97         for (;;) { \
  98                 u64 now = local_clock(); \
  99                 if (!(ATOMIC)) \
 100                         preempt_enable(); \
 101                 /* Guarantee COND check prior to timeout */ \
 102                 barrier(); \
 103                 if (COND) { \
 104                         ret = 0; \
 105                         break; \
 106                 } \
 107                 if (now - base >= timeout) { \
 108                         ret = -ETIMEDOUT; \
 109                         break; \
 110                 } \
 111                 cpu_relax(); \
 112                 if (!(ATOMIC)) { \
 113                         preempt_disable(); \
 114                         if (unlikely(cpu != smp_processor_id())) { \
 115                                 timeout -= now - base; \
 116                                 cpu = smp_processor_id(); \
 117                                 base = local_clock(); \
 118                         } \
 119                 } \
 120         } \
 121         ret; \
 122 })
 123
 124 #define wait_for_us(COND, US) \
 125 ({ \
 126         int ret__; \
 127         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 128         if ((US) > 10) \
 129                 ret__ = _wait_for((COND), (US), 10, 10); \
 130         else \
 131                 ret__ = _wait_for_atomic((COND), (US), 0); \
 132         ret__; \
 133 })
 134
 135 #define wait_for_atomic_us(COND, US) \
 136 ({ \
 137         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 138         BUILD_BUG_ON((US) > 50000); \
 139         _wait_for_atomic((COND), (US), 1); \
 140 })
 141
 142 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
 143
 144 #define KHz(x) (1000 * (x))
 145 #define MHz(x) KHz(1000 * (x))
 146
 147 #define KBps(x) (1000 * (x))
 148 #define MBps(x) KBps(1000 * (x))
 149 #define GBps(x) ((u64)1000 * MBps((x)))
 150
 151 /*
 152  * Display related stuff
 153  */
 154
 155 /* store information about an Ixxx DVO */
 156 /* The i830->i865 use multiple DVOs with multiple i2cs */
 157 /* the i915, i945 have a single sDVO i2c bus - which is different */
 158 #define MAX_OUTPUTS 6
 159 /* maximum connectors per crtcs in the mode set */
 160
 161 #define INTEL_I2C_BUS_DVO 1
 162 #define INTEL_I2C_BUS_SDVO 2
 163
 164 /* these are outputs from the chip - integrated only
 165    external chips are via DVO or SDVO output */
 166 enum intel_output_type {
 167         INTEL_OUTPUT_UNUSED = 0,
 168         INTEL_OUTPUT_ANALOG = 1,
 169         INTEL_OUTPUT_DVO = 2,
 170         INTEL_OUTPUT_SDVO = 3,
 171         INTEL_OUTPUT_LVDS = 4,
 172         INTEL_OUTPUT_TVOUT = 5,
 173         INTEL_OUTPUT_HDMI = 6,
 174         INTEL_OUTPUT_DP = 7,
 175         INTEL_OUTPUT_EDP = 8,
 176         INTEL_OUTPUT_DSI = 9,
 177         INTEL_OUTPUT_DDI = 10,
 178         INTEL_OUTPUT_DP_MST = 11,
 179 };
 180
 181 #define INTEL_DVO_CHIP_NONE 0
 182 #define INTEL_DVO_CHIP_LVDS 1
 183 #define INTEL_DVO_CHIP_TMDS 2
 184 #define INTEL_DVO_CHIP_TVOUT 4
 185
 186 #define INTEL_DSI_VIDEO_MODE    0
 187 #define INTEL_DSI_COMMAND_MODE  1
 188
 189 struct intel_framebuffer {
 190         struct drm_framebuffer base;
 191         struct intel_rotation_info rot_info;
 192
 193         /* for each plane in the normal GTT view */
 194         struct {
 195                 unsigned int x, y;
 196         } normal[2];
 197         /* for each plane in the rotated GTT view */
 198         struct {
 199                 unsigned int x, y;
 200                 unsigned int pitch; /* pixels */
 201         } rotated[2];
 202 };
 203
 204 struct intel_fbdev {
 205         struct drm_fb_helper helper;
 206         struct intel_framebuffer *fb;
 207         struct i915_vma *vma;
 208         unsigned long vma_flags;
 209         async_cookie_t cookie;
 210         int preferred_bpp;
 211 };
 212
 213 struct intel_encoder {
 214         struct drm_encoder base;
 215
 216         enum intel_output_type type;
 217         enum port port;
 218         unsigned int cloneable;
 219         bool (*hotplug)(struct intel_encoder *encoder,
 220                         struct intel_connector *connector);
 221         enum intel_output_type (*compute_output_type)(struct intel_encoder *,
 222                                                       struct intel_crtc_state *,
 223                                                       struct drm_connector_state *);
 224         bool (*compute_config)(struct intel_encoder *,
 225                                struct intel_crtc_state *,
 226                                struct drm_connector_state *);
 227         void (*pre_pll_enable)(struct intel_encoder *,
 228                                const struct intel_crtc_state *,
 229                                const struct drm_connector_state *);
 230         void (*pre_enable)(struct intel_encoder *,
 231                            const struct intel_crtc_state *,
 232                            const struct drm_connector_state *);
 233         void (*enable)(struct intel_encoder *,
 234                        const struct intel_crtc_state *,
 235                        const struct drm_connector_state *);
 236         void (*disable)(struct intel_encoder *,
 237                         const struct intel_crtc_state *,
 238                         const struct drm_connector_state *);
 239         void (*post_disable)(struct intel_encoder *,
 240                              const struct intel_crtc_state *,
 241                              const struct drm_connector_state *);
 242         void (*post_pll_disable)(struct intel_encoder *,
 243                                  const struct intel_crtc_state *,
 244                                  const struct drm_connector_state *);
 245         /* Read out the current hw state of this connector, returning true if
 246          * the encoder is active. If the encoder is enabled it also set the pipe
 247          * it is connected to in the pipe parameter. */
 248         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 249         /* Reconstructs the equivalent mode flags for the current hardware
 250          * state. This must be called _after_ display->get_pipe_config has
 251          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 252          * be set correctly before calling this function. */
 253         void (*get_config)(struct intel_encoder *,
 254                            struct intel_crtc_state *pipe_config);
 255         /* Returns a mask of power domains that need to be referenced as part
 256          * of the hardware state readout code. */
 257         u64 (*get_power_domains)(struct intel_encoder *encoder,
 258                                  struct intel_crtc_state *crtc_state);
 259         /*
 260          * Called during system suspend after all pending requests for the
 261          * encoder are flushed (for example for DP AUX transactions) and
 262          * device interrupts are disabled.
 263          */
 264         void (*suspend)(struct intel_encoder *);
 265         int crtc_mask;
 266         enum hpd_pin hpd_pin;
 267         enum intel_display_power_domain power_domain;
 268         /* for communication with audio component; protected by av_mutex */
 269         const struct drm_connector *audio_connector;
 270 };
 271
 272 struct intel_panel {
 273         struct drm_display_mode *fixed_mode;
 274         struct drm_display_mode *downclock_mode;
 275
 276         /* backlight */
 277         struct {
 278                 bool present;
 279                 u32 level;
 280                 u32 min;
 281                 u32 max;
 282                 bool enabled;
 283                 bool combination_mode;  /* gen 2/4 only */
 284                 bool active_low_pwm;
 285                 bool alternate_pwm_increment;   /* lpt+ */
 286
 287                 /* PWM chip */
 288                 bool util_pin_active_low;       /* bxt+ */
 289                 u8 controller;          /* bxt+ only */
 290                 struct pwm_device *pwm;
 291
 292                 struct backlight_device *device;
 293
 294                 /* Connector and platform specific backlight functions */
 295                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 296                 uint32_t (*get)(struct intel_connector *connector);
 297                 void (*set)(const struct drm_connector_state *conn_state, uint32_t level);
 298                 void (*disable)(const struct drm_connector_state *conn_state);
 299                 void (*enable)(const struct intel_crtc_state *crtc_state,
 300                                const struct drm_connector_state *conn_state);
 301                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 302                                       uint32_t hz);
 303                 void (*power)(struct intel_connector *, bool enable);
 304         } backlight;
 305 };
 306
 307 /*
 308  * This structure serves as a translation layer between the generic HDCP code
 309  * and the bus-specific code. What that means is that HDCP over HDMI differs
 310  * from HDCP over DP, so to account for these differences, we need to
 311  * communicate with the receiver through this shim.
 312  *
 313  * For completeness, the 2 buses differ in the following ways:
 314  *      - DP AUX vs. DDC
 315  *              HDCP registers on the receiver are set via DP AUX for DP, and
 316  *              they are set via DDC for HDMI.
 317  *      - Receiver register offsets
 318  *              The offsets of the registers are different for DP vs. HDMI
 319  *      - Receiver register masks/offsets
 320  *              For instance, the ready bit for the KSV fifo is in a different
 321  *              place on DP vs HDMI
 322  *      - Receiver register names
 323  *              Seriously. In the DP spec, the 16-bit register containing
 324  *              downstream information is called BINFO, on HDMI it's called
 325  *              BSTATUS. To confuse matters further, DP has a BSTATUS register
 326  *              with a completely different definition.
 327  *      - KSV FIFO
 328  *              On HDMI, the ksv fifo is read all at once, whereas on DP it must
 329  *              be read 3 keys at a time
 330  *      - Aksv output
 331  *              Since Aksv is hidden in hardware, there's different procedures
 332  *              to send it over DP AUX vs DDC
 333  */
 334 struct intel_hdcp_shim {
 335         /* Outputs the transmitter's An and Aksv values to the receiver. */
 336         int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
 337
 338         /* Reads the receiver's key selection vector */
 339         int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
 340
 341         /*
 342          * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
 343          * definitions are the same in the respective specs, but the names are
 344          * different. Call it BSTATUS since that's the name the HDMI spec
 345          * uses and it was there first.
 346          */
 347         int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
 348                             u8 *bstatus);
 349
 350         /* Determines whether a repeater is present downstream */
 351         int (*repeater_present)(struct intel_digital_port *intel_dig_port,
 352                                 bool *repeater_present);
 353
 354         /* Reads the receiver's Ri' value */
 355         int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
 356
 357         /* Determines if the receiver's KSV FIFO is ready for consumption */
 358         int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
 359                               bool *ksv_ready);
 360
 361         /* Reads the ksv fifo for num_downstream devices */
 362         int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
 363                              int num_downstream, u8 *ksv_fifo);
 364
 365         /* Reads a 32-bit part of V' from the receiver */
 366         int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
 367                                  int i, u32 *part);
 368
 369         /* Enables HDCP signalling on the port */
 370         int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
 371                                  bool enable);
 372
 373         /* Ensures the link is still protected */
 374         bool (*check_link)(struct intel_digital_port *intel_dig_port);
 375
 376         /* Detects panel's hdcp capability. This is optional for HDMI. */
 377         int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
 378                             bool *hdcp_capable);
 379 };
 380
 381 struct intel_connector {
 382         struct drm_connector base;
 383         /*
 384          * The fixed encoder this connector is connected to.
 385          */
 386         struct intel_encoder *encoder;
 387
 388         /* ACPI device id for ACPI and driver cooperation */
 389         u32 acpi_device_id;
 390
 391         /* Reads out the current hw, returning true if the connector is enabled
 392          * and active (i.e. dpms ON state). */
 393         bool (*get_hw_state)(struct intel_connector *);
 394
 395         /* Panel info for eDP and LVDS */
 396         struct intel_panel panel;
 397
 398         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 399         struct edid *edid;
 400         struct edid *detect_edid;
 401
 402         /* since POLL and HPD connectors may use the same HPD line keep the native
 403            state of connector->polled in case hotplug storm detection changes it */
 404         u8 polled;
 405
 406         void *port; /* store this opaque as its illegal to dereference it */
 407
 408         struct intel_dp *mst_port;
 409
 410         /* Work struct to schedule a uevent on link train failure */
 411         struct work_struct modeset_retry_work;
 412
 413         const struct intel_hdcp_shim *hdcp_shim;
 414         struct mutex hdcp_mutex;
 415         uint64_t hdcp_value; /* protected by hdcp_mutex */
 416         struct delayed_work hdcp_check_work;
 417         struct work_struct hdcp_prop_work;
 418 };
 419
 420 struct intel_digital_connector_state {
 421         struct drm_connector_state base;
 422
 423         enum hdmi_force_audio force_audio;
 424         int broadcast_rgb;
 425 };
 426
 427 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
 428
 429 struct dpll {
 430         /* given values */
 431         int n;
 432         int m1, m2;
 433         int p1, p2;
 434         /* derived values */
 435         int     dot;
 436         int     vco;
 437         int     m;
 438         int     p;
 439 };
 440
 441 struct intel_atomic_state {
 442         struct drm_atomic_state base;
 443
 444         struct {
 445                 /*
 446                  * Logical state of cdclk (used for all scaling, watermark,
 447                  * etc. calculations and checks). This is computed as if all
 448                  * enabled crtcs were active.
 449                  */
 450                 struct intel_cdclk_state logical;
 451
 452                 /*
 453                  * Actual state of cdclk, can be different from the logical
 454                  * state only when all crtc's are DPMS off.
 455                  */
 456                 struct intel_cdclk_state actual;
 457         } cdclk;
 458
 459         bool dpll_set, modeset;
 460
 461         /*
 462          * Does this transaction change the pipes that are active?  This mask
 463          * tracks which CRTC's have changed their active state at the end of
 464          * the transaction (not counting the temporary disable during modesets).
 465          * This mask should only be non-zero when intel_state->modeset is true,
 466          * but the converse is not necessarily true; simply changing a mode may
 467          * not flip the final active status of any CRTC's
 468          */
 469         unsigned int active_pipe_changes;
 470
 471         unsigned int active_crtcs;
 472         /* minimum acceptable cdclk for each pipe */
 473         int min_cdclk[I915_MAX_PIPES];
 474         /* minimum acceptable voltage level for each pipe */
 475         u8 min_voltage_level[I915_MAX_PIPES];
 476
 477         struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
 478
 479         /*
 480          * Current watermarks can't be trusted during hardware readout, so
 481          * don't bother calculating intermediate watermarks.
 482          */
 483         bool skip_intermediate_wm;
 484
 485         /* Gen9+ only */
 486         struct skl_ddb_values wm_results;
 487
 488         struct i915_sw_fence commit_ready;
 489
 490         struct llist_node freed;
 491 };
 492
 493 struct intel_plane_state {
 494         struct drm_plane_state base;
 495         struct i915_vma *vma;
 496         unsigned long flags;
 497 #define PLANE_HAS_FENCE BIT(0)
 498
 499         struct {
 500                 u32 offset;
 501                 int x, y;
 502         } main;
 503         struct {
 504                 u32 offset;
 505                 int x, y;
 506         } aux;
 507
 508         /* plane control register */
 509         u32 ctl;
 510
 511         /* plane color control register */
 512         u32 color_ctl;
 513
 514         /*
 515          * scaler_id
 516          *    = -1 : not using a scaler
 517          *    >=  0 : using a scalers
 518          *
 519          * plane requiring a scaler:
 520          *   - During check_plane, its bit is set in
 521          *     crtc_state->scaler_state.scaler_users by calling helper function
 522          *     update_scaler_plane.
 523          *   - scaler_id indicates the scaler it got assigned.
 524          *
 525          * plane doesn't require a scaler:
 526          *   - this can happen when scaling is no more required or plane simply
 527          *     got disabled.
 528          *   - During check_plane, corresponding bit is reset in
 529          *     crtc_state->scaler_state.scaler_users by calling helper function
 530          *     update_scaler_plane.
 531          */
 532         int scaler_id;
 533
 534         struct drm_intel_sprite_colorkey ckey;
 535 };
 536
 537 struct intel_initial_plane_config {
 538         struct intel_framebuffer *fb;
 539         unsigned int tiling;
 540         int size;
 541         u32 base;
 542 };
 543
 544 #define SKL_MIN_SRC_W 8
 545 #define SKL_MAX_SRC_W 4096
 546 #define SKL_MIN_SRC_H 8
 547 #define SKL_MAX_SRC_H 4096
 548 #define SKL_MIN_DST_W 8
 549 #define SKL_MAX_DST_W 4096
 550 #define SKL_MIN_DST_H 8
 551 #define SKL_MAX_DST_H 4096
 552 #define ICL_MAX_SRC_W 5120
 553 #define ICL_MAX_SRC_H 4096
 554 #define ICL_MAX_DST_W 5120
 555 #define ICL_MAX_DST_H 4096
 556 #define SKL_MIN_YUV_420_SRC_W 16
 557 #define SKL_MIN_YUV_420_SRC_H 16
 558
 559 struct intel_scaler {
 560         int in_use;
 561         uint32_t mode;
 562 };
 563
 564 struct intel_crtc_scaler_state {
 565 #define SKL_NUM_SCALERS 2
 566         struct intel_scaler scalers[SKL_NUM_SCALERS];
 567
 568         /*
 569          * scaler_users: keeps track of users requesting scalers on this crtc.
 570          *
 571          *     If a bit is set, a user is using a scaler.
 572          *     Here user can be a plane or crtc as defined below:
 573          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 574          *       bit 31    - crtc
 575          *
 576          * Instead of creating a new index to cover planes and crtc, using
 577          * existing drm_plane_index for planes which is well less than 31
 578          * planes and bit 31 for crtc. This should be fine to cover all
 579          * our platforms.
 580          *
 581          * intel_atomic_setup_scalers will setup available scalers to users
 582          * requesting scalers. It will gracefully fail if request exceeds
 583          * avilability.
 584          */
 585 #define SKL_CRTC_INDEX 31
 586         unsigned scaler_users;
 587
 588         /* scaler used by crtc for panel fitting purpose */
 589         int scaler_id;
 590 };
 591
 592 /* drm_mode->private_flags */
 593 #define I915_MODE_FLAG_INHERITED 1
 594 /* Flag to get scanline using frame time stamps */
 595 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
 596
 597 struct intel_pipe_wm {
 598         struct intel_wm_level wm[5];
 599         uint32_t linetime;
 600         bool fbc_wm_enabled;
 601         bool pipe_enabled;
 602         bool sprites_enabled;
 603         bool sprites_scaled;
 604 };
 605
 606 struct skl_plane_wm {
 607         struct skl_wm_level wm[8];
 608         struct skl_wm_level uv_wm[8];
 609         struct skl_wm_level trans_wm;
 610         bool is_planar;
 611 };
 612
 613 struct skl_pipe_wm {
 614         struct skl_plane_wm planes[I915_MAX_PLANES];
 615         uint32_t linetime;
 616 };
 617
 618 enum vlv_wm_level {
 619         VLV_WM_LEVEL_PM2,
 620         VLV_WM_LEVEL_PM5,
 621         VLV_WM_LEVEL_DDR_DVFS,
 622         NUM_VLV_WM_LEVELS,
 623 };
 624
 625 struct vlv_wm_state {
 626         struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
 627         struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
 628         uint8_t num_levels;
 629         bool cxsr;
 630 };
 631
 632 struct vlv_fifo_state {
 633         u16 plane[I915_MAX_PLANES];
 634 };
 635
 636 enum g4x_wm_level {
 637         G4X_WM_LEVEL_NORMAL,
 638         G4X_WM_LEVEL_SR,
 639         G4X_WM_LEVEL_HPLL,
 640         NUM_G4X_WM_LEVELS,
 641 };
 642
 643 struct g4x_wm_state {
 644         struct g4x_pipe_wm wm;
 645         struct g4x_sr_wm sr;
 646         struct g4x_sr_wm hpll;
 647         bool cxsr;
 648         bool hpll_en;
 649         bool fbc_en;
 650 };
 651
 652 struct intel_crtc_wm_state {
 653         union {
 654                 struct {
 655                         /*
 656                          * Intermediate watermarks; these can be
 657                          * programmed immediately since they satisfy
 658                          * both the current configuration we're
 659                          * switching away from and the new
 660                          * configuration we're switching to.
 661                          */
 662                         struct intel_pipe_wm intermediate;
 663
 664                         /*
 665                          * Optimal watermarks, programmed post-vblank
 666                          * when this state is committed.
 667                          */
 668                         struct intel_pipe_wm optimal;
 669                 } ilk;
 670
 671                 struct {
 672                         /* gen9+ only needs 1-step wm programming */
 673                         struct skl_pipe_wm optimal;
 674                         struct skl_ddb_entry ddb;
 675                 } skl;
 676
 677                 struct {
 678                         /* "raw" watermarks (not inverted) */
 679                         struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
 680                         /* intermediate watermarks (inverted) */
 681                         struct vlv_wm_state intermediate;
 682                         /* optimal watermarks (inverted) */
 683                         struct vlv_wm_state optimal;
 684                         /* display FIFO split */
 685                         struct vlv_fifo_state fifo_state;
 686                 } vlv;
 687
 688                 struct {
 689                         /* "raw" watermarks */
 690                         struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
 691                         /* intermediate watermarks */
 692                         struct g4x_wm_state intermediate;
 693                         /* optimal watermarks */
 694                         struct g4x_wm_state optimal;
 695                 } g4x;
 696         };
 697
 698         /*
 699          * Platforms with two-step watermark programming will need to
 700          * update watermark programming post-vblank to switch from the
 701          * safe intermediate watermarks to the optimal final
 702          * watermarks.
 703          */
 704         bool need_postvbl_update;
 705 };
 706
 707 struct intel_crtc_state {
 708         struct drm_crtc_state base;
 709
 710         /**
 711          * quirks - bitfield with hw state readout quirks
 712          *
 713          * For various reasons the hw state readout code might not be able to
 714          * completely faithfully read out the current state. These cases are
 715          * tracked with quirk flags so that fastboot and state checker can act
 716          * accordingly.
 717          */
 718 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 719         unsigned long quirks;
 720
 721         unsigned fb_bits; /* framebuffers to flip */
 722         bool update_pipe; /* can a fast modeset be performed? */
 723         bool disable_cxsr;
 724         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 725         bool fb_changed; /* fb on any of the planes is changed */
 726         bool fifo_changed; /* FIFO split is changed */
 727
 728         /* Pipe source size (ie. panel fitter input size)
 729          * All planes will be positioned inside this space,
 730          * and get clipped at the edges. */
 731         int pipe_src_w, pipe_src_h;
 732
 733         /*
 734          * Pipe pixel rate, adjusted for
 735          * panel fitter/pipe scaler downscaling.
 736          */
 737         unsigned int pixel_rate;
 738
 739         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 740          * between pch encoders and cpu encoders. */
 741         bool has_pch_encoder;
 742
 743         /* Are we sending infoframes on the attached port */
 744         bool has_infoframe;
 745
 746         /* CPU Transcoder for the pipe. Currently this can only differ from the
 747          * pipe on Haswell and later (where we have a special eDP transcoder)
 748          * and Broxton (where we have special DSI transcoders). */
 749         enum transcoder cpu_transcoder;
 750
 751         /*
 752          * Use reduced/limited/broadcast rbg range, compressing from the full
 753          * range fed into the crtcs.
 754          */
 755         bool limited_color_range;
 756
 757         /* Bitmask of encoder types (enum intel_output_type)
 758          * driven by the pipe.
 759          */
 760         unsigned int output_types;
 761
 762         /* Whether we should send NULL infoframes. Required for audio. */
 763         bool has_hdmi_sink;
 764
 765         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 766          * has_dp_encoder is set. */
 767         bool has_audio;
 768
 769         /*
 770          * Enable dithering, used when the selected pipe bpp doesn't match the
 771          * plane bpp.
 772          */
 773         bool dither;
 774
 775         /*
 776          * Dither gets enabled for 18bpp which causes CRC mismatch errors for
 777          * compliance video pattern tests.
 778          * Disable dither only if it is a compliance test request for
 779          * 18bpp.
 780          */
 781         bool dither_force_disable;
 782
 783         /* Controls for the clock computation, to override various stages. */
 784         bool clock_set;
 785
 786         /* SDVO TV has a bunch of special case. To make multifunction encoders
 787          * work correctly, we need to track this at runtime.*/
 788         bool sdvo_tv_clock;
 789
 790         /*
 791          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 792          * required. This is set in the 2nd loop of calling encoder's
 793          * ->compute_config if the first pick doesn't work out.
 794          */
 795         bool bw_constrained;
 796
 797         /* Settings for the intel dpll used on pretty much everything but
 798          * haswell. */
 799         struct dpll dpll;
 800
 801         /* Selected dpll when shared or NULL. */
 802         struct intel_shared_dpll *shared_dpll;
 803
 804         /* Actual register state of the dpll, for shared dpll cross-checking. */
 805         struct intel_dpll_hw_state dpll_hw_state;
 806
 807         /* DSI PLL registers */
 808         struct {
 809                 u32 ctrl, div;
 810         } dsi_pll;
 811
 812         int pipe_bpp;
 813         struct intel_link_m_n dp_m_n;
 814
 815         /* m2_n2 for eDP downclock */
 816         struct intel_link_m_n dp_m2_n2;
 817         bool has_drrs;
 818
 819         bool has_psr;
 820         bool has_psr2;
 821
 822         /*
 823          * Frequence the dpll for the port should run at. Differs from the
 824          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 825          * already multiplied by pixel_multiplier.
 826          */
 827         int port_clock;
 828
 829         /* Used by SDVO (and if we ever fix it, HDMI). */
 830         unsigned pixel_multiplier;
 831
 832         uint8_t lane_count;
 833
 834         /*
 835          * Used by platforms having DP/HDMI PHY with programmable lane
 836          * latency optimization.
 837          */
 838         uint8_t lane_lat_optim_mask;
 839
 840         /* minimum acceptable voltage level */
 841         u8 min_voltage_level;
 842
 843         /* Panel fitter controls for gen2-gen4 + VLV */
 844         struct {
 845                 u32 control;
 846                 u32 pgm_ratios;
 847                 u32 lvds_border_bits;
 848         } gmch_pfit;
 849
 850         /* Panel fitter placement and size for Ironlake+ */
 851         struct {
 852                 u32 pos;
 853                 u32 size;
 854                 bool enabled;
 855                 bool force_thru;
 856         } pch_pfit;
 857
 858         /* FDI configuration, only valid if has_pch_encoder is set. */
 859         int fdi_lanes;
 860         struct intel_link_m_n fdi_m_n;
 861
 862         bool ips_enabled;
 863         bool ips_force_disable;
 864
 865         bool enable_fbc;
 866
 867         bool double_wide;
 868
 869         int pbn;
 870
 871         struct intel_crtc_scaler_state scaler_state;
 872
 873         /* w/a for waiting 2 vblanks during crtc enable */
 874         enum pipe hsw_workaround_pipe;
 875
 876         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 877         bool disable_lp_wm;
 878
 879         struct intel_crtc_wm_state wm;
 880
 881         /* Gamma mode programmed on the pipe */
 882         uint32_t gamma_mode;
 883
 884         /* bitmask of visible planes (enum plane_id) */
 885         u8 active_planes;
 886         u8 nv12_planes;
 887
 888         /* HDMI scrambling status */
 889         bool hdmi_scrambling;
 890
 891         /* HDMI High TMDS char rate ratio */
 892         bool hdmi_high_tmds_clock_ratio;
 893
 894         /* output format is YCBCR 4:2:0 */
 895         bool ycbcr420;
 896 };
 897
 898 struct intel_crtc {
 899         struct drm_crtc base;
 900         enum pipe pipe;
 901         /*
 902          * Whether the crtc and the connected output pipeline is active. Implies
 903          * that crtc->enabled is set, i.e. the current mode configuration has
 904          * some outputs connected to this crtc.
 905          */
 906         bool active;
 907         u8 plane_ids_mask;
 908         unsigned long long enabled_power_domains;
 909         struct intel_overlay *overlay;
 910
 911         struct intel_crtc_state *config;
 912
 913         /* global reset count when the last flip was submitted */
 914         unsigned int reset_count;
 915
 916         /* Access to these should be protected by dev_priv->irq_lock. */
 917         bool cpu_fifo_underrun_disabled;
 918         bool pch_fifo_underrun_disabled;
 919
 920         /* per-pipe watermark state */
 921         struct {
 922                 /* watermarks currently being used  */
 923                 union {
 924                         struct intel_pipe_wm ilk;
 925                         struct vlv_wm_state vlv;
 926                         struct g4x_wm_state g4x;
 927                 } active;
 928         } wm;
 929
 930         int scanline_offset;
 931
 932         struct {
 933                 unsigned start_vbl_count;
 934                 ktime_t start_vbl_time;
 935                 int min_vbl, max_vbl;
 936                 int scanline_start;
 937         } debug;
 938
 939         /* scalers available on this crtc */
 940         int num_scalers;
 941 };
 942
 943 struct intel_plane {
 944         struct drm_plane base;
 945         enum i9xx_plane_id i9xx_plane;
 946         enum plane_id id;
 947         enum pipe pipe;
 948         bool can_scale;
 949         bool has_fbc;
 950         bool has_ccs;
 951         int max_downscale;
 952         uint32_t frontbuffer_bit;
 953
 954         struct {
 955                 u32 base, cntl, size;
 956         } cursor;
 957
 958         /*
 959          * NOTE: Do not place new plane state fields here (e.g., when adding
 960          * new plane properties).  New runtime state should now be placed in
 961          * the intel_plane_state structure and accessed via plane_state.
 962          */
 963
 964         void (*update_plane)(struct intel_plane *plane,
 965                              const struct intel_crtc_state *crtc_state,
 966                              const struct intel_plane_state *plane_state);
 967         void (*disable_plane)(struct intel_plane *plane,
 968                               struct intel_crtc *crtc);
 969         bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
 970         int (*check_plane)(struct intel_plane *plane,
 971                            struct intel_crtc_state *crtc_state,
 972                            struct intel_plane_state *state);
 973 };
 974
 975 struct intel_watermark_params {
 976         u16 fifo_size;
 977         u16 max_wm;
 978         u8 default_wm;
 979         u8 guard_size;
 980         u8 cacheline_size;
 981 };
 982
 983 struct cxsr_latency {
 984         bool is_desktop : 1;
 985         bool is_ddr3 : 1;
 986         u16 fsb_freq;
 987         u16 mem_freq;
 988         u16 display_sr;
 989         u16 display_hpll_disable;
 990         u16 cursor_sr;
 991         u16 cursor_hpll_disable;
 992 };
 993
 994 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 995 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 996 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 997 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 998 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 999 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1000 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1001 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
1002 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1003
1004 struct intel_hdmi {
1005         i915_reg_t hdmi_reg;
1006         int ddc_bus;
1007         struct {
1008                 enum drm_dp_dual_mode_type type;
1009                 int max_tmds_clock;
1010         } dp_dual_mode;
1011         bool has_hdmi_sink;
1012         bool has_audio;
1013         bool rgb_quant_range_selectable;
1014         struct intel_connector *attached_connector;
1015 };
1016
1017 struct intel_dp_mst_encoder;
1018 #define DP_MAX_DOWNSTREAM_PORTS         0x10
1019
1020 /*
1021  * enum link_m_n_set:
1022  *      When platform provides two set of M_N registers for dp, we can
1023  *      program them and switch between them incase of DRRS.
1024  *      But When only one such register is provided, we have to program the
1025  *      required divider value on that registers itself based on the DRRS state.
1026  *
1027  * M1_N1        : Program dp_m_n on M1_N1 registers
1028  *                        dp_m2_n2 on M2_N2 registers (If supported)
1029  *
1030  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
1031  *                        M2_N2 registers are not supported
1032  */
1033
1034 enum link_m_n_set {
1035         /* Sets the m1_n1 and m2_n2 */
1036         M1_N1 = 0,
1037         M2_N2
1038 };
1039
1040 struct intel_dp_compliance_data {
1041         unsigned long edid;
1042         uint8_t video_pattern;
1043         uint16_t hdisplay, vdisplay;
1044         uint8_t bpc;
1045 };
1046
1047 struct intel_dp_compliance {
1048         unsigned long test_type;
1049         struct intel_dp_compliance_data test_data;
1050         bool test_active;
1051         int test_link_rate;
1052         u8 test_lane_count;
1053 };
1054
1055 struct intel_dp {
1056         i915_reg_t output_reg;
1057         uint32_t DP;
1058         int link_rate;
1059         uint8_t lane_count;
1060         uint8_t sink_count;
1061         bool link_mst;
1062         bool link_trained;
1063         bool has_audio;
1064         bool detect_done;
1065         bool reset_link_params;
1066         enum aux_ch aux_ch;
1067         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
1068         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1069         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1070         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1071         /* source rates */
1072         int num_source_rates;
1073         const int *source_rates;
1074         /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1075         int num_sink_rates;
1076         int sink_rates[DP_MAX_SUPPORTED_RATES];
1077         bool use_rate_select;
1078         /* intersection of source and sink rates */
1079         int num_common_rates;
1080         int common_rates[DP_MAX_SUPPORTED_RATES];
1081         /* Max lane count for the current link */
1082         int max_link_lane_count;
1083         /* Max rate for the current link */
1084         int max_link_rate;
1085         /* sink or branch descriptor */
1086         struct drm_dp_desc desc;
1087         struct drm_dp_aux aux;
1088         enum intel_display_power_domain aux_power_domain;
1089         uint8_t train_set[4];
1090         int panel_power_up_delay;
1091         int panel_power_down_delay;
1092         int panel_power_cycle_delay;
1093         int backlight_on_delay;
1094         int backlight_off_delay;
1095         struct delayed_work panel_vdd_work;
1096         bool want_panel_vdd;
1097         unsigned long last_power_on;
1098         unsigned long last_backlight_off;
1099         ktime_t panel_power_off_time;
1100
1101         struct notifier_block edp_notifier;
1102
1103         /*
1104          * Pipe whose power sequencer is currently locked into
1105          * this port. Only relevant on VLV/CHV.
1106          */
1107         enum pipe pps_pipe;
1108         /*
1109          * Pipe currently driving the port. Used for preventing
1110          * the use of the PPS for any pipe currentrly driving
1111          * external DP as that will mess things up on VLV.
1112          */
1113         enum pipe active_pipe;
1114         /*
1115          * Set if the sequencer may be reset due to a power transition,
1116          * requiring a reinitialization. Only relevant on BXT.
1117          */
1118         bool pps_reset;
1119         struct edp_power_seq pps_delays;
1120
1121         bool can_mst; /* this port supports mst */
1122         bool is_mst;
1123         int active_mst_links;
1124         /* connector directly attached - won't be use for modeset in mst world */
1125         struct intel_connector *attached_connector;
1126
1127         /* mst connector list */
1128         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1129         struct drm_dp_mst_topology_mgr mst_mgr;
1130
1131         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1132         /*
1133          * This function returns the value we have to program the AUX_CTL
1134          * register with to kick off an AUX transaction.
1135          */
1136         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
1137                                      int send_bytes,
1138                                      uint32_t aux_clock_divider);
1139
1140         i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1141         i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1142
1143         /* This is called before a link training is starterd */
1144         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1145
1146         /* Displayport compliance testing */
1147         struct intel_dp_compliance compliance;
1148 };
1149
1150 struct intel_lspcon {
1151         bool active;
1152         enum drm_lspcon_mode mode;
1153 };
1154
1155 struct intel_digital_port {
1156         struct intel_encoder base;
1157         u32 saved_port_bits;
1158         struct intel_dp dp;
1159         struct intel_hdmi hdmi;
1160         struct intel_lspcon lspcon;
1161         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1162         bool release_cl2_override;
1163         uint8_t max_lanes;
1164         enum intel_display_power_domain ddi_io_power_domain;
1165
1166         void (*write_infoframe)(struct drm_encoder *encoder,
1167                                 const struct intel_crtc_state *crtc_state,
1168                                 unsigned int type,
1169                                 const void *frame, ssize_t len);
1170         void (*set_infoframes)(struct drm_encoder *encoder,
1171                                bool enable,
1172                                const struct intel_crtc_state *crtc_state,
1173                                const struct drm_connector_state *conn_state);
1174         bool (*infoframe_enabled)(struct drm_encoder *encoder,
1175                                   const struct intel_crtc_state *pipe_config);
1176 };
1177
1178 struct intel_dp_mst_encoder {
1179         struct intel_encoder base;
1180         enum pipe pipe;
1181         struct intel_digital_port *primary;
1182         struct intel_connector *connector;
1183 };
1184
1185 static inline enum dpio_channel
1186 vlv_dport_to_channel(struct intel_digital_port *dport)
1187 {
1188         switch (dport->base.port) {
1189         case PORT_B:
1190         case PORT_D:
1191                 return DPIO_CH0;
1192         case PORT_C:
1193                 return DPIO_CH1;
1194         default:
1195                 BUG();
1196         }
1197 }
1198
1199 static inline enum dpio_phy
1200 vlv_dport_to_phy(struct intel_digital_port *dport)
1201 {
1202         switch (dport->base.port) {
1203         case PORT_B:
1204         case PORT_C:
1205                 return DPIO_PHY0;
1206         case PORT_D:
1207                 return DPIO_PHY1;
1208         default:
1209                 BUG();
1210         }
1211 }
1212
1213 static inline enum dpio_channel
1214 vlv_pipe_to_channel(enum pipe pipe)
1215 {
1216         switch (pipe) {
1217         case PIPE_A:
1218         case PIPE_C:
1219                 return DPIO_CH0;
1220         case PIPE_B:
1221                 return DPIO_CH1;
1222         default:
1223                 BUG();
1224         }
1225 }
1226
1227 static inline struct intel_crtc *
1228 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1229 {
1230         return dev_priv->pipe_to_crtc_mapping[pipe];
1231 }
1232
1233 static inline struct intel_crtc *
1234 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1235 {
1236         return dev_priv->plane_to_crtc_mapping[plane];
1237 }
1238
1239 struct intel_load_detect_pipe {
1240         struct drm_atomic_state *restore_state;
1241 };
1242
1243 static inline struct intel_encoder *
1244 intel_attached_encoder(struct drm_connector *connector)
1245 {
1246         return to_intel_connector(connector)->encoder;
1247 }
1248
1249 static inline struct intel_digital_port *
1250 enc_to_dig_port(struct drm_encoder *encoder)
1251 {
1252         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1253
1254         switch (intel_encoder->type) {
1255         case INTEL_OUTPUT_DDI:
1256                 WARN_ON(!HAS_DDI(to_i915(encoder->dev)));
1257                 /* fall through */
1258         case INTEL_OUTPUT_DP:
1259         case INTEL_OUTPUT_EDP:
1260         case INTEL_OUTPUT_HDMI:
1261                 return container_of(encoder, struct intel_digital_port,
1262                                     base.base);
1263         default:
1264                 return NULL;
1265         }
1266 }
1267
1268 static inline struct intel_dp_mst_encoder *
1269 enc_to_mst(struct drm_encoder *encoder)
1270 {
1271         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1272 }
1273
1274 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1275 {
1276         return &enc_to_dig_port(encoder)->dp;
1277 }
1278
1279 static inline struct intel_digital_port *
1280 dp_to_dig_port(struct intel_dp *intel_dp)
1281 {
1282         return container_of(intel_dp, struct intel_digital_port, dp);
1283 }
1284
1285 static inline struct intel_lspcon *
1286 dp_to_lspcon(struct intel_dp *intel_dp)
1287 {
1288         return &dp_to_dig_port(intel_dp)->lspcon;
1289 }
1290
1291 static inline struct intel_digital_port *
1292 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1293 {
1294         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1295 }
1296
1297 static inline struct intel_plane_state *
1298 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1299                                  struct intel_plane *plane)
1300 {
1301         return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1302                                                                    &plane->base));
1303 }
1304
1305 static inline struct intel_crtc_state *
1306 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1307                                 struct intel_crtc *crtc)
1308 {
1309         return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1310                                                                  &crtc->base));
1311 }
1312
1313 static inline struct intel_crtc_state *
1314 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1315                                 struct intel_crtc *crtc)
1316 {
1317         return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1318                                                                  &crtc->base));
1319 }
1320
1321 /* intel_fifo_underrun.c */
1322 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1323                                            enum pipe pipe, bool enable);
1324 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1325                                            enum pipe pch_transcoder,
1326                                            bool enable);
1327 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1328                                          enum pipe pipe);
1329 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1330                                          enum pipe pch_transcoder);
1331 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1332 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1333
1334 /* i915_irq.c */
1335 bool gen11_reset_one_iir(struct drm_i915_private * const i915,
1336                          const unsigned int bank,
1337                          const unsigned int bit);
1338 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1339 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1340 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1341 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1342 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1343 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1344 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1345 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1346
1347 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1348                                             u32 mask)
1349 {
1350         return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
1351 }
1352
1353 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1354 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1355 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1356 {
1357         /*
1358          * We only use drm_irq_uninstall() at unload and VT switch, so
1359          * this is the only thing we need to check.
1360          */
1361         return dev_priv->runtime_pm.irqs_enabled;
1362 }
1363
1364 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1365 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1366                                      u8 pipe_mask);
1367 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1368                                      u8 pipe_mask);
1369 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1370 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1371 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1372
1373 /* intel_crt.c */
1374 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
1375                             i915_reg_t adpa_reg, enum pipe *pipe);
1376 void intel_crt_init(struct drm_i915_private *dev_priv);
1377 void intel_crt_reset(struct drm_encoder *encoder);
1378
1379 /* intel_ddi.c */
1380 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1381                                 const struct intel_crtc_state *old_crtc_state,
1382                                 const struct drm_connector_state *old_conn_state);
1383 void hsw_fdi_link_train(struct intel_crtc *crtc,
1384                         const struct intel_crtc_state *crtc_state);
1385 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1386 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1387 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1388 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1389                                        enum transcoder cpu_transcoder);
1390 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1391 void intel_ddi_disable_pipe_clock(const  struct intel_crtc_state *crtc_state);
1392 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1393 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1394 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1395 void intel_ddi_get_config(struct intel_encoder *encoder,
1396                           struct intel_crtc_state *pipe_config);
1397
1398 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1399                                     bool state);
1400 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
1401                                          struct intel_crtc_state *crtc_state);
1402 u32 bxt_signal_levels(struct intel_dp *intel_dp);
1403 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1404 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1405 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,
1406                                  u8 voltage_swing);
1407 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1408                                      bool enable);
1409 void icl_map_plls_to_ports(struct drm_crtc *crtc,
1410                            struct intel_crtc_state *crtc_state,
1411                            struct drm_atomic_state *old_state);
1412 void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
1413                              struct intel_crtc_state *crtc_state,
1414                              struct drm_atomic_state *old_state);
1415
1416 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1417                                    int plane, unsigned int height);
1418
1419 /* intel_audio.c */
1420 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1421 void intel_audio_codec_enable(struct intel_encoder *encoder,
1422                               const struct intel_crtc_state *crtc_state,
1423                               const struct drm_connector_state *conn_state);
1424 void intel_audio_codec_disable(struct intel_encoder *encoder,
1425                                const struct intel_crtc_state *old_crtc_state,
1426                                const struct drm_connector_state *old_conn_state);
1427 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1428 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1429 void intel_audio_init(struct drm_i915_private *dev_priv);
1430 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1431
1432 /* intel_cdclk.c */
1433 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
1434 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1435 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1436 void cnl_init_cdclk(struct drm_i915_private *dev_priv);
1437 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
1438 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1439 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1440 void icl_init_cdclk(struct drm_i915_private *dev_priv);
1441 void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
1442 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1443 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1444 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1445 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1446 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
1447                                const struct intel_cdclk_state *b);
1448 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
1449                          const struct intel_cdclk_state *b);
1450 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1451                      const struct intel_cdclk_state *cdclk_state);
1452 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
1453                             const char *context);
1454
1455 /* intel_display.c */
1456 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1457 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1458 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1459 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1460 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1461 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1462                       const char *name, u32 reg, int ref_freq);
1463 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1464                            const char *name, u32 reg);
1465 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1466 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1467 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1468 unsigned int intel_fb_xy_to_linear(int x, int y,
1469                                    const struct intel_plane_state *state,
1470                                    int plane);
1471 void intel_add_fb_offsets(int *x, int *y,
1472                           const struct intel_plane_state *state, int plane);
1473 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1474 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1475 void intel_mark_busy(struct drm_i915_private *dev_priv);
1476 void intel_mark_idle(struct drm_i915_private *dev_priv);
1477 int intel_display_suspend(struct drm_device *dev);
1478 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1479 void intel_encoder_destroy(struct drm_encoder *encoder);
1480 int intel_connector_init(struct intel_connector *);
1481 struct intel_connector *intel_connector_alloc(void);
1482 void intel_connector_free(struct intel_connector *connector);
1483 bool intel_connector_get_hw_state(struct intel_connector *connector);
1484 void intel_connector_attach_encoder(struct intel_connector *connector,
1485                                     struct intel_encoder *encoder);
1486 struct drm_display_mode *
1487 intel_encoder_current_mode(struct intel_encoder *encoder);
1488 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
1489 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
1490                               enum port port);
1491
1492 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1493 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
1494                                       struct drm_file *file_priv);
1495 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1496                                              enum pipe pipe);
1497 static inline bool
1498 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1499                     enum intel_output_type type)
1500 {
1501         return crtc_state->output_types & (1 << type);
1502 }
1503 static inline bool
1504 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1505 {
1506         return crtc_state->output_types &
1507                 ((1 << INTEL_OUTPUT_DP) |
1508                  (1 << INTEL_OUTPUT_DP_MST) |
1509                  (1 << INTEL_OUTPUT_EDP));
1510 }
1511 static inline void
1512 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1513 {
1514         drm_wait_one_vblank(&dev_priv->drm, pipe);
1515 }
1516 static inline void
1517 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1518 {
1519         const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1520
1521         if (crtc->active)
1522                 intel_wait_for_vblank(dev_priv, pipe);
1523 }
1524
1525 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1526
1527 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1528 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1529                          struct intel_digital_port *dport,
1530                          unsigned int expected_mask);
1531 int intel_get_load_detect_pipe(struct drm_connector *connector,
1532                                const struct drm_display_mode *mode,
1533                                struct intel_load_detect_pipe *old,
1534                                struct drm_modeset_acquire_ctx *ctx);
1535 void intel_release_load_detect_pipe(struct drm_connector *connector,
1536                                     struct intel_load_detect_pipe *old,
1537                                     struct drm_modeset_acquire_ctx *ctx);
1538 struct i915_vma *
1539 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1540                            unsigned int rotation,
1541                            bool uses_fence,
1542                            unsigned long *out_flags);
1543 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
1544 struct drm_framebuffer *
1545 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1546                          struct drm_mode_fb_cmd2 *mode_cmd);
1547 int intel_prepare_plane_fb(struct drm_plane *plane,
1548                            struct drm_plane_state *new_state);
1549 void intel_cleanup_plane_fb(struct drm_plane *plane,
1550                             struct drm_plane_state *old_state);
1551 int intel_plane_atomic_get_property(struct drm_plane *plane,
1552                                     const struct drm_plane_state *state,
1553                                     struct drm_property *property,
1554                                     uint64_t *val);
1555 int intel_plane_atomic_set_property(struct drm_plane *plane,
1556                                     struct drm_plane_state *state,
1557                                     struct drm_property *property,
1558                                     uint64_t val);
1559 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
1560                                     struct drm_crtc_state *crtc_state,
1561                                     const struct intel_plane_state *old_plane_state,
1562                                     struct drm_plane_state *plane_state);
1563
1564 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1565                                     enum pipe pipe);
1566
1567 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1568                      const struct dpll *dpll);
1569 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1570 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1571
1572 /* modesetting asserts */
1573 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1574                            enum pipe pipe);
1575 void assert_pll(struct drm_i915_private *dev_priv,
1576                 enum pipe pipe, bool state);
1577 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1578 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1579 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1580 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1581 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1582 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1583                        enum pipe pipe, bool state);
1584 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1585 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1586 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1587 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1588 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1589 u32 intel_compute_tile_offset(int *x, int *y,
1590                               const struct intel_plane_state *state, int plane);
1591 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1592 void intel_finish_reset(struct drm_i915_private *dev_priv);
1593 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1594 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1595 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1596 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1597 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1598 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1599 unsigned int skl_cdclk_get_vco(unsigned int freq);
1600 void intel_dp_get_m_n(struct intel_crtc *crtc,
1601                       struct intel_crtc_state *pipe_config);
1602 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1603 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1604 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1605                         struct dpll *best_clock);
1606 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1607
1608 bool intel_crtc_active(struct intel_crtc *crtc);
1609 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
1610 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
1611 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
1612 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1613 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1614                                  struct intel_crtc_state *pipe_config);
1615 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
1616                                   struct intel_crtc_state *crtc_state);
1617
1618 u16 skl_scaler_calc_phase(int sub, bool chroma_center);
1619 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1620 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
1621                   uint32_t pixel_format);
1622
1623 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1624 {
1625         return i915_ggtt_offset(state->vma);
1626 }
1627
1628 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
1629                         const struct intel_plane_state *plane_state);
1630 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1631                   const struct intel_plane_state *plane_state);
1632 u32 glk_color_ctl(const struct intel_plane_state *plane_state);
1633 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1634                      unsigned int rotation);
1635 int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
1636                             struct intel_plane_state *plane_state);
1637 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1638 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
1639
1640 /* intel_csr.c */
1641 void intel_csr_ucode_init(struct drm_i915_private *);
1642 void intel_csr_load_program(struct drm_i915_private *);
1643 void intel_csr_ucode_fini(struct drm_i915_private *);
1644 void intel_csr_ucode_suspend(struct drm_i915_private *);
1645 void intel_csr_ucode_resume(struct drm_i915_private *);
1646
1647 /* intel_dp.c */
1648 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
1649                            i915_reg_t dp_reg, enum port port,
1650                            enum pipe *pipe);
1651 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1652                    enum port port);
1653 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1654                              struct intel_connector *intel_connector);
1655 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1656                               int link_rate, uint8_t lane_count,
1657                               bool link_mst);
1658 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1659                                             int link_rate, uint8_t lane_count);
1660 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1661 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1662 int intel_dp_retrain_link(struct intel_encoder *encoder,
1663                           struct drm_modeset_acquire_ctx *ctx);
1664 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1665 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1666 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1667 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1668 int intel_dp_sink_crc(struct intel_dp *intel_dp,
1669                       struct intel_crtc_state *crtc_state, u8 *crc);
1670 bool intel_dp_compute_config(struct intel_encoder *encoder,
1671                              struct intel_crtc_state *pipe_config,
1672                              struct drm_connector_state *conn_state);
1673 bool intel_dp_is_edp(struct intel_dp *intel_dp);
1674 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
1675 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1676                                   bool long_hpd);
1677 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1678                             const struct drm_connector_state *conn_state);
1679 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
1680 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1681 void intel_edp_panel_on(struct intel_dp *intel_dp);
1682 void intel_edp_panel_off(struct intel_dp *intel_dp);
1683 void intel_dp_mst_suspend(struct drm_device *dev);
1684 void intel_dp_mst_resume(struct drm_device *dev);
1685 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1686 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1687 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1688 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1689 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1690 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1691 void intel_plane_destroy(struct drm_plane *plane);
1692 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1693                            const struct intel_crtc_state *crtc_state);
1694 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1695                             const struct intel_crtc_state *crtc_state);
1696 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1697                                unsigned int frontbuffer_bits);
1698 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1699                           unsigned int frontbuffer_bits);
1700
1701 void
1702 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1703                                        uint8_t dp_train_pat);
1704 void
1705 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1706 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1707 uint8_t
1708 intel_dp_voltage_max(struct intel_dp *intel_dp);
1709 uint8_t
1710 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1711 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1712                            uint8_t *link_bw, uint8_t *rate_select);
1713 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1714 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
1715 bool
1716 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1717
1718 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1719 {
1720         return ~((1 << lane_count) - 1) & 0xf;
1721 }
1722
1723 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1724 int intel_dp_link_required(int pixel_clock, int bpp);
1725 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1726 bool intel_digital_port_connected(struct intel_encoder *encoder);
1727
1728 /* intel_dp_aux_backlight.c */
1729 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1730
1731 /* intel_dp_mst.c */
1732 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1733 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1734 /* vlv_dsi.c */
1735 void vlv_dsi_init(struct drm_i915_private *dev_priv);
1736
1737 /* intel_dsi_dcs_backlight.c */
1738 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1739
1740 /* intel_dvo.c */
1741 void intel_dvo_init(struct drm_i915_private *dev_priv);
1742 /* intel_hotplug.c */
1743 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1744 bool intel_encoder_hotplug(struct intel_encoder *encoder,
1745                            struct intel_connector *connector);
1746
1747 /* legacy fbdev emulation in intel_fbdev.c */
1748 #ifdef CONFIG_DRM_FBDEV_EMULATION
1749 extern int intel_fbdev_init(struct drm_device *dev);
1750 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1751 extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv);
1752 extern void intel_fbdev_fini(struct drm_i915_private *dev_priv);
1753 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1754 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1755 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1756 #else
1757 static inline int intel_fbdev_init(struct drm_device *dev)
1758 {
1759         return 0;
1760 }
1761
1762 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1763 {
1764 }
1765
1766 static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
1767 {
1768 }
1769
1770 static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv)
1771 {
1772 }
1773
1774 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1775 {
1776 }
1777
1778 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1779 {
1780 }
1781
1782 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1783 {
1784 }
1785 #endif
1786
1787 /* intel_fbc.c */
1788 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1789                            struct intel_atomic_state *state);
1790 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1791 void intel_fbc_pre_update(struct intel_crtc *crtc,
1792                           struct intel_crtc_state *crtc_state,
1793                           struct intel_plane_state *plane_state);
1794 void intel_fbc_post_update(struct intel_crtc *crtc);
1795 void intel_fbc_init(struct drm_i915_private *dev_priv);
1796 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1797 void intel_fbc_enable(struct intel_crtc *crtc,
1798                       struct intel_crtc_state *crtc_state,
1799                       struct intel_plane_state *plane_state);
1800 void intel_fbc_disable(struct intel_crtc *crtc);
1801 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1802 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1803                           unsigned int frontbuffer_bits,
1804                           enum fb_op_origin origin);
1805 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1806                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1807 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1808 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1809 int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv);
1810
1811 /* intel_hdmi.c */
1812 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1813                      enum port port);
1814 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1815                                struct intel_connector *intel_connector);
1816 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1817 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1818                                struct intel_crtc_state *pipe_config,
1819                                struct drm_connector_state *conn_state);
1820 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
1821                                        struct drm_connector *connector,
1822                                        bool high_tmds_clock_ratio,
1823                                        bool scrambling);
1824 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1825 void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
1826
1827
1828 /* intel_lvds.c */
1829 bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,
1830                              i915_reg_t lvds_reg, enum pipe *pipe);
1831 void intel_lvds_init(struct drm_i915_private *dev_priv);
1832 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1833 bool intel_is_dual_link_lvds(struct drm_device *dev);
1834
1835
1836 /* intel_modes.c */
1837 int intel_connector_update_modes(struct drm_connector *connector,
1838                                  struct edid *edid);
1839 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1840 void intel_attach_force_audio_property(struct drm_connector *connector);
1841 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1842 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1843
1844
1845 /* intel_overlay.c */
1846 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1847 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1848 int intel_overlay_switch_off(struct intel_overlay *overlay);
1849 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1850                                   struct drm_file *file_priv);
1851 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1852                               struct drm_file *file_priv);
1853 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1854
1855
1856 /* intel_panel.c */
1857 int intel_panel_init(struct intel_panel *panel,
1858                      struct drm_display_mode *fixed_mode,
1859                      struct drm_display_mode *downclock_mode);
1860 void intel_panel_fini(struct intel_panel *panel);
1861 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1862                             struct drm_display_mode *adjusted_mode);
1863 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1864                              struct intel_crtc_state *pipe_config,
1865                              int fitting_mode);
1866 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1867                               struct intel_crtc_state *pipe_config,
1868                               int fitting_mode);
1869 void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
1870                                     u32 level, u32 max);
1871 int intel_panel_setup_backlight(struct drm_connector *connector,
1872                                 enum pipe pipe);
1873 void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
1874                                   const struct drm_connector_state *conn_state);
1875 void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state);
1876 void intel_panel_destroy_backlight(struct drm_connector *connector);
1877 enum drm_connector_status intel_panel_detect(struct drm_i915_private *dev_priv);
1878 extern struct drm_display_mode *intel_find_panel_downclock(
1879                                 struct drm_i915_private *dev_priv,
1880                                 struct drm_display_mode *fixed_mode,
1881                                 struct drm_connector *connector);
1882
1883 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1884 int intel_backlight_device_register(struct intel_connector *connector);
1885 void intel_backlight_device_unregister(struct intel_connector *connector);
1886 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1887 static inline int intel_backlight_device_register(struct intel_connector *connector)
1888 {
1889         return 0;
1890 }
1891 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1892 {
1893 }
1894 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1895
1896 /* intel_hdcp.c */
1897 void intel_hdcp_atomic_check(struct drm_connector *connector,
1898                              struct drm_connector_state *old_state,
1899                              struct drm_connector_state *new_state);
1900 int intel_hdcp_init(struct intel_connector *connector,
1901                     const struct intel_hdcp_shim *hdcp_shim);
1902 int intel_hdcp_enable(struct intel_connector *connector);
1903 int intel_hdcp_disable(struct intel_connector *connector);
1904 int intel_hdcp_check_link(struct intel_connector *connector);
1905 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
1906
1907 /* intel_psr.c */
1908 #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
1909 void intel_psr_init_dpcd(struct intel_dp *intel_dp);
1910 void intel_psr_enable(struct intel_dp *intel_dp,
1911                       const struct intel_crtc_state *crtc_state);
1912 void intel_psr_disable(struct intel_dp *intel_dp,
1913                       const struct intel_crtc_state *old_crtc_state);
1914 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1915                           unsigned frontbuffer_bits,
1916                           enum fb_op_origin origin);
1917 void intel_psr_flush(struct drm_i915_private *dev_priv,
1918                      unsigned frontbuffer_bits,
1919                      enum fb_op_origin origin);
1920 void intel_psr_init(struct drm_i915_private *dev_priv);
1921 void intel_psr_compute_config(struct intel_dp *intel_dp,
1922                               struct intel_crtc_state *crtc_state);
1923 void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool debug);
1924 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
1925 void intel_psr_short_pulse(struct intel_dp *intel_dp);
1926 int intel_psr_wait_for_idle(struct drm_i915_private *dev_priv);
1927
1928 /* intel_runtime_pm.c */
1929 int intel_power_domains_init(struct drm_i915_private *);
1930 void intel_power_domains_fini(struct drm_i915_private *);
1931 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1932 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1933 void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
1934 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1935 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1936 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1937 const char *
1938 intel_display_power_domain_str(enum intel_display_power_domain domain);
1939
1940 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1941                                     enum intel_display_power_domain domain);
1942 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1943                                       enum intel_display_power_domain domain);
1944 void intel_display_power_get(struct drm_i915_private *dev_priv,
1945                              enum intel_display_power_domain domain);
1946 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1947                                         enum intel_display_power_domain domain);
1948 void intel_display_power_put(struct drm_i915_private *dev_priv,
1949                              enum intel_display_power_domain domain);
1950 void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
1951                             u8 req_slices);
1952
1953 static inline void
1954 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1955 {
1956         WARN_ONCE(dev_priv->runtime_pm.suspended,
1957                   "Device suspended during HW access\n");
1958 }
1959
1960 static inline void
1961 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1962 {
1963         assert_rpm_device_not_suspended(dev_priv);
1964         WARN_ONCE(!atomic_read(&dev_priv->runtime_pm.wakeref_count),
1965                   "RPM wakelock ref not held during HW access");
1966 }
1967
1968 /**
1969  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1970  * @dev_priv: i915 device instance
1971  *
1972  * This function disable asserts that check if we hold an RPM wakelock
1973  * reference, while keeping the device-not-suspended checks still enabled.
1974  * It's meant to be used only in special circumstances where our rule about
1975  * the wakelock refcount wrt. the device power state doesn't hold. According
1976  * to this rule at any point where we access the HW or want to keep the HW in
1977  * an active state we must hold an RPM wakelock reference acquired via one of
1978  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1979  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1980  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1981  * users should avoid using this function.
1982  *
1983  * Any calls to this function must have a symmetric call to
1984  * enable_rpm_wakeref_asserts().
1985  */
1986 static inline void
1987 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1988 {
1989         atomic_inc(&dev_priv->runtime_pm.wakeref_count);
1990 }
1991
1992 /**
1993  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1994  * @dev_priv: i915 device instance
1995  *
1996  * This function re-enables the RPM assert checks after disabling them with
1997  * disable_rpm_wakeref_asserts. It's meant to be used only in special
1998  * circumstances otherwise its use should be avoided.
1999  *
2000  * Any calls to this function must have a symmetric call to
2001  * disable_rpm_wakeref_asserts().
2002  */
2003 static inline void
2004 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
2005 {
2006         atomic_dec(&dev_priv->runtime_pm.wakeref_count);
2007 }
2008
2009 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
2010 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
2011 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
2012 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
2013
2014 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
2015
2016 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
2017                              bool override, unsigned int mask);
2018 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
2019                           enum dpio_channel ch, bool override);
2020
2021
2022 /* intel_pm.c */
2023 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
2024 void intel_suspend_hw(struct drm_i915_private *dev_priv);
2025 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
2026 void intel_update_watermarks(struct intel_crtc *crtc);
2027 void intel_init_pm(struct drm_i915_private *dev_priv);
2028 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
2029 void intel_pm_setup(struct drm_i915_private *dev_priv);
2030 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
2031 void intel_gpu_ips_teardown(void);
2032 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
2033 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
2034 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
2035 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
2036 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
2037 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
2038 void gen6_rps_busy(struct drm_i915_private *dev_priv);
2039 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
2040 void gen6_rps_idle(struct drm_i915_private *dev_priv);
2041 void gen6_rps_boost(struct i915_request *rq, struct intel_rps_client *rps);
2042 void g4x_wm_get_hw_state(struct drm_device *dev);
2043 void vlv_wm_get_hw_state(struct drm_device *dev);
2044 void ilk_wm_get_hw_state(struct drm_device *dev);
2045 void skl_wm_get_hw_state(struct drm_device *dev);
2046 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2047                           struct skl_ddb_allocation *ddb /* out */);
2048 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
2049                               struct skl_pipe_wm *out);
2050 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
2051 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
2052 bool intel_can_enable_sagv(struct drm_atomic_state *state);
2053 int intel_enable_sagv(struct drm_i915_private *dev_priv);
2054 int intel_disable_sagv(struct drm_i915_private *dev_priv);
2055 bool skl_wm_level_equals(const struct skl_wm_level *l1,
2056                          const struct skl_wm_level *l2);
2057 bool skl_ddb_allocation_overlaps(struct drm_i915_private *dev_priv,
2058                                  const struct skl_ddb_entry **entries,
2059                                  const struct skl_ddb_entry *ddb,
2060                                  int ignore);
2061 bool ilk_disable_lp_wm(struct drm_device *dev);
2062 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
2063                                   struct intel_crtc_state *cstate);
2064 void intel_init_ipc(struct drm_i915_private *dev_priv);
2065 void intel_enable_ipc(struct drm_i915_private *dev_priv);
2066
2067 /* intel_sdvo.c */
2068 bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
2069                              i915_reg_t sdvo_reg, enum pipe *pipe);
2070 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
2071                      i915_reg_t reg, enum port port);
2072
2073
2074 /* intel_sprite.c */
2075 bool intel_format_is_yuv(u32 format);
2076 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
2077                              int usecs);
2078 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
2079                                               enum pipe pipe, int plane);
2080 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
2081                                     struct drm_file *file_priv);
2082 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
2083 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
2084 void skl_update_plane(struct intel_plane *plane,
2085                       const struct intel_crtc_state *crtc_state,
2086                       const struct intel_plane_state *plane_state);
2087 void skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc);
2088 bool skl_plane_get_hw_state(struct intel_plane *plane, enum pipe *pipe);
2089 bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
2090                        enum pipe pipe, enum plane_id plane_id);
2091 bool intel_format_is_yuv(uint32_t format);
2092 bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
2093                           enum pipe pipe, enum plane_id plane_id);
2094
2095 /* intel_tv.c */
2096 void intel_tv_init(struct drm_i915_private *dev_priv);
2097
2098 /* intel_atomic.c */
2099 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
2100                                                 const struct drm_connector_state *state,
2101                                                 struct drm_property *property,
2102                                                 uint64_t *val);
2103 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
2104                                                 struct drm_connector_state *state,
2105                                                 struct drm_property *property,
2106                                                 uint64_t val);
2107 int intel_digital_connector_atomic_check(struct drm_connector *conn,
2108                                          struct drm_connector_state *new_state);
2109 struct drm_connector_state *
2110 intel_digital_connector_duplicate_state(struct drm_connector *connector);
2111
2112 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
2113 void intel_crtc_destroy_state(struct drm_crtc *crtc,
2114                                struct drm_crtc_state *state);
2115 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
2116 void intel_atomic_state_clear(struct drm_atomic_state *);
2117
2118 static inline struct intel_crtc_state *
2119 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
2120                             struct intel_crtc *crtc)
2121 {
2122         struct drm_crtc_state *crtc_state;
2123         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
2124         if (IS_ERR(crtc_state))
2125                 return ERR_CAST(crtc_state);
2126
2127         return to_intel_crtc_state(crtc_state);
2128 }
2129
2130 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
2131                                struct intel_crtc *intel_crtc,
2132                                struct intel_crtc_state *crtc_state);
2133
2134 /* intel_atomic_plane.c */
2135 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
2136 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
2137 void intel_plane_destroy_state(struct drm_plane *plane,
2138                                struct drm_plane_state *state);
2139 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
2140 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
2141                                         struct intel_crtc_state *crtc_state,
2142                                         const struct intel_plane_state *old_plane_state,
2143                                         struct intel_plane_state *intel_state);
2144
2145 /* intel_color.c */
2146 void intel_color_init(struct drm_crtc *crtc);
2147 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
2148 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
2149 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
2150
2151 /* intel_lspcon.c */
2152 bool lspcon_init(struct intel_digital_port *intel_dig_port);
2153 void lspcon_resume(struct intel_lspcon *lspcon);
2154 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
2155
2156 /* intel_pipe_crc.c */
2157 #ifdef CONFIG_DEBUG_FS
2158 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
2159                               size_t *values_cnt);
2160 void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc);
2161 void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc);
2162 #else
2163 #define intel_crtc_set_crc_source NULL
2164 static inline void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
2165 {
2166 }
2167
2168 static inline void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc)
2169 {
2170 }
2171 #endif
2172 #endif /* __INTEL_DRV_H__ */