Merge airlied/drm-next into drm-intel-next-queued
[muen/linux.git] / drivers / gpu / drm / i915 / intel_drv.h
1 /*
2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3  * Copyright (c) 2007-2008 Intel Corporation
4  *   Jesse Barnes <jesse.barnes@intel.com>
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice (including the next
14  * paragraph) shall be included in all copies or substantial portions of the
15  * Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23  * IN THE SOFTWARE.
24  */
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
27
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <linux/sched/clock.h>
32 #include <drm/i915_drm.h>
33 #include "i915_drv.h"
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_encoder.h>
37 #include <drm/drm_fb_helper.h>
38 #include <drm/drm_dp_dual_mode_helper.h>
39 #include <drm/drm_dp_mst_helper.h>
40 #include <drm/drm_rect.h>
41 #include <drm/drm_atomic.h>
42
43 /**
44  * _wait_for - magic (register) wait macro
45  *
46  * Does the right thing for modeset paths when run under kdgb or similar atomic
47  * contexts. Note that it's important that we check the condition again after
48  * having timed out, since the timeout could be due to preemption or similar and
49  * we've never had a chance to check the condition before the timeout.
50  *
51  * TODO: When modesetting has fully transitioned to atomic, the below
52  * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
53  * added.
54  */
55 #define _wait_for(COND, US, W) ({ \
56         unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1;   \
57         int ret__;                                                      \
58         for (;;) {                                                      \
59                 bool expired__ = time_after(jiffies, timeout__);        \
60                 if (COND) {                                             \
61                         ret__ = 0;                                      \
62                         break;                                          \
63                 }                                                       \
64                 if (expired__) {                                        \
65                         ret__ = -ETIMEDOUT;                             \
66                         break;                                          \
67                 }                                                       \
68                 if ((W) && drm_can_sleep()) {                           \
69                         usleep_range((W), (W)*2);                       \
70                 } else {                                                \
71                         cpu_relax();                                    \
72                 }                                                       \
73         }                                                               \
74         ret__;                                                          \
75 })
76
77 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 1000)
78
79 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
80 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
81 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
82 #else
83 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
84 #endif
85
86 #define _wait_for_atomic(COND, US, ATOMIC) \
87 ({ \
88         int cpu, ret, timeout = (US) * 1000; \
89         u64 base; \
90         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
91         if (!(ATOMIC)) { \
92                 preempt_disable(); \
93                 cpu = smp_processor_id(); \
94         } \
95         base = local_clock(); \
96         for (;;) { \
97                 u64 now = local_clock(); \
98                 if (!(ATOMIC)) \
99                         preempt_enable(); \
100                 if (COND) { \
101                         ret = 0; \
102                         break; \
103                 } \
104                 if (now - base >= timeout) { \
105                         ret = -ETIMEDOUT; \
106                         break; \
107                 } \
108                 cpu_relax(); \
109                 if (!(ATOMIC)) { \
110                         preempt_disable(); \
111                         if (unlikely(cpu != smp_processor_id())) { \
112                                 timeout -= now - base; \
113                                 cpu = smp_processor_id(); \
114                                 base = local_clock(); \
115                         } \
116                 } \
117         } \
118         ret; \
119 })
120
121 #define wait_for_us(COND, US) \
122 ({ \
123         int ret__; \
124         BUILD_BUG_ON(!__builtin_constant_p(US)); \
125         if ((US) > 10) \
126                 ret__ = _wait_for((COND), (US), 10); \
127         else \
128                 ret__ = _wait_for_atomic((COND), (US), 0); \
129         ret__; \
130 })
131
132 #define wait_for_atomic_us(COND, US) \
133 ({ \
134         BUILD_BUG_ON(!__builtin_constant_p(US)); \
135         BUILD_BUG_ON((US) > 50000); \
136         _wait_for_atomic((COND), (US), 1); \
137 })
138
139 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
140
141 #define KHz(x) (1000 * (x))
142 #define MHz(x) KHz(1000 * (x))
143
144 /*
145  * Display related stuff
146  */
147
148 /* store information about an Ixxx DVO */
149 /* The i830->i865 use multiple DVOs with multiple i2cs */
150 /* the i915, i945 have a single sDVO i2c bus - which is different */
151 #define MAX_OUTPUTS 6
152 /* maximum connectors per crtcs in the mode set */
153
154 /* Maximum cursor sizes */
155 #define GEN2_CURSOR_WIDTH 64
156 #define GEN2_CURSOR_HEIGHT 64
157 #define MAX_CURSOR_WIDTH 256
158 #define MAX_CURSOR_HEIGHT 256
159
160 #define INTEL_I2C_BUS_DVO 1
161 #define INTEL_I2C_BUS_SDVO 2
162
163 /* these are outputs from the chip - integrated only
164    external chips are via DVO or SDVO output */
165 enum intel_output_type {
166         INTEL_OUTPUT_UNUSED = 0,
167         INTEL_OUTPUT_ANALOG = 1,
168         INTEL_OUTPUT_DVO = 2,
169         INTEL_OUTPUT_SDVO = 3,
170         INTEL_OUTPUT_LVDS = 4,
171         INTEL_OUTPUT_TVOUT = 5,
172         INTEL_OUTPUT_HDMI = 6,
173         INTEL_OUTPUT_DP = 7,
174         INTEL_OUTPUT_EDP = 8,
175         INTEL_OUTPUT_DSI = 9,
176         INTEL_OUTPUT_UNKNOWN = 10,
177         INTEL_OUTPUT_DP_MST = 11,
178 };
179
180 #define INTEL_DVO_CHIP_NONE 0
181 #define INTEL_DVO_CHIP_LVDS 1
182 #define INTEL_DVO_CHIP_TMDS 2
183 #define INTEL_DVO_CHIP_TVOUT 4
184
185 #define INTEL_DSI_VIDEO_MODE    0
186 #define INTEL_DSI_COMMAND_MODE  1
187
188 struct intel_framebuffer {
189         struct drm_framebuffer base;
190         struct drm_i915_gem_object *obj;
191         struct intel_rotation_info rot_info;
192
193         /* for each plane in the normal GTT view */
194         struct {
195                 unsigned int x, y;
196         } normal[2];
197         /* for each plane in the rotated GTT view */
198         struct {
199                 unsigned int x, y;
200                 unsigned int pitch; /* pixels */
201         } rotated[2];
202 };
203
204 struct intel_fbdev {
205         struct drm_fb_helper helper;
206         struct intel_framebuffer *fb;
207         struct i915_vma *vma;
208         async_cookie_t cookie;
209         int preferred_bpp;
210 };
211
212 struct intel_encoder {
213         struct drm_encoder base;
214
215         enum intel_output_type type;
216         enum port port;
217         unsigned int cloneable;
218         void (*hot_plug)(struct intel_encoder *);
219         bool (*compute_config)(struct intel_encoder *,
220                                struct intel_crtc_state *,
221                                struct drm_connector_state *);
222         void (*pre_pll_enable)(struct intel_encoder *,
223                                struct intel_crtc_state *,
224                                struct drm_connector_state *);
225         void (*pre_enable)(struct intel_encoder *,
226                            struct intel_crtc_state *,
227                            struct drm_connector_state *);
228         void (*enable)(struct intel_encoder *,
229                        struct intel_crtc_state *,
230                        struct drm_connector_state *);
231         void (*disable)(struct intel_encoder *,
232                         struct intel_crtc_state *,
233                         struct drm_connector_state *);
234         void (*post_disable)(struct intel_encoder *,
235                              struct intel_crtc_state *,
236                              struct drm_connector_state *);
237         void (*post_pll_disable)(struct intel_encoder *,
238                                  struct intel_crtc_state *,
239                                  struct drm_connector_state *);
240         /* Read out the current hw state of this connector, returning true if
241          * the encoder is active. If the encoder is enabled it also set the pipe
242          * it is connected to in the pipe parameter. */
243         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
244         /* Reconstructs the equivalent mode flags for the current hardware
245          * state. This must be called _after_ display->get_pipe_config has
246          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
247          * be set correctly before calling this function. */
248         void (*get_config)(struct intel_encoder *,
249                            struct intel_crtc_state *pipe_config);
250         /* Returns a mask of power domains that need to be referenced as part
251          * of the hardware state readout code. */
252         u64 (*get_power_domains)(struct intel_encoder *encoder);
253         /*
254          * Called during system suspend after all pending requests for the
255          * encoder are flushed (for example for DP AUX transactions) and
256          * device interrupts are disabled.
257          */
258         void (*suspend)(struct intel_encoder *);
259         int crtc_mask;
260         enum hpd_pin hpd_pin;
261         enum intel_display_power_domain power_domain;
262         /* for communication with audio component; protected by av_mutex */
263         const struct drm_connector *audio_connector;
264 };
265
266 struct intel_panel {
267         struct drm_display_mode *fixed_mode;
268         struct drm_display_mode *downclock_mode;
269
270         /* backlight */
271         struct {
272                 bool present;
273                 u32 level;
274                 u32 min;
275                 u32 max;
276                 bool enabled;
277                 bool combination_mode;  /* gen 2/4 only */
278                 bool active_low_pwm;
279                 bool alternate_pwm_increment;   /* lpt+ */
280
281                 /* PWM chip */
282                 bool util_pin_active_low;       /* bxt+ */
283                 u8 controller;          /* bxt+ only */
284                 struct pwm_device *pwm;
285
286                 struct backlight_device *device;
287
288                 /* Connector and platform specific backlight functions */
289                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
290                 uint32_t (*get)(struct intel_connector *connector);
291                 void (*set)(const struct drm_connector_state *conn_state, uint32_t level);
292                 void (*disable)(const struct drm_connector_state *conn_state);
293                 void (*enable)(const struct intel_crtc_state *crtc_state,
294                                const struct drm_connector_state *conn_state);
295                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
296                                       uint32_t hz);
297                 void (*power)(struct intel_connector *, bool enable);
298         } backlight;
299 };
300
301 struct intel_connector {
302         struct drm_connector base;
303         /*
304          * The fixed encoder this connector is connected to.
305          */
306         struct intel_encoder *encoder;
307
308         /* ACPI device id for ACPI and driver cooperation */
309         u32 acpi_device_id;
310
311         /* Reads out the current hw, returning true if the connector is enabled
312          * and active (i.e. dpms ON state). */
313         bool (*get_hw_state)(struct intel_connector *);
314
315         /* Panel info for eDP and LVDS */
316         struct intel_panel panel;
317
318         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
319         struct edid *edid;
320         struct edid *detect_edid;
321
322         /* since POLL and HPD connectors may use the same HPD line keep the native
323            state of connector->polled in case hotplug storm detection changes it */
324         u8 polled;
325
326         void *port; /* store this opaque as its illegal to dereference it */
327
328         struct intel_dp *mst_port;
329
330         /* Work struct to schedule a uevent on link train failure */
331         struct work_struct modeset_retry_work;
332 };
333
334 struct intel_digital_connector_state {
335         struct drm_connector_state base;
336
337         enum hdmi_force_audio force_audio;
338         int broadcast_rgb;
339 };
340
341 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
342
343 struct dpll {
344         /* given values */
345         int n;
346         int m1, m2;
347         int p1, p2;
348         /* derived values */
349         int     dot;
350         int     vco;
351         int     m;
352         int     p;
353 };
354
355 struct intel_atomic_state {
356         struct drm_atomic_state base;
357
358         struct {
359                 /*
360                  * Logical state of cdclk (used for all scaling, watermark,
361                  * etc. calculations and checks). This is computed as if all
362                  * enabled crtcs were active.
363                  */
364                 struct intel_cdclk_state logical;
365
366                 /*
367                  * Actual state of cdclk, can be different from the logical
368                  * state only when all crtc's are DPMS off.
369                  */
370                 struct intel_cdclk_state actual;
371         } cdclk;
372
373         bool dpll_set, modeset;
374
375         /*
376          * Does this transaction change the pipes that are active?  This mask
377          * tracks which CRTC's have changed their active state at the end of
378          * the transaction (not counting the temporary disable during modesets).
379          * This mask should only be non-zero when intel_state->modeset is true,
380          * but the converse is not necessarily true; simply changing a mode may
381          * not flip the final active status of any CRTC's
382          */
383         unsigned int active_pipe_changes;
384
385         unsigned int active_crtcs;
386         unsigned int min_pixclk[I915_MAX_PIPES];
387
388         struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
389
390         /*
391          * Current watermarks can't be trusted during hardware readout, so
392          * don't bother calculating intermediate watermarks.
393          */
394         bool skip_intermediate_wm;
395
396         /* Gen9+ only */
397         struct skl_wm_values wm_results;
398
399         struct i915_sw_fence commit_ready;
400
401         struct llist_node freed;
402 };
403
404 struct intel_plane_state {
405         struct drm_plane_state base;
406         struct drm_rect clip;
407         struct i915_vma *vma;
408
409         struct {
410                 u32 offset;
411                 int x, y;
412         } main;
413         struct {
414                 u32 offset;
415                 int x, y;
416         } aux;
417
418         /* plane control register */
419         u32 ctl;
420
421         /*
422          * scaler_id
423          *    = -1 : not using a scaler
424          *    >=  0 : using a scalers
425          *
426          * plane requiring a scaler:
427          *   - During check_plane, its bit is set in
428          *     crtc_state->scaler_state.scaler_users by calling helper function
429          *     update_scaler_plane.
430          *   - scaler_id indicates the scaler it got assigned.
431          *
432          * plane doesn't require a scaler:
433          *   - this can happen when scaling is no more required or plane simply
434          *     got disabled.
435          *   - During check_plane, corresponding bit is reset in
436          *     crtc_state->scaler_state.scaler_users by calling helper function
437          *     update_scaler_plane.
438          */
439         int scaler_id;
440
441         struct drm_intel_sprite_colorkey ckey;
442 };
443
444 struct intel_initial_plane_config {
445         struct intel_framebuffer *fb;
446         unsigned int tiling;
447         int size;
448         u32 base;
449 };
450
451 #define SKL_MIN_SRC_W 8
452 #define SKL_MAX_SRC_W 4096
453 #define SKL_MIN_SRC_H 8
454 #define SKL_MAX_SRC_H 4096
455 #define SKL_MIN_DST_W 8
456 #define SKL_MAX_DST_W 4096
457 #define SKL_MIN_DST_H 8
458 #define SKL_MAX_DST_H 4096
459
460 struct intel_scaler {
461         int in_use;
462         uint32_t mode;
463 };
464
465 struct intel_crtc_scaler_state {
466 #define SKL_NUM_SCALERS 2
467         struct intel_scaler scalers[SKL_NUM_SCALERS];
468
469         /*
470          * scaler_users: keeps track of users requesting scalers on this crtc.
471          *
472          *     If a bit is set, a user is using a scaler.
473          *     Here user can be a plane or crtc as defined below:
474          *       bits 0-30 - plane (bit position is index from drm_plane_index)
475          *       bit 31    - crtc
476          *
477          * Instead of creating a new index to cover planes and crtc, using
478          * existing drm_plane_index for planes which is well less than 31
479          * planes and bit 31 for crtc. This should be fine to cover all
480          * our platforms.
481          *
482          * intel_atomic_setup_scalers will setup available scalers to users
483          * requesting scalers. It will gracefully fail if request exceeds
484          * avilability.
485          */
486 #define SKL_CRTC_INDEX 31
487         unsigned scaler_users;
488
489         /* scaler used by crtc for panel fitting purpose */
490         int scaler_id;
491 };
492
493 /* drm_mode->private_flags */
494 #define I915_MODE_FLAG_INHERITED 1
495
496 struct intel_pipe_wm {
497         struct intel_wm_level wm[5];
498         struct intel_wm_level raw_wm[5];
499         uint32_t linetime;
500         bool fbc_wm_enabled;
501         bool pipe_enabled;
502         bool sprites_enabled;
503         bool sprites_scaled;
504 };
505
506 struct skl_plane_wm {
507         struct skl_wm_level wm[8];
508         struct skl_wm_level trans_wm;
509 };
510
511 struct skl_pipe_wm {
512         struct skl_plane_wm planes[I915_MAX_PLANES];
513         uint32_t linetime;
514 };
515
516 enum vlv_wm_level {
517         VLV_WM_LEVEL_PM2,
518         VLV_WM_LEVEL_PM5,
519         VLV_WM_LEVEL_DDR_DVFS,
520         NUM_VLV_WM_LEVELS,
521 };
522
523 struct vlv_wm_state {
524         struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
525         struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
526         uint8_t num_levels;
527         bool cxsr;
528 };
529
530 struct vlv_fifo_state {
531         u16 plane[I915_MAX_PLANES];
532 };
533
534 enum g4x_wm_level {
535         G4X_WM_LEVEL_NORMAL,
536         G4X_WM_LEVEL_SR,
537         G4X_WM_LEVEL_HPLL,
538         NUM_G4X_WM_LEVELS,
539 };
540
541 struct g4x_wm_state {
542         struct g4x_pipe_wm wm;
543         struct g4x_sr_wm sr;
544         struct g4x_sr_wm hpll;
545         bool cxsr;
546         bool hpll_en;
547         bool fbc_en;
548 };
549
550 struct intel_crtc_wm_state {
551         union {
552                 struct {
553                         /*
554                          * Intermediate watermarks; these can be
555                          * programmed immediately since they satisfy
556                          * both the current configuration we're
557                          * switching away from and the new
558                          * configuration we're switching to.
559                          */
560                         struct intel_pipe_wm intermediate;
561
562                         /*
563                          * Optimal watermarks, programmed post-vblank
564                          * when this state is committed.
565                          */
566                         struct intel_pipe_wm optimal;
567                 } ilk;
568
569                 struct {
570                         /* gen9+ only needs 1-step wm programming */
571                         struct skl_pipe_wm optimal;
572                         struct skl_ddb_entry ddb;
573                 } skl;
574
575                 struct {
576                         /* "raw" watermarks (not inverted) */
577                         struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
578                         /* intermediate watermarks (inverted) */
579                         struct vlv_wm_state intermediate;
580                         /* optimal watermarks (inverted) */
581                         struct vlv_wm_state optimal;
582                         /* display FIFO split */
583                         struct vlv_fifo_state fifo_state;
584                 } vlv;
585
586                 struct {
587                         /* "raw" watermarks */
588                         struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
589                         /* intermediate watermarks */
590                         struct g4x_wm_state intermediate;
591                         /* optimal watermarks */
592                         struct g4x_wm_state optimal;
593                 } g4x;
594         };
595
596         /*
597          * Platforms with two-step watermark programming will need to
598          * update watermark programming post-vblank to switch from the
599          * safe intermediate watermarks to the optimal final
600          * watermarks.
601          */
602         bool need_postvbl_update;
603 };
604
605 struct intel_crtc_state {
606         struct drm_crtc_state base;
607
608         /**
609          * quirks - bitfield with hw state readout quirks
610          *
611          * For various reasons the hw state readout code might not be able to
612          * completely faithfully read out the current state. These cases are
613          * tracked with quirk flags so that fastboot and state checker can act
614          * accordingly.
615          */
616 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
617         unsigned long quirks;
618
619         unsigned fb_bits; /* framebuffers to flip */
620         bool update_pipe; /* can a fast modeset be performed? */
621         bool disable_cxsr;
622         bool update_wm_pre, update_wm_post; /* watermarks are updated */
623         bool fb_changed; /* fb on any of the planes is changed */
624         bool fifo_changed; /* FIFO split is changed */
625
626         /* Pipe source size (ie. panel fitter input size)
627          * All planes will be positioned inside this space,
628          * and get clipped at the edges. */
629         int pipe_src_w, pipe_src_h;
630
631         /*
632          * Pipe pixel rate, adjusted for
633          * panel fitter/pipe scaler downscaling.
634          */
635         unsigned int pixel_rate;
636
637         /* Whether to set up the PCH/FDI. Note that we never allow sharing
638          * between pch encoders and cpu encoders. */
639         bool has_pch_encoder;
640
641         /* Are we sending infoframes on the attached port */
642         bool has_infoframe;
643
644         /* CPU Transcoder for the pipe. Currently this can only differ from the
645          * pipe on Haswell and later (where we have a special eDP transcoder)
646          * and Broxton (where we have special DSI transcoders). */
647         enum transcoder cpu_transcoder;
648
649         /*
650          * Use reduced/limited/broadcast rbg range, compressing from the full
651          * range fed into the crtcs.
652          */
653         bool limited_color_range;
654
655         /* Bitmask of encoder types (enum intel_output_type)
656          * driven by the pipe.
657          */
658         unsigned int output_types;
659
660         /* Whether we should send NULL infoframes. Required for audio. */
661         bool has_hdmi_sink;
662
663         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
664          * has_dp_encoder is set. */
665         bool has_audio;
666
667         /*
668          * Enable dithering, used when the selected pipe bpp doesn't match the
669          * plane bpp.
670          */
671         bool dither;
672
673         /*
674          * Dither gets enabled for 18bpp which causes CRC mismatch errors for
675          * compliance video pattern tests.
676          * Disable dither only if it is a compliance test request for
677          * 18bpp.
678          */
679         bool dither_force_disable;
680
681         /* Controls for the clock computation, to override various stages. */
682         bool clock_set;
683
684         /* SDVO TV has a bunch of special case. To make multifunction encoders
685          * work correctly, we need to track this at runtime.*/
686         bool sdvo_tv_clock;
687
688         /*
689          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
690          * required. This is set in the 2nd loop of calling encoder's
691          * ->compute_config if the first pick doesn't work out.
692          */
693         bool bw_constrained;
694
695         /* Settings for the intel dpll used on pretty much everything but
696          * haswell. */
697         struct dpll dpll;
698
699         /* Selected dpll when shared or NULL. */
700         struct intel_shared_dpll *shared_dpll;
701
702         /* Actual register state of the dpll, for shared dpll cross-checking. */
703         struct intel_dpll_hw_state dpll_hw_state;
704
705         /* DSI PLL registers */
706         struct {
707                 u32 ctrl, div;
708         } dsi_pll;
709
710         int pipe_bpp;
711         struct intel_link_m_n dp_m_n;
712
713         /* m2_n2 for eDP downclock */
714         struct intel_link_m_n dp_m2_n2;
715         bool has_drrs;
716
717         /*
718          * Frequence the dpll for the port should run at. Differs from the
719          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
720          * already multiplied by pixel_multiplier.
721          */
722         int port_clock;
723
724         /* Used by SDVO (and if we ever fix it, HDMI). */
725         unsigned pixel_multiplier;
726
727         uint8_t lane_count;
728
729         /*
730          * Used by platforms having DP/HDMI PHY with programmable lane
731          * latency optimization.
732          */
733         uint8_t lane_lat_optim_mask;
734
735         /* Panel fitter controls for gen2-gen4 + VLV */
736         struct {
737                 u32 control;
738                 u32 pgm_ratios;
739                 u32 lvds_border_bits;
740         } gmch_pfit;
741
742         /* Panel fitter placement and size for Ironlake+ */
743         struct {
744                 u32 pos;
745                 u32 size;
746                 bool enabled;
747                 bool force_thru;
748         } pch_pfit;
749
750         /* FDI configuration, only valid if has_pch_encoder is set. */
751         int fdi_lanes;
752         struct intel_link_m_n fdi_m_n;
753
754         bool ips_enabled;
755
756         bool enable_fbc;
757
758         bool double_wide;
759
760         int pbn;
761
762         struct intel_crtc_scaler_state scaler_state;
763
764         /* w/a for waiting 2 vblanks during crtc enable */
765         enum pipe hsw_workaround_pipe;
766
767         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
768         bool disable_lp_wm;
769
770         struct intel_crtc_wm_state wm;
771
772         /* Gamma mode programmed on the pipe */
773         uint32_t gamma_mode;
774
775         /* bitmask of visible planes (enum plane_id) */
776         u8 active_planes;
777
778         /* HDMI scrambling status */
779         bool hdmi_scrambling;
780
781         /* HDMI High TMDS char rate ratio */
782         bool hdmi_high_tmds_clock_ratio;
783
784         /* output format is YCBCR 4:2:0 */
785         bool ycbcr420;
786 };
787
788 struct intel_crtc {
789         struct drm_crtc base;
790         enum pipe pipe;
791         enum plane plane;
792         /*
793          * Whether the crtc and the connected output pipeline is active. Implies
794          * that crtc->enabled is set, i.e. the current mode configuration has
795          * some outputs connected to this crtc.
796          */
797         bool active;
798         bool lowfreq_avail;
799         u8 plane_ids_mask;
800         unsigned long long enabled_power_domains;
801         struct intel_overlay *overlay;
802
803         /* Display surface base address adjustement for pageflips. Note that on
804          * gen4+ this only adjusts up to a tile, offsets within a tile are
805          * handled in the hw itself (with the TILEOFF register). */
806         u32 dspaddr_offset;
807         int adjusted_x;
808         int adjusted_y;
809
810         struct intel_crtc_state *config;
811
812         /* global reset count when the last flip was submitted */
813         unsigned int reset_count;
814
815         /* Access to these should be protected by dev_priv->irq_lock. */
816         bool cpu_fifo_underrun_disabled;
817         bool pch_fifo_underrun_disabled;
818
819         /* per-pipe watermark state */
820         struct {
821                 /* watermarks currently being used  */
822                 union {
823                         struct intel_pipe_wm ilk;
824                         struct vlv_wm_state vlv;
825                         struct g4x_wm_state g4x;
826                 } active;
827         } wm;
828
829         int scanline_offset;
830
831         struct {
832                 unsigned start_vbl_count;
833                 ktime_t start_vbl_time;
834                 int min_vbl, max_vbl;
835                 int scanline_start;
836         } debug;
837
838         /* scalers available on this crtc */
839         int num_scalers;
840 };
841
842 struct intel_plane {
843         struct drm_plane base;
844         u8 plane;
845         enum plane_id id;
846         enum pipe pipe;
847         bool can_scale;
848         int max_downscale;
849         uint32_t frontbuffer_bit;
850
851         struct {
852                 u32 base, cntl, size;
853         } cursor;
854
855         /*
856          * NOTE: Do not place new plane state fields here (e.g., when adding
857          * new plane properties).  New runtime state should now be placed in
858          * the intel_plane_state structure and accessed via plane_state.
859          */
860
861         void (*update_plane)(struct intel_plane *plane,
862                              const struct intel_crtc_state *crtc_state,
863                              const struct intel_plane_state *plane_state);
864         void (*disable_plane)(struct intel_plane *plane,
865                               struct intel_crtc *crtc);
866         int (*check_plane)(struct intel_plane *plane,
867                            struct intel_crtc_state *crtc_state,
868                            struct intel_plane_state *state);
869 };
870
871 struct intel_watermark_params {
872         u16 fifo_size;
873         u16 max_wm;
874         u8 default_wm;
875         u8 guard_size;
876         u8 cacheline_size;
877 };
878
879 struct cxsr_latency {
880         bool is_desktop : 1;
881         bool is_ddr3 : 1;
882         u16 fsb_freq;
883         u16 mem_freq;
884         u16 display_sr;
885         u16 display_hpll_disable;
886         u16 cursor_sr;
887         u16 cursor_hpll_disable;
888 };
889
890 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
891 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
892 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
893 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
894 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
895 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
896 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
897 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
898 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
899
900 struct intel_hdmi {
901         i915_reg_t hdmi_reg;
902         int ddc_bus;
903         struct {
904                 enum drm_dp_dual_mode_type type;
905                 int max_tmds_clock;
906         } dp_dual_mode;
907         bool has_hdmi_sink;
908         bool has_audio;
909         bool rgb_quant_range_selectable;
910         struct intel_connector *attached_connector;
911         void (*write_infoframe)(struct drm_encoder *encoder,
912                                 const struct intel_crtc_state *crtc_state,
913                                 enum hdmi_infoframe_type type,
914                                 const void *frame, ssize_t len);
915         void (*set_infoframes)(struct drm_encoder *encoder,
916                                bool enable,
917                                const struct intel_crtc_state *crtc_state,
918                                const struct drm_connector_state *conn_state);
919         bool (*infoframe_enabled)(struct drm_encoder *encoder,
920                                   const struct intel_crtc_state *pipe_config);
921 };
922
923 struct intel_dp_mst_encoder;
924 #define DP_MAX_DOWNSTREAM_PORTS         0x10
925
926 /*
927  * enum link_m_n_set:
928  *      When platform provides two set of M_N registers for dp, we can
929  *      program them and switch between them incase of DRRS.
930  *      But When only one such register is provided, we have to program the
931  *      required divider value on that registers itself based on the DRRS state.
932  *
933  * M1_N1        : Program dp_m_n on M1_N1 registers
934  *                        dp_m2_n2 on M2_N2 registers (If supported)
935  *
936  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
937  *                        M2_N2 registers are not supported
938  */
939
940 enum link_m_n_set {
941         /* Sets the m1_n1 and m2_n2 */
942         M1_N1 = 0,
943         M2_N2
944 };
945
946 struct intel_dp_compliance_data {
947         unsigned long edid;
948         uint8_t video_pattern;
949         uint16_t hdisplay, vdisplay;
950         uint8_t bpc;
951 };
952
953 struct intel_dp_compliance {
954         unsigned long test_type;
955         struct intel_dp_compliance_data test_data;
956         bool test_active;
957         int test_link_rate;
958         u8 test_lane_count;
959 };
960
961 struct intel_dp {
962         i915_reg_t output_reg;
963         i915_reg_t aux_ch_ctl_reg;
964         i915_reg_t aux_ch_data_reg[5];
965         uint32_t DP;
966         int link_rate;
967         uint8_t lane_count;
968         uint8_t sink_count;
969         bool link_mst;
970         bool has_audio;
971         bool detect_done;
972         bool channel_eq_status;
973         bool reset_link_params;
974         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
975         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
976         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
977         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
978         /* source rates */
979         int num_source_rates;
980         const int *source_rates;
981         /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
982         int num_sink_rates;
983         int sink_rates[DP_MAX_SUPPORTED_RATES];
984         bool use_rate_select;
985         /* intersection of source and sink rates */
986         int num_common_rates;
987         int common_rates[DP_MAX_SUPPORTED_RATES];
988         /* Max lane count for the current link */
989         int max_link_lane_count;
990         /* Max rate for the current link */
991         int max_link_rate;
992         /* sink or branch descriptor */
993         struct drm_dp_desc desc;
994         struct drm_dp_aux aux;
995         enum intel_display_power_domain aux_power_domain;
996         uint8_t train_set[4];
997         int panel_power_up_delay;
998         int panel_power_down_delay;
999         int panel_power_cycle_delay;
1000         int backlight_on_delay;
1001         int backlight_off_delay;
1002         struct delayed_work panel_vdd_work;
1003         bool want_panel_vdd;
1004         unsigned long last_power_on;
1005         unsigned long last_backlight_off;
1006         ktime_t panel_power_off_time;
1007
1008         struct notifier_block edp_notifier;
1009
1010         /*
1011          * Pipe whose power sequencer is currently locked into
1012          * this port. Only relevant on VLV/CHV.
1013          */
1014         enum pipe pps_pipe;
1015         /*
1016          * Pipe currently driving the port. Used for preventing
1017          * the use of the PPS for any pipe currentrly driving
1018          * external DP as that will mess things up on VLV.
1019          */
1020         enum pipe active_pipe;
1021         /*
1022          * Set if the sequencer may be reset due to a power transition,
1023          * requiring a reinitialization. Only relevant on BXT.
1024          */
1025         bool pps_reset;
1026         struct edp_power_seq pps_delays;
1027
1028         bool can_mst; /* this port supports mst */
1029         bool is_mst;
1030         int active_mst_links;
1031         /* connector directly attached - won't be use for modeset in mst world */
1032         struct intel_connector *attached_connector;
1033
1034         /* mst connector list */
1035         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1036         struct drm_dp_mst_topology_mgr mst_mgr;
1037
1038         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1039         /*
1040          * This function returns the value we have to program the AUX_CTL
1041          * register with to kick off an AUX transaction.
1042          */
1043         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
1044                                      bool has_aux_irq,
1045                                      int send_bytes,
1046                                      uint32_t aux_clock_divider);
1047
1048         /* This is called before a link training is starterd */
1049         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1050
1051         /* Displayport compliance testing */
1052         struct intel_dp_compliance compliance;
1053 };
1054
1055 struct intel_lspcon {
1056         bool active;
1057         enum drm_lspcon_mode mode;
1058 };
1059
1060 struct intel_digital_port {
1061         struct intel_encoder base;
1062         enum port port;
1063         u32 saved_port_bits;
1064         struct intel_dp dp;
1065         struct intel_hdmi hdmi;
1066         struct intel_lspcon lspcon;
1067         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1068         bool release_cl2_override;
1069         uint8_t max_lanes;
1070         enum intel_display_power_domain ddi_io_power_domain;
1071 };
1072
1073 struct intel_dp_mst_encoder {
1074         struct intel_encoder base;
1075         enum pipe pipe;
1076         struct intel_digital_port *primary;
1077         struct intel_connector *connector;
1078 };
1079
1080 static inline enum dpio_channel
1081 vlv_dport_to_channel(struct intel_digital_port *dport)
1082 {
1083         switch (dport->port) {
1084         case PORT_B:
1085         case PORT_D:
1086                 return DPIO_CH0;
1087         case PORT_C:
1088                 return DPIO_CH1;
1089         default:
1090                 BUG();
1091         }
1092 }
1093
1094 static inline enum dpio_phy
1095 vlv_dport_to_phy(struct intel_digital_port *dport)
1096 {
1097         switch (dport->port) {
1098         case PORT_B:
1099         case PORT_C:
1100                 return DPIO_PHY0;
1101         case PORT_D:
1102                 return DPIO_PHY1;
1103         default:
1104                 BUG();
1105         }
1106 }
1107
1108 static inline enum dpio_channel
1109 vlv_pipe_to_channel(enum pipe pipe)
1110 {
1111         switch (pipe) {
1112         case PIPE_A:
1113         case PIPE_C:
1114                 return DPIO_CH0;
1115         case PIPE_B:
1116                 return DPIO_CH1;
1117         default:
1118                 BUG();
1119         }
1120 }
1121
1122 static inline struct intel_crtc *
1123 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1124 {
1125         return dev_priv->pipe_to_crtc_mapping[pipe];
1126 }
1127
1128 static inline struct intel_crtc *
1129 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum plane plane)
1130 {
1131         return dev_priv->plane_to_crtc_mapping[plane];
1132 }
1133
1134 struct intel_load_detect_pipe {
1135         struct drm_atomic_state *restore_state;
1136 };
1137
1138 static inline struct intel_encoder *
1139 intel_attached_encoder(struct drm_connector *connector)
1140 {
1141         return to_intel_connector(connector)->encoder;
1142 }
1143
1144 static inline struct intel_digital_port *
1145 enc_to_dig_port(struct drm_encoder *encoder)
1146 {
1147         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1148
1149         switch (intel_encoder->type) {
1150         case INTEL_OUTPUT_UNKNOWN:
1151                 WARN_ON(!HAS_DDI(to_i915(encoder->dev)));
1152         case INTEL_OUTPUT_DP:
1153         case INTEL_OUTPUT_EDP:
1154         case INTEL_OUTPUT_HDMI:
1155                 return container_of(encoder, struct intel_digital_port,
1156                                     base.base);
1157         default:
1158                 return NULL;
1159         }
1160 }
1161
1162 static inline struct intel_dp_mst_encoder *
1163 enc_to_mst(struct drm_encoder *encoder)
1164 {
1165         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1166 }
1167
1168 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1169 {
1170         return &enc_to_dig_port(encoder)->dp;
1171 }
1172
1173 static inline struct intel_digital_port *
1174 dp_to_dig_port(struct intel_dp *intel_dp)
1175 {
1176         return container_of(intel_dp, struct intel_digital_port, dp);
1177 }
1178
1179 static inline struct intel_lspcon *
1180 dp_to_lspcon(struct intel_dp *intel_dp)
1181 {
1182         return &dp_to_dig_port(intel_dp)->lspcon;
1183 }
1184
1185 static inline struct intel_digital_port *
1186 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1187 {
1188         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1189 }
1190
1191 /* intel_fifo_underrun.c */
1192 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1193                                            enum pipe pipe, bool enable);
1194 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1195                                            enum pipe pch_transcoder,
1196                                            bool enable);
1197 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1198                                          enum pipe pipe);
1199 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1200                                          enum pipe pch_transcoder);
1201 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1202 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1203
1204 /* i915_irq.c */
1205 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1206 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1207 void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 mask);
1208 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1209 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1210 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1211 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1212 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1213 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1214 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1215
1216 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1217                                             u32 mask)
1218 {
1219         return mask & ~i915->rps.pm_intrmsk_mbz;
1220 }
1221
1222 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1223 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1224 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1225 {
1226         /*
1227          * We only use drm_irq_uninstall() at unload and VT switch, so
1228          * this is the only thing we need to check.
1229          */
1230         return dev_priv->pm.irqs_enabled;
1231 }
1232
1233 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1234 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1235                                      u8 pipe_mask);
1236 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1237                                      u8 pipe_mask);
1238 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1239 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1240 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1241
1242 /* intel_crt.c */
1243 void intel_crt_init(struct drm_i915_private *dev_priv);
1244 void intel_crt_reset(struct drm_encoder *encoder);
1245
1246 /* intel_ddi.c */
1247 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1248                                 struct intel_crtc_state *old_crtc_state,
1249                                 struct drm_connector_state *old_conn_state);
1250 void hsw_fdi_link_train(struct intel_crtc *crtc,
1251                         const struct intel_crtc_state *crtc_state);
1252 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1253 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1254 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1255 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1256 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1257                                        enum transcoder cpu_transcoder);
1258 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1259 void intel_ddi_disable_pipe_clock(const  struct intel_crtc_state *crtc_state);
1260 struct intel_encoder *
1261 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1262 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1263 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1264 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1265 bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
1266                                  struct intel_crtc *intel_crtc);
1267 void intel_ddi_get_config(struct intel_encoder *encoder,
1268                           struct intel_crtc_state *pipe_config);
1269
1270 void intel_ddi_clock_get(struct intel_encoder *encoder,
1271                          struct intel_crtc_state *pipe_config);
1272 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1273                                     bool state);
1274 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1275 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1276
1277 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1278                                    int plane, unsigned int height);
1279
1280 /* intel_audio.c */
1281 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1282 void intel_audio_codec_enable(struct intel_encoder *encoder,
1283                               const struct intel_crtc_state *crtc_state,
1284                               const struct drm_connector_state *conn_state);
1285 void intel_audio_codec_disable(struct intel_encoder *encoder);
1286 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1287 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1288 void intel_audio_init(struct drm_i915_private *dev_priv);
1289 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1290
1291 /* intel_cdclk.c */
1292 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1293 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1294 void cnl_init_cdclk(struct drm_i915_private *dev_priv);
1295 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
1296 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1297 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1298 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1299 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1300 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1301 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1302 bool intel_cdclk_state_compare(const struct intel_cdclk_state *a,
1303                                const struct intel_cdclk_state *b);
1304 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1305                      const struct intel_cdclk_state *cdclk_state);
1306
1307 /* intel_display.c */
1308 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1309 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1310 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1311 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1312 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1313 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1314                       const char *name, u32 reg, int ref_freq);
1315 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1316                            const char *name, u32 reg);
1317 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1318 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1319 extern const struct drm_plane_funcs intel_plane_funcs;
1320 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1321 unsigned int intel_fb_xy_to_linear(int x, int y,
1322                                    const struct intel_plane_state *state,
1323                                    int plane);
1324 void intel_add_fb_offsets(int *x, int *y,
1325                           const struct intel_plane_state *state, int plane);
1326 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1327 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1328 void intel_mark_busy(struct drm_i915_private *dev_priv);
1329 void intel_mark_idle(struct drm_i915_private *dev_priv);
1330 int intel_display_suspend(struct drm_device *dev);
1331 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1332 void intel_encoder_destroy(struct drm_encoder *encoder);
1333 int intel_connector_init(struct intel_connector *);
1334 struct intel_connector *intel_connector_alloc(void);
1335 bool intel_connector_get_hw_state(struct intel_connector *connector);
1336 void intel_connector_attach_encoder(struct intel_connector *connector,
1337                                     struct intel_encoder *encoder);
1338 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1339                                              struct drm_crtc *crtc);
1340 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1341 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1342                                 struct drm_file *file_priv);
1343 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1344                                              enum pipe pipe);
1345 static inline bool
1346 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1347                     enum intel_output_type type)
1348 {
1349         return crtc_state->output_types & (1 << type);
1350 }
1351 static inline bool
1352 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1353 {
1354         return crtc_state->output_types &
1355                 ((1 << INTEL_OUTPUT_DP) |
1356                  (1 << INTEL_OUTPUT_DP_MST) |
1357                  (1 << INTEL_OUTPUT_EDP));
1358 }
1359 static inline void
1360 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1361 {
1362         drm_wait_one_vblank(&dev_priv->drm, pipe);
1363 }
1364 static inline void
1365 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1366 {
1367         const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1368
1369         if (crtc->active)
1370                 intel_wait_for_vblank(dev_priv, pipe);
1371 }
1372
1373 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1374
1375 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1376 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1377                          struct intel_digital_port *dport,
1378                          unsigned int expected_mask);
1379 int intel_get_load_detect_pipe(struct drm_connector *connector,
1380                                struct drm_display_mode *mode,
1381                                struct intel_load_detect_pipe *old,
1382                                struct drm_modeset_acquire_ctx *ctx);
1383 void intel_release_load_detect_pipe(struct drm_connector *connector,
1384                                     struct intel_load_detect_pipe *old,
1385                                     struct drm_modeset_acquire_ctx *ctx);
1386 struct i915_vma *
1387 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1388 void intel_unpin_fb_vma(struct i915_vma *vma);
1389 struct drm_framebuffer *
1390 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1391                          struct drm_mode_fb_cmd2 *mode_cmd);
1392 int intel_prepare_plane_fb(struct drm_plane *plane,
1393                            struct drm_plane_state *new_state);
1394 void intel_cleanup_plane_fb(struct drm_plane *plane,
1395                             struct drm_plane_state *old_state);
1396 int intel_plane_atomic_get_property(struct drm_plane *plane,
1397                                     const struct drm_plane_state *state,
1398                                     struct drm_property *property,
1399                                     uint64_t *val);
1400 int intel_plane_atomic_set_property(struct drm_plane *plane,
1401                                     struct drm_plane_state *state,
1402                                     struct drm_property *property,
1403                                     uint64_t val);
1404 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1405                                     struct drm_plane_state *plane_state);
1406
1407 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1408                                     enum pipe pipe);
1409
1410 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1411                      const struct dpll *dpll);
1412 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1413 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1414
1415 /* modesetting asserts */
1416 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1417                            enum pipe pipe);
1418 void assert_pll(struct drm_i915_private *dev_priv,
1419                 enum pipe pipe, bool state);
1420 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1421 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1422 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1423 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1424 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1425 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1426                        enum pipe pipe, bool state);
1427 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1428 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1429 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1430 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1431 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1432 u32 intel_compute_tile_offset(int *x, int *y,
1433                               const struct intel_plane_state *state, int plane);
1434 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1435 void intel_finish_reset(struct drm_i915_private *dev_priv);
1436 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1437 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1438 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1439 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1440 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1441 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1442 unsigned int skl_cdclk_get_vco(unsigned int freq);
1443 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1444 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1445 void intel_dp_get_m_n(struct intel_crtc *crtc,
1446                       struct intel_crtc_state *pipe_config);
1447 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1448 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1449 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1450                         struct dpll *best_clock);
1451 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1452
1453 bool intel_crtc_active(struct intel_crtc *crtc);
1454 void hsw_enable_ips(struct intel_crtc *crtc);
1455 void hsw_disable_ips(struct intel_crtc *crtc);
1456 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1457 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1458                                  struct intel_crtc_state *pipe_config);
1459
1460 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1461 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1462
1463 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1464 {
1465         return i915_ggtt_offset(state->vma);
1466 }
1467
1468 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1469                   const struct intel_plane_state *plane_state);
1470 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1471                      unsigned int rotation);
1472 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1473 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1474
1475 /* intel_csr.c */
1476 void intel_csr_ucode_init(struct drm_i915_private *);
1477 void intel_csr_load_program(struct drm_i915_private *);
1478 void intel_csr_ucode_fini(struct drm_i915_private *);
1479 void intel_csr_ucode_suspend(struct drm_i915_private *);
1480 void intel_csr_ucode_resume(struct drm_i915_private *);
1481
1482 /* intel_dp.c */
1483 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1484                    enum port port);
1485 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1486                              struct intel_connector *intel_connector);
1487 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1488                               int link_rate, uint8_t lane_count,
1489                               bool link_mst);
1490 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1491                                             int link_rate, uint8_t lane_count);
1492 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1493 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1494 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1495 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1496 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1497 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1498 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1499 bool intel_dp_compute_config(struct intel_encoder *encoder,
1500                              struct intel_crtc_state *pipe_config,
1501                              struct drm_connector_state *conn_state);
1502 bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port);
1503 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1504                                   bool long_hpd);
1505 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1506                             const struct drm_connector_state *conn_state);
1507 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
1508 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1509 void intel_edp_panel_on(struct intel_dp *intel_dp);
1510 void intel_edp_panel_off(struct intel_dp *intel_dp);
1511 void intel_dp_mst_suspend(struct drm_device *dev);
1512 void intel_dp_mst_resume(struct drm_device *dev);
1513 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1514 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1515 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1516 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1517 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1518 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1519 void intel_plane_destroy(struct drm_plane *plane);
1520 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1521                            struct intel_crtc_state *crtc_state);
1522 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1523                            struct intel_crtc_state *crtc_state);
1524 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1525                                unsigned int frontbuffer_bits);
1526 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1527                           unsigned int frontbuffer_bits);
1528
1529 void
1530 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1531                                        uint8_t dp_train_pat);
1532 void
1533 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1534 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1535 uint8_t
1536 intel_dp_voltage_max(struct intel_dp *intel_dp);
1537 uint8_t
1538 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1539 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1540                            uint8_t *link_bw, uint8_t *rate_select);
1541 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1542 bool
1543 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1544
1545 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1546 {
1547         return ~((1 << lane_count) - 1) & 0xf;
1548 }
1549
1550 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1551 int intel_dp_link_required(int pixel_clock, int bpp);
1552 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1553 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1554                                   struct intel_digital_port *port);
1555
1556 /* intel_dp_aux_backlight.c */
1557 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1558
1559 /* intel_dp_mst.c */
1560 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1561 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1562 /* intel_dsi.c */
1563 void intel_dsi_init(struct drm_i915_private *dev_priv);
1564
1565 /* intel_dsi_dcs_backlight.c */
1566 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1567
1568 /* intel_dvo.c */
1569 void intel_dvo_init(struct drm_i915_private *dev_priv);
1570 /* intel_hotplug.c */
1571 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1572
1573
1574 /* legacy fbdev emulation in intel_fbdev.c */
1575 #ifdef CONFIG_DRM_FBDEV_EMULATION
1576 extern int intel_fbdev_init(struct drm_device *dev);
1577 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1578 extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv);
1579 extern void intel_fbdev_fini(struct drm_i915_private *dev_priv);
1580 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1581 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1582 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1583 #else
1584 static inline int intel_fbdev_init(struct drm_device *dev)
1585 {
1586         return 0;
1587 }
1588
1589 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1590 {
1591 }
1592
1593 static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
1594 {
1595 }
1596
1597 static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv)
1598 {
1599 }
1600
1601 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1602 {
1603 }
1604
1605 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1606 {
1607 }
1608
1609 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1610 {
1611 }
1612 #endif
1613
1614 /* intel_fbc.c */
1615 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1616                            struct drm_atomic_state *state);
1617 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1618 void intel_fbc_pre_update(struct intel_crtc *crtc,
1619                           struct intel_crtc_state *crtc_state,
1620                           struct intel_plane_state *plane_state);
1621 void intel_fbc_post_update(struct intel_crtc *crtc);
1622 void intel_fbc_init(struct drm_i915_private *dev_priv);
1623 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1624 void intel_fbc_enable(struct intel_crtc *crtc,
1625                       struct intel_crtc_state *crtc_state,
1626                       struct intel_plane_state *plane_state);
1627 void intel_fbc_disable(struct intel_crtc *crtc);
1628 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1629 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1630                           unsigned int frontbuffer_bits,
1631                           enum fb_op_origin origin);
1632 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1633                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1634 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1635 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1636
1637 /* intel_hdmi.c */
1638 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1639                      enum port port);
1640 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1641                                struct intel_connector *intel_connector);
1642 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1643 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1644                                struct intel_crtc_state *pipe_config,
1645                                struct drm_connector_state *conn_state);
1646 void intel_hdmi_handle_sink_scrambling(struct intel_encoder *intel_encoder,
1647                                        struct drm_connector *connector,
1648                                        bool high_tmds_clock_ratio,
1649                                        bool scrambling);
1650 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1651
1652
1653 /* intel_lvds.c */
1654 void intel_lvds_init(struct drm_i915_private *dev_priv);
1655 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1656 bool intel_is_dual_link_lvds(struct drm_device *dev);
1657
1658
1659 /* intel_modes.c */
1660 int intel_connector_update_modes(struct drm_connector *connector,
1661                                  struct edid *edid);
1662 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1663 void intel_attach_force_audio_property(struct drm_connector *connector);
1664 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1665 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1666
1667
1668 /* intel_overlay.c */
1669 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1670 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1671 int intel_overlay_switch_off(struct intel_overlay *overlay);
1672 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1673                                   struct drm_file *file_priv);
1674 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1675                               struct drm_file *file_priv);
1676 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1677
1678
1679 /* intel_panel.c */
1680 int intel_panel_init(struct intel_panel *panel,
1681                      struct drm_display_mode *fixed_mode,
1682                      struct drm_display_mode *downclock_mode);
1683 void intel_panel_fini(struct intel_panel *panel);
1684 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1685                             struct drm_display_mode *adjusted_mode);
1686 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1687                              struct intel_crtc_state *pipe_config,
1688                              int fitting_mode);
1689 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1690                               struct intel_crtc_state *pipe_config,
1691                               int fitting_mode);
1692 void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
1693                                     u32 level, u32 max);
1694 int intel_panel_setup_backlight(struct drm_connector *connector,
1695                                 enum pipe pipe);
1696 void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
1697                                   const struct drm_connector_state *conn_state);
1698 void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state);
1699 void intel_panel_destroy_backlight(struct drm_connector *connector);
1700 enum drm_connector_status intel_panel_detect(struct drm_i915_private *dev_priv);
1701 extern struct drm_display_mode *intel_find_panel_downclock(
1702                                 struct drm_i915_private *dev_priv,
1703                                 struct drm_display_mode *fixed_mode,
1704                                 struct drm_connector *connector);
1705
1706 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1707 int intel_backlight_device_register(struct intel_connector *connector);
1708 void intel_backlight_device_unregister(struct intel_connector *connector);
1709 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1710 static int intel_backlight_device_register(struct intel_connector *connector)
1711 {
1712         return 0;
1713 }
1714 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1715 {
1716 }
1717 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1718
1719
1720 /* intel_psr.c */
1721 void intel_psr_enable(struct intel_dp *intel_dp);
1722 void intel_psr_disable(struct intel_dp *intel_dp);
1723 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1724                           unsigned frontbuffer_bits);
1725 void intel_psr_flush(struct drm_i915_private *dev_priv,
1726                      unsigned frontbuffer_bits,
1727                      enum fb_op_origin origin);
1728 void intel_psr_init(struct drm_i915_private *dev_priv);
1729 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1730                                    unsigned frontbuffer_bits);
1731
1732 /* intel_runtime_pm.c */
1733 int intel_power_domains_init(struct drm_i915_private *);
1734 void intel_power_domains_fini(struct drm_i915_private *);
1735 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1736 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1737 void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
1738 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1739 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1740 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1741 const char *
1742 intel_display_power_domain_str(enum intel_display_power_domain domain);
1743
1744 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1745                                     enum intel_display_power_domain domain);
1746 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1747                                       enum intel_display_power_domain domain);
1748 void intel_display_power_get(struct drm_i915_private *dev_priv,
1749                              enum intel_display_power_domain domain);
1750 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1751                                         enum intel_display_power_domain domain);
1752 void intel_display_power_put(struct drm_i915_private *dev_priv,
1753                              enum intel_display_power_domain domain);
1754
1755 static inline void
1756 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1757 {
1758         WARN_ONCE(dev_priv->pm.suspended,
1759                   "Device suspended during HW access\n");
1760 }
1761
1762 static inline void
1763 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1764 {
1765         assert_rpm_device_not_suspended(dev_priv);
1766         WARN_ONCE(!atomic_read(&dev_priv->pm.wakeref_count),
1767                   "RPM wakelock ref not held during HW access");
1768 }
1769
1770 /**
1771  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1772  * @dev_priv: i915 device instance
1773  *
1774  * This function disable asserts that check if we hold an RPM wakelock
1775  * reference, while keeping the device-not-suspended checks still enabled.
1776  * It's meant to be used only in special circumstances where our rule about
1777  * the wakelock refcount wrt. the device power state doesn't hold. According
1778  * to this rule at any point where we access the HW or want to keep the HW in
1779  * an active state we must hold an RPM wakelock reference acquired via one of
1780  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1781  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1782  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1783  * users should avoid using this function.
1784  *
1785  * Any calls to this function must have a symmetric call to
1786  * enable_rpm_wakeref_asserts().
1787  */
1788 static inline void
1789 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1790 {
1791         atomic_inc(&dev_priv->pm.wakeref_count);
1792 }
1793
1794 /**
1795  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1796  * @dev_priv: i915 device instance
1797  *
1798  * This function re-enables the RPM assert checks after disabling them with
1799  * disable_rpm_wakeref_asserts. It's meant to be used only in special
1800  * circumstances otherwise its use should be avoided.
1801  *
1802  * Any calls to this function must have a symmetric call to
1803  * disable_rpm_wakeref_asserts().
1804  */
1805 static inline void
1806 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1807 {
1808         atomic_dec(&dev_priv->pm.wakeref_count);
1809 }
1810
1811 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1812 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1813 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1814 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1815
1816 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1817
1818 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1819                              bool override, unsigned int mask);
1820 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1821                           enum dpio_channel ch, bool override);
1822
1823
1824 /* intel_pm.c */
1825 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
1826 void intel_suspend_hw(struct drm_i915_private *dev_priv);
1827 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
1828 void intel_update_watermarks(struct intel_crtc *crtc);
1829 void intel_init_pm(struct drm_i915_private *dev_priv);
1830 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1831 void intel_pm_setup(struct drm_i915_private *dev_priv);
1832 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1833 void intel_gpu_ips_teardown(void);
1834 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1835 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1836 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
1837 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1838 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
1839 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1840 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1841 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1842 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1843 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1844 void gen6_rps_boost(struct drm_i915_gem_request *rq,
1845                     struct intel_rps_client *rps);
1846 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1847 void g4x_wm_get_hw_state(struct drm_device *dev);
1848 void vlv_wm_get_hw_state(struct drm_device *dev);
1849 void ilk_wm_get_hw_state(struct drm_device *dev);
1850 void skl_wm_get_hw_state(struct drm_device *dev);
1851 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1852                           struct skl_ddb_allocation *ddb /* out */);
1853 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
1854                               struct skl_pipe_wm *out);
1855 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
1856 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
1857 bool intel_can_enable_sagv(struct drm_atomic_state *state);
1858 int intel_enable_sagv(struct drm_i915_private *dev_priv);
1859 int intel_disable_sagv(struct drm_i915_private *dev_priv);
1860 bool skl_wm_level_equals(const struct skl_wm_level *l1,
1861                          const struct skl_wm_level *l2);
1862 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
1863                                  const struct skl_ddb_entry *ddb,
1864                                  int ignore);
1865 bool ilk_disable_lp_wm(struct drm_device *dev);
1866 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1867 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
1868                                   struct intel_crtc_state *cstate);
1869 static inline int intel_enable_rc6(void)
1870 {
1871         return i915.enable_rc6;
1872 }
1873
1874 /* intel_sdvo.c */
1875 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
1876                      i915_reg_t reg, enum port port);
1877
1878
1879 /* intel_sprite.c */
1880 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
1881                              int usecs);
1882 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1883                                               enum pipe pipe, int plane);
1884 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1885                               struct drm_file *file_priv);
1886 void intel_pipe_update_start(struct intel_crtc *crtc);
1887 void intel_pipe_update_end(struct intel_crtc *crtc);
1888
1889 /* intel_tv.c */
1890 void intel_tv_init(struct drm_i915_private *dev_priv);
1891
1892 /* intel_atomic.c */
1893 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
1894                                                 const struct drm_connector_state *state,
1895                                                 struct drm_property *property,
1896                                                 uint64_t *val);
1897 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
1898                                                 struct drm_connector_state *state,
1899                                                 struct drm_property *property,
1900                                                 uint64_t val);
1901 int intel_digital_connector_atomic_check(struct drm_connector *conn,
1902                                          struct drm_connector_state *new_state);
1903 struct drm_connector_state *
1904 intel_digital_connector_duplicate_state(struct drm_connector *connector);
1905
1906 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1907 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1908                                struct drm_crtc_state *state);
1909 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1910 void intel_atomic_state_clear(struct drm_atomic_state *);
1911
1912 static inline struct intel_crtc_state *
1913 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1914                             struct intel_crtc *crtc)
1915 {
1916         struct drm_crtc_state *crtc_state;
1917         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1918         if (IS_ERR(crtc_state))
1919                 return ERR_CAST(crtc_state);
1920
1921         return to_intel_crtc_state(crtc_state);
1922 }
1923
1924 static inline struct intel_crtc_state *
1925 intel_atomic_get_existing_crtc_state(struct drm_atomic_state *state,
1926                                      struct intel_crtc *crtc)
1927 {
1928         struct drm_crtc_state *crtc_state;
1929
1930         crtc_state = drm_atomic_get_existing_crtc_state(state, &crtc->base);
1931
1932         if (crtc_state)
1933                 return to_intel_crtc_state(crtc_state);
1934         else
1935                 return NULL;
1936 }
1937
1938 static inline struct intel_plane_state *
1939 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1940                                       struct intel_plane *plane)
1941 {
1942         struct drm_plane_state *plane_state;
1943
1944         plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1945
1946         return to_intel_plane_state(plane_state);
1947 }
1948
1949 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
1950                                struct intel_crtc *intel_crtc,
1951                                struct intel_crtc_state *crtc_state);
1952
1953 /* intel_atomic_plane.c */
1954 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1955 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1956 void intel_plane_destroy_state(struct drm_plane *plane,
1957                                struct drm_plane_state *state);
1958 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1959 int intel_plane_atomic_check_with_state(struct intel_crtc_state *crtc_state,
1960                                         struct intel_plane_state *intel_state);
1961
1962 /* intel_color.c */
1963 void intel_color_init(struct drm_crtc *crtc);
1964 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1965 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
1966 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1967
1968 /* intel_lspcon.c */
1969 bool lspcon_init(struct intel_digital_port *intel_dig_port);
1970 void lspcon_resume(struct intel_lspcon *lspcon);
1971 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
1972
1973 /* intel_pipe_crc.c */
1974 int intel_pipe_crc_create(struct drm_minor *minor);
1975 #ifdef CONFIG_DEBUG_FS
1976 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
1977                               size_t *values_cnt);
1978 #else
1979 #define intel_crtc_set_crc_source NULL
1980 #endif
1981 extern const struct file_operations i915_display_crc_ctl_fops;
1982 #endif /* __INTEL_DRV_H__ */