Merge airlied/drm-next into drm-intel-next-queued
[muen/linux.git] / drivers / gpu / drm / i915 / intel_hdmi.c
1 /*
2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
3  * Copyright © 2006-2009 Intel Corporation
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice (including the next
13  * paragraph) shall be included in all copies or substantial portions of the
14  * Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22  * DEALINGS IN THE SOFTWARE.
23  *
24  * Authors:
25  *      Eric Anholt <eric@anholt.net>
26  *      Jesse Barnes <jesse.barnes@intel.com>
27  */
28
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include <linux/hdmi.h>
33 #include <drm/drmP.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_edid.h>
37 #include <drm/drm_scdc_helper.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
40 #include <drm/intel_lpe_audio.h>
41 #include "i915_drv.h"
42
43 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
44 {
45         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
46 }
47
48 static void
49 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
50 {
51         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
52         struct drm_i915_private *dev_priv = to_i915(dev);
53         uint32_t enabled_bits;
54
55         enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
56
57         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
58              "HDMI port enabled, expecting disabled\n");
59 }
60
61 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
62 {
63         struct intel_digital_port *intel_dig_port =
64                 container_of(encoder, struct intel_digital_port, base.base);
65         return &intel_dig_port->hdmi;
66 }
67
68 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
69 {
70         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
71 }
72
73 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
74 {
75         switch (type) {
76         case HDMI_INFOFRAME_TYPE_AVI:
77                 return VIDEO_DIP_SELECT_AVI;
78         case HDMI_INFOFRAME_TYPE_SPD:
79                 return VIDEO_DIP_SELECT_SPD;
80         case HDMI_INFOFRAME_TYPE_VENDOR:
81                 return VIDEO_DIP_SELECT_VENDOR;
82         default:
83                 MISSING_CASE(type);
84                 return 0;
85         }
86 }
87
88 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
89 {
90         switch (type) {
91         case HDMI_INFOFRAME_TYPE_AVI:
92                 return VIDEO_DIP_ENABLE_AVI;
93         case HDMI_INFOFRAME_TYPE_SPD:
94                 return VIDEO_DIP_ENABLE_SPD;
95         case HDMI_INFOFRAME_TYPE_VENDOR:
96                 return VIDEO_DIP_ENABLE_VENDOR;
97         default:
98                 MISSING_CASE(type);
99                 return 0;
100         }
101 }
102
103 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
104 {
105         switch (type) {
106         case HDMI_INFOFRAME_TYPE_AVI:
107                 return VIDEO_DIP_ENABLE_AVI_HSW;
108         case HDMI_INFOFRAME_TYPE_SPD:
109                 return VIDEO_DIP_ENABLE_SPD_HSW;
110         case HDMI_INFOFRAME_TYPE_VENDOR:
111                 return VIDEO_DIP_ENABLE_VS_HSW;
112         default:
113                 MISSING_CASE(type);
114                 return 0;
115         }
116 }
117
118 static i915_reg_t
119 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
120                  enum transcoder cpu_transcoder,
121                  enum hdmi_infoframe_type type,
122                  int i)
123 {
124         switch (type) {
125         case HDMI_INFOFRAME_TYPE_AVI:
126                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
127         case HDMI_INFOFRAME_TYPE_SPD:
128                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
129         case HDMI_INFOFRAME_TYPE_VENDOR:
130                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
131         default:
132                 MISSING_CASE(type);
133                 return INVALID_MMIO_REG;
134         }
135 }
136
137 static void g4x_write_infoframe(struct drm_encoder *encoder,
138                                 const struct intel_crtc_state *crtc_state,
139                                 enum hdmi_infoframe_type type,
140                                 const void *frame, ssize_t len)
141 {
142         const uint32_t *data = frame;
143         struct drm_device *dev = encoder->dev;
144         struct drm_i915_private *dev_priv = to_i915(dev);
145         u32 val = I915_READ(VIDEO_DIP_CTL);
146         int i;
147
148         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
149
150         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
151         val |= g4x_infoframe_index(type);
152
153         val &= ~g4x_infoframe_enable(type);
154
155         I915_WRITE(VIDEO_DIP_CTL, val);
156
157         mmiowb();
158         for (i = 0; i < len; i += 4) {
159                 I915_WRITE(VIDEO_DIP_DATA, *data);
160                 data++;
161         }
162         /* Write every possible data byte to force correct ECC calculation. */
163         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
164                 I915_WRITE(VIDEO_DIP_DATA, 0);
165         mmiowb();
166
167         val |= g4x_infoframe_enable(type);
168         val &= ~VIDEO_DIP_FREQ_MASK;
169         val |= VIDEO_DIP_FREQ_VSYNC;
170
171         I915_WRITE(VIDEO_DIP_CTL, val);
172         POSTING_READ(VIDEO_DIP_CTL);
173 }
174
175 static bool g4x_infoframe_enabled(struct drm_encoder *encoder,
176                                   const struct intel_crtc_state *pipe_config)
177 {
178         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
179         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
180         u32 val = I915_READ(VIDEO_DIP_CTL);
181
182         if ((val & VIDEO_DIP_ENABLE) == 0)
183                 return false;
184
185         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
186                 return false;
187
188         return val & (VIDEO_DIP_ENABLE_AVI |
189                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
190 }
191
192 static void ibx_write_infoframe(struct drm_encoder *encoder,
193                                 const struct intel_crtc_state *crtc_state,
194                                 enum hdmi_infoframe_type type,
195                                 const void *frame, ssize_t len)
196 {
197         const uint32_t *data = frame;
198         struct drm_device *dev = encoder->dev;
199         struct drm_i915_private *dev_priv = to_i915(dev);
200         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
201         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
202         u32 val = I915_READ(reg);
203         int i;
204
205         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
206
207         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
208         val |= g4x_infoframe_index(type);
209
210         val &= ~g4x_infoframe_enable(type);
211
212         I915_WRITE(reg, val);
213
214         mmiowb();
215         for (i = 0; i < len; i += 4) {
216                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
217                 data++;
218         }
219         /* Write every possible data byte to force correct ECC calculation. */
220         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
221                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
222         mmiowb();
223
224         val |= g4x_infoframe_enable(type);
225         val &= ~VIDEO_DIP_FREQ_MASK;
226         val |= VIDEO_DIP_FREQ_VSYNC;
227
228         I915_WRITE(reg, val);
229         POSTING_READ(reg);
230 }
231
232 static bool ibx_infoframe_enabled(struct drm_encoder *encoder,
233                                   const struct intel_crtc_state *pipe_config)
234 {
235         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
236         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
237         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
238         i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
239         u32 val = I915_READ(reg);
240
241         if ((val & VIDEO_DIP_ENABLE) == 0)
242                 return false;
243
244         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
245                 return false;
246
247         return val & (VIDEO_DIP_ENABLE_AVI |
248                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
249                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
250 }
251
252 static void cpt_write_infoframe(struct drm_encoder *encoder,
253                                 const struct intel_crtc_state *crtc_state,
254                                 enum hdmi_infoframe_type type,
255                                 const void *frame, ssize_t len)
256 {
257         const uint32_t *data = frame;
258         struct drm_device *dev = encoder->dev;
259         struct drm_i915_private *dev_priv = to_i915(dev);
260         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
261         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
262         u32 val = I915_READ(reg);
263         int i;
264
265         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
266
267         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
268         val |= g4x_infoframe_index(type);
269
270         /* The DIP control register spec says that we need to update the AVI
271          * infoframe without clearing its enable bit */
272         if (type != HDMI_INFOFRAME_TYPE_AVI)
273                 val &= ~g4x_infoframe_enable(type);
274
275         I915_WRITE(reg, val);
276
277         mmiowb();
278         for (i = 0; i < len; i += 4) {
279                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
280                 data++;
281         }
282         /* Write every possible data byte to force correct ECC calculation. */
283         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
284                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
285         mmiowb();
286
287         val |= g4x_infoframe_enable(type);
288         val &= ~VIDEO_DIP_FREQ_MASK;
289         val |= VIDEO_DIP_FREQ_VSYNC;
290
291         I915_WRITE(reg, val);
292         POSTING_READ(reg);
293 }
294
295 static bool cpt_infoframe_enabled(struct drm_encoder *encoder,
296                                   const struct intel_crtc_state *pipe_config)
297 {
298         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
299         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
300         u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
301
302         if ((val & VIDEO_DIP_ENABLE) == 0)
303                 return false;
304
305         return val & (VIDEO_DIP_ENABLE_AVI |
306                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
307                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
308 }
309
310 static void vlv_write_infoframe(struct drm_encoder *encoder,
311                                 const struct intel_crtc_state *crtc_state,
312                                 enum hdmi_infoframe_type type,
313                                 const void *frame, ssize_t len)
314 {
315         const uint32_t *data = frame;
316         struct drm_device *dev = encoder->dev;
317         struct drm_i915_private *dev_priv = to_i915(dev);
318         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
319         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
320         u32 val = I915_READ(reg);
321         int i;
322
323         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
324
325         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
326         val |= g4x_infoframe_index(type);
327
328         val &= ~g4x_infoframe_enable(type);
329
330         I915_WRITE(reg, val);
331
332         mmiowb();
333         for (i = 0; i < len; i += 4) {
334                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
335                 data++;
336         }
337         /* Write every possible data byte to force correct ECC calculation. */
338         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
339                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
340         mmiowb();
341
342         val |= g4x_infoframe_enable(type);
343         val &= ~VIDEO_DIP_FREQ_MASK;
344         val |= VIDEO_DIP_FREQ_VSYNC;
345
346         I915_WRITE(reg, val);
347         POSTING_READ(reg);
348 }
349
350 static bool vlv_infoframe_enabled(struct drm_encoder *encoder,
351                                   const struct intel_crtc_state *pipe_config)
352 {
353         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
354         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
355         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
356         u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
357
358         if ((val & VIDEO_DIP_ENABLE) == 0)
359                 return false;
360
361         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
362                 return false;
363
364         return val & (VIDEO_DIP_ENABLE_AVI |
365                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
366                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
367 }
368
369 static void hsw_write_infoframe(struct drm_encoder *encoder,
370                                 const struct intel_crtc_state *crtc_state,
371                                 enum hdmi_infoframe_type type,
372                                 const void *frame, ssize_t len)
373 {
374         const uint32_t *data = frame;
375         struct drm_device *dev = encoder->dev;
376         struct drm_i915_private *dev_priv = to_i915(dev);
377         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
378         i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
379         i915_reg_t data_reg;
380         int i;
381         u32 val = I915_READ(ctl_reg);
382
383         data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
384
385         val &= ~hsw_infoframe_enable(type);
386         I915_WRITE(ctl_reg, val);
387
388         mmiowb();
389         for (i = 0; i < len; i += 4) {
390                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
391                                             type, i >> 2), *data);
392                 data++;
393         }
394         /* Write every possible data byte to force correct ECC calculation. */
395         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
396                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
397                                             type, i >> 2), 0);
398         mmiowb();
399
400         val |= hsw_infoframe_enable(type);
401         I915_WRITE(ctl_reg, val);
402         POSTING_READ(ctl_reg);
403 }
404
405 static bool hsw_infoframe_enabled(struct drm_encoder *encoder,
406                                   const struct intel_crtc_state *pipe_config)
407 {
408         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
409         u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
410
411         return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
412                       VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
413                       VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
414 }
415
416 /*
417  * The data we write to the DIP data buffer registers is 1 byte bigger than the
418  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
419  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
420  * used for both technologies.
421  *
422  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
423  * DW1:       DB3       | DB2 | DB1 | DB0
424  * DW2:       DB7       | DB6 | DB5 | DB4
425  * DW3: ...
426  *
427  * (HB is Header Byte, DB is Data Byte)
428  *
429  * The hdmi pack() functions don't know about that hardware specific hole so we
430  * trick them by giving an offset into the buffer and moving back the header
431  * bytes by one.
432  */
433 static void intel_write_infoframe(struct drm_encoder *encoder,
434                                   const struct intel_crtc_state *crtc_state,
435                                   union hdmi_infoframe *frame)
436 {
437         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
438         uint8_t buffer[VIDEO_DIP_DATA_SIZE];
439         ssize_t len;
440
441         /* see comment above for the reason for this offset */
442         len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
443         if (len < 0)
444                 return;
445
446         /* Insert the 'hole' (see big comment above) at position 3 */
447         buffer[0] = buffer[1];
448         buffer[1] = buffer[2];
449         buffer[2] = buffer[3];
450         buffer[3] = 0;
451         len++;
452
453         intel_hdmi->write_infoframe(encoder, crtc_state, frame->any.type, buffer, len);
454 }
455
456 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
457                                          const struct intel_crtc_state *crtc_state)
458 {
459         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
460         const struct drm_display_mode *adjusted_mode =
461                 &crtc_state->base.adjusted_mode;
462         struct drm_connector *connector = &intel_hdmi->attached_connector->base;
463         bool is_hdmi2_sink = connector->display_info.hdmi.scdc.supported;
464         union hdmi_infoframe frame;
465         int ret;
466
467         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
468                                                        adjusted_mode,
469                                                        is_hdmi2_sink);
470         if (ret < 0) {
471                 DRM_ERROR("couldn't fill AVI infoframe\n");
472                 return;
473         }
474
475         if (crtc_state->ycbcr420)
476                 frame.avi.colorspace = HDMI_COLORSPACE_YUV420;
477         else
478                 frame.avi.colorspace = HDMI_COLORSPACE_RGB;
479
480         drm_hdmi_avi_infoframe_quant_range(&frame.avi, adjusted_mode,
481                                            crtc_state->limited_color_range ?
482                                            HDMI_QUANTIZATION_RANGE_LIMITED :
483                                            HDMI_QUANTIZATION_RANGE_FULL,
484                                            intel_hdmi->rgb_quant_range_selectable);
485
486         /* TODO: handle pixel repetition for YCBCR420 outputs */
487         intel_write_infoframe(encoder, crtc_state, &frame);
488 }
489
490 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder,
491                                          const struct intel_crtc_state *crtc_state)
492 {
493         union hdmi_infoframe frame;
494         int ret;
495
496         ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
497         if (ret < 0) {
498                 DRM_ERROR("couldn't fill SPD infoframe\n");
499                 return;
500         }
501
502         frame.spd.sdi = HDMI_SPD_SDI_PC;
503
504         intel_write_infoframe(encoder, crtc_state, &frame);
505 }
506
507 static void
508 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
509                               const struct intel_crtc_state *crtc_state)
510 {
511         union hdmi_infoframe frame;
512         int ret;
513
514         ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
515                                                           &crtc_state->base.adjusted_mode);
516         if (ret < 0)
517                 return;
518
519         intel_write_infoframe(encoder, crtc_state, &frame);
520 }
521
522 static void g4x_set_infoframes(struct drm_encoder *encoder,
523                                bool enable,
524                                const struct intel_crtc_state *crtc_state,
525                                const struct drm_connector_state *conn_state)
526 {
527         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
528         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
529         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
530         i915_reg_t reg = VIDEO_DIP_CTL;
531         u32 val = I915_READ(reg);
532         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
533
534         assert_hdmi_port_disabled(intel_hdmi);
535
536         /* If the registers were not initialized yet, they might be zeroes,
537          * which means we're selecting the AVI DIP and we're setting its
538          * frequency to once. This seems to really confuse the HW and make
539          * things stop working (the register spec says the AVI always needs to
540          * be sent every VSync). So here we avoid writing to the register more
541          * than we need and also explicitly select the AVI DIP and explicitly
542          * set its frequency to every VSync. Avoiding to write it twice seems to
543          * be enough to solve the problem, but being defensive shouldn't hurt us
544          * either. */
545         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
546
547         if (!enable) {
548                 if (!(val & VIDEO_DIP_ENABLE))
549                         return;
550                 if (port != (val & VIDEO_DIP_PORT_MASK)) {
551                         DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
552                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
553                         return;
554                 }
555                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
556                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
557                 I915_WRITE(reg, val);
558                 POSTING_READ(reg);
559                 return;
560         }
561
562         if (port != (val & VIDEO_DIP_PORT_MASK)) {
563                 if (val & VIDEO_DIP_ENABLE) {
564                         DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
565                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
566                         return;
567                 }
568                 val &= ~VIDEO_DIP_PORT_MASK;
569                 val |= port;
570         }
571
572         val |= VIDEO_DIP_ENABLE;
573         val &= ~(VIDEO_DIP_ENABLE_AVI |
574                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
575
576         I915_WRITE(reg, val);
577         POSTING_READ(reg);
578
579         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
580         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
581         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
582 }
583
584 static bool hdmi_sink_is_deep_color(const struct drm_connector_state *conn_state)
585 {
586         struct drm_connector *connector = conn_state->connector;
587
588         /*
589          * HDMI cloning is only supported on g4x which doesn't
590          * support deep color or GCP infoframes anyway so no
591          * need to worry about multiple HDMI sinks here.
592          */
593
594         return connector->display_info.bpc > 8;
595 }
596
597 /*
598  * Determine if default_phase=1 can be indicated in the GCP infoframe.
599  *
600  * From HDMI specification 1.4a:
601  * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
602  * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
603  * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
604  * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
605  *   phase of 0
606  */
607 static bool gcp_default_phase_possible(int pipe_bpp,
608                                        const struct drm_display_mode *mode)
609 {
610         unsigned int pixels_per_group;
611
612         switch (pipe_bpp) {
613         case 30:
614                 /* 4 pixels in 5 clocks */
615                 pixels_per_group = 4;
616                 break;
617         case 36:
618                 /* 2 pixels in 3 clocks */
619                 pixels_per_group = 2;
620                 break;
621         case 48:
622                 /* 1 pixel in 2 clocks */
623                 pixels_per_group = 1;
624                 break;
625         default:
626                 /* phase information not relevant for 8bpc */
627                 return false;
628         }
629
630         return mode->crtc_hdisplay % pixels_per_group == 0 &&
631                 mode->crtc_htotal % pixels_per_group == 0 &&
632                 mode->crtc_hblank_start % pixels_per_group == 0 &&
633                 mode->crtc_hblank_end % pixels_per_group == 0 &&
634                 mode->crtc_hsync_start % pixels_per_group == 0 &&
635                 mode->crtc_hsync_end % pixels_per_group == 0 &&
636                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
637                  mode->crtc_htotal/2 % pixels_per_group == 0);
638 }
639
640 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder,
641                                          const struct intel_crtc_state *crtc_state,
642                                          const struct drm_connector_state *conn_state)
643 {
644         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
645         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
646         i915_reg_t reg;
647         u32 val = 0;
648
649         if (HAS_DDI(dev_priv))
650                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
651         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
652                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
653         else if (HAS_PCH_SPLIT(dev_priv))
654                 reg = TVIDEO_DIP_GCP(crtc->pipe);
655         else
656                 return false;
657
658         /* Indicate color depth whenever the sink supports deep color */
659         if (hdmi_sink_is_deep_color(conn_state))
660                 val |= GCP_COLOR_INDICATION;
661
662         /* Enable default_phase whenever the display mode is suitably aligned */
663         if (gcp_default_phase_possible(crtc_state->pipe_bpp,
664                                        &crtc_state->base.adjusted_mode))
665                 val |= GCP_DEFAULT_PHASE_ENABLE;
666
667         I915_WRITE(reg, val);
668
669         return val != 0;
670 }
671
672 static void ibx_set_infoframes(struct drm_encoder *encoder,
673                                bool enable,
674                                const struct intel_crtc_state *crtc_state,
675                                const struct drm_connector_state *conn_state)
676 {
677         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
678         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
679         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
680         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
681         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
682         u32 val = I915_READ(reg);
683         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
684
685         assert_hdmi_port_disabled(intel_hdmi);
686
687         /* See the big comment in g4x_set_infoframes() */
688         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
689
690         if (!enable) {
691                 if (!(val & VIDEO_DIP_ENABLE))
692                         return;
693                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
694                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
695                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
696                 I915_WRITE(reg, val);
697                 POSTING_READ(reg);
698                 return;
699         }
700
701         if (port != (val & VIDEO_DIP_PORT_MASK)) {
702                 WARN(val & VIDEO_DIP_ENABLE,
703                      "DIP already enabled on port %c\n",
704                      (val & VIDEO_DIP_PORT_MASK) >> 29);
705                 val &= ~VIDEO_DIP_PORT_MASK;
706                 val |= port;
707         }
708
709         val |= VIDEO_DIP_ENABLE;
710         val &= ~(VIDEO_DIP_ENABLE_AVI |
711                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
712                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
713
714         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
715                 val |= VIDEO_DIP_ENABLE_GCP;
716
717         I915_WRITE(reg, val);
718         POSTING_READ(reg);
719
720         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
721         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
722         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
723 }
724
725 static void cpt_set_infoframes(struct drm_encoder *encoder,
726                                bool enable,
727                                const struct intel_crtc_state *crtc_state,
728                                const struct drm_connector_state *conn_state)
729 {
730         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
731         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
732         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
733         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
734         u32 val = I915_READ(reg);
735
736         assert_hdmi_port_disabled(intel_hdmi);
737
738         /* See the big comment in g4x_set_infoframes() */
739         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
740
741         if (!enable) {
742                 if (!(val & VIDEO_DIP_ENABLE))
743                         return;
744                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
745                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
746                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
747                 I915_WRITE(reg, val);
748                 POSTING_READ(reg);
749                 return;
750         }
751
752         /* Set both together, unset both together: see the spec. */
753         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
754         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
755                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
756
757         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
758                 val |= VIDEO_DIP_ENABLE_GCP;
759
760         I915_WRITE(reg, val);
761         POSTING_READ(reg);
762
763         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
764         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
765         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
766 }
767
768 static void vlv_set_infoframes(struct drm_encoder *encoder,
769                                bool enable,
770                                const struct intel_crtc_state *crtc_state,
771                                const struct drm_connector_state *conn_state)
772 {
773         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
774         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
775         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
776         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
777         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
778         u32 val = I915_READ(reg);
779         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
780
781         assert_hdmi_port_disabled(intel_hdmi);
782
783         /* See the big comment in g4x_set_infoframes() */
784         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
785
786         if (!enable) {
787                 if (!(val & VIDEO_DIP_ENABLE))
788                         return;
789                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
790                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
791                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
792                 I915_WRITE(reg, val);
793                 POSTING_READ(reg);
794                 return;
795         }
796
797         if (port != (val & VIDEO_DIP_PORT_MASK)) {
798                 WARN(val & VIDEO_DIP_ENABLE,
799                      "DIP already enabled on port %c\n",
800                      (val & VIDEO_DIP_PORT_MASK) >> 29);
801                 val &= ~VIDEO_DIP_PORT_MASK;
802                 val |= port;
803         }
804
805         val |= VIDEO_DIP_ENABLE;
806         val &= ~(VIDEO_DIP_ENABLE_AVI |
807                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
808                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
809
810         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
811                 val |= VIDEO_DIP_ENABLE_GCP;
812
813         I915_WRITE(reg, val);
814         POSTING_READ(reg);
815
816         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
817         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
818         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
819 }
820
821 static void hsw_set_infoframes(struct drm_encoder *encoder,
822                                bool enable,
823                                const struct intel_crtc_state *crtc_state,
824                                const struct drm_connector_state *conn_state)
825 {
826         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
827         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
828         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
829         u32 val = I915_READ(reg);
830
831         assert_hdmi_port_disabled(intel_hdmi);
832
833         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
834                  VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
835                  VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
836
837         if (!enable) {
838                 I915_WRITE(reg, val);
839                 POSTING_READ(reg);
840                 return;
841         }
842
843         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
844                 val |= VIDEO_DIP_ENABLE_GCP_HSW;
845
846         I915_WRITE(reg, val);
847         POSTING_READ(reg);
848
849         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
850         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
851         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
852 }
853
854 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
855 {
856         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
857         struct i2c_adapter *adapter =
858                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
859
860         if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
861                 return;
862
863         DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
864                       enable ? "Enabling" : "Disabling");
865
866         drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
867                                          adapter, enable);
868 }
869
870 static void intel_hdmi_prepare(struct intel_encoder *encoder,
871                                const struct intel_crtc_state *crtc_state)
872 {
873         struct drm_device *dev = encoder->base.dev;
874         struct drm_i915_private *dev_priv = to_i915(dev);
875         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
876         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
877         const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
878         u32 hdmi_val;
879
880         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
881
882         hdmi_val = SDVO_ENCODING_HDMI;
883         if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
884                 hdmi_val |= HDMI_COLOR_RANGE_16_235;
885         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
886                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
887         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
888                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
889
890         if (crtc_state->pipe_bpp > 24)
891                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
892         else
893                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
894
895         if (crtc_state->has_hdmi_sink)
896                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
897
898         if (HAS_PCH_CPT(dev_priv))
899                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
900         else if (IS_CHERRYVIEW(dev_priv))
901                 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
902         else
903                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
904
905         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
906         POSTING_READ(intel_hdmi->hdmi_reg);
907 }
908
909 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
910                                     enum pipe *pipe)
911 {
912         struct drm_device *dev = encoder->base.dev;
913         struct drm_i915_private *dev_priv = to_i915(dev);
914         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
915         u32 tmp;
916         bool ret;
917
918         if (!intel_display_power_get_if_enabled(dev_priv,
919                                                 encoder->power_domain))
920                 return false;
921
922         ret = false;
923
924         tmp = I915_READ(intel_hdmi->hdmi_reg);
925
926         if (!(tmp & SDVO_ENABLE))
927                 goto out;
928
929         if (HAS_PCH_CPT(dev_priv))
930                 *pipe = PORT_TO_PIPE_CPT(tmp);
931         else if (IS_CHERRYVIEW(dev_priv))
932                 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
933         else
934                 *pipe = PORT_TO_PIPE(tmp);
935
936         ret = true;
937
938 out:
939         intel_display_power_put(dev_priv, encoder->power_domain);
940
941         return ret;
942 }
943
944 static void intel_hdmi_get_config(struct intel_encoder *encoder,
945                                   struct intel_crtc_state *pipe_config)
946 {
947         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
948         struct drm_device *dev = encoder->base.dev;
949         struct drm_i915_private *dev_priv = to_i915(dev);
950         u32 tmp, flags = 0;
951         int dotclock;
952
953         tmp = I915_READ(intel_hdmi->hdmi_reg);
954
955         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
956                 flags |= DRM_MODE_FLAG_PHSYNC;
957         else
958                 flags |= DRM_MODE_FLAG_NHSYNC;
959
960         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
961                 flags |= DRM_MODE_FLAG_PVSYNC;
962         else
963                 flags |= DRM_MODE_FLAG_NVSYNC;
964
965         if (tmp & HDMI_MODE_SELECT_HDMI)
966                 pipe_config->has_hdmi_sink = true;
967
968         if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
969                 pipe_config->has_infoframe = true;
970
971         if (tmp & SDVO_AUDIO_ENABLE)
972                 pipe_config->has_audio = true;
973
974         if (!HAS_PCH_SPLIT(dev_priv) &&
975             tmp & HDMI_COLOR_RANGE_16_235)
976                 pipe_config->limited_color_range = true;
977
978         pipe_config->base.adjusted_mode.flags |= flags;
979
980         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
981                 dotclock = pipe_config->port_clock * 2 / 3;
982         else
983                 dotclock = pipe_config->port_clock;
984
985         if (pipe_config->pixel_multiplier)
986                 dotclock /= pipe_config->pixel_multiplier;
987
988         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
989
990         pipe_config->lane_count = 4;
991 }
992
993 static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
994                                     struct intel_crtc_state *pipe_config,
995                                     struct drm_connector_state *conn_state)
996 {
997         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
998
999         WARN_ON(!pipe_config->has_hdmi_sink);
1000         DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
1001                          pipe_name(crtc->pipe));
1002         intel_audio_codec_enable(encoder, pipe_config, conn_state);
1003 }
1004
1005 static void g4x_enable_hdmi(struct intel_encoder *encoder,
1006                             struct intel_crtc_state *pipe_config,
1007                             struct drm_connector_state *conn_state)
1008 {
1009         struct drm_device *dev = encoder->base.dev;
1010         struct drm_i915_private *dev_priv = to_i915(dev);
1011         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1012         u32 temp;
1013
1014         temp = I915_READ(intel_hdmi->hdmi_reg);
1015
1016         temp |= SDVO_ENABLE;
1017         if (pipe_config->has_audio)
1018                 temp |= SDVO_AUDIO_ENABLE;
1019
1020         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1021         POSTING_READ(intel_hdmi->hdmi_reg);
1022
1023         if (pipe_config->has_audio)
1024                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1025 }
1026
1027 static void ibx_enable_hdmi(struct intel_encoder *encoder,
1028                             struct intel_crtc_state *pipe_config,
1029                             struct drm_connector_state *conn_state)
1030 {
1031         struct drm_device *dev = encoder->base.dev;
1032         struct drm_i915_private *dev_priv = to_i915(dev);
1033         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1034         u32 temp;
1035
1036         temp = I915_READ(intel_hdmi->hdmi_reg);
1037
1038         temp |= SDVO_ENABLE;
1039         if (pipe_config->has_audio)
1040                 temp |= SDVO_AUDIO_ENABLE;
1041
1042         /*
1043          * HW workaround, need to write this twice for issue
1044          * that may result in first write getting masked.
1045          */
1046         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1047         POSTING_READ(intel_hdmi->hdmi_reg);
1048         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1049         POSTING_READ(intel_hdmi->hdmi_reg);
1050
1051         /*
1052          * HW workaround, need to toggle enable bit off and on
1053          * for 12bpc with pixel repeat.
1054          *
1055          * FIXME: BSpec says this should be done at the end of
1056          * of the modeset sequence, so not sure if this isn't too soon.
1057          */
1058         if (pipe_config->pipe_bpp > 24 &&
1059             pipe_config->pixel_multiplier > 1) {
1060                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1061                 POSTING_READ(intel_hdmi->hdmi_reg);
1062
1063                 /*
1064                  * HW workaround, need to write this twice for issue
1065                  * that may result in first write getting masked.
1066                  */
1067                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1068                 POSTING_READ(intel_hdmi->hdmi_reg);
1069                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1070                 POSTING_READ(intel_hdmi->hdmi_reg);
1071         }
1072
1073         if (pipe_config->has_audio)
1074                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1075 }
1076
1077 static void cpt_enable_hdmi(struct intel_encoder *encoder,
1078                             struct intel_crtc_state *pipe_config,
1079                             struct drm_connector_state *conn_state)
1080 {
1081         struct drm_device *dev = encoder->base.dev;
1082         struct drm_i915_private *dev_priv = to_i915(dev);
1083         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1084         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1085         enum pipe pipe = crtc->pipe;
1086         u32 temp;
1087
1088         temp = I915_READ(intel_hdmi->hdmi_reg);
1089
1090         temp |= SDVO_ENABLE;
1091         if (pipe_config->has_audio)
1092                 temp |= SDVO_AUDIO_ENABLE;
1093
1094         /*
1095          * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1096          *
1097          * The procedure for 12bpc is as follows:
1098          * 1. disable HDMI clock gating
1099          * 2. enable HDMI with 8bpc
1100          * 3. enable HDMI with 12bpc
1101          * 4. enable HDMI clock gating
1102          */
1103
1104         if (pipe_config->pipe_bpp > 24) {
1105                 I915_WRITE(TRANS_CHICKEN1(pipe),
1106                            I915_READ(TRANS_CHICKEN1(pipe)) |
1107                            TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1108
1109                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1110                 temp |= SDVO_COLOR_FORMAT_8bpc;
1111         }
1112
1113         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1114         POSTING_READ(intel_hdmi->hdmi_reg);
1115
1116         if (pipe_config->pipe_bpp > 24) {
1117                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1118                 temp |= HDMI_COLOR_FORMAT_12bpc;
1119
1120                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1121                 POSTING_READ(intel_hdmi->hdmi_reg);
1122
1123                 I915_WRITE(TRANS_CHICKEN1(pipe),
1124                            I915_READ(TRANS_CHICKEN1(pipe)) &
1125                            ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1126         }
1127
1128         if (pipe_config->has_audio)
1129                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1130 }
1131
1132 static void vlv_enable_hdmi(struct intel_encoder *encoder,
1133                             struct intel_crtc_state *pipe_config,
1134                             struct drm_connector_state *conn_state)
1135 {
1136 }
1137
1138 static void intel_disable_hdmi(struct intel_encoder *encoder,
1139                                struct intel_crtc_state *old_crtc_state,
1140                                struct drm_connector_state *old_conn_state)
1141 {
1142         struct drm_device *dev = encoder->base.dev;
1143         struct drm_i915_private *dev_priv = to_i915(dev);
1144         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1145         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1146         u32 temp;
1147
1148         temp = I915_READ(intel_hdmi->hdmi_reg);
1149
1150         temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1151         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1152         POSTING_READ(intel_hdmi->hdmi_reg);
1153
1154         /*
1155          * HW workaround for IBX, we need to move the port
1156          * to transcoder A after disabling it to allow the
1157          * matching DP port to be enabled on transcoder A.
1158          */
1159         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
1160                 /*
1161                  * We get CPU/PCH FIFO underruns on the other pipe when
1162                  * doing the workaround. Sweep them under the rug.
1163                  */
1164                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1165                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1166
1167                 temp &= ~SDVO_PIPE_B_SELECT;
1168                 temp |= SDVO_ENABLE;
1169                 /*
1170                  * HW workaround, need to write this twice for issue
1171                  * that may result in first write getting masked.
1172                  */
1173                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1174                 POSTING_READ(intel_hdmi->hdmi_reg);
1175                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1176                 POSTING_READ(intel_hdmi->hdmi_reg);
1177
1178                 temp &= ~SDVO_ENABLE;
1179                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1180                 POSTING_READ(intel_hdmi->hdmi_reg);
1181
1182                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
1183                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1184                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1185         }
1186
1187         intel_hdmi->set_infoframes(&encoder->base, false, old_crtc_state, old_conn_state);
1188
1189         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1190 }
1191
1192 static void g4x_disable_hdmi(struct intel_encoder *encoder,
1193                              struct intel_crtc_state *old_crtc_state,
1194                              struct drm_connector_state *old_conn_state)
1195 {
1196         if (old_crtc_state->has_audio)
1197                 intel_audio_codec_disable(encoder);
1198
1199         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1200 }
1201
1202 static void pch_disable_hdmi(struct intel_encoder *encoder,
1203                              struct intel_crtc_state *old_crtc_state,
1204                              struct drm_connector_state *old_conn_state)
1205 {
1206         if (old_crtc_state->has_audio)
1207                 intel_audio_codec_disable(encoder);
1208 }
1209
1210 static void pch_post_disable_hdmi(struct intel_encoder *encoder,
1211                                   struct intel_crtc_state *old_crtc_state,
1212                                   struct drm_connector_state *old_conn_state)
1213 {
1214         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1215 }
1216
1217 static int intel_hdmi_source_max_tmds_clock(struct drm_i915_private *dev_priv)
1218 {
1219         if (IS_G4X(dev_priv))
1220                 return 165000;
1221         else if (IS_GEMINILAKE(dev_priv))
1222                 return 594000;
1223         else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)
1224                 return 300000;
1225         else
1226                 return 225000;
1227 }
1228
1229 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1230                                  bool respect_downstream_limits,
1231                                  bool force_dvi)
1232 {
1233         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1234         int max_tmds_clock = intel_hdmi_source_max_tmds_clock(to_i915(dev));
1235
1236         if (respect_downstream_limits) {
1237                 struct intel_connector *connector = hdmi->attached_connector;
1238                 const struct drm_display_info *info = &connector->base.display_info;
1239
1240                 if (hdmi->dp_dual_mode.max_tmds_clock)
1241                         max_tmds_clock = min(max_tmds_clock,
1242                                              hdmi->dp_dual_mode.max_tmds_clock);
1243
1244                 if (info->max_tmds_clock)
1245                         max_tmds_clock = min(max_tmds_clock,
1246                                              info->max_tmds_clock);
1247                 else if (!hdmi->has_hdmi_sink || force_dvi)
1248                         max_tmds_clock = min(max_tmds_clock, 165000);
1249         }
1250
1251         return max_tmds_clock;
1252 }
1253
1254 static enum drm_mode_status
1255 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1256                       int clock, bool respect_downstream_limits,
1257                       bool force_dvi)
1258 {
1259         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1260
1261         if (clock < 25000)
1262                 return MODE_CLOCK_LOW;
1263         if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi))
1264                 return MODE_CLOCK_HIGH;
1265
1266         /* BXT DPLL can't generate 223-240 MHz */
1267         if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
1268                 return MODE_CLOCK_RANGE;
1269
1270         /* CHV DPLL can't generate 216-240 MHz */
1271         if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1272                 return MODE_CLOCK_RANGE;
1273
1274         return MODE_OK;
1275 }
1276
1277 static enum drm_mode_status
1278 intel_hdmi_mode_valid(struct drm_connector *connector,
1279                       struct drm_display_mode *mode)
1280 {
1281         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1282         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1283         struct drm_i915_private *dev_priv = to_i915(dev);
1284         enum drm_mode_status status;
1285         int clock;
1286         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1287         bool force_dvi =
1288                 READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI;
1289
1290         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1291                 return MODE_NO_DBLESCAN;
1292
1293         clock = mode->clock;
1294
1295         if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1296                 clock *= 2;
1297
1298         if (clock > max_dotclk)
1299                 return MODE_CLOCK_HIGH;
1300
1301         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1302                 clock *= 2;
1303
1304         if (drm_mode_is_420_only(&connector->display_info, mode))
1305                 clock /= 2;
1306
1307         /* check if we can do 8bpc */
1308         status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi);
1309
1310         /* if we can't do 8bpc we may still be able to do 12bpc */
1311         if (!HAS_GMCH_DISPLAY(dev_priv) && status != MODE_OK && hdmi->has_hdmi_sink && !force_dvi)
1312                 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true, force_dvi);
1313
1314         return status;
1315 }
1316
1317 static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
1318 {
1319         struct drm_i915_private *dev_priv =
1320                 to_i915(crtc_state->base.crtc->dev);
1321         struct drm_atomic_state *state = crtc_state->base.state;
1322         struct drm_connector_state *connector_state;
1323         struct drm_connector *connector;
1324         int i;
1325
1326         if (HAS_GMCH_DISPLAY(dev_priv))
1327                 return false;
1328
1329         /*
1330          * HDMI 12bpc affects the clocks, so it's only possible
1331          * when not cloning with other encoder types.
1332          */
1333         if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
1334                 return false;
1335
1336         for_each_new_connector_in_state(state, connector, connector_state, i) {
1337                 const struct drm_display_info *info = &connector->display_info;
1338
1339                 if (connector_state->crtc != crtc_state->base.crtc)
1340                         continue;
1341
1342                 if (crtc_state->ycbcr420) {
1343                         const struct drm_hdmi_info *hdmi = &info->hdmi;
1344
1345                         if (!(hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36))
1346                                 return false;
1347                 } else {
1348                         if (!(info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36))
1349                                 return false;
1350                 }
1351         }
1352
1353         /* Display Wa #1139 */
1354         if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
1355             crtc_state->base.adjusted_mode.htotal > 5460)
1356                 return false;
1357
1358         return true;
1359 }
1360
1361 static bool
1362 intel_hdmi_ycbcr420_config(struct drm_connector *connector,
1363                            struct intel_crtc_state *config,
1364                            int *clock_12bpc, int *clock_8bpc)
1365 {
1366         struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
1367
1368         if (!connector->ycbcr_420_allowed) {
1369                 DRM_ERROR("Platform doesn't support YCBCR420 output\n");
1370                 return false;
1371         }
1372
1373         /* YCBCR420 TMDS rate requirement is half the pixel clock */
1374         config->port_clock /= 2;
1375         *clock_12bpc /= 2;
1376         *clock_8bpc /= 2;
1377         config->ycbcr420 = true;
1378
1379         /* YCBCR 420 output conversion needs a scaler */
1380         if (skl_update_scaler_crtc(config)) {
1381                 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
1382                 return false;
1383         }
1384
1385         intel_pch_panel_fitting(intel_crtc, config,
1386                                 DRM_MODE_SCALE_FULLSCREEN);
1387
1388         return true;
1389 }
1390
1391 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1392                                struct intel_crtc_state *pipe_config,
1393                                struct drm_connector_state *conn_state)
1394 {
1395         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1396         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1397         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1398         struct drm_connector *connector = conn_state->connector;
1399         struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
1400         struct intel_digital_connector_state *intel_conn_state =
1401                 to_intel_digital_connector_state(conn_state);
1402         int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1403         int clock_12bpc = clock_8bpc * 3 / 2;
1404         int desired_bpp;
1405         bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
1406
1407         pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink;
1408
1409         if (pipe_config->has_hdmi_sink)
1410                 pipe_config->has_infoframe = true;
1411
1412         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1413                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1414                 pipe_config->limited_color_range =
1415                         pipe_config->has_hdmi_sink &&
1416                         drm_default_rgb_quant_range(adjusted_mode) ==
1417                         HDMI_QUANTIZATION_RANGE_LIMITED;
1418         } else {
1419                 pipe_config->limited_color_range =
1420                         intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
1421         }
1422
1423         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1424                 pipe_config->pixel_multiplier = 2;
1425                 clock_8bpc *= 2;
1426                 clock_12bpc *= 2;
1427         }
1428
1429         if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
1430                 if (!intel_hdmi_ycbcr420_config(connector, pipe_config,
1431                                                 &clock_12bpc, &clock_8bpc)) {
1432                         DRM_ERROR("Can't support YCBCR420 output\n");
1433                         return false;
1434                 }
1435         }
1436
1437         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
1438                 pipe_config->has_pch_encoder = true;
1439
1440         if (pipe_config->has_hdmi_sink) {
1441                 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1442                         pipe_config->has_audio = intel_hdmi->has_audio;
1443                 else
1444                         pipe_config->has_audio =
1445                                 intel_conn_state->force_audio == HDMI_AUDIO_ON;
1446         }
1447
1448         /*
1449          * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1450          * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1451          * outputs. We also need to check that the higher clock still fits
1452          * within limits.
1453          */
1454         if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && !force_dvi &&
1455             hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true, force_dvi) == MODE_OK &&
1456             hdmi_12bpc_possible(pipe_config)) {
1457                 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1458                 desired_bpp = 12*3;
1459
1460                 /* Need to adjust the port link by 1.5x for 12bpc. */
1461                 pipe_config->port_clock = clock_12bpc;
1462         } else {
1463                 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1464                 desired_bpp = 8*3;
1465
1466                 pipe_config->port_clock = clock_8bpc;
1467         }
1468
1469         if (!pipe_config->bw_constrained) {
1470                 DRM_DEBUG_KMS("forcing pipe bpp to %i for HDMI\n", desired_bpp);
1471                 pipe_config->pipe_bpp = desired_bpp;
1472         }
1473
1474         if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1475                                   false, force_dvi) != MODE_OK) {
1476                 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1477                 return false;
1478         }
1479
1480         /* Set user selected PAR to incoming mode's member */
1481         adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
1482
1483         pipe_config->lane_count = 4;
1484
1485         if (scdc->scrambling.supported && IS_GEMINILAKE(dev_priv)) {
1486                 if (scdc->scrambling.low_rates)
1487                         pipe_config->hdmi_scrambling = true;
1488
1489                 if (pipe_config->port_clock > 340000) {
1490                         pipe_config->hdmi_scrambling = true;
1491                         pipe_config->hdmi_high_tmds_clock_ratio = true;
1492                 }
1493         }
1494
1495         return true;
1496 }
1497
1498 static void
1499 intel_hdmi_unset_edid(struct drm_connector *connector)
1500 {
1501         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1502
1503         intel_hdmi->has_hdmi_sink = false;
1504         intel_hdmi->has_audio = false;
1505         intel_hdmi->rgb_quant_range_selectable = false;
1506
1507         intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
1508         intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
1509
1510         kfree(to_intel_connector(connector)->detect_edid);
1511         to_intel_connector(connector)->detect_edid = NULL;
1512 }
1513
1514 static void
1515 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
1516 {
1517         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1518         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1519         enum port port = hdmi_to_dig_port(hdmi)->port;
1520         struct i2c_adapter *adapter =
1521                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1522         enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
1523
1524         /*
1525          * Type 1 DVI adaptors are not required to implement any
1526          * registers, so we can't always detect their presence.
1527          * Ideally we should be able to check the state of the
1528          * CONFIG1 pin, but no such luck on our hardware.
1529          *
1530          * The only method left to us is to check the VBT to see
1531          * if the port is a dual mode capable DP port. But let's
1532          * only do that when we sucesfully read the EDID, to avoid
1533          * confusing log messages about DP dual mode adaptors when
1534          * there's nothing connected to the port.
1535          */
1536         if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
1537                 if (has_edid &&
1538                     intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
1539                         DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
1540                         type = DRM_DP_DUAL_MODE_TYPE1_DVI;
1541                 } else {
1542                         type = DRM_DP_DUAL_MODE_NONE;
1543                 }
1544         }
1545
1546         if (type == DRM_DP_DUAL_MODE_NONE)
1547                 return;
1548
1549         hdmi->dp_dual_mode.type = type;
1550         hdmi->dp_dual_mode.max_tmds_clock =
1551                 drm_dp_dual_mode_max_tmds_clock(type, adapter);
1552
1553         DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
1554                       drm_dp_get_dual_mode_type_name(type),
1555                       hdmi->dp_dual_mode.max_tmds_clock);
1556 }
1557
1558 static bool
1559 intel_hdmi_set_edid(struct drm_connector *connector)
1560 {
1561         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1562         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1563         struct edid *edid;
1564         bool connected = false;
1565
1566         intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1567
1568         edid = drm_get_edid(connector,
1569                             intel_gmbus_get_adapter(dev_priv,
1570                             intel_hdmi->ddc_bus));
1571
1572         intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
1573
1574         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1575
1576         to_intel_connector(connector)->detect_edid = edid;
1577         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1578                 intel_hdmi->rgb_quant_range_selectable =
1579                         drm_rgb_quant_range_selectable(edid);
1580
1581                 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1582                 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
1583
1584                 connected = true;
1585         }
1586
1587         return connected;
1588 }
1589
1590 static enum drm_connector_status
1591 intel_hdmi_detect(struct drm_connector *connector, bool force)
1592 {
1593         enum drm_connector_status status;
1594         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1595
1596         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1597                       connector->base.id, connector->name);
1598
1599         intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1600
1601         intel_hdmi_unset_edid(connector);
1602
1603         if (intel_hdmi_set_edid(connector)) {
1604                 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1605
1606                 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1607                 status = connector_status_connected;
1608         } else
1609                 status = connector_status_disconnected;
1610
1611         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1612
1613         return status;
1614 }
1615
1616 static void
1617 intel_hdmi_force(struct drm_connector *connector)
1618 {
1619         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1620
1621         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1622                       connector->base.id, connector->name);
1623
1624         intel_hdmi_unset_edid(connector);
1625
1626         if (connector->status != connector_status_connected)
1627                 return;
1628
1629         intel_hdmi_set_edid(connector);
1630         hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1631 }
1632
1633 static int intel_hdmi_get_modes(struct drm_connector *connector)
1634 {
1635         struct edid *edid;
1636
1637         edid = to_intel_connector(connector)->detect_edid;
1638         if (edid == NULL)
1639                 return 0;
1640
1641         return intel_connector_update_modes(connector, edid);
1642 }
1643
1644 static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
1645                                   struct intel_crtc_state *pipe_config,
1646                                   struct drm_connector_state *conn_state)
1647 {
1648         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1649
1650         intel_hdmi_prepare(encoder, pipe_config);
1651
1652         intel_hdmi->set_infoframes(&encoder->base,
1653                                    pipe_config->has_hdmi_sink,
1654                                    pipe_config, conn_state);
1655 }
1656
1657 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
1658                                 struct intel_crtc_state *pipe_config,
1659                                 struct drm_connector_state *conn_state)
1660 {
1661         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1662         struct intel_hdmi *intel_hdmi = &dport->hdmi;
1663         struct drm_device *dev = encoder->base.dev;
1664         struct drm_i915_private *dev_priv = to_i915(dev);
1665
1666         vlv_phy_pre_encoder_enable(encoder);
1667
1668         /* HDMI 1.0V-2dB */
1669         vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
1670                                  0x2b247878);
1671
1672         intel_hdmi->set_infoframes(&encoder->base,
1673                                    pipe_config->has_hdmi_sink,
1674                                    pipe_config, conn_state);
1675
1676         g4x_enable_hdmi(encoder, pipe_config, conn_state);
1677
1678         vlv_wait_port_ready(dev_priv, dport, 0x0);
1679 }
1680
1681 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
1682                                     struct intel_crtc_state *pipe_config,
1683                                     struct drm_connector_state *conn_state)
1684 {
1685         intel_hdmi_prepare(encoder, pipe_config);
1686
1687         vlv_phy_pre_pll_enable(encoder);
1688 }
1689
1690 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
1691                                     struct intel_crtc_state *pipe_config,
1692                                     struct drm_connector_state *conn_state)
1693 {
1694         intel_hdmi_prepare(encoder, pipe_config);
1695
1696         chv_phy_pre_pll_enable(encoder);
1697 }
1698
1699 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
1700                                       struct intel_crtc_state *old_crtc_state,
1701                                       struct drm_connector_state *old_conn_state)
1702 {
1703         chv_phy_post_pll_disable(encoder);
1704 }
1705
1706 static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
1707                                   struct intel_crtc_state *old_crtc_state,
1708                                   struct drm_connector_state *old_conn_state)
1709 {
1710         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1711         vlv_phy_reset_lanes(encoder);
1712 }
1713
1714 static void chv_hdmi_post_disable(struct intel_encoder *encoder,
1715                                   struct intel_crtc_state *old_crtc_state,
1716                                   struct drm_connector_state *old_conn_state)
1717 {
1718         struct drm_device *dev = encoder->base.dev;
1719         struct drm_i915_private *dev_priv = to_i915(dev);
1720
1721         mutex_lock(&dev_priv->sb_lock);
1722
1723         /* Assert data lane reset */
1724         chv_data_lane_soft_reset(encoder, true);
1725
1726         mutex_unlock(&dev_priv->sb_lock);
1727 }
1728
1729 static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
1730                                 struct intel_crtc_state *pipe_config,
1731                                 struct drm_connector_state *conn_state)
1732 {
1733         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1734         struct intel_hdmi *intel_hdmi = &dport->hdmi;
1735         struct drm_device *dev = encoder->base.dev;
1736         struct drm_i915_private *dev_priv = to_i915(dev);
1737
1738         chv_phy_pre_encoder_enable(encoder);
1739
1740         /* FIXME: Program the support xxx V-dB */
1741         /* Use 800mV-0dB */
1742         chv_set_phy_signal_level(encoder, 128, 102, false);
1743
1744         intel_hdmi->set_infoframes(&encoder->base,
1745                                    pipe_config->has_hdmi_sink,
1746                                    pipe_config, conn_state);
1747
1748         g4x_enable_hdmi(encoder, pipe_config, conn_state);
1749
1750         vlv_wait_port_ready(dev_priv, dport, 0x0);
1751
1752         /* Second common lane will stay alive on its own now */
1753         chv_phy_release_cl2_override(encoder);
1754 }
1755
1756 static void intel_hdmi_destroy(struct drm_connector *connector)
1757 {
1758         kfree(to_intel_connector(connector)->detect_edid);
1759         drm_connector_cleanup(connector);
1760         kfree(connector);
1761 }
1762
1763 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1764         .detect = intel_hdmi_detect,
1765         .force = intel_hdmi_force,
1766         .fill_modes = drm_helper_probe_single_connector_modes,
1767         .atomic_get_property = intel_digital_connector_atomic_get_property,
1768         .atomic_set_property = intel_digital_connector_atomic_set_property,
1769         .late_register = intel_connector_register,
1770         .early_unregister = intel_connector_unregister,
1771         .destroy = intel_hdmi_destroy,
1772         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1773         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1774 };
1775
1776 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1777         .get_modes = intel_hdmi_get_modes,
1778         .mode_valid = intel_hdmi_mode_valid,
1779         .atomic_check = intel_digital_connector_atomic_check,
1780 };
1781
1782 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1783         .destroy = intel_encoder_destroy,
1784 };
1785
1786 static void
1787 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1788 {
1789         intel_attach_force_audio_property(connector);
1790         intel_attach_broadcast_rgb_property(connector);
1791         intel_attach_aspect_ratio_property(connector);
1792         connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1793 }
1794
1795 /*
1796  * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
1797  * @encoder: intel_encoder
1798  * @connector: drm_connector
1799  * @high_tmds_clock_ratio = bool to indicate if the function needs to set
1800  *  or reset the high tmds clock ratio for scrambling
1801  * @scrambling: bool to Indicate if the function needs to set or reset
1802  *  sink scrambling
1803  *
1804  * This function handles scrambling on HDMI 2.0 capable sinks.
1805  * If required clock rate is > 340 Mhz && scrambling is supported by sink
1806  * it enables scrambling. This should be called before enabling the HDMI
1807  * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
1808  * detect a scrambled clock within 100 ms.
1809  */
1810 void intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
1811                                        struct drm_connector *connector,
1812                                        bool high_tmds_clock_ratio,
1813                                        bool scrambling)
1814 {
1815         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1816         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1817         struct drm_scrambling *sink_scrambling =
1818                                 &connector->display_info.hdmi.scdc.scrambling;
1819         struct i2c_adapter *adptr = intel_gmbus_get_adapter(dev_priv,
1820                                                            intel_hdmi->ddc_bus);
1821         bool ret;
1822
1823         if (!sink_scrambling->supported)
1824                 return;
1825
1826         DRM_DEBUG_KMS("Setting sink scrambling for enc:%s connector:%s\n",
1827                       encoder->base.name, connector->name);
1828
1829         /* Set TMDS bit clock ratio to 1/40 or 1/10 */
1830         ret = drm_scdc_set_high_tmds_clock_ratio(adptr, high_tmds_clock_ratio);
1831         if (!ret) {
1832                 DRM_ERROR("Set TMDS ratio failed\n");
1833                 return;
1834         }
1835
1836         /* Enable/disable sink scrambling */
1837         ret = drm_scdc_set_scrambling(adptr, scrambling);
1838         if (!ret) {
1839                 DRM_ERROR("Set sink scrambling failed\n");
1840                 return;
1841         }
1842
1843         DRM_DEBUG_KMS("sink scrambling handled\n");
1844 }
1845
1846 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
1847                              enum port port)
1848 {
1849         const struct ddi_vbt_port_info *info =
1850                 &dev_priv->vbt.ddi_port_info[port];
1851         u8 ddc_pin;
1852
1853         if (info->alternate_ddc_pin) {
1854                 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
1855                               info->alternate_ddc_pin, port_name(port));
1856                 return info->alternate_ddc_pin;
1857         }
1858
1859         switch (port) {
1860         case PORT_B:
1861                 if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
1862                         ddc_pin = GMBUS_PIN_1_BXT;
1863                 else
1864                         ddc_pin = GMBUS_PIN_DPB;
1865                 break;
1866         case PORT_C:
1867                 if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
1868                         ddc_pin = GMBUS_PIN_2_BXT;
1869                 else
1870                         ddc_pin = GMBUS_PIN_DPC;
1871                 break;
1872         case PORT_D:
1873                 if (HAS_PCH_CNP(dev_priv))
1874                         ddc_pin = GMBUS_PIN_4_CNP;
1875                 else if (IS_CHERRYVIEW(dev_priv))
1876                         ddc_pin = GMBUS_PIN_DPD_CHV;
1877                 else
1878                         ddc_pin = GMBUS_PIN_DPD;
1879                 break;
1880         default:
1881                 MISSING_CASE(port);
1882                 ddc_pin = GMBUS_PIN_DPB;
1883                 break;
1884         }
1885
1886         DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
1887                       ddc_pin, port_name(port));
1888
1889         return ddc_pin;
1890 }
1891
1892 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1893                                struct intel_connector *intel_connector)
1894 {
1895         struct drm_connector *connector = &intel_connector->base;
1896         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1897         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1898         struct drm_device *dev = intel_encoder->base.dev;
1899         struct drm_i915_private *dev_priv = to_i915(dev);
1900         enum port port = intel_dig_port->port;
1901
1902         DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
1903                       port_name(port));
1904
1905         if (WARN(intel_dig_port->max_lanes < 4,
1906                  "Not enough lanes (%d) for HDMI on port %c\n",
1907                  intel_dig_port->max_lanes, port_name(port)))
1908                 return;
1909
1910         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
1911                            DRM_MODE_CONNECTOR_HDMIA);
1912         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
1913
1914         connector->interlace_allowed = 1;
1915         connector->doublescan_allowed = 0;
1916         connector->stereo_allowed = 1;
1917
1918         if (IS_GEMINILAKE(dev_priv))
1919                 connector->ycbcr_420_allowed = true;
1920
1921         intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
1922
1923         switch (port) {
1924         case PORT_B:
1925                 intel_encoder->hpd_pin = HPD_PORT_B;
1926                 break;
1927         case PORT_C:
1928                 intel_encoder->hpd_pin = HPD_PORT_C;
1929                 break;
1930         case PORT_D:
1931                 intel_encoder->hpd_pin = HPD_PORT_D;
1932                 break;
1933         case PORT_E:
1934                 intel_encoder->hpd_pin = HPD_PORT_E;
1935                 break;
1936         default:
1937                 MISSING_CASE(port);
1938                 return;
1939         }
1940
1941         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1942                 intel_hdmi->write_infoframe = vlv_write_infoframe;
1943                 intel_hdmi->set_infoframes = vlv_set_infoframes;
1944                 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
1945         } else if (IS_G4X(dev_priv)) {
1946                 intel_hdmi->write_infoframe = g4x_write_infoframe;
1947                 intel_hdmi->set_infoframes = g4x_set_infoframes;
1948                 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
1949         } else if (HAS_DDI(dev_priv)) {
1950                 intel_hdmi->write_infoframe = hsw_write_infoframe;
1951                 intel_hdmi->set_infoframes = hsw_set_infoframes;
1952                 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
1953         } else if (HAS_PCH_IBX(dev_priv)) {
1954                 intel_hdmi->write_infoframe = ibx_write_infoframe;
1955                 intel_hdmi->set_infoframes = ibx_set_infoframes;
1956                 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
1957         } else {
1958                 intel_hdmi->write_infoframe = cpt_write_infoframe;
1959                 intel_hdmi->set_infoframes = cpt_set_infoframes;
1960                 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
1961         }
1962
1963         if (HAS_DDI(dev_priv))
1964                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1965         else
1966                 intel_connector->get_hw_state = intel_connector_get_hw_state;
1967
1968         intel_hdmi_add_properties(intel_hdmi, connector);
1969
1970         intel_connector_attach_encoder(intel_connector, intel_encoder);
1971         intel_hdmi->attached_connector = intel_connector;
1972
1973         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1974          * 0xd.  Failure to do so will result in spurious interrupts being
1975          * generated on the port when a cable is not attached.
1976          */
1977         if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
1978                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1979                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1980         }
1981 }
1982
1983 void intel_hdmi_init(struct drm_i915_private *dev_priv,
1984                      i915_reg_t hdmi_reg, enum port port)
1985 {
1986         struct intel_digital_port *intel_dig_port;
1987         struct intel_encoder *intel_encoder;
1988         struct intel_connector *intel_connector;
1989
1990         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1991         if (!intel_dig_port)
1992                 return;
1993
1994         intel_connector = intel_connector_alloc();
1995         if (!intel_connector) {
1996                 kfree(intel_dig_port);
1997                 return;
1998         }
1999
2000         intel_encoder = &intel_dig_port->base;
2001
2002         drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
2003                          &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
2004                          "HDMI %c", port_name(port));
2005
2006         intel_encoder->compute_config = intel_hdmi_compute_config;
2007         if (HAS_PCH_SPLIT(dev_priv)) {
2008                 intel_encoder->disable = pch_disable_hdmi;
2009                 intel_encoder->post_disable = pch_post_disable_hdmi;
2010         } else {
2011                 intel_encoder->disable = g4x_disable_hdmi;
2012         }
2013         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
2014         intel_encoder->get_config = intel_hdmi_get_config;
2015         if (IS_CHERRYVIEW(dev_priv)) {
2016                 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
2017                 intel_encoder->pre_enable = chv_hdmi_pre_enable;
2018                 intel_encoder->enable = vlv_enable_hdmi;
2019                 intel_encoder->post_disable = chv_hdmi_post_disable;
2020                 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
2021         } else if (IS_VALLEYVIEW(dev_priv)) {
2022                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
2023                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
2024                 intel_encoder->enable = vlv_enable_hdmi;
2025                 intel_encoder->post_disable = vlv_hdmi_post_disable;
2026         } else {
2027                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
2028                 if (HAS_PCH_CPT(dev_priv))
2029                         intel_encoder->enable = cpt_enable_hdmi;
2030                 else if (HAS_PCH_IBX(dev_priv))
2031                         intel_encoder->enable = ibx_enable_hdmi;
2032                 else
2033                         intel_encoder->enable = g4x_enable_hdmi;
2034         }
2035
2036         intel_encoder->type = INTEL_OUTPUT_HDMI;
2037         intel_encoder->power_domain = intel_port_to_power_domain(port);
2038         intel_encoder->port = port;
2039         if (IS_CHERRYVIEW(dev_priv)) {
2040                 if (port == PORT_D)
2041                         intel_encoder->crtc_mask = 1 << 2;
2042                 else
2043                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2044         } else {
2045                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2046         }
2047         intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
2048         /*
2049          * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2050          * to work on real hardware. And since g4x can send infoframes to
2051          * only one port anyway, nothing is lost by allowing it.
2052          */
2053         if (IS_G4X(dev_priv))
2054                 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
2055
2056         intel_dig_port->port = port;
2057         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
2058         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
2059         intel_dig_port->max_lanes = 4;
2060
2061         intel_hdmi_init_connector(intel_dig_port, intel_connector);
2062 }