drm/i915: Suspend submission tasklets around wedging
[muen/linux.git] / drivers / gpu / drm / i915 / intel_lrc.c
1 /*
2  * Copyright © 2014 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Authors:
24  *    Ben Widawsky <ben@bwidawsk.net>
25  *    Michel Thierry <michel.thierry@intel.com>
26  *    Thomas Daniel <thomas.daniel@intel.com>
27  *    Oscar Mateo <oscar.mateo@intel.com>
28  *
29  */
30
31 /**
32  * DOC: Logical Rings, Logical Ring Contexts and Execlists
33  *
34  * Motivation:
35  * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36  * These expanded contexts enable a number of new abilities, especially
37  * "Execlists" (also implemented in this file).
38  *
39  * One of the main differences with the legacy HW contexts is that logical
40  * ring contexts incorporate many more things to the context's state, like
41  * PDPs or ringbuffer control registers:
42  *
43  * The reason why PDPs are included in the context is straightforward: as
44  * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45  * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46  * instead, the GPU will do it for you on the context switch.
47  *
48  * But, what about the ringbuffer control registers (head, tail, etc..)?
49  * shouldn't we just need a set of those per engine command streamer? This is
50  * where the name "Logical Rings" starts to make sense: by virtualizing the
51  * rings, the engine cs shifts to a new "ring buffer" with every context
52  * switch. When you want to submit a workload to the GPU you: A) choose your
53  * context, B) find its appropriate virtualized ring, C) write commands to it
54  * and then, finally, D) tell the GPU to switch to that context.
55  *
56  * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57  * to a contexts is via a context execution list, ergo "Execlists".
58  *
59  * LRC implementation:
60  * Regarding the creation of contexts, we have:
61  *
62  * - One global default context.
63  * - One local default context for each opened fd.
64  * - One local extra context for each context create ioctl call.
65  *
66  * Now that ringbuffers belong per-context (and not per-engine, like before)
67  * and that contexts are uniquely tied to a given engine (and not reusable,
68  * like before) we need:
69  *
70  * - One ringbuffer per-engine inside each context.
71  * - One backing object per-engine inside each context.
72  *
73  * The global default context starts its life with these new objects fully
74  * allocated and populated. The local default context for each opened fd is
75  * more complex, because we don't know at creation time which engine is going
76  * to use them. To handle this, we have implemented a deferred creation of LR
77  * contexts:
78  *
79  * The local context starts its life as a hollow or blank holder, that only
80  * gets populated for a given engine once we receive an execbuffer. If later
81  * on we receive another execbuffer ioctl for the same context but a different
82  * engine, we allocate/populate a new ringbuffer and context backing object and
83  * so on.
84  *
85  * Finally, regarding local contexts created using the ioctl call: as they are
86  * only allowed with the render ring, we can allocate & populate them right
87  * away (no need to defer anything, at least for now).
88  *
89  * Execlists implementation:
90  * Execlists are the new method by which, on gen8+ hardware, workloads are
91  * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92  * This method works as follows:
93  *
94  * When a request is committed, its commands (the BB start and any leading or
95  * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96  * for the appropriate context. The tail pointer in the hardware context is not
97  * updated at this time, but instead, kept by the driver in the ringbuffer
98  * structure. A structure representing this request is added to a request queue
99  * for the appropriate engine: this structure contains a copy of the context's
100  * tail after the request was written to the ring buffer and a pointer to the
101  * context itself.
102  *
103  * If the engine's request queue was empty before the request was added, the
104  * queue is processed immediately. Otherwise the queue will be processed during
105  * a context switch interrupt. In any case, elements on the queue will get sent
106  * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107  * globally unique 20-bits submission ID.
108  *
109  * When execution of a request completes, the GPU updates the context status
110  * buffer with a context complete event and generates a context switch interrupt.
111  * During the interrupt handling, the driver examines the events in the buffer:
112  * for each context complete event, if the announced ID matches that on the head
113  * of the request queue, then that request is retired and removed from the queue.
114  *
115  * After processing, if any requests were retired and the queue is not empty
116  * then a new execution list can be submitted. The two requests at the front of
117  * the queue are next to be submitted but since a context may not occur twice in
118  * an execution list, if subsequent requests have the same ID as the first then
119  * the two requests must be combined. This is done simply by discarding requests
120  * at the head of the queue until either only one requests is left (in which case
121  * we use a NULL second context) or the first two requests have unique IDs.
122  *
123  * By always executing the first two requests in the queue the driver ensures
124  * that the GPU is kept as busy as possible. In the case where a single context
125  * completes but a second context is still executing, the request for this second
126  * context will be at the head of the queue when we remove the first one. This
127  * request will then be resubmitted along with a new request for a different context,
128  * which will cause the hardware to continue executing the second request and queue
129  * the new request (the GPU detects the condition of a context getting preempted
130  * with the same context and optimizes the context switch flow by not doing
131  * preemption, but just sampling the new tail pointer).
132  *
133  */
134 #include <linux/interrupt.h>
135
136 #include <drm/drmP.h>
137 #include <drm/i915_drm.h>
138 #include "i915_drv.h"
139 #include "i915_gem_render_state.h"
140 #include "intel_mocs.h"
141
142 #define RING_EXECLIST_QFULL             (1 << 0x2)
143 #define RING_EXECLIST1_VALID            (1 << 0x3)
144 #define RING_EXECLIST0_VALID            (1 << 0x4)
145 #define RING_EXECLIST_ACTIVE_STATUS     (3 << 0xE)
146 #define RING_EXECLIST1_ACTIVE           (1 << 0x11)
147 #define RING_EXECLIST0_ACTIVE           (1 << 0x12)
148
149 #define GEN8_CTX_STATUS_IDLE_ACTIVE     (1 << 0)
150 #define GEN8_CTX_STATUS_PREEMPTED       (1 << 1)
151 #define GEN8_CTX_STATUS_ELEMENT_SWITCH  (1 << 2)
152 #define GEN8_CTX_STATUS_ACTIVE_IDLE     (1 << 3)
153 #define GEN8_CTX_STATUS_COMPLETE        (1 << 4)
154 #define GEN8_CTX_STATUS_LITE_RESTORE    (1 << 15)
155
156 #define GEN8_CTX_STATUS_COMPLETED_MASK \
157          (GEN8_CTX_STATUS_COMPLETE | GEN8_CTX_STATUS_PREEMPTED)
158
159 #define CTX_LRI_HEADER_0                0x01
160 #define CTX_CONTEXT_CONTROL             0x02
161 #define CTX_RING_HEAD                   0x04
162 #define CTX_RING_TAIL                   0x06
163 #define CTX_RING_BUFFER_START           0x08
164 #define CTX_RING_BUFFER_CONTROL         0x0a
165 #define CTX_BB_HEAD_U                   0x0c
166 #define CTX_BB_HEAD_L                   0x0e
167 #define CTX_BB_STATE                    0x10
168 #define CTX_SECOND_BB_HEAD_U            0x12
169 #define CTX_SECOND_BB_HEAD_L            0x14
170 #define CTX_SECOND_BB_STATE             0x16
171 #define CTX_BB_PER_CTX_PTR              0x18
172 #define CTX_RCS_INDIRECT_CTX            0x1a
173 #define CTX_RCS_INDIRECT_CTX_OFFSET     0x1c
174 #define CTX_LRI_HEADER_1                0x21
175 #define CTX_CTX_TIMESTAMP               0x22
176 #define CTX_PDP3_UDW                    0x24
177 #define CTX_PDP3_LDW                    0x26
178 #define CTX_PDP2_UDW                    0x28
179 #define CTX_PDP2_LDW                    0x2a
180 #define CTX_PDP1_UDW                    0x2c
181 #define CTX_PDP1_LDW                    0x2e
182 #define CTX_PDP0_UDW                    0x30
183 #define CTX_PDP0_LDW                    0x32
184 #define CTX_LRI_HEADER_2                0x41
185 #define CTX_R_PWR_CLK_STATE             0x42
186 #define CTX_GPGPU_CSR_BASE_ADDRESS      0x44
187
188 #define CTX_REG(reg_state, pos, reg, val) do { \
189         (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
190         (reg_state)[(pos)+1] = (val); \
191 } while (0)
192
193 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do {                \
194         const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
195         reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
196         reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
197 } while (0)
198
199 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
200         reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
201         reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
202 } while (0)
203
204 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT        0x17
205 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT        0x26
206 #define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT       0x19
207
208 /* Typical size of the average request (2 pipecontrols and a MI_BB) */
209 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
210 #define WA_TAIL_DWORDS 2
211 #define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS)
212 #define PREEMPT_ID 0x1
213
214 static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
215                                             struct intel_engine_cs *engine);
216 static void execlists_init_reg_state(u32 *reg_state,
217                                      struct i915_gem_context *ctx,
218                                      struct intel_engine_cs *engine,
219                                      struct intel_ring *ring);
220
221 /**
222  * intel_lr_context_descriptor_update() - calculate & cache the descriptor
223  *                                        descriptor for a pinned context
224  * @ctx: Context to work on
225  * @engine: Engine the descriptor will be used with
226  *
227  * The context descriptor encodes various attributes of a context,
228  * including its GTT address and some flags. Because it's fairly
229  * expensive to calculate, we'll just do it once and cache the result,
230  * which remains valid until the context is unpinned.
231  *
232  * This is what a descriptor looks like, from LSB to MSB::
233  *
234  *      bits  0-11:    flags, GEN8_CTX_* (cached in ctx->desc_template)
235  *      bits 12-31:    LRCA, GTT address of (the HWSP of) this context
236  *      bits 32-52:    ctx ID, a globally unique tag
237  *      bits 53-54:    mbz, reserved for use by hardware
238  *      bits 55-63:    group ID, currently unused and set to 0
239  */
240 static void
241 intel_lr_context_descriptor_update(struct i915_gem_context *ctx,
242                                    struct intel_engine_cs *engine)
243 {
244         struct intel_context *ce = &ctx->engine[engine->id];
245         u64 desc;
246
247         BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<<GEN8_CTX_ID_WIDTH));
248
249         desc = ctx->desc_template;                              /* bits  0-11 */
250         desc |= i915_ggtt_offset(ce->state) + LRC_HEADER_PAGES * PAGE_SIZE;
251                                                                 /* bits 12-31 */
252         desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT;           /* bits 32-52 */
253
254         ce->lrc_desc = desc;
255 }
256
257 static struct i915_priolist *
258 lookup_priolist(struct intel_engine_cs *engine,
259                 struct i915_priotree *pt,
260                 int prio)
261 {
262         struct intel_engine_execlists * const execlists = &engine->execlists;
263         struct i915_priolist *p;
264         struct rb_node **parent, *rb;
265         bool first = true;
266
267         if (unlikely(execlists->no_priolist))
268                 prio = I915_PRIORITY_NORMAL;
269
270 find_priolist:
271         /* most positive priority is scheduled first, equal priorities fifo */
272         rb = NULL;
273         parent = &execlists->queue.rb_node;
274         while (*parent) {
275                 rb = *parent;
276                 p = rb_entry(rb, typeof(*p), node);
277                 if (prio > p->priority) {
278                         parent = &rb->rb_left;
279                 } else if (prio < p->priority) {
280                         parent = &rb->rb_right;
281                         first = false;
282                 } else {
283                         return p;
284                 }
285         }
286
287         if (prio == I915_PRIORITY_NORMAL) {
288                 p = &execlists->default_priolist;
289         } else {
290                 p = kmem_cache_alloc(engine->i915->priorities, GFP_ATOMIC);
291                 /* Convert an allocation failure to a priority bump */
292                 if (unlikely(!p)) {
293                         prio = I915_PRIORITY_NORMAL; /* recurses just once */
294
295                         /* To maintain ordering with all rendering, after an
296                          * allocation failure we have to disable all scheduling.
297                          * Requests will then be executed in fifo, and schedule
298                          * will ensure that dependencies are emitted in fifo.
299                          * There will be still some reordering with existing
300                          * requests, so if userspace lied about their
301                          * dependencies that reordering may be visible.
302                          */
303                         execlists->no_priolist = true;
304                         goto find_priolist;
305                 }
306         }
307
308         p->priority = prio;
309         INIT_LIST_HEAD(&p->requests);
310         rb_link_node(&p->node, rb, parent);
311         rb_insert_color(&p->node, &execlists->queue);
312
313         if (first)
314                 execlists->first = &p->node;
315
316         return ptr_pack_bits(p, first, 1);
317 }
318
319 static void unwind_wa_tail(struct drm_i915_gem_request *rq)
320 {
321         rq->tail = intel_ring_wrap(rq->ring, rq->wa_tail - WA_TAIL_BYTES);
322         assert_ring_tail_valid(rq->ring, rq->tail);
323 }
324
325 static void __unwind_incomplete_requests(struct intel_engine_cs *engine)
326 {
327         struct drm_i915_gem_request *rq, *rn;
328         struct i915_priolist *uninitialized_var(p);
329         int last_prio = I915_PRIORITY_INVALID;
330
331         lockdep_assert_held(&engine->timeline->lock);
332
333         list_for_each_entry_safe_reverse(rq, rn,
334                                          &engine->timeline->requests,
335                                          link) {
336                 if (i915_gem_request_completed(rq))
337                         return;
338
339                 __i915_gem_request_unsubmit(rq);
340                 unwind_wa_tail(rq);
341
342                 GEM_BUG_ON(rq->priotree.priority == I915_PRIORITY_INVALID);
343                 if (rq->priotree.priority != last_prio) {
344                         p = lookup_priolist(engine,
345                                             &rq->priotree,
346                                             rq->priotree.priority);
347                         p = ptr_mask_bits(p, 1);
348
349                         last_prio = rq->priotree.priority;
350                 }
351
352                 list_add(&rq->priotree.link, &p->requests);
353         }
354 }
355
356 void
357 execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists)
358 {
359         struct intel_engine_cs *engine =
360                 container_of(execlists, typeof(*engine), execlists);
361
362         spin_lock_irq(&engine->timeline->lock);
363         __unwind_incomplete_requests(engine);
364         spin_unlock_irq(&engine->timeline->lock);
365 }
366
367 static inline void
368 execlists_context_status_change(struct drm_i915_gem_request *rq,
369                                 unsigned long status)
370 {
371         /*
372          * Only used when GVT-g is enabled now. When GVT-g is disabled,
373          * The compiler should eliminate this function as dead-code.
374          */
375         if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
376                 return;
377
378         atomic_notifier_call_chain(&rq->engine->context_status_notifier,
379                                    status, rq);
380 }
381
382 static inline void
383 execlists_context_schedule_in(struct drm_i915_gem_request *rq)
384 {
385         execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN);
386         intel_engine_context_in(rq->engine);
387 }
388
389 static inline void
390 execlists_context_schedule_out(struct drm_i915_gem_request *rq)
391 {
392         intel_engine_context_out(rq->engine);
393         execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT);
394 }
395
396 static void
397 execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
398 {
399         ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
400         ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
401         ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
402         ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
403 }
404
405 static u64 execlists_update_context(struct drm_i915_gem_request *rq)
406 {
407         struct intel_context *ce = &rq->ctx->engine[rq->engine->id];
408         struct i915_hw_ppgtt *ppgtt =
409                 rq->ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
410         u32 *reg_state = ce->lrc_reg_state;
411
412         reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail);
413
414         /* True 32b PPGTT with dynamic page allocation: update PDP
415          * registers and point the unallocated PDPs to scratch page.
416          * PML4 is allocated during ppgtt init, so this is not needed
417          * in 48-bit mode.
418          */
419         if (ppgtt && !i915_vm_is_48bit(&ppgtt->base))
420                 execlists_update_context_pdps(ppgtt, reg_state);
421
422         return ce->lrc_desc;
423 }
424
425 static inline void elsp_write(u64 desc, u32 __iomem *elsp)
426 {
427         writel(upper_32_bits(desc), elsp);
428         writel(lower_32_bits(desc), elsp);
429 }
430
431 static void execlists_submit_ports(struct intel_engine_cs *engine)
432 {
433         struct execlist_port *port = engine->execlists.port;
434         unsigned int n;
435
436         for (n = execlists_num_ports(&engine->execlists); n--; ) {
437                 struct drm_i915_gem_request *rq;
438                 unsigned int count;
439                 u64 desc;
440
441                 rq = port_unpack(&port[n], &count);
442                 if (rq) {
443                         GEM_BUG_ON(count > !n);
444                         if (!count++)
445                                 execlists_context_schedule_in(rq);
446                         port_set(&port[n], port_pack(rq, count));
447                         desc = execlists_update_context(rq);
448                         GEM_DEBUG_EXEC(port[n].context_id = upper_32_bits(desc));
449
450                         GEM_TRACE("%s in[%d]:  ctx=%d.%d, seqno=%x\n",
451                                   engine->name, n,
452                                   port[n].context_id, count,
453                                   rq->global_seqno);
454                 } else {
455                         GEM_BUG_ON(!n);
456                         desc = 0;
457                 }
458
459                 elsp_write(desc, engine->execlists.elsp);
460         }
461         execlists_clear_active(&engine->execlists, EXECLISTS_ACTIVE_HWACK);
462 }
463
464 static bool ctx_single_port_submission(const struct i915_gem_context *ctx)
465 {
466         return (IS_ENABLED(CONFIG_DRM_I915_GVT) &&
467                 i915_gem_context_force_single_submission(ctx));
468 }
469
470 static bool can_merge_ctx(const struct i915_gem_context *prev,
471                           const struct i915_gem_context *next)
472 {
473         if (prev != next)
474                 return false;
475
476         if (ctx_single_port_submission(prev))
477                 return false;
478
479         return true;
480 }
481
482 static void port_assign(struct execlist_port *port,
483                         struct drm_i915_gem_request *rq)
484 {
485         GEM_BUG_ON(rq == port_request(port));
486
487         if (port_isset(port))
488                 i915_gem_request_put(port_request(port));
489
490         port_set(port, port_pack(i915_gem_request_get(rq), port_count(port)));
491 }
492
493 static void inject_preempt_context(struct intel_engine_cs *engine)
494 {
495         struct intel_context *ce =
496                 &engine->i915->preempt_context->engine[engine->id];
497         unsigned int n;
498
499         GEM_BUG_ON(engine->i915->preempt_context->hw_id != PREEMPT_ID);
500         GEM_BUG_ON(!IS_ALIGNED(ce->ring->size, WA_TAIL_BYTES));
501
502         memset(ce->ring->vaddr + ce->ring->tail, 0, WA_TAIL_BYTES);
503         ce->ring->tail += WA_TAIL_BYTES;
504         ce->ring->tail &= (ce->ring->size - 1);
505         ce->lrc_reg_state[CTX_RING_TAIL+1] = ce->ring->tail;
506
507         GEM_TRACE("%s\n", engine->name);
508         for (n = execlists_num_ports(&engine->execlists); --n; )
509                 elsp_write(0, engine->execlists.elsp);
510
511         elsp_write(ce->lrc_desc, engine->execlists.elsp);
512         execlists_clear_active(&engine->execlists, EXECLISTS_ACTIVE_HWACK);
513 }
514
515 static void execlists_dequeue(struct intel_engine_cs *engine)
516 {
517         struct intel_engine_execlists * const execlists = &engine->execlists;
518         struct execlist_port *port = execlists->port;
519         const struct execlist_port * const last_port =
520                 &execlists->port[execlists->port_mask];
521         struct drm_i915_gem_request *last = port_request(port);
522         struct rb_node *rb;
523         bool submit = false;
524
525         /* Hardware submission is through 2 ports. Conceptually each port
526          * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is
527          * static for a context, and unique to each, so we only execute
528          * requests belonging to a single context from each ring. RING_HEAD
529          * is maintained by the CS in the context image, it marks the place
530          * where it got up to last time, and through RING_TAIL we tell the CS
531          * where we want to execute up to this time.
532          *
533          * In this list the requests are in order of execution. Consecutive
534          * requests from the same context are adjacent in the ringbuffer. We
535          * can combine these requests into a single RING_TAIL update:
536          *
537          *              RING_HEAD...req1...req2
538          *                                    ^- RING_TAIL
539          * since to execute req2 the CS must first execute req1.
540          *
541          * Our goal then is to point each port to the end of a consecutive
542          * sequence of requests as being the most optimal (fewest wake ups
543          * and context switches) submission.
544          */
545
546         spin_lock_irq(&engine->timeline->lock);
547         rb = execlists->first;
548         GEM_BUG_ON(rb_first(&execlists->queue) != rb);
549         if (!rb)
550                 goto unlock;
551
552         if (last) {
553                 /*
554                  * Don't resubmit or switch until all outstanding
555                  * preemptions (lite-restore) are seen. Then we
556                  * know the next preemption status we see corresponds
557                  * to this ELSP update.
558                  */
559                 GEM_BUG_ON(!port_count(&port[0]));
560                 if (port_count(&port[0]) > 1)
561                         goto unlock;
562
563                 /*
564                  * If we write to ELSP a second time before the HW has had
565                  * a chance to respond to the previous write, we can confuse
566                  * the HW and hit "undefined behaviour". After writing to ELSP,
567                  * we must then wait until we see a context-switch event from
568                  * the HW to indicate that it has had a chance to respond.
569                  */
570                 if (!execlists_is_active(execlists, EXECLISTS_ACTIVE_HWACK))
571                         goto unlock;
572
573                 if (HAS_LOGICAL_RING_PREEMPTION(engine->i915) &&
574                     rb_entry(rb, struct i915_priolist, node)->priority >
575                     max(last->priotree.priority, 0)) {
576                         /*
577                          * Switch to our empty preempt context so
578                          * the state of the GPU is known (idle).
579                          */
580                         inject_preempt_context(engine);
581                         execlists_set_active(execlists,
582                                              EXECLISTS_ACTIVE_PREEMPT);
583                         goto unlock;
584                 } else {
585                         /*
586                          * In theory, we could coalesce more requests onto
587                          * the second port (the first port is active, with
588                          * no preemptions pending). However, that means we
589                          * then have to deal with the possible lite-restore
590                          * of the second port (as we submit the ELSP, there
591                          * may be a context-switch) but also we may complete
592                          * the resubmission before the context-switch. Ergo,
593                          * coalescing onto the second port will cause a
594                          * preemption event, but we cannot predict whether
595                          * that will affect port[0] or port[1].
596                          *
597                          * If the second port is already active, we can wait
598                          * until the next context-switch before contemplating
599                          * new requests. The GPU will be busy and we should be
600                          * able to resubmit the new ELSP before it idles,
601                          * avoiding pipeline bubbles (momentary pauses where
602                          * the driver is unable to keep up the supply of new
603                          * work).
604                          */
605                         if (port_count(&port[1]))
606                                 goto unlock;
607
608                         /* WaIdleLiteRestore:bdw,skl
609                          * Apply the wa NOOPs to prevent
610                          * ring:HEAD == req:TAIL as we resubmit the
611                          * request. See gen8_emit_breadcrumb() for
612                          * where we prepare the padding after the
613                          * end of the request.
614                          */
615                         last->tail = last->wa_tail;
616                 }
617         }
618
619         do {
620                 struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
621                 struct drm_i915_gem_request *rq, *rn;
622
623                 list_for_each_entry_safe(rq, rn, &p->requests, priotree.link) {
624                         /*
625                          * Can we combine this request with the current port?
626                          * It has to be the same context/ringbuffer and not
627                          * have any exceptions (e.g. GVT saying never to
628                          * combine contexts).
629                          *
630                          * If we can combine the requests, we can execute both
631                          * by updating the RING_TAIL to point to the end of the
632                          * second request, and so we never need to tell the
633                          * hardware about the first.
634                          */
635                         if (last && !can_merge_ctx(rq->ctx, last->ctx)) {
636                                 /*
637                                  * If we are on the second port and cannot
638                                  * combine this request with the last, then we
639                                  * are done.
640                                  */
641                                 if (port == last_port) {
642                                         __list_del_many(&p->requests,
643                                                         &rq->priotree.link);
644                                         goto done;
645                                 }
646
647                                 /*
648                                  * If GVT overrides us we only ever submit
649                                  * port[0], leaving port[1] empty. Note that we
650                                  * also have to be careful that we don't queue
651                                  * the same context (even though a different
652                                  * request) to the second port.
653                                  */
654                                 if (ctx_single_port_submission(last->ctx) ||
655                                     ctx_single_port_submission(rq->ctx)) {
656                                         __list_del_many(&p->requests,
657                                                         &rq->priotree.link);
658                                         goto done;
659                                 }
660
661                                 GEM_BUG_ON(last->ctx == rq->ctx);
662
663                                 if (submit)
664                                         port_assign(port, last);
665                                 port++;
666
667                                 GEM_BUG_ON(port_isset(port));
668                         }
669
670                         INIT_LIST_HEAD(&rq->priotree.link);
671                         __i915_gem_request_submit(rq);
672                         trace_i915_gem_request_in(rq, port_index(port, execlists));
673                         last = rq;
674                         submit = true;
675                 }
676
677                 rb = rb_next(rb);
678                 rb_erase(&p->node, &execlists->queue);
679                 INIT_LIST_HEAD(&p->requests);
680                 if (p->priority != I915_PRIORITY_NORMAL)
681                         kmem_cache_free(engine->i915->priorities, p);
682         } while (rb);
683 done:
684         execlists->first = rb;
685         if (submit)
686                 port_assign(port, last);
687 unlock:
688         spin_unlock_irq(&engine->timeline->lock);
689
690         if (submit) {
691                 execlists_set_active(execlists, EXECLISTS_ACTIVE_USER);
692                 execlists_submit_ports(engine);
693         }
694 }
695
696 void
697 execlists_cancel_port_requests(struct intel_engine_execlists * const execlists)
698 {
699         struct execlist_port *port = execlists->port;
700         unsigned int num_ports = execlists_num_ports(execlists);
701
702         while (num_ports-- && port_isset(port)) {
703                 struct drm_i915_gem_request *rq = port_request(port);
704
705                 GEM_BUG_ON(!execlists->active);
706                 intel_engine_context_out(rq->engine);
707                 execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_PREEMPTED);
708                 i915_gem_request_put(rq);
709
710                 memset(port, 0, sizeof(*port));
711                 port++;
712         }
713 }
714
715 static void execlists_cancel_requests(struct intel_engine_cs *engine)
716 {
717         struct intel_engine_execlists * const execlists = &engine->execlists;
718         struct drm_i915_gem_request *rq, *rn;
719         struct rb_node *rb;
720         unsigned long flags;
721
722         GEM_TRACE("%s\n", engine->name);
723
724         spin_lock_irqsave(&engine->timeline->lock, flags);
725
726         /* Cancel the requests on the HW and clear the ELSP tracker. */
727         execlists_cancel_port_requests(execlists);
728
729         /* Mark all executing requests as skipped. */
730         list_for_each_entry(rq, &engine->timeline->requests, link) {
731                 GEM_BUG_ON(!rq->global_seqno);
732                 if (!i915_gem_request_completed(rq))
733                         dma_fence_set_error(&rq->fence, -EIO);
734         }
735
736         /* Flush the queued requests to the timeline list (for retiring). */
737         rb = execlists->first;
738         while (rb) {
739                 struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
740
741                 list_for_each_entry_safe(rq, rn, &p->requests, priotree.link) {
742                         INIT_LIST_HEAD(&rq->priotree.link);
743
744                         dma_fence_set_error(&rq->fence, -EIO);
745                         __i915_gem_request_submit(rq);
746                 }
747
748                 rb = rb_next(rb);
749                 rb_erase(&p->node, &execlists->queue);
750                 INIT_LIST_HEAD(&p->requests);
751                 if (p->priority != I915_PRIORITY_NORMAL)
752                         kmem_cache_free(engine->i915->priorities, p);
753         }
754
755         /* Remaining _unready_ requests will be nop'ed when submitted */
756
757
758         execlists->queue = RB_ROOT;
759         execlists->first = NULL;
760         GEM_BUG_ON(port_isset(execlists->port));
761
762         /*
763          * The port is checked prior to scheduling a tasklet, but
764          * just in case we have suspended the tasklet to do the
765          * wedging make sure that when it wakes, it decides there
766          * is no work to do by clearing the irq_posted bit.
767          */
768         clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
769
770         /* Mark all CS interrupts as complete */
771         execlists->active = 0;
772
773         spin_unlock_irqrestore(&engine->timeline->lock, flags);
774 }
775
776 /*
777  * Check the unread Context Status Buffers and manage the submission of new
778  * contexts to the ELSP accordingly.
779  */
780 static void execlists_submission_tasklet(unsigned long data)
781 {
782         struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
783         struct intel_engine_execlists * const execlists = &engine->execlists;
784         struct execlist_port * const port = execlists->port;
785         struct drm_i915_private *dev_priv = engine->i915;
786
787         /* We can skip acquiring intel_runtime_pm_get() here as it was taken
788          * on our behalf by the request (see i915_gem_mark_busy()) and it will
789          * not be relinquished until the device is idle (see
790          * i915_gem_idle_work_handler()). As a precaution, we make sure
791          * that all ELSP are drained i.e. we have processed the CSB,
792          * before allowing ourselves to idle and calling intel_runtime_pm_put().
793          */
794         GEM_BUG_ON(!dev_priv->gt.awake);
795
796         intel_uncore_forcewake_get(dev_priv, execlists->fw_domains);
797
798         /* Prefer doing test_and_clear_bit() as a two stage operation to avoid
799          * imposing the cost of a locked atomic transaction when submitting a
800          * new request (outside of the context-switch interrupt).
801          */
802         while (test_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted)) {
803                 /* The HWSP contains a (cacheable) mirror of the CSB */
804                 const u32 *buf =
805                         &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
806                 unsigned int head, tail;
807
808                 if (unlikely(execlists->csb_use_mmio)) {
809                         buf = (u32 * __force)
810                                 (dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
811                         execlists->csb_head = -1; /* force mmio read of CSB ptrs */
812                 }
813
814                 /* The write will be ordered by the uncached read (itself
815                  * a memory barrier), so we do not need another in the form
816                  * of a locked instruction. The race between the interrupt
817                  * handler and the split test/clear is harmless as we order
818                  * our clear before the CSB read. If the interrupt arrived
819                  * first between the test and the clear, we read the updated
820                  * CSB and clear the bit. If the interrupt arrives as we read
821                  * the CSB or later (i.e. after we had cleared the bit) the bit
822                  * is set and we do a new loop.
823                  */
824                 __clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
825                 if (unlikely(execlists->csb_head == -1)) { /* following a reset */
826                         head = readl(dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)));
827                         tail = GEN8_CSB_WRITE_PTR(head);
828                         head = GEN8_CSB_READ_PTR(head);
829                         execlists->csb_head = head;
830                 } else {
831                         const int write_idx =
832                                 intel_hws_csb_write_index(dev_priv) -
833                                 I915_HWS_CSB_BUF0_INDEX;
834
835                         head = execlists->csb_head;
836                         tail = READ_ONCE(buf[write_idx]);
837                 }
838                 GEM_TRACE("%s cs-irq head=%d [%d], tail=%d [%d]\n",
839                           engine->name,
840                           head, GEN8_CSB_READ_PTR(readl(dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)))),
841                           tail, GEN8_CSB_WRITE_PTR(readl(dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)))));
842
843                 while (head != tail) {
844                         struct drm_i915_gem_request *rq;
845                         unsigned int status;
846                         unsigned int count;
847
848                         if (++head == GEN8_CSB_ENTRIES)
849                                 head = 0;
850
851                         /* We are flying near dragons again.
852                          *
853                          * We hold a reference to the request in execlist_port[]
854                          * but no more than that. We are operating in softirq
855                          * context and so cannot hold any mutex or sleep. That
856                          * prevents us stopping the requests we are processing
857                          * in port[] from being retired simultaneously (the
858                          * breadcrumb will be complete before we see the
859                          * context-switch). As we only hold the reference to the
860                          * request, any pointer chasing underneath the request
861                          * is subject to a potential use-after-free. Thus we
862                          * store all of the bookkeeping within port[] as
863                          * required, and avoid using unguarded pointers beneath
864                          * request itself. The same applies to the atomic
865                          * status notifier.
866                          */
867
868                         status = READ_ONCE(buf[2 * head]); /* maybe mmio! */
869                         GEM_TRACE("%s csb[%d]: status=0x%08x:0x%08x, active=0x%x\n",
870                                   engine->name, head,
871                                   status, buf[2*head + 1],
872                                   execlists->active);
873
874                         if (status & (GEN8_CTX_STATUS_IDLE_ACTIVE |
875                                       GEN8_CTX_STATUS_PREEMPTED))
876                                 execlists_set_active(execlists,
877                                                      EXECLISTS_ACTIVE_HWACK);
878                         if (status & GEN8_CTX_STATUS_ACTIVE_IDLE)
879                                 execlists_clear_active(execlists,
880                                                        EXECLISTS_ACTIVE_HWACK);
881
882                         if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK))
883                                 continue;
884
885                         /* We should never get a COMPLETED | IDLE_ACTIVE! */
886                         GEM_BUG_ON(status & GEN8_CTX_STATUS_IDLE_ACTIVE);
887
888                         if (status & GEN8_CTX_STATUS_COMPLETE &&
889                             buf[2*head + 1] == PREEMPT_ID) {
890                                 GEM_TRACE("%s preempt-idle\n", engine->name);
891
892                                 execlists_cancel_port_requests(execlists);
893                                 execlists_unwind_incomplete_requests(execlists);
894
895                                 GEM_BUG_ON(!execlists_is_active(execlists,
896                                                                 EXECLISTS_ACTIVE_PREEMPT));
897                                 execlists_clear_active(execlists,
898                                                        EXECLISTS_ACTIVE_PREEMPT);
899                                 continue;
900                         }
901
902                         if (status & GEN8_CTX_STATUS_PREEMPTED &&
903                             execlists_is_active(execlists,
904                                                 EXECLISTS_ACTIVE_PREEMPT))
905                                 continue;
906
907                         GEM_BUG_ON(!execlists_is_active(execlists,
908                                                         EXECLISTS_ACTIVE_USER));
909
910                         /* Check the context/desc id for this event matches */
911                         GEM_DEBUG_BUG_ON(buf[2 * head + 1] != port->context_id);
912
913                         rq = port_unpack(port, &count);
914                         GEM_TRACE("%s out[0]: ctx=%d.%d, seqno=%x\n",
915                                   engine->name,
916                                   port->context_id, count,
917                                   rq ? rq->global_seqno : 0);
918                         GEM_BUG_ON(count == 0);
919                         if (--count == 0) {
920                                 GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED);
921                                 GEM_BUG_ON(port_isset(&port[1]) &&
922                                            !(status & GEN8_CTX_STATUS_ELEMENT_SWITCH));
923                                 GEM_BUG_ON(!i915_gem_request_completed(rq));
924                                 execlists_context_schedule_out(rq);
925                                 trace_i915_gem_request_out(rq);
926                                 i915_gem_request_put(rq);
927
928                                 execlists_port_complete(execlists, port);
929                         } else {
930                                 port_set(port, port_pack(rq, count));
931                         }
932
933                         /* After the final element, the hw should be idle */
934                         GEM_BUG_ON(port_count(port) == 0 &&
935                                    !(status & GEN8_CTX_STATUS_ACTIVE_IDLE));
936                         if (port_count(port) == 0)
937                                 execlists_clear_active(execlists,
938                                                        EXECLISTS_ACTIVE_USER);
939                 }
940
941                 if (head != execlists->csb_head) {
942                         execlists->csb_head = head;
943                         writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, head << 8),
944                                dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)));
945                 }
946         }
947
948         if (!execlists_is_active(execlists, EXECLISTS_ACTIVE_PREEMPT))
949                 execlists_dequeue(engine);
950
951         intel_uncore_forcewake_put(dev_priv, execlists->fw_domains);
952 }
953
954 static void insert_request(struct intel_engine_cs *engine,
955                            struct i915_priotree *pt,
956                            int prio)
957 {
958         struct i915_priolist *p = lookup_priolist(engine, pt, prio);
959
960         list_add_tail(&pt->link, &ptr_mask_bits(p, 1)->requests);
961         if (ptr_unmask_bits(p, 1))
962                 tasklet_hi_schedule(&engine->execlists.tasklet);
963 }
964
965 static void execlists_submit_request(struct drm_i915_gem_request *request)
966 {
967         struct intel_engine_cs *engine = request->engine;
968         unsigned long flags;
969
970         /* Will be called from irq-context when using foreign fences. */
971         spin_lock_irqsave(&engine->timeline->lock, flags);
972
973         insert_request(engine, &request->priotree, request->priotree.priority);
974
975         GEM_BUG_ON(!engine->execlists.first);
976         GEM_BUG_ON(list_empty(&request->priotree.link));
977
978         spin_unlock_irqrestore(&engine->timeline->lock, flags);
979 }
980
981 static struct drm_i915_gem_request *pt_to_request(struct i915_priotree *pt)
982 {
983         return container_of(pt, struct drm_i915_gem_request, priotree);
984 }
985
986 static struct intel_engine_cs *
987 pt_lock_engine(struct i915_priotree *pt, struct intel_engine_cs *locked)
988 {
989         struct intel_engine_cs *engine = pt_to_request(pt)->engine;
990
991         GEM_BUG_ON(!locked);
992
993         if (engine != locked) {
994                 spin_unlock(&locked->timeline->lock);
995                 spin_lock(&engine->timeline->lock);
996         }
997
998         return engine;
999 }
1000
1001 static void execlists_schedule(struct drm_i915_gem_request *request, int prio)
1002 {
1003         struct intel_engine_cs *engine;
1004         struct i915_dependency *dep, *p;
1005         struct i915_dependency stack;
1006         LIST_HEAD(dfs);
1007
1008         GEM_BUG_ON(prio == I915_PRIORITY_INVALID);
1009
1010         if (i915_gem_request_completed(request))
1011                 return;
1012
1013         if (prio <= READ_ONCE(request->priotree.priority))
1014                 return;
1015
1016         /* Need BKL in order to use the temporary link inside i915_dependency */
1017         lockdep_assert_held(&request->i915->drm.struct_mutex);
1018
1019         stack.signaler = &request->priotree;
1020         list_add(&stack.dfs_link, &dfs);
1021
1022         /* Recursively bump all dependent priorities to match the new request.
1023          *
1024          * A naive approach would be to use recursion:
1025          * static void update_priorities(struct i915_priotree *pt, prio) {
1026          *      list_for_each_entry(dep, &pt->signalers_list, signal_link)
1027          *              update_priorities(dep->signal, prio)
1028          *      insert_request(pt);
1029          * }
1030          * but that may have unlimited recursion depth and so runs a very
1031          * real risk of overunning the kernel stack. Instead, we build
1032          * a flat list of all dependencies starting with the current request.
1033          * As we walk the list of dependencies, we add all of its dependencies
1034          * to the end of the list (this may include an already visited
1035          * request) and continue to walk onwards onto the new dependencies. The
1036          * end result is a topological list of requests in reverse order, the
1037          * last element in the list is the request we must execute first.
1038          */
1039         list_for_each_entry_safe(dep, p, &dfs, dfs_link) {
1040                 struct i915_priotree *pt = dep->signaler;
1041
1042                 /* Within an engine, there can be no cycle, but we may
1043                  * refer to the same dependency chain multiple times
1044                  * (redundant dependencies are not eliminated) and across
1045                  * engines.
1046                  */
1047                 list_for_each_entry(p, &pt->signalers_list, signal_link) {
1048                         if (i915_gem_request_completed(pt_to_request(p->signaler)))
1049                                 continue;
1050
1051                         GEM_BUG_ON(p->signaler->priority < pt->priority);
1052                         if (prio > READ_ONCE(p->signaler->priority))
1053                                 list_move_tail(&p->dfs_link, &dfs);
1054                 }
1055
1056                 list_safe_reset_next(dep, p, dfs_link);
1057         }
1058
1059         /* If we didn't need to bump any existing priorities, and we haven't
1060          * yet submitted this request (i.e. there is no potential race with
1061          * execlists_submit_request()), we can set our own priority and skip
1062          * acquiring the engine locks.
1063          */
1064         if (request->priotree.priority == I915_PRIORITY_INVALID) {
1065                 GEM_BUG_ON(!list_empty(&request->priotree.link));
1066                 request->priotree.priority = prio;
1067                 if (stack.dfs_link.next == stack.dfs_link.prev)
1068                         return;
1069                 __list_del_entry(&stack.dfs_link);
1070         }
1071
1072         engine = request->engine;
1073         spin_lock_irq(&engine->timeline->lock);
1074
1075         /* Fifo and depth-first replacement ensure our deps execute before us */
1076         list_for_each_entry_safe_reverse(dep, p, &dfs, dfs_link) {
1077                 struct i915_priotree *pt = dep->signaler;
1078
1079                 INIT_LIST_HEAD(&dep->dfs_link);
1080
1081                 engine = pt_lock_engine(pt, engine);
1082
1083                 if (prio <= pt->priority)
1084                         continue;
1085
1086                 pt->priority = prio;
1087                 if (!list_empty(&pt->link)) {
1088                         __list_del_entry(&pt->link);
1089                         insert_request(engine, pt, prio);
1090                 }
1091         }
1092
1093         spin_unlock_irq(&engine->timeline->lock);
1094 }
1095
1096 static int __context_pin(struct i915_gem_context *ctx, struct i915_vma *vma)
1097 {
1098         unsigned int flags;
1099         int err;
1100
1101         /*
1102          * Clear this page out of any CPU caches for coherent swap-in/out.
1103          * We only want to do this on the first bind so that we do not stall
1104          * on an active context (which by nature is already on the GPU).
1105          */
1106         if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
1107                 err = i915_gem_object_set_to_gtt_domain(vma->obj, true);
1108                 if (err)
1109                         return err;
1110         }
1111
1112         flags = PIN_GLOBAL | PIN_HIGH;
1113         if (ctx->ggtt_offset_bias)
1114                 flags |= PIN_OFFSET_BIAS | ctx->ggtt_offset_bias;
1115
1116         return i915_vma_pin(vma, 0, GEN8_LR_CONTEXT_ALIGN, flags);
1117 }
1118
1119 static struct intel_ring *
1120 execlists_context_pin(struct intel_engine_cs *engine,
1121                       struct i915_gem_context *ctx)
1122 {
1123         struct intel_context *ce = &ctx->engine[engine->id];
1124         void *vaddr;
1125         int ret;
1126
1127         lockdep_assert_held(&ctx->i915->drm.struct_mutex);
1128
1129         if (likely(ce->pin_count++))
1130                 goto out;
1131         GEM_BUG_ON(!ce->pin_count); /* no overflow please! */
1132
1133         if (!ce->state) {
1134                 ret = execlists_context_deferred_alloc(ctx, engine);
1135                 if (ret)
1136                         goto err;
1137         }
1138         GEM_BUG_ON(!ce->state);
1139
1140         ret = __context_pin(ctx, ce->state);
1141         if (ret)
1142                 goto err;
1143
1144         vaddr = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB);
1145         if (IS_ERR(vaddr)) {
1146                 ret = PTR_ERR(vaddr);
1147                 goto unpin_vma;
1148         }
1149
1150         ret = intel_ring_pin(ce->ring, ctx->i915, ctx->ggtt_offset_bias);
1151         if (ret)
1152                 goto unpin_map;
1153
1154         intel_lr_context_descriptor_update(ctx, engine);
1155
1156         ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
1157         ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
1158                 i915_ggtt_offset(ce->ring->vma);
1159
1160         ce->state->obj->pin_global++;
1161         i915_gem_context_get(ctx);
1162 out:
1163         return ce->ring;
1164
1165 unpin_map:
1166         i915_gem_object_unpin_map(ce->state->obj);
1167 unpin_vma:
1168         __i915_vma_unpin(ce->state);
1169 err:
1170         ce->pin_count = 0;
1171         return ERR_PTR(ret);
1172 }
1173
1174 static void execlists_context_unpin(struct intel_engine_cs *engine,
1175                                     struct i915_gem_context *ctx)
1176 {
1177         struct intel_context *ce = &ctx->engine[engine->id];
1178
1179         lockdep_assert_held(&ctx->i915->drm.struct_mutex);
1180         GEM_BUG_ON(ce->pin_count == 0);
1181
1182         if (--ce->pin_count)
1183                 return;
1184
1185         intel_ring_unpin(ce->ring);
1186
1187         ce->state->obj->pin_global--;
1188         i915_gem_object_unpin_map(ce->state->obj);
1189         i915_vma_unpin(ce->state);
1190
1191         i915_gem_context_put(ctx);
1192 }
1193
1194 static int execlists_request_alloc(struct drm_i915_gem_request *request)
1195 {
1196         struct intel_engine_cs *engine = request->engine;
1197         struct intel_context *ce = &request->ctx->engine[engine->id];
1198         int ret;
1199
1200         GEM_BUG_ON(!ce->pin_count);
1201
1202         /* Flush enough space to reduce the likelihood of waiting after
1203          * we start building the request - in which case we will just
1204          * have to repeat work.
1205          */
1206         request->reserved_space += EXECLISTS_REQUEST_SIZE;
1207
1208         ret = intel_ring_wait_for_space(request->ring, request->reserved_space);
1209         if (ret)
1210                 return ret;
1211
1212         /* Note that after this point, we have committed to using
1213          * this request as it is being used to both track the
1214          * state of engine initialisation and liveness of the
1215          * golden renderstate above. Think twice before you try
1216          * to cancel/unwind this request now.
1217          */
1218
1219         request->reserved_space -= EXECLISTS_REQUEST_SIZE;
1220         return 0;
1221 }
1222
1223 /*
1224  * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1225  * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1226  * but there is a slight complication as this is applied in WA batch where the
1227  * values are only initialized once so we cannot take register value at the
1228  * beginning and reuse it further; hence we save its value to memory, upload a
1229  * constant value with bit21 set and then we restore it back with the saved value.
1230  * To simplify the WA, a constant value is formed by using the default value
1231  * of this register. This shouldn't be a problem because we are only modifying
1232  * it for a short period and this batch in non-premptible. We can ofcourse
1233  * use additional instructions that read the actual value of the register
1234  * at that time and set our bit of interest but it makes the WA complicated.
1235  *
1236  * This WA is also required for Gen9 so extracting as a function avoids
1237  * code duplication.
1238  */
1239 static u32 *
1240 gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch)
1241 {
1242         *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
1243         *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1244         *batch++ = i915_ggtt_offset(engine->scratch) + 256;
1245         *batch++ = 0;
1246
1247         *batch++ = MI_LOAD_REGISTER_IMM(1);
1248         *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1249         *batch++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES;
1250
1251         batch = gen8_emit_pipe_control(batch,
1252                                        PIPE_CONTROL_CS_STALL |
1253                                        PIPE_CONTROL_DC_FLUSH_ENABLE,
1254                                        0);
1255
1256         *batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
1257         *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1258         *batch++ = i915_ggtt_offset(engine->scratch) + 256;
1259         *batch++ = 0;
1260
1261         return batch;
1262 }
1263
1264 /*
1265  * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1266  * initialized at the beginning and shared across all contexts but this field
1267  * helps us to have multiple batches at different offsets and select them based
1268  * on a criteria. At the moment this batch always start at the beginning of the page
1269  * and at this point we don't have multiple wa_ctx batch buffers.
1270  *
1271  * The number of WA applied are not known at the beginning; we use this field
1272  * to return the no of DWORDS written.
1273  *
1274  * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1275  * so it adds NOOPs as padding to make it cacheline aligned.
1276  * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1277  * makes a complete batch buffer.
1278  */
1279 static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1280 {
1281         /* WaDisableCtxRestoreArbitration:bdw,chv */
1282         *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1283
1284         /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1285         if (IS_BROADWELL(engine->i915))
1286                 batch = gen8_emit_flush_coherentl3_wa(engine, batch);
1287
1288         /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1289         /* Actual scratch location is at 128 bytes offset */
1290         batch = gen8_emit_pipe_control(batch,
1291                                        PIPE_CONTROL_FLUSH_L3 |
1292                                        PIPE_CONTROL_GLOBAL_GTT_IVB |
1293                                        PIPE_CONTROL_CS_STALL |
1294                                        PIPE_CONTROL_QW_WRITE,
1295                                        i915_ggtt_offset(engine->scratch) +
1296                                        2 * CACHELINE_BYTES);
1297
1298         *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1299
1300         /* Pad to end of cacheline */
1301         while ((unsigned long)batch % CACHELINE_BYTES)
1302                 *batch++ = MI_NOOP;
1303
1304         /*
1305          * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1306          * execution depends on the length specified in terms of cache lines
1307          * in the register CTX_RCS_INDIRECT_CTX
1308          */
1309
1310         return batch;
1311 }
1312
1313 static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1314 {
1315         *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1316
1317         /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */
1318         batch = gen8_emit_flush_coherentl3_wa(engine, batch);
1319
1320         /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */
1321         *batch++ = MI_LOAD_REGISTER_IMM(1);
1322         *batch++ = i915_mmio_reg_offset(COMMON_SLICE_CHICKEN2);
1323         *batch++ = _MASKED_BIT_DISABLE(
1324                         GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE);
1325         *batch++ = MI_NOOP;
1326
1327         /* WaClearSlmSpaceAtContextSwitch:kbl */
1328         /* Actual scratch location is at 128 bytes offset */
1329         if (IS_KBL_REVID(engine->i915, 0, KBL_REVID_A0)) {
1330                 batch = gen8_emit_pipe_control(batch,
1331                                                PIPE_CONTROL_FLUSH_L3 |
1332                                                PIPE_CONTROL_GLOBAL_GTT_IVB |
1333                                                PIPE_CONTROL_CS_STALL |
1334                                                PIPE_CONTROL_QW_WRITE,
1335                                                i915_ggtt_offset(engine->scratch)
1336                                                + 2 * CACHELINE_BYTES);
1337         }
1338
1339         /* WaMediaPoolStateCmdInWABB:bxt,glk */
1340         if (HAS_POOLED_EU(engine->i915)) {
1341                 /*
1342                  * EU pool configuration is setup along with golden context
1343                  * during context initialization. This value depends on
1344                  * device type (2x6 or 3x6) and needs to be updated based
1345                  * on which subslice is disabled especially for 2x6
1346                  * devices, however it is safe to load default
1347                  * configuration of 3x6 device instead of masking off
1348                  * corresponding bits because HW ignores bits of a disabled
1349                  * subslice and drops down to appropriate config. Please
1350                  * see render_state_setup() in i915_gem_render_state.c for
1351                  * possible configurations, to avoid duplication they are
1352                  * not shown here again.
1353                  */
1354                 *batch++ = GEN9_MEDIA_POOL_STATE;
1355                 *batch++ = GEN9_MEDIA_POOL_ENABLE;
1356                 *batch++ = 0x00777000;
1357                 *batch++ = 0;
1358                 *batch++ = 0;
1359                 *batch++ = 0;
1360         }
1361
1362         *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1363
1364         /* Pad to end of cacheline */
1365         while ((unsigned long)batch % CACHELINE_BYTES)
1366                 *batch++ = MI_NOOP;
1367
1368         return batch;
1369 }
1370
1371 #define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE)
1372
1373 static int lrc_setup_wa_ctx(struct intel_engine_cs *engine)
1374 {
1375         struct drm_i915_gem_object *obj;
1376         struct i915_vma *vma;
1377         int err;
1378
1379         obj = i915_gem_object_create(engine->i915, CTX_WA_BB_OBJ_SIZE);
1380         if (IS_ERR(obj))
1381                 return PTR_ERR(obj);
1382
1383         vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL);
1384         if (IS_ERR(vma)) {
1385                 err = PTR_ERR(vma);
1386                 goto err;
1387         }
1388
1389         err = i915_vma_pin(vma, 0, PAGE_SIZE, PIN_GLOBAL | PIN_HIGH);
1390         if (err)
1391                 goto err;
1392
1393         engine->wa_ctx.vma = vma;
1394         return 0;
1395
1396 err:
1397         i915_gem_object_put(obj);
1398         return err;
1399 }
1400
1401 static void lrc_destroy_wa_ctx(struct intel_engine_cs *engine)
1402 {
1403         i915_vma_unpin_and_release(&engine->wa_ctx.vma);
1404 }
1405
1406 typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch);
1407
1408 static int intel_init_workaround_bb(struct intel_engine_cs *engine)
1409 {
1410         struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
1411         struct i915_wa_ctx_bb *wa_bb[2] = { &wa_ctx->indirect_ctx,
1412                                             &wa_ctx->per_ctx };
1413         wa_bb_func_t wa_bb_fn[2];
1414         struct page *page;
1415         void *batch, *batch_ptr;
1416         unsigned int i;
1417         int ret;
1418
1419         if (WARN_ON(engine->id != RCS || !engine->scratch))
1420                 return -EINVAL;
1421
1422         switch (INTEL_GEN(engine->i915)) {
1423         case 10:
1424                 return 0;
1425         case 9:
1426                 wa_bb_fn[0] = gen9_init_indirectctx_bb;
1427                 wa_bb_fn[1] = NULL;
1428                 break;
1429         case 8:
1430                 wa_bb_fn[0] = gen8_init_indirectctx_bb;
1431                 wa_bb_fn[1] = NULL;
1432                 break;
1433         default:
1434                 MISSING_CASE(INTEL_GEN(engine->i915));
1435                 return 0;
1436         }
1437
1438         ret = lrc_setup_wa_ctx(engine);
1439         if (ret) {
1440                 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
1441                 return ret;
1442         }
1443
1444         page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0);
1445         batch = batch_ptr = kmap_atomic(page);
1446
1447         /*
1448          * Emit the two workaround batch buffers, recording the offset from the
1449          * start of the workaround batch buffer object for each and their
1450          * respective sizes.
1451          */
1452         for (i = 0; i < ARRAY_SIZE(wa_bb_fn); i++) {
1453                 wa_bb[i]->offset = batch_ptr - batch;
1454                 if (WARN_ON(!IS_ALIGNED(wa_bb[i]->offset, CACHELINE_BYTES))) {
1455                         ret = -EINVAL;
1456                         break;
1457                 }
1458                 if (wa_bb_fn[i])
1459                         batch_ptr = wa_bb_fn[i](engine, batch_ptr);
1460                 wa_bb[i]->size = batch_ptr - (batch + wa_bb[i]->offset);
1461         }
1462
1463         BUG_ON(batch_ptr - batch > CTX_WA_BB_OBJ_SIZE);
1464
1465         kunmap_atomic(batch);
1466         if (ret)
1467                 lrc_destroy_wa_ctx(engine);
1468
1469         return ret;
1470 }
1471
1472 static u8 gtiir[] = {
1473         [RCS] = 0,
1474         [BCS] = 0,
1475         [VCS] = 1,
1476         [VCS2] = 1,
1477         [VECS] = 3,
1478 };
1479
1480 static int gen8_init_common_ring(struct intel_engine_cs *engine)
1481 {
1482         struct drm_i915_private *dev_priv = engine->i915;
1483         struct intel_engine_execlists * const execlists = &engine->execlists;
1484         int ret;
1485
1486         ret = intel_mocs_init_engine(engine);
1487         if (ret)
1488                 return ret;
1489
1490         intel_engine_reset_breadcrumbs(engine);
1491         intel_engine_init_hangcheck(engine);
1492
1493         I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
1494         I915_WRITE(RING_MODE_GEN7(engine),
1495                    _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1496         I915_WRITE(RING_HWS_PGA(engine->mmio_base),
1497                    engine->status_page.ggtt_offset);
1498         POSTING_READ(RING_HWS_PGA(engine->mmio_base));
1499
1500         DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name);
1501
1502         GEM_BUG_ON(engine->id >= ARRAY_SIZE(gtiir));
1503
1504         /*
1505          * Clear any pending interrupt state.
1506          *
1507          * We do it twice out of paranoia that some of the IIR are double
1508          * buffered, and if we only reset it once there may still be
1509          * an interrupt pending.
1510          */
1511         I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]),
1512                    GT_CONTEXT_SWITCH_INTERRUPT << engine->irq_shift);
1513         I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]),
1514                    GT_CONTEXT_SWITCH_INTERRUPT << engine->irq_shift);
1515         clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
1516         execlists->csb_head = -1;
1517         execlists->active = 0;
1518
1519         execlists->elsp =
1520                 dev_priv->regs + i915_mmio_reg_offset(RING_ELSP(engine));
1521
1522         /* After a GPU reset, we may have requests to replay */
1523         if (execlists->first)
1524                 tasklet_schedule(&execlists->tasklet);
1525
1526         return 0;
1527 }
1528
1529 static int gen8_init_render_ring(struct intel_engine_cs *engine)
1530 {
1531         struct drm_i915_private *dev_priv = engine->i915;
1532         int ret;
1533
1534         ret = gen8_init_common_ring(engine);
1535         if (ret)
1536                 return ret;
1537
1538         /* We need to disable the AsyncFlip performance optimisations in order
1539          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1540          * programmed to '1' on all products.
1541          *
1542          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1543          */
1544         I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1545
1546         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1547
1548         return init_workarounds_ring(engine);
1549 }
1550
1551 static int gen9_init_render_ring(struct intel_engine_cs *engine)
1552 {
1553         int ret;
1554
1555         ret = gen8_init_common_ring(engine);
1556         if (ret)
1557                 return ret;
1558
1559         return init_workarounds_ring(engine);
1560 }
1561
1562 static void reset_common_ring(struct intel_engine_cs *engine,
1563                               struct drm_i915_gem_request *request)
1564 {
1565         struct intel_engine_execlists * const execlists = &engine->execlists;
1566         struct intel_context *ce;
1567         unsigned long flags;
1568
1569         GEM_TRACE("%s seqno=%x\n",
1570                   engine->name, request ? request->global_seqno : 0);
1571         spin_lock_irqsave(&engine->timeline->lock, flags);
1572
1573         /*
1574          * Catch up with any missed context-switch interrupts.
1575          *
1576          * Ideally we would just read the remaining CSB entries now that we
1577          * know the gpu is idle. However, the CSB registers are sometimes^W
1578          * often trashed across a GPU reset! Instead we have to rely on
1579          * guessing the missed context-switch events by looking at what
1580          * requests were completed.
1581          */
1582         execlists_cancel_port_requests(execlists);
1583
1584         /* Push back any incomplete requests for replay after the reset. */
1585         __unwind_incomplete_requests(engine);
1586
1587         spin_unlock_irqrestore(&engine->timeline->lock, flags);
1588
1589         /* If the request was innocent, we leave the request in the ELSP
1590          * and will try to replay it on restarting. The context image may
1591          * have been corrupted by the reset, in which case we may have
1592          * to service a new GPU hang, but more likely we can continue on
1593          * without impact.
1594          *
1595          * If the request was guilty, we presume the context is corrupt
1596          * and have to at least restore the RING register in the context
1597          * image back to the expected values to skip over the guilty request.
1598          */
1599         if (!request || request->fence.error != -EIO)
1600                 return;
1601
1602         /* We want a simple context + ring to execute the breadcrumb update.
1603          * We cannot rely on the context being intact across the GPU hang,
1604          * so clear it and rebuild just what we need for the breadcrumb.
1605          * All pending requests for this context will be zapped, and any
1606          * future request will be after userspace has had the opportunity
1607          * to recreate its own state.
1608          */
1609         ce = &request->ctx->engine[engine->id];
1610         execlists_init_reg_state(ce->lrc_reg_state,
1611                                  request->ctx, engine, ce->ring);
1612
1613         /* Move the RING_HEAD onto the breadcrumb, past the hanging batch */
1614         ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
1615                 i915_ggtt_offset(ce->ring->vma);
1616         ce->lrc_reg_state[CTX_RING_HEAD+1] = request->postfix;
1617
1618         request->ring->head = request->postfix;
1619         intel_ring_update_space(request->ring);
1620
1621         /* Reset WaIdleLiteRestore:bdw,skl as well */
1622         unwind_wa_tail(request);
1623 }
1624
1625 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
1626 {
1627         struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt;
1628         struct intel_engine_cs *engine = req->engine;
1629         const int num_lri_cmds = GEN8_3LVL_PDPES * 2;
1630         u32 *cs;
1631         int i;
1632
1633         cs = intel_ring_begin(req, num_lri_cmds * 2 + 2);
1634         if (IS_ERR(cs))
1635                 return PTR_ERR(cs);
1636
1637         *cs++ = MI_LOAD_REGISTER_IMM(num_lri_cmds);
1638         for (i = GEN8_3LVL_PDPES - 1; i >= 0; i--) {
1639                 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
1640
1641                 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i));
1642                 *cs++ = upper_32_bits(pd_daddr);
1643                 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i));
1644                 *cs++ = lower_32_bits(pd_daddr);
1645         }
1646
1647         *cs++ = MI_NOOP;
1648         intel_ring_advance(req, cs);
1649
1650         return 0;
1651 }
1652
1653 static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
1654                               u64 offset, u32 len,
1655                               const unsigned int flags)
1656 {
1657         u32 *cs;
1658         int ret;
1659
1660         /* Don't rely in hw updating PDPs, specially in lite-restore.
1661          * Ideally, we should set Force PD Restore in ctx descriptor,
1662          * but we can't. Force Restore would be a second option, but
1663          * it is unsafe in case of lite-restore (because the ctx is
1664          * not idle). PML4 is allocated during ppgtt init so this is
1665          * not needed in 48-bit.*/
1666         if (req->ctx->ppgtt &&
1667             (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings) &&
1668             !i915_vm_is_48bit(&req->ctx->ppgtt->base) &&
1669             !intel_vgpu_active(req->i915)) {
1670                 ret = intel_logical_ring_emit_pdps(req);
1671                 if (ret)
1672                         return ret;
1673
1674                 req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine);
1675         }
1676
1677         cs = intel_ring_begin(req, 4);
1678         if (IS_ERR(cs))
1679                 return PTR_ERR(cs);
1680
1681         /*
1682          * WaDisableCtxRestoreArbitration:bdw,chv
1683          *
1684          * We don't need to perform MI_ARB_ENABLE as often as we do (in
1685          * particular all the gen that do not need the w/a at all!), if we
1686          * took care to make sure that on every switch into this context
1687          * (both ordinary and for preemption) that arbitrartion was enabled
1688          * we would be fine. However, there doesn't seem to be a downside to
1689          * being paranoid and making sure it is set before each batch and
1690          * every context-switch.
1691          *
1692          * Note that if we fail to enable arbitration before the request
1693          * is complete, then we do not see the context-switch interrupt and
1694          * the engine hangs (with RING_HEAD == RING_TAIL).
1695          *
1696          * That satisfies both the GPGPU w/a and our heavy-handed paranoia.
1697          */
1698         *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1699
1700         /* FIXME(BDW): Address space and security selectors. */
1701         *cs++ = MI_BATCH_BUFFER_START_GEN8 |
1702                 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8)) |
1703                 (flags & I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0);
1704         *cs++ = lower_32_bits(offset);
1705         *cs++ = upper_32_bits(offset);
1706         intel_ring_advance(req, cs);
1707
1708         return 0;
1709 }
1710
1711 static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine)
1712 {
1713         struct drm_i915_private *dev_priv = engine->i915;
1714         I915_WRITE_IMR(engine,
1715                        ~(engine->irq_enable_mask | engine->irq_keep_mask));
1716         POSTING_READ_FW(RING_IMR(engine->mmio_base));
1717 }
1718
1719 static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine)
1720 {
1721         struct drm_i915_private *dev_priv = engine->i915;
1722         I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
1723 }
1724
1725 static int gen8_emit_flush(struct drm_i915_gem_request *request, u32 mode)
1726 {
1727         u32 cmd, *cs;
1728
1729         cs = intel_ring_begin(request, 4);
1730         if (IS_ERR(cs))
1731                 return PTR_ERR(cs);
1732
1733         cmd = MI_FLUSH_DW + 1;
1734
1735         /* We always require a command barrier so that subsequent
1736          * commands, such as breadcrumb interrupts, are strictly ordered
1737          * wrt the contents of the write cache being flushed to memory
1738          * (and thus being coherent from the CPU).
1739          */
1740         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1741
1742         if (mode & EMIT_INVALIDATE) {
1743                 cmd |= MI_INVALIDATE_TLB;
1744                 if (request->engine->id == VCS)
1745                         cmd |= MI_INVALIDATE_BSD;
1746         }
1747
1748         *cs++ = cmd;
1749         *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
1750         *cs++ = 0; /* upper addr */
1751         *cs++ = 0; /* value */
1752         intel_ring_advance(request, cs);
1753
1754         return 0;
1755 }
1756
1757 static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
1758                                   u32 mode)
1759 {
1760         struct intel_engine_cs *engine = request->engine;
1761         u32 scratch_addr =
1762                 i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES;
1763         bool vf_flush_wa = false, dc_flush_wa = false;
1764         u32 *cs, flags = 0;
1765         int len;
1766
1767         flags |= PIPE_CONTROL_CS_STALL;
1768
1769         if (mode & EMIT_FLUSH) {
1770                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1771                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1772                 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
1773                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
1774         }
1775
1776         if (mode & EMIT_INVALIDATE) {
1777                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1778                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1779                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1780                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1781                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1782                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1783                 flags |= PIPE_CONTROL_QW_WRITE;
1784                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1785
1786                 /*
1787                  * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
1788                  * pipe control.
1789                  */
1790                 if (IS_GEN9(request->i915))
1791                         vf_flush_wa = true;
1792
1793                 /* WaForGAMHang:kbl */
1794                 if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0))
1795                         dc_flush_wa = true;
1796         }
1797
1798         len = 6;
1799
1800         if (vf_flush_wa)
1801                 len += 6;
1802
1803         if (dc_flush_wa)
1804                 len += 12;
1805
1806         cs = intel_ring_begin(request, len);
1807         if (IS_ERR(cs))
1808                 return PTR_ERR(cs);
1809
1810         if (vf_flush_wa)
1811                 cs = gen8_emit_pipe_control(cs, 0, 0);
1812
1813         if (dc_flush_wa)
1814                 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE,
1815                                             0);
1816
1817         cs = gen8_emit_pipe_control(cs, flags, scratch_addr);
1818
1819         if (dc_flush_wa)
1820                 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_CS_STALL, 0);
1821
1822         intel_ring_advance(request, cs);
1823
1824         return 0;
1825 }
1826
1827 /*
1828  * Reserve space for 2 NOOPs at the end of each request to be
1829  * used as a workaround for not being allowed to do lite
1830  * restore with HEAD==TAIL (WaIdleLiteRestore).
1831  */
1832 static void gen8_emit_wa_tail(struct drm_i915_gem_request *request, u32 *cs)
1833 {
1834         /* Ensure there's always at least one preemption point per-request. */
1835         *cs++ = MI_ARB_CHECK;
1836         *cs++ = MI_NOOP;
1837         request->wa_tail = intel_ring_offset(request, cs);
1838 }
1839
1840 static void gen8_emit_breadcrumb(struct drm_i915_gem_request *request, u32 *cs)
1841 {
1842         /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
1843         BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5));
1844
1845         cs = gen8_emit_ggtt_write(cs, request->global_seqno,
1846                                   intel_hws_seqno_address(request->engine));
1847         *cs++ = MI_USER_INTERRUPT;
1848         *cs++ = MI_NOOP;
1849         request->tail = intel_ring_offset(request, cs);
1850         assert_ring_tail_valid(request->ring, request->tail);
1851
1852         gen8_emit_wa_tail(request, cs);
1853 }
1854 static const int gen8_emit_breadcrumb_sz = 6 + WA_TAIL_DWORDS;
1855
1856 static void gen8_emit_breadcrumb_rcs(struct drm_i915_gem_request *request,
1857                                         u32 *cs)
1858 {
1859         /* We're using qword write, seqno should be aligned to 8 bytes. */
1860         BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1);
1861
1862         cs = gen8_emit_ggtt_write_rcs(cs, request->global_seqno,
1863                                       intel_hws_seqno_address(request->engine));
1864         *cs++ = MI_USER_INTERRUPT;
1865         *cs++ = MI_NOOP;
1866         request->tail = intel_ring_offset(request, cs);
1867         assert_ring_tail_valid(request->ring, request->tail);
1868
1869         gen8_emit_wa_tail(request, cs);
1870 }
1871 static const int gen8_emit_breadcrumb_rcs_sz = 8 + WA_TAIL_DWORDS;
1872
1873 static int gen8_init_rcs_context(struct drm_i915_gem_request *req)
1874 {
1875         int ret;
1876
1877         ret = intel_ring_workarounds_emit(req);
1878         if (ret)
1879                 return ret;
1880
1881         ret = intel_rcs_context_init_mocs(req);
1882         /*
1883          * Failing to program the MOCS is non-fatal.The system will not
1884          * run at peak performance. So generate an error and carry on.
1885          */
1886         if (ret)
1887                 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1888
1889         return i915_gem_render_state_emit(req);
1890 }
1891
1892 /**
1893  * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1894  * @engine: Engine Command Streamer.
1895  */
1896 void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
1897 {
1898         struct drm_i915_private *dev_priv;
1899
1900         /*
1901          * Tasklet cannot be active at this point due intel_mark_active/idle
1902          * so this is just for documentation.
1903          */
1904         if (WARN_ON(test_bit(TASKLET_STATE_SCHED,
1905                              &engine->execlists.tasklet.state)))
1906                 tasklet_kill(&engine->execlists.tasklet);
1907
1908         dev_priv = engine->i915;
1909
1910         if (engine->buffer) {
1911                 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
1912         }
1913
1914         if (engine->cleanup)
1915                 engine->cleanup(engine);
1916
1917         intel_engine_cleanup_common(engine);
1918
1919         lrc_destroy_wa_ctx(engine);
1920         engine->i915 = NULL;
1921         dev_priv->engine[engine->id] = NULL;
1922         kfree(engine);
1923 }
1924
1925 static void execlists_set_default_submission(struct intel_engine_cs *engine)
1926 {
1927         engine->submit_request = execlists_submit_request;
1928         engine->cancel_requests = execlists_cancel_requests;
1929         engine->schedule = execlists_schedule;
1930         engine->execlists.tasklet.func = execlists_submission_tasklet;
1931
1932         engine->park = NULL;
1933         engine->unpark = NULL;
1934
1935         engine->flags |= I915_ENGINE_SUPPORTS_STATS;
1936 }
1937
1938 static void
1939 logical_ring_default_vfuncs(struct intel_engine_cs *engine)
1940 {
1941         /* Default vfuncs which can be overriden by each engine. */
1942         engine->init_hw = gen8_init_common_ring;
1943         engine->reset_hw = reset_common_ring;
1944
1945         engine->context_pin = execlists_context_pin;
1946         engine->context_unpin = execlists_context_unpin;
1947
1948         engine->request_alloc = execlists_request_alloc;
1949
1950         engine->emit_flush = gen8_emit_flush;
1951         engine->emit_breadcrumb = gen8_emit_breadcrumb;
1952         engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_sz;
1953
1954         engine->set_default_submission = execlists_set_default_submission;
1955
1956         engine->irq_enable = gen8_logical_ring_enable_irq;
1957         engine->irq_disable = gen8_logical_ring_disable_irq;
1958         engine->emit_bb_start = gen8_emit_bb_start;
1959 }
1960
1961 static inline void
1962 logical_ring_default_irqs(struct intel_engine_cs *engine)
1963 {
1964         unsigned shift = engine->irq_shift;
1965         engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
1966         engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
1967 }
1968
1969 static void
1970 logical_ring_setup(struct intel_engine_cs *engine)
1971 {
1972         struct drm_i915_private *dev_priv = engine->i915;
1973         enum forcewake_domains fw_domains;
1974
1975         intel_engine_setup_common(engine);
1976
1977         /* Intentionally left blank. */
1978         engine->buffer = NULL;
1979
1980         fw_domains = intel_uncore_forcewake_for_reg(dev_priv,
1981                                                     RING_ELSP(engine),
1982                                                     FW_REG_WRITE);
1983
1984         fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
1985                                                      RING_CONTEXT_STATUS_PTR(engine),
1986                                                      FW_REG_READ | FW_REG_WRITE);
1987
1988         fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
1989                                                      RING_CONTEXT_STATUS_BUF_BASE(engine),
1990                                                      FW_REG_READ);
1991
1992         engine->execlists.fw_domains = fw_domains;
1993
1994         tasklet_init(&engine->execlists.tasklet,
1995                      execlists_submission_tasklet, (unsigned long)engine);
1996
1997         logical_ring_default_vfuncs(engine);
1998         logical_ring_default_irqs(engine);
1999 }
2000
2001 static int logical_ring_init(struct intel_engine_cs *engine)
2002 {
2003         int ret;
2004
2005         ret = intel_engine_init_common(engine);
2006         if (ret)
2007                 goto error;
2008
2009         return 0;
2010
2011 error:
2012         intel_logical_ring_cleanup(engine);
2013         return ret;
2014 }
2015
2016 int logical_render_ring_init(struct intel_engine_cs *engine)
2017 {
2018         struct drm_i915_private *dev_priv = engine->i915;
2019         int ret;
2020
2021         logical_ring_setup(engine);
2022
2023         if (HAS_L3_DPF(dev_priv))
2024                 engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2025
2026         /* Override some for render ring. */
2027         if (INTEL_GEN(dev_priv) >= 9)
2028                 engine->init_hw = gen9_init_render_ring;
2029         else
2030                 engine->init_hw = gen8_init_render_ring;
2031         engine->init_context = gen8_init_rcs_context;
2032         engine->emit_flush = gen8_emit_flush_render;
2033         engine->emit_breadcrumb = gen8_emit_breadcrumb_rcs;
2034         engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_rcs_sz;
2035
2036         ret = intel_engine_create_scratch(engine, PAGE_SIZE);
2037         if (ret)
2038                 return ret;
2039
2040         ret = intel_init_workaround_bb(engine);
2041         if (ret) {
2042                 /*
2043                  * We continue even if we fail to initialize WA batch
2044                  * because we only expect rare glitches but nothing
2045                  * critical to prevent us from using GPU
2046                  */
2047                 DRM_ERROR("WA batch buffer initialization failed: %d\n",
2048                           ret);
2049         }
2050
2051         return logical_ring_init(engine);
2052 }
2053
2054 int logical_xcs_ring_init(struct intel_engine_cs *engine)
2055 {
2056         logical_ring_setup(engine);
2057
2058         return logical_ring_init(engine);
2059 }
2060
2061 static u32
2062 make_rpcs(struct drm_i915_private *dev_priv)
2063 {
2064         u32 rpcs = 0;
2065
2066         /*
2067          * No explicit RPCS request is needed to ensure full
2068          * slice/subslice/EU enablement prior to Gen9.
2069         */
2070         if (INTEL_GEN(dev_priv) < 9)
2071                 return 0;
2072
2073         /*
2074          * Starting in Gen9, render power gating can leave
2075          * slice/subslice/EU in a partially enabled state. We
2076          * must make an explicit request through RPCS for full
2077          * enablement.
2078         */
2079         if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) {
2080                 rpcs |= GEN8_RPCS_S_CNT_ENABLE;
2081                 rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) <<
2082                         GEN8_RPCS_S_CNT_SHIFT;
2083                 rpcs |= GEN8_RPCS_ENABLE;
2084         }
2085
2086         if (INTEL_INFO(dev_priv)->sseu.has_subslice_pg) {
2087                 rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
2088                 rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask) <<
2089                         GEN8_RPCS_SS_CNT_SHIFT;
2090                 rpcs |= GEN8_RPCS_ENABLE;
2091         }
2092
2093         if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) {
2094                 rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
2095                         GEN8_RPCS_EU_MIN_SHIFT;
2096                 rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
2097                         GEN8_RPCS_EU_MAX_SHIFT;
2098                 rpcs |= GEN8_RPCS_ENABLE;
2099         }
2100
2101         return rpcs;
2102 }
2103
2104 static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
2105 {
2106         u32 indirect_ctx_offset;
2107
2108         switch (INTEL_GEN(engine->i915)) {
2109         default:
2110                 MISSING_CASE(INTEL_GEN(engine->i915));
2111                 /* fall through */
2112         case 10:
2113                 indirect_ctx_offset =
2114                         GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2115                 break;
2116         case 9:
2117                 indirect_ctx_offset =
2118                         GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2119                 break;
2120         case 8:
2121                 indirect_ctx_offset =
2122                         GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2123                 break;
2124         }
2125
2126         return indirect_ctx_offset;
2127 }
2128
2129 static void execlists_init_reg_state(u32 *regs,
2130                                      struct i915_gem_context *ctx,
2131                                      struct intel_engine_cs *engine,
2132                                      struct intel_ring *ring)
2133 {
2134         struct drm_i915_private *dev_priv = engine->i915;
2135         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: dev_priv->mm.aliasing_ppgtt;
2136         u32 base = engine->mmio_base;
2137         bool rcs = engine->id == RCS;
2138
2139         /* A context is actually a big batch buffer with several
2140          * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The
2141          * values we are setting here are only for the first context restore:
2142          * on a subsequent save, the GPU will recreate this batchbuffer with new
2143          * values (including all the missing MI_LOAD_REGISTER_IMM commands that
2144          * we are not initializing here).
2145          */
2146         regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) |
2147                                  MI_LRI_FORCE_POSTED;
2148
2149         CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(engine),
2150                 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
2151                                    (HAS_RESOURCE_STREAMER(dev_priv) ?
2152                                    CTX_CTRL_RS_CTX_ENABLE : 0)));
2153         CTX_REG(regs, CTX_RING_HEAD, RING_HEAD(base), 0);
2154         CTX_REG(regs, CTX_RING_TAIL, RING_TAIL(base), 0);
2155         CTX_REG(regs, CTX_RING_BUFFER_START, RING_START(base), 0);
2156         CTX_REG(regs, CTX_RING_BUFFER_CONTROL, RING_CTL(base),
2157                 RING_CTL_SIZE(ring->size) | RING_VALID);
2158         CTX_REG(regs, CTX_BB_HEAD_U, RING_BBADDR_UDW(base), 0);
2159         CTX_REG(regs, CTX_BB_HEAD_L, RING_BBADDR(base), 0);
2160         CTX_REG(regs, CTX_BB_STATE, RING_BBSTATE(base), RING_BB_PPGTT);
2161         CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0);
2162         CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0);
2163         CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0);
2164         if (rcs) {
2165                 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
2166
2167                 CTX_REG(regs, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(base), 0);
2168                 CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET,
2169                         RING_INDIRECT_CTX_OFFSET(base), 0);
2170                 if (wa_ctx->indirect_ctx.size) {
2171                         u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
2172
2173                         regs[CTX_RCS_INDIRECT_CTX + 1] =
2174                                 (ggtt_offset + wa_ctx->indirect_ctx.offset) |
2175                                 (wa_ctx->indirect_ctx.size / CACHELINE_BYTES);
2176
2177                         regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] =
2178                                 intel_lr_indirect_ctx_offset(engine) << 6;
2179                 }
2180
2181                 CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0);
2182                 if (wa_ctx->per_ctx.size) {
2183                         u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
2184
2185                         regs[CTX_BB_PER_CTX_PTR + 1] =
2186                                 (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01;
2187                 }
2188         }
2189
2190         regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
2191
2192         CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0);
2193         /* PDP values well be assigned later if needed */
2194         CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3), 0);
2195         CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3), 0);
2196         CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2), 0);
2197         CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2), 0);
2198         CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1), 0);
2199         CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1), 0);
2200         CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
2201         CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
2202
2203         if (ppgtt && i915_vm_is_48bit(&ppgtt->base)) {
2204                 /* 64b PPGTT (48bit canonical)
2205                  * PDP0_DESCRIPTOR contains the base address to PML4 and
2206                  * other PDP Descriptors are ignored.
2207                  */
2208                 ASSIGN_CTX_PML4(ppgtt, regs);
2209         }
2210
2211         if (rcs) {
2212                 regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
2213                 CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
2214                         make_rpcs(dev_priv));
2215
2216                 i915_oa_init_reg_state(engine, ctx, regs);
2217         }
2218 }
2219
2220 static int
2221 populate_lr_context(struct i915_gem_context *ctx,
2222                     struct drm_i915_gem_object *ctx_obj,
2223                     struct intel_engine_cs *engine,
2224                     struct intel_ring *ring)
2225 {
2226         void *vaddr;
2227         u32 *regs;
2228         int ret;
2229
2230         ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
2231         if (ret) {
2232                 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2233                 return ret;
2234         }
2235
2236         vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB);
2237         if (IS_ERR(vaddr)) {
2238                 ret = PTR_ERR(vaddr);
2239                 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret);
2240                 return ret;
2241         }
2242         ctx_obj->mm.dirty = true;
2243
2244         if (engine->default_state) {
2245                 /*
2246                  * We only want to copy over the template context state;
2247                  * skipping over the headers reserved for GuC communication,
2248                  * leaving those as zero.
2249                  */
2250                 const unsigned long start = LRC_HEADER_PAGES * PAGE_SIZE;
2251                 void *defaults;
2252
2253                 defaults = i915_gem_object_pin_map(engine->default_state,
2254                                                    I915_MAP_WB);
2255                 if (IS_ERR(defaults))
2256                         return PTR_ERR(defaults);
2257
2258                 memcpy(vaddr + start, defaults + start, engine->context_size);
2259                 i915_gem_object_unpin_map(engine->default_state);
2260         }
2261
2262         /* The second page of the context object contains some fields which must
2263          * be set up prior to the first execution. */
2264         regs = vaddr + LRC_STATE_PN * PAGE_SIZE;
2265         execlists_init_reg_state(regs, ctx, engine, ring);
2266         if (!engine->default_state)
2267                 regs[CTX_CONTEXT_CONTROL + 1] |=
2268                         _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
2269
2270         i915_gem_object_unpin_map(ctx_obj);
2271
2272         return 0;
2273 }
2274
2275 static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
2276                                             struct intel_engine_cs *engine)
2277 {
2278         struct drm_i915_gem_object *ctx_obj;
2279         struct intel_context *ce = &ctx->engine[engine->id];
2280         struct i915_vma *vma;
2281         uint32_t context_size;
2282         struct intel_ring *ring;
2283         int ret;
2284
2285         WARN_ON(ce->state);
2286
2287         context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE);
2288
2289         /*
2290          * Before the actual start of the context image, we insert a few pages
2291          * for our own use and for sharing with the GuC.
2292          */
2293         context_size += LRC_HEADER_PAGES * PAGE_SIZE;
2294
2295         ctx_obj = i915_gem_object_create(ctx->i915, context_size);
2296         if (IS_ERR(ctx_obj)) {
2297                 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2298                 return PTR_ERR(ctx_obj);
2299         }
2300
2301         vma = i915_vma_instance(ctx_obj, &ctx->i915->ggtt.base, NULL);
2302         if (IS_ERR(vma)) {
2303                 ret = PTR_ERR(vma);
2304                 goto error_deref_obj;
2305         }
2306
2307         ring = intel_engine_create_ring(engine, ctx->ring_size);
2308         if (IS_ERR(ring)) {
2309                 ret = PTR_ERR(ring);
2310                 goto error_deref_obj;
2311         }
2312
2313         ret = populate_lr_context(ctx, ctx_obj, engine, ring);
2314         if (ret) {
2315                 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
2316                 goto error_ring_free;
2317         }
2318
2319         ce->ring = ring;
2320         ce->state = vma;
2321
2322         return 0;
2323
2324 error_ring_free:
2325         intel_ring_free(ring);
2326 error_deref_obj:
2327         i915_gem_object_put(ctx_obj);
2328         return ret;
2329 }
2330
2331 void intel_lr_context_resume(struct drm_i915_private *dev_priv)
2332 {
2333         struct intel_engine_cs *engine;
2334         struct i915_gem_context *ctx;
2335         enum intel_engine_id id;
2336
2337         /* Because we emit WA_TAIL_DWORDS there may be a disparity
2338          * between our bookkeeping in ce->ring->head and ce->ring->tail and
2339          * that stored in context. As we only write new commands from
2340          * ce->ring->tail onwards, everything before that is junk. If the GPU
2341          * starts reading from its RING_HEAD from the context, it may try to
2342          * execute that junk and die.
2343          *
2344          * So to avoid that we reset the context images upon resume. For
2345          * simplicity, we just zero everything out.
2346          */
2347         list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
2348                 for_each_engine(engine, dev_priv, id) {
2349                         struct intel_context *ce = &ctx->engine[engine->id];
2350                         u32 *reg;
2351
2352                         if (!ce->state)
2353                                 continue;
2354
2355                         reg = i915_gem_object_pin_map(ce->state->obj,
2356                                                       I915_MAP_WB);
2357                         if (WARN_ON(IS_ERR(reg)))
2358                                 continue;
2359
2360                         reg += LRC_STATE_PN * PAGE_SIZE / sizeof(*reg);
2361                         reg[CTX_RING_HEAD+1] = 0;
2362                         reg[CTX_RING_TAIL+1] = 0;
2363
2364                         ce->state->obj->mm.dirty = true;
2365                         i915_gem_object_unpin_map(ce->state->obj);
2366
2367                         intel_ring_reset(ce->ring, 0);
2368                 }
2369         }
2370 }