4b7340ee629091515db27957f8d215c0b996179b
[muen/linux.git] / drivers / gpu / drm / sun4i / sun4i_tcon.c
1 /*
2  * Copyright (C) 2015 Free Electrons
3  * Copyright (C) 2015 NextThing Co
4  *
5  * Maxime Ripard <maxime.ripard@free-electrons.com>
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  */
12
13 #include <drm/drmP.h>
14 #include <drm/drm_atomic_helper.h>
15 #include <drm/drm_crtc.h>
16 #include <drm/drm_crtc_helper.h>
17 #include <drm/drm_encoder.h>
18 #include <drm/drm_modes.h>
19 #include <drm/drm_of.h>
20
21 #include <uapi/drm/drm_mode.h>
22
23 #include <linux/component.h>
24 #include <linux/ioport.h>
25 #include <linux/of_address.h>
26 #include <linux/of_device.h>
27 #include <linux/of_irq.h>
28 #include <linux/regmap.h>
29 #include <linux/reset.h>
30
31 #include "sun4i_crtc.h"
32 #include "sun4i_dotclock.h"
33 #include "sun4i_drv.h"
34 #include "sun4i_lvds.h"
35 #include "sun4i_rgb.h"
36 #include "sun4i_tcon.h"
37 #include "sunxi_engine.h"
38
39 static struct drm_connector *sun4i_tcon_get_connector(const struct drm_encoder *encoder)
40 {
41         struct drm_connector *connector;
42         struct drm_connector_list_iter iter;
43
44         drm_connector_list_iter_begin(encoder->dev, &iter);
45         drm_for_each_connector_iter(connector, &iter)
46                 if (connector->encoder == encoder) {
47                         drm_connector_list_iter_end(&iter);
48                         return connector;
49                 }
50         drm_connector_list_iter_end(&iter);
51
52         return NULL;
53 }
54
55 static int sun4i_tcon_get_pixel_depth(const struct drm_encoder *encoder)
56 {
57         struct drm_connector *connector;
58         struct drm_display_info *info;
59
60         connector = sun4i_tcon_get_connector(encoder);
61         if (!connector)
62                 return -EINVAL;
63
64         info = &connector->display_info;
65         if (info->num_bus_formats != 1)
66                 return -EINVAL;
67
68         switch (info->bus_formats[0]) {
69         case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
70                 return 18;
71
72         case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
73         case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
74                 return 24;
75         }
76
77         return -EINVAL;
78 }
79
80 static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel,
81                                           bool enabled)
82 {
83         struct clk *clk;
84
85         switch (channel) {
86         case 0:
87                 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
88                                    SUN4I_TCON0_CTL_TCON_ENABLE,
89                                    enabled ? SUN4I_TCON0_CTL_TCON_ENABLE : 0);
90                 clk = tcon->dclk;
91                 break;
92         case 1:
93                 WARN_ON(!tcon->quirks->has_channel_1);
94                 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
95                                    SUN4I_TCON1_CTL_TCON_ENABLE,
96                                    enabled ? SUN4I_TCON1_CTL_TCON_ENABLE : 0);
97                 clk = tcon->sclk1;
98                 break;
99         default:
100                 DRM_WARN("Unknown channel... doing nothing\n");
101                 return;
102         }
103
104         if (enabled)
105                 clk_prepare_enable(clk);
106         else
107                 clk_disable_unprepare(clk);
108 }
109
110 static void sun4i_tcon_lvds_set_status(struct sun4i_tcon *tcon,
111                                        const struct drm_encoder *encoder,
112                                        bool enabled)
113 {
114         if (enabled) {
115                 u8 val;
116
117                 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
118                                    SUN4I_TCON0_LVDS_IF_EN,
119                                    SUN4I_TCON0_LVDS_IF_EN);
120
121                 /*
122                  * As their name suggest, these values only apply to the A31
123                  * and later SoCs. We'll have to rework this when merging
124                  * support for the older SoCs.
125                  */
126                 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
127                              SUN6I_TCON0_LVDS_ANA0_C(2) |
128                              SUN6I_TCON0_LVDS_ANA0_V(3) |
129                              SUN6I_TCON0_LVDS_ANA0_PD(2) |
130                              SUN6I_TCON0_LVDS_ANA0_EN_LDO);
131                 udelay(2);
132
133                 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
134                                    SUN6I_TCON0_LVDS_ANA0_EN_MB,
135                                    SUN6I_TCON0_LVDS_ANA0_EN_MB);
136                 udelay(2);
137
138                 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
139                                    SUN6I_TCON0_LVDS_ANA0_EN_DRVC,
140                                    SUN6I_TCON0_LVDS_ANA0_EN_DRVC);
141
142                 if (sun4i_tcon_get_pixel_depth(encoder) == 18)
143                         val = 7;
144                 else
145                         val = 0xf;
146
147                 regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
148                                   SUN6I_TCON0_LVDS_ANA0_EN_DRVD(0xf),
149                                   SUN6I_TCON0_LVDS_ANA0_EN_DRVD(val));
150         } else {
151                 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
152                                    SUN4I_TCON0_LVDS_IF_EN, 0);
153         }
154 }
155
156 void sun4i_tcon_set_status(struct sun4i_tcon *tcon,
157                            const struct drm_encoder *encoder,
158                            bool enabled)
159 {
160         bool is_lvds = false;
161         int channel;
162
163         switch (encoder->encoder_type) {
164         case DRM_MODE_ENCODER_LVDS:
165                 is_lvds = true;
166                 /* Fallthrough */
167         case DRM_MODE_ENCODER_NONE:
168                 channel = 0;
169                 break;
170         case DRM_MODE_ENCODER_TMDS:
171         case DRM_MODE_ENCODER_TVDAC:
172                 channel = 1;
173                 break;
174         default:
175                 DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n");
176                 return;
177         }
178
179         if (is_lvds && !enabled)
180                 sun4i_tcon_lvds_set_status(tcon, encoder, false);
181
182         regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
183                            SUN4I_TCON_GCTL_TCON_ENABLE,
184                            enabled ? SUN4I_TCON_GCTL_TCON_ENABLE : 0);
185
186         if (is_lvds && enabled)
187                 sun4i_tcon_lvds_set_status(tcon, encoder, true);
188
189         sun4i_tcon_channel_set_status(tcon, channel, enabled);
190 }
191
192 void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable)
193 {
194         u32 mask, val = 0;
195
196         DRM_DEBUG_DRIVER("%sabling VBLANK interrupt\n", enable ? "En" : "Dis");
197
198         mask = SUN4I_TCON_GINT0_VBLANK_ENABLE(0) |
199                SUN4I_TCON_GINT0_VBLANK_ENABLE(1);
200
201         if (enable)
202                 val = mask;
203
204         regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, mask, val);
205 }
206 EXPORT_SYMBOL(sun4i_tcon_enable_vblank);
207
208 /*
209  * This function is a helper for TCON output muxing. The TCON output
210  * muxing control register in earlier SoCs (without the TCON TOP block)
211  * are located in TCON0. This helper returns a pointer to TCON0's
212  * sun4i_tcon structure, or NULL if not found.
213  */
214 static struct sun4i_tcon *sun4i_get_tcon0(struct drm_device *drm)
215 {
216         struct sun4i_drv *drv = drm->dev_private;
217         struct sun4i_tcon *tcon;
218
219         list_for_each_entry(tcon, &drv->tcon_list, list)
220                 if (tcon->id == 0)
221                         return tcon;
222
223         dev_warn(drm->dev,
224                  "TCON0 not found, display output muxing may not work\n");
225
226         return NULL;
227 }
228
229 void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel,
230                         const struct drm_encoder *encoder)
231 {
232         int ret = -ENOTSUPP;
233
234         if (tcon->quirks->set_mux)
235                 ret = tcon->quirks->set_mux(tcon, encoder);
236
237         DRM_DEBUG_DRIVER("Muxing encoder %s to CRTC %s: %d\n",
238                          encoder->name, encoder->crtc->name, ret);
239 }
240
241 static int sun4i_tcon_get_clk_delay(const struct drm_display_mode *mode,
242                                     int channel)
243 {
244         int delay = mode->vtotal - mode->vdisplay;
245
246         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
247                 delay /= 2;
248
249         if (channel == 1)
250                 delay -= 2;
251
252         delay = min(delay, 30);
253
254         DRM_DEBUG_DRIVER("TCON %d clock delay %u\n", channel, delay);
255
256         return delay;
257 }
258
259 static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon,
260                                         const struct drm_display_mode *mode)
261 {
262         /* Configure the dot clock */
263         clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
264
265         /* Set the resolution */
266         regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
267                      SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
268                      SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
269 }
270
271 static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon,
272                                       const struct drm_encoder *encoder,
273                                       const struct drm_display_mode *mode)
274 {
275         unsigned int bp;
276         u8 clk_delay;
277         u32 reg, val = 0;
278
279         tcon->dclk_min_div = 7;
280         tcon->dclk_max_div = 7;
281         sun4i_tcon0_mode_set_common(tcon, mode);
282
283         /* Adjust clock delay */
284         clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
285         regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
286                            SUN4I_TCON0_CTL_CLK_DELAY_MASK,
287                            SUN4I_TCON0_CTL_CLK_DELAY(clk_delay));
288
289         /*
290          * This is called a backporch in the register documentation,
291          * but it really is the back porch + hsync
292          */
293         bp = mode->crtc_htotal - mode->crtc_hsync_start;
294         DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
295                          mode->crtc_htotal, bp);
296
297         /* Set horizontal display timings */
298         regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG,
299                      SUN4I_TCON0_BASIC1_H_TOTAL(mode->htotal) |
300                      SUN4I_TCON0_BASIC1_H_BACKPORCH(bp));
301
302         /*
303          * This is called a backporch in the register documentation,
304          * but it really is the back porch + hsync
305          */
306         bp = mode->crtc_vtotal - mode->crtc_vsync_start;
307         DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
308                          mode->crtc_vtotal, bp);
309
310         /* Set vertical display timings */
311         regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG,
312                      SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) |
313                      SUN4I_TCON0_BASIC2_V_BACKPORCH(bp));
314
315         reg = SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0 |
316                 SUN4I_TCON0_LVDS_IF_DATA_POL_NORMAL |
317                 SUN4I_TCON0_LVDS_IF_CLK_POL_NORMAL;
318         if (sun4i_tcon_get_pixel_depth(encoder) == 24)
319                 reg |= SUN4I_TCON0_LVDS_IF_BITWIDTH_24BITS;
320         else
321                 reg |= SUN4I_TCON0_LVDS_IF_BITWIDTH_18BITS;
322
323         regmap_write(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, reg);
324
325         /* Setup the polarity of the various signals */
326         if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
327                 val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE;
328
329         if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
330                 val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
331
332         regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val);
333
334         /* Map output pins to channel 0 */
335         regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
336                            SUN4I_TCON_GCTL_IOMAP_MASK,
337                            SUN4I_TCON_GCTL_IOMAP_TCON0);
338 }
339
340 static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
341                                      const struct drm_display_mode *mode)
342 {
343         unsigned int bp, hsync, vsync;
344         u8 clk_delay;
345         u32 val = 0;
346
347         tcon->dclk_min_div = 6;
348         tcon->dclk_max_div = 127;
349         sun4i_tcon0_mode_set_common(tcon, mode);
350
351         /* Adjust clock delay */
352         clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
353         regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
354                            SUN4I_TCON0_CTL_CLK_DELAY_MASK,
355                            SUN4I_TCON0_CTL_CLK_DELAY(clk_delay));
356
357         /*
358          * This is called a backporch in the register documentation,
359          * but it really is the back porch + hsync
360          */
361         bp = mode->crtc_htotal - mode->crtc_hsync_start;
362         DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
363                          mode->crtc_htotal, bp);
364
365         /* Set horizontal display timings */
366         regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG,
367                      SUN4I_TCON0_BASIC1_H_TOTAL(mode->crtc_htotal) |
368                      SUN4I_TCON0_BASIC1_H_BACKPORCH(bp));
369
370         /*
371          * This is called a backporch in the register documentation,
372          * but it really is the back porch + hsync
373          */
374         bp = mode->crtc_vtotal - mode->crtc_vsync_start;
375         DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
376                          mode->crtc_vtotal, bp);
377
378         /* Set vertical display timings */
379         regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG,
380                      SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) |
381                      SUN4I_TCON0_BASIC2_V_BACKPORCH(bp));
382
383         /* Set Hsync and Vsync length */
384         hsync = mode->crtc_hsync_end - mode->crtc_hsync_start;
385         vsync = mode->crtc_vsync_end - mode->crtc_vsync_start;
386         DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync);
387         regmap_write(tcon->regs, SUN4I_TCON0_BASIC3_REG,
388                      SUN4I_TCON0_BASIC3_V_SYNC(vsync) |
389                      SUN4I_TCON0_BASIC3_H_SYNC(hsync));
390
391         /* Setup the polarity of the various signals */
392         if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
393                 val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE;
394
395         if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
396                 val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
397
398         regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG,
399                            SUN4I_TCON0_IO_POL_HSYNC_POSITIVE | SUN4I_TCON0_IO_POL_VSYNC_POSITIVE,
400                            val);
401
402         /* Map output pins to channel 0 */
403         regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
404                            SUN4I_TCON_GCTL_IOMAP_MASK,
405                            SUN4I_TCON_GCTL_IOMAP_TCON0);
406
407         /* Enable the output on the pins */
408         regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0);
409 }
410
411 static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
412                                  const struct drm_display_mode *mode)
413 {
414         unsigned int bp, hsync, vsync, vtotal;
415         u8 clk_delay;
416         u32 val;
417
418         WARN_ON(!tcon->quirks->has_channel_1);
419
420         /* Configure the dot clock */
421         clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000);
422
423         /* Adjust clock delay */
424         clk_delay = sun4i_tcon_get_clk_delay(mode, 1);
425         regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
426                            SUN4I_TCON1_CTL_CLK_DELAY_MASK,
427                            SUN4I_TCON1_CTL_CLK_DELAY(clk_delay));
428
429         /* Set interlaced mode */
430         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
431                 val = SUN4I_TCON1_CTL_INTERLACE_ENABLE;
432         else
433                 val = 0;
434         regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
435                            SUN4I_TCON1_CTL_INTERLACE_ENABLE,
436                            val);
437
438         /* Set the input resolution */
439         regmap_write(tcon->regs, SUN4I_TCON1_BASIC0_REG,
440                      SUN4I_TCON1_BASIC0_X(mode->crtc_hdisplay) |
441                      SUN4I_TCON1_BASIC0_Y(mode->crtc_vdisplay));
442
443         /* Set the upscaling resolution */
444         regmap_write(tcon->regs, SUN4I_TCON1_BASIC1_REG,
445                      SUN4I_TCON1_BASIC1_X(mode->crtc_hdisplay) |
446                      SUN4I_TCON1_BASIC1_Y(mode->crtc_vdisplay));
447
448         /* Set the output resolution */
449         regmap_write(tcon->regs, SUN4I_TCON1_BASIC2_REG,
450                      SUN4I_TCON1_BASIC2_X(mode->crtc_hdisplay) |
451                      SUN4I_TCON1_BASIC2_Y(mode->crtc_vdisplay));
452
453         /* Set horizontal display timings */
454         bp = mode->crtc_htotal - mode->crtc_hsync_start;
455         DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
456                          mode->htotal, bp);
457         regmap_write(tcon->regs, SUN4I_TCON1_BASIC3_REG,
458                      SUN4I_TCON1_BASIC3_H_TOTAL(mode->crtc_htotal) |
459                      SUN4I_TCON1_BASIC3_H_BACKPORCH(bp));
460
461         bp = mode->crtc_vtotal - mode->crtc_vsync_start;
462         DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
463                          mode->crtc_vtotal, bp);
464
465         /*
466          * The vertical resolution needs to be doubled in all
467          * cases. We could use crtc_vtotal and always multiply by two,
468          * but that leads to a rounding error in interlace when vtotal
469          * is odd.
470          *
471          * This happens with TV's PAL for example, where vtotal will
472          * be 625, crtc_vtotal 312, and thus crtc_vtotal * 2 will be
473          * 624, which apparently confuses the hardware.
474          *
475          * To work around this, we will always use vtotal, and
476          * multiply by two only if we're not in interlace.
477          */
478         vtotal = mode->vtotal;
479         if (!(mode->flags & DRM_MODE_FLAG_INTERLACE))
480                 vtotal = vtotal * 2;
481
482         /* Set vertical display timings */
483         regmap_write(tcon->regs, SUN4I_TCON1_BASIC4_REG,
484                      SUN4I_TCON1_BASIC4_V_TOTAL(vtotal) |
485                      SUN4I_TCON1_BASIC4_V_BACKPORCH(bp));
486
487         /* Set Hsync and Vsync length */
488         hsync = mode->crtc_hsync_end - mode->crtc_hsync_start;
489         vsync = mode->crtc_vsync_end - mode->crtc_vsync_start;
490         DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync);
491         regmap_write(tcon->regs, SUN4I_TCON1_BASIC5_REG,
492                      SUN4I_TCON1_BASIC5_V_SYNC(vsync) |
493                      SUN4I_TCON1_BASIC5_H_SYNC(hsync));
494
495         /* Map output pins to channel 1 */
496         regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
497                            SUN4I_TCON_GCTL_IOMAP_MASK,
498                            SUN4I_TCON_GCTL_IOMAP_TCON1);
499 }
500
501 void sun4i_tcon_mode_set(struct sun4i_tcon *tcon,
502                          const struct drm_encoder *encoder,
503                          const struct drm_display_mode *mode)
504 {
505         switch (encoder->encoder_type) {
506         case DRM_MODE_ENCODER_LVDS:
507                 sun4i_tcon0_mode_set_lvds(tcon, encoder, mode);
508                 break;
509         case DRM_MODE_ENCODER_NONE:
510                 sun4i_tcon0_mode_set_rgb(tcon, mode);
511                 sun4i_tcon_set_mux(tcon, 0, encoder);
512                 break;
513         case DRM_MODE_ENCODER_TVDAC:
514         case DRM_MODE_ENCODER_TMDS:
515                 sun4i_tcon1_mode_set(tcon, mode);
516                 sun4i_tcon_set_mux(tcon, 1, encoder);
517                 break;
518         default:
519                 DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n");
520         }
521 }
522 EXPORT_SYMBOL(sun4i_tcon_mode_set);
523
524 static void sun4i_tcon_finish_page_flip(struct drm_device *dev,
525                                         struct sun4i_crtc *scrtc)
526 {
527         unsigned long flags;
528
529         spin_lock_irqsave(&dev->event_lock, flags);
530         if (scrtc->event) {
531                 drm_crtc_send_vblank_event(&scrtc->crtc, scrtc->event);
532                 drm_crtc_vblank_put(&scrtc->crtc);
533                 scrtc->event = NULL;
534         }
535         spin_unlock_irqrestore(&dev->event_lock, flags);
536 }
537
538 static irqreturn_t sun4i_tcon_handler(int irq, void *private)
539 {
540         struct sun4i_tcon *tcon = private;
541         struct drm_device *drm = tcon->drm;
542         struct sun4i_crtc *scrtc = tcon->crtc;
543         struct sunxi_engine *engine = scrtc->engine;
544         unsigned int status;
545
546         regmap_read(tcon->regs, SUN4I_TCON_GINT0_REG, &status);
547
548         if (!(status & (SUN4I_TCON_GINT0_VBLANK_INT(0) |
549                         SUN4I_TCON_GINT0_VBLANK_INT(1))))
550                 return IRQ_NONE;
551
552         drm_crtc_handle_vblank(&scrtc->crtc);
553         sun4i_tcon_finish_page_flip(drm, scrtc);
554
555         /* Acknowledge the interrupt */
556         regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG,
557                            SUN4I_TCON_GINT0_VBLANK_INT(0) |
558                            SUN4I_TCON_GINT0_VBLANK_INT(1),
559                            0);
560
561         if (engine->ops->vblank_quirk)
562                 engine->ops->vblank_quirk(engine);
563
564         return IRQ_HANDLED;
565 }
566
567 static int sun4i_tcon_init_clocks(struct device *dev,
568                                   struct sun4i_tcon *tcon)
569 {
570         tcon->clk = devm_clk_get(dev, "ahb");
571         if (IS_ERR(tcon->clk)) {
572                 dev_err(dev, "Couldn't get the TCON bus clock\n");
573                 return PTR_ERR(tcon->clk);
574         }
575         clk_prepare_enable(tcon->clk);
576
577         tcon->sclk0 = devm_clk_get(dev, "tcon-ch0");
578         if (IS_ERR(tcon->sclk0)) {
579                 dev_err(dev, "Couldn't get the TCON channel 0 clock\n");
580                 return PTR_ERR(tcon->sclk0);
581         }
582
583         if (tcon->quirks->has_channel_1) {
584                 tcon->sclk1 = devm_clk_get(dev, "tcon-ch1");
585                 if (IS_ERR(tcon->sclk1)) {
586                         dev_err(dev, "Couldn't get the TCON channel 1 clock\n");
587                         return PTR_ERR(tcon->sclk1);
588                 }
589         }
590
591         return 0;
592 }
593
594 static void sun4i_tcon_free_clocks(struct sun4i_tcon *tcon)
595 {
596         clk_disable_unprepare(tcon->clk);
597 }
598
599 static int sun4i_tcon_init_irq(struct device *dev,
600                                struct sun4i_tcon *tcon)
601 {
602         struct platform_device *pdev = to_platform_device(dev);
603         int irq, ret;
604
605         irq = platform_get_irq(pdev, 0);
606         if (irq < 0) {
607                 dev_err(dev, "Couldn't retrieve the TCON interrupt\n");
608                 return irq;
609         }
610
611         ret = devm_request_irq(dev, irq, sun4i_tcon_handler, 0,
612                                dev_name(dev), tcon);
613         if (ret) {
614                 dev_err(dev, "Couldn't request the IRQ\n");
615                 return ret;
616         }
617
618         return 0;
619 }
620
621 static struct regmap_config sun4i_tcon_regmap_config = {
622         .reg_bits       = 32,
623         .val_bits       = 32,
624         .reg_stride     = 4,
625         .max_register   = 0x800,
626 };
627
628 static int sun4i_tcon_init_regmap(struct device *dev,
629                                   struct sun4i_tcon *tcon)
630 {
631         struct platform_device *pdev = to_platform_device(dev);
632         struct resource *res;
633         void __iomem *regs;
634
635         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
636         regs = devm_ioremap_resource(dev, res);
637         if (IS_ERR(regs))
638                 return PTR_ERR(regs);
639
640         tcon->regs = devm_regmap_init_mmio(dev, regs,
641                                            &sun4i_tcon_regmap_config);
642         if (IS_ERR(tcon->regs)) {
643                 dev_err(dev, "Couldn't create the TCON regmap\n");
644                 return PTR_ERR(tcon->regs);
645         }
646
647         /* Make sure the TCON is disabled and all IRQs are off */
648         regmap_write(tcon->regs, SUN4I_TCON_GCTL_REG, 0);
649         regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0);
650         regmap_write(tcon->regs, SUN4I_TCON_GINT1_REG, 0);
651
652         /* Disable IO lines and set them to tristate */
653         regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, ~0);
654         regmap_write(tcon->regs, SUN4I_TCON1_IO_TRI_REG, ~0);
655
656         return 0;
657 }
658
659 /*
660  * On SoCs with the old display pipeline design (Display Engine 1.0),
661  * the TCON is always tied to just one backend. Hence we can traverse
662  * the of_graph upwards to find the backend our tcon is connected to,
663  * and take its ID as our own.
664  *
665  * We can either identify backends from their compatible strings, which
666  * means maintaining a large list of them. Or, since the backend is
667  * registered and binded before the TCON, we can just go through the
668  * list of registered backends and compare the device node.
669  *
670  * As the structures now store engines instead of backends, here this
671  * function in fact searches the corresponding engine, and the ID is
672  * requested via the get_id function of the engine.
673  */
674 static struct sunxi_engine *
675 sun4i_tcon_find_engine_traverse(struct sun4i_drv *drv,
676                                 struct device_node *node)
677 {
678         struct device_node *port, *ep, *remote;
679         struct sunxi_engine *engine = ERR_PTR(-EINVAL);
680
681         port = of_graph_get_port_by_id(node, 0);
682         if (!port)
683                 return ERR_PTR(-EINVAL);
684
685         /*
686          * This only works if there is only one path from the TCON
687          * to any display engine. Otherwise the probe order of the
688          * TCONs and display engines is not guaranteed. They may
689          * either bind to the wrong one, or worse, bind to the same
690          * one if additional checks are not done.
691          *
692          * Bail out if there are multiple input connections.
693          */
694         if (of_get_available_child_count(port) != 1)
695                 goto out_put_port;
696
697         /* Get the first connection without specifying an ID */
698         ep = of_get_next_available_child(port, NULL);
699         if (!ep)
700                 goto out_put_port;
701
702         remote = of_graph_get_remote_port_parent(ep);
703         if (!remote)
704                 goto out_put_ep;
705
706         /* does this node match any registered engines? */
707         list_for_each_entry(engine, &drv->engine_list, list)
708                 if (remote == engine->node)
709                         goto out_put_remote;
710
711         /* keep looking through upstream ports */
712         engine = sun4i_tcon_find_engine_traverse(drv, remote);
713
714 out_put_remote:
715         of_node_put(remote);
716 out_put_ep:
717         of_node_put(ep);
718 out_put_port:
719         of_node_put(port);
720
721         return engine;
722 }
723
724 /*
725  * The device tree binding says that the remote endpoint ID of any
726  * connection between components, up to and including the TCON, of
727  * the display pipeline should be equal to the actual ID of the local
728  * component. Thus we can look at any one of the input connections of
729  * the TCONs, and use that connection's remote endpoint ID as our own.
730  *
731  * Since the user of this function already finds the input port,
732  * the port is passed in directly without further checks.
733  */
734 static int sun4i_tcon_of_get_id_from_port(struct device_node *port)
735 {
736         struct device_node *ep;
737         int ret = -EINVAL;
738
739         /* try finding an upstream endpoint */
740         for_each_available_child_of_node(port, ep) {
741                 struct device_node *remote;
742                 u32 reg;
743
744                 remote = of_graph_get_remote_endpoint(ep);
745                 if (!remote)
746                         continue;
747
748                 ret = of_property_read_u32(remote, "reg", &reg);
749                 if (ret)
750                         continue;
751
752                 ret = reg;
753         }
754
755         return ret;
756 }
757
758 /*
759  * Once we know the TCON's id, we can look through the list of
760  * engines to find a matching one. We assume all engines have
761  * been probed and added to the list.
762  */
763 static struct sunxi_engine *sun4i_tcon_get_engine_by_id(struct sun4i_drv *drv,
764                                                         int id)
765 {
766         struct sunxi_engine *engine;
767
768         list_for_each_entry(engine, &drv->engine_list, list)
769                 if (engine->id == id)
770                         return engine;
771
772         return ERR_PTR(-EINVAL);
773 }
774
775 /*
776  * On SoCs with the old display pipeline design (Display Engine 1.0),
777  * we assumed the TCON was always tied to just one backend. However
778  * this proved not to be the case. On the A31, the TCON can select
779  * either backend as its source. On the A20 (and likely on the A10),
780  * the backend can choose which TCON to output to.
781  *
782  * The device tree binding says that the remote endpoint ID of any
783  * connection between components, up to and including the TCON, of
784  * the display pipeline should be equal to the actual ID of the local
785  * component. Thus we should be able to look at any one of the input
786  * connections of the TCONs, and use that connection's remote endpoint
787  * ID as our own.
788  *
789  * However  the connections between the backend and TCON were assumed
790  * to be always singular, and their endpoit IDs were all incorrectly
791  * set to 0. This means for these old device trees, we cannot just look
792  * up the remote endpoint ID of a TCON input endpoint. TCON1 would be
793  * incorrectly identified as TCON0.
794  *
795  * This function first checks if the TCON node has 2 input endpoints.
796  * If so, then the device tree is a corrected version, and it will use
797  * sun4i_tcon_of_get_id() and sun4i_tcon_get_engine_by_id() from above
798  * to fetch the ID and engine directly. If not, then it is likely an
799  * old device trees, where the endpoint IDs were incorrect, but did not
800  * have endpoint connections between the backend and TCON across
801  * different display pipelines. It will fall back to the old method of
802  * traversing the  of_graph to try and find a matching engine by device
803  * node.
804  *
805  * In the case of single display pipeline device trees, either method
806  * works.
807  */
808 static struct sunxi_engine *sun4i_tcon_find_engine(struct sun4i_drv *drv,
809                                                    struct device_node *node)
810 {
811         struct device_node *port;
812         struct sunxi_engine *engine;
813
814         port = of_graph_get_port_by_id(node, 0);
815         if (!port)
816                 return ERR_PTR(-EINVAL);
817
818         /*
819          * Is this a corrected device tree with cross pipeline
820          * connections between the backend and TCON?
821          */
822         if (of_get_child_count(port) > 1) {
823                 /* Get our ID directly from an upstream endpoint */
824                 int id = sun4i_tcon_of_get_id_from_port(port);
825
826                 /* Get our engine by matching our ID */
827                 engine = sun4i_tcon_get_engine_by_id(drv, id);
828
829                 of_node_put(port);
830                 return engine;
831         }
832
833         /* Fallback to old method by traversing input endpoints */
834         of_node_put(port);
835         return sun4i_tcon_find_engine_traverse(drv, node);
836 }
837
838 static int sun4i_tcon_bind(struct device *dev, struct device *master,
839                            void *data)
840 {
841         struct drm_device *drm = data;
842         struct sun4i_drv *drv = drm->dev_private;
843         struct sunxi_engine *engine;
844         struct device_node *remote;
845         struct sun4i_tcon *tcon;
846         bool has_lvds_rst, has_lvds_alt, can_lvds;
847         int ret;
848
849         engine = sun4i_tcon_find_engine(drv, dev->of_node);
850         if (IS_ERR(engine)) {
851                 dev_err(dev, "Couldn't find matching engine\n");
852                 return -EPROBE_DEFER;
853         }
854
855         tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL);
856         if (!tcon)
857                 return -ENOMEM;
858         dev_set_drvdata(dev, tcon);
859         tcon->drm = drm;
860         tcon->dev = dev;
861         tcon->id = engine->id;
862         tcon->quirks = of_device_get_match_data(dev);
863
864         tcon->lcd_rst = devm_reset_control_get(dev, "lcd");
865         if (IS_ERR(tcon->lcd_rst)) {
866                 dev_err(dev, "Couldn't get our reset line\n");
867                 return PTR_ERR(tcon->lcd_rst);
868         }
869
870         /* Make sure our TCON is reset */
871         ret = reset_control_reset(tcon->lcd_rst);
872         if (ret) {
873                 dev_err(dev, "Couldn't deassert our reset line\n");
874                 return ret;
875         }
876
877         /*
878          * This can only be made optional since we've had DT nodes
879          * without the LVDS reset properties.
880          *
881          * If the property is missing, just disable LVDS, and print a
882          * warning.
883          */
884         tcon->lvds_rst = devm_reset_control_get_optional(dev, "lvds");
885         if (IS_ERR(tcon->lvds_rst)) {
886                 dev_err(dev, "Couldn't get our reset line\n");
887                 return PTR_ERR(tcon->lvds_rst);
888         } else if (tcon->lvds_rst) {
889                 has_lvds_rst = true;
890                 reset_control_reset(tcon->lvds_rst);
891         } else {
892                 has_lvds_rst = false;
893         }
894
895         /*
896          * This can only be made optional since we've had DT nodes
897          * without the LVDS reset properties.
898          *
899          * If the property is missing, just disable LVDS, and print a
900          * warning.
901          */
902         if (tcon->quirks->has_lvds_alt) {
903                 tcon->lvds_pll = devm_clk_get(dev, "lvds-alt");
904                 if (IS_ERR(tcon->lvds_pll)) {
905                         if (PTR_ERR(tcon->lvds_pll) == -ENOENT) {
906                                 has_lvds_alt = false;
907                         } else {
908                                 dev_err(dev, "Couldn't get the LVDS PLL\n");
909                                 return PTR_ERR(tcon->lvds_pll);
910                         }
911                 } else {
912                         has_lvds_alt = true;
913                 }
914         }
915
916         if (!has_lvds_rst || (tcon->quirks->has_lvds_alt && !has_lvds_alt)) {
917                 dev_warn(dev,
918                          "Missing LVDS properties, Please upgrade your DT\n");
919                 dev_warn(dev, "LVDS output disabled\n");
920                 can_lvds = false;
921         } else {
922                 can_lvds = true;
923         }
924
925         ret = sun4i_tcon_init_clocks(dev, tcon);
926         if (ret) {
927                 dev_err(dev, "Couldn't init our TCON clocks\n");
928                 goto err_assert_reset;
929         }
930
931         ret = sun4i_tcon_init_regmap(dev, tcon);
932         if (ret) {
933                 dev_err(dev, "Couldn't init our TCON regmap\n");
934                 goto err_free_clocks;
935         }
936
937         ret = sun4i_dclk_create(dev, tcon);
938         if (ret) {
939                 dev_err(dev, "Couldn't create our TCON dot clock\n");
940                 goto err_free_clocks;
941         }
942
943         ret = sun4i_tcon_init_irq(dev, tcon);
944         if (ret) {
945                 dev_err(dev, "Couldn't init our TCON interrupts\n");
946                 goto err_free_dotclock;
947         }
948
949         tcon->crtc = sun4i_crtc_init(drm, engine, tcon);
950         if (IS_ERR(tcon->crtc)) {
951                 dev_err(dev, "Couldn't create our CRTC\n");
952                 ret = PTR_ERR(tcon->crtc);
953                 goto err_free_dotclock;
954         }
955
956         /*
957          * If we have an LVDS panel connected to the TCON, we should
958          * just probe the LVDS connector. Otherwise, just probe RGB as
959          * we used to.
960          */
961         remote = of_graph_get_remote_node(dev->of_node, 1, 0);
962         if (of_device_is_compatible(remote, "panel-lvds"))
963                 if (can_lvds)
964                         ret = sun4i_lvds_init(drm, tcon);
965                 else
966                         ret = -EINVAL;
967         else
968                 ret = sun4i_rgb_init(drm, tcon);
969         of_node_put(remote);
970
971         if (ret < 0)
972                 goto err_free_dotclock;
973
974         if (tcon->quirks->needs_de_be_mux) {
975                 /*
976                  * We assume there is no dynamic muxing of backends
977                  * and TCONs, so we select the backend with same ID.
978                  *
979                  * While dynamic selection might be interesting, since
980                  * the CRTC is tied to the TCON, while the layers are
981                  * tied to the backends, this means, we will need to
982                  * switch between groups of layers. There might not be
983                  * a way to represent this constraint in DRM.
984                  */
985                 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
986                                    SUN4I_TCON0_CTL_SRC_SEL_MASK,
987                                    tcon->id);
988                 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
989                                    SUN4I_TCON1_CTL_SRC_SEL_MASK,
990                                    tcon->id);
991         }
992
993         list_add_tail(&tcon->list, &drv->tcon_list);
994
995         return 0;
996
997 err_free_dotclock:
998         sun4i_dclk_free(tcon);
999 err_free_clocks:
1000         sun4i_tcon_free_clocks(tcon);
1001 err_assert_reset:
1002         reset_control_assert(tcon->lcd_rst);
1003         return ret;
1004 }
1005
1006 static void sun4i_tcon_unbind(struct device *dev, struct device *master,
1007                               void *data)
1008 {
1009         struct sun4i_tcon *tcon = dev_get_drvdata(dev);
1010
1011         list_del(&tcon->list);
1012         sun4i_dclk_free(tcon);
1013         sun4i_tcon_free_clocks(tcon);
1014 }
1015
1016 static const struct component_ops sun4i_tcon_ops = {
1017         .bind   = sun4i_tcon_bind,
1018         .unbind = sun4i_tcon_unbind,
1019 };
1020
1021 static int sun4i_tcon_probe(struct platform_device *pdev)
1022 {
1023         struct device_node *node = pdev->dev.of_node;
1024         struct drm_bridge *bridge;
1025         struct drm_panel *panel;
1026         int ret;
1027
1028         ret = drm_of_find_panel_or_bridge(node, 1, 0, &panel, &bridge);
1029         if (ret == -EPROBE_DEFER)
1030                 return ret;
1031
1032         return component_add(&pdev->dev, &sun4i_tcon_ops);
1033 }
1034
1035 static int sun4i_tcon_remove(struct platform_device *pdev)
1036 {
1037         component_del(&pdev->dev, &sun4i_tcon_ops);
1038
1039         return 0;
1040 }
1041
1042 /* platform specific TCON muxing callbacks */
1043 static int sun4i_a10_tcon_set_mux(struct sun4i_tcon *tcon,
1044                                   const struct drm_encoder *encoder)
1045 {
1046         struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev);
1047         u32 shift;
1048
1049         if (!tcon0)
1050                 return -EINVAL;
1051
1052         switch (encoder->encoder_type) {
1053         case DRM_MODE_ENCODER_TMDS:
1054                 /* HDMI */
1055                 shift = 8;
1056                 break;
1057         default:
1058                 return -EINVAL;
1059         }
1060
1061         regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG,
1062                            0x3 << shift, tcon->id << shift);
1063
1064         return 0;
1065 }
1066
1067 static int sun5i_a13_tcon_set_mux(struct sun4i_tcon *tcon,
1068                                   const struct drm_encoder *encoder)
1069 {
1070         u32 val;
1071
1072         if (encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
1073                 val = 1;
1074         else
1075                 val = 0;
1076
1077         /*
1078          * FIXME: Undocumented bits
1079          */
1080         return regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, val);
1081 }
1082
1083 static int sun6i_tcon_set_mux(struct sun4i_tcon *tcon,
1084                               const struct drm_encoder *encoder)
1085 {
1086         struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev);
1087         u32 shift;
1088
1089         if (!tcon0)
1090                 return -EINVAL;
1091
1092         switch (encoder->encoder_type) {
1093         case DRM_MODE_ENCODER_TMDS:
1094                 /* HDMI */
1095                 shift = 8;
1096                 break;
1097         default:
1098                 /* TODO A31 has MIPI DSI but A31s does not */
1099                 return -EINVAL;
1100         }
1101
1102         regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG,
1103                            0x3 << shift, tcon->id << shift);
1104
1105         return 0;
1106 }
1107
1108 static const struct sun4i_tcon_quirks sun4i_a10_quirks = {
1109         .has_channel_1          = true,
1110         .set_mux                = sun4i_a10_tcon_set_mux,
1111 };
1112
1113 static const struct sun4i_tcon_quirks sun5i_a13_quirks = {
1114         .has_channel_1          = true,
1115         .set_mux                = sun5i_a13_tcon_set_mux,
1116 };
1117
1118 static const struct sun4i_tcon_quirks sun6i_a31_quirks = {
1119         .has_channel_1          = true,
1120         .has_lvds_alt           = true,
1121         .needs_de_be_mux        = true,
1122         .set_mux                = sun6i_tcon_set_mux,
1123 };
1124
1125 static const struct sun4i_tcon_quirks sun6i_a31s_quirks = {
1126         .has_channel_1          = true,
1127         .needs_de_be_mux        = true,
1128 };
1129
1130 static const struct sun4i_tcon_quirks sun7i_a20_quirks = {
1131         .has_channel_1          = true,
1132         /* Same display pipeline structure as A10 */
1133         .set_mux                = sun4i_a10_tcon_set_mux,
1134 };
1135
1136 static const struct sun4i_tcon_quirks sun8i_a33_quirks = {
1137         .has_lvds_alt           = true,
1138 };
1139
1140 static const struct sun4i_tcon_quirks sun8i_a83t_lcd_quirks = {
1141         /* nothing is supported */
1142 };
1143
1144 static const struct sun4i_tcon_quirks sun8i_v3s_quirks = {
1145         /* nothing is supported */
1146 };
1147
1148 /* sun4i_drv uses this list to check if a device node is a TCON */
1149 const struct of_device_id sun4i_tcon_of_table[] = {
1150         { .compatible = "allwinner,sun4i-a10-tcon", .data = &sun4i_a10_quirks },
1151         { .compatible = "allwinner,sun5i-a13-tcon", .data = &sun5i_a13_quirks },
1152         { .compatible = "allwinner,sun6i-a31-tcon", .data = &sun6i_a31_quirks },
1153         { .compatible = "allwinner,sun6i-a31s-tcon", .data = &sun6i_a31s_quirks },
1154         { .compatible = "allwinner,sun7i-a20-tcon", .data = &sun7i_a20_quirks },
1155         { .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks },
1156         { .compatible = "allwinner,sun8i-a83t-tcon-lcd", .data = &sun8i_a83t_lcd_quirks },
1157         { .compatible = "allwinner,sun8i-v3s-tcon", .data = &sun8i_v3s_quirks },
1158         { }
1159 };
1160 MODULE_DEVICE_TABLE(of, sun4i_tcon_of_table);
1161 EXPORT_SYMBOL(sun4i_tcon_of_table);
1162
1163 static struct platform_driver sun4i_tcon_platform_driver = {
1164         .probe          = sun4i_tcon_probe,
1165         .remove         = sun4i_tcon_remove,
1166         .driver         = {
1167                 .name           = "sun4i-tcon",
1168                 .of_match_table = sun4i_tcon_of_table,
1169         },
1170 };
1171 module_platform_driver(sun4i_tcon_platform_driver);
1172
1173 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1174 MODULE_DESCRIPTION("Allwinner A10 Timing Controller Driver");
1175 MODULE_LICENSE("GPL");