drivers/gpu/drm/tegra/sor.c

   1 /*
   2  * Copyright (C) 2013 NVIDIA Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/clk-provider.h>
  11 #include <linux/debugfs.h>
  12 #include <linux/gpio.h>
  13 #include <linux/io.h>
  14 #include <linux/of_device.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/regulator/consumer.h>
  18 #include <linux/reset.h>
  19
  20 #include <soc/tegra/pmc.h>
  21
  22 #include <drm/drm_atomic_helper.h>
  23 #include <drm/drm_dp_helper.h>
  24 #include <drm/drm_panel.h>
  25
  26 #include "dc.h"
  27 #include "drm.h"
  28 #include "sor.h"
  29 #include "trace.h"
  30
  31 #define SOR_REKEY 0x38
  32
  33 struct tegra_sor_hdmi_settings {
  34         unsigned long frequency;
  35
  36         u8 vcocap;
  37         u8 ichpmp;
  38         u8 loadadj;
  39         u8 termadj;
  40         u8 tx_pu;
  41         u8 bg_vref;
  42
  43         u8 drive_current[4];
  44         u8 preemphasis[4];
  45 };
  46
  47 #if 1
  48 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
  49         {
  50                 .frequency = 54000000,
  51                 .vcocap = 0x0,
  52                 .ichpmp = 0x1,
  53                 .loadadj = 0x3,
  54                 .termadj = 0x9,
  55                 .tx_pu = 0x10,
  56                 .bg_vref = 0x8,
  57                 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
  58                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  59         }, {
  60                 .frequency = 75000000,
  61                 .vcocap = 0x3,
  62                 .ichpmp = 0x1,
  63                 .loadadj = 0x3,
  64                 .termadj = 0x9,
  65                 .tx_pu = 0x40,
  66                 .bg_vref = 0x8,
  67                 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
  68                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  69         }, {
  70                 .frequency = 150000000,
  71                 .vcocap = 0x3,
  72                 .ichpmp = 0x1,
  73                 .loadadj = 0x3,
  74                 .termadj = 0x9,
  75                 .tx_pu = 0x66,
  76                 .bg_vref = 0x8,
  77                 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
  78                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  79         }, {
  80                 .frequency = 300000000,
  81                 .vcocap = 0x3,
  82                 .ichpmp = 0x1,
  83                 .loadadj = 0x3,
  84                 .termadj = 0x9,
  85                 .tx_pu = 0x66,
  86                 .bg_vref = 0xa,
  87                 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
  88                 .preemphasis = { 0x00, 0x17, 0x17, 0x17 },
  89         }, {
  90                 .frequency = 600000000,
  91                 .vcocap = 0x3,
  92                 .ichpmp = 0x1,
  93                 .loadadj = 0x3,
  94                 .termadj = 0x9,
  95                 .tx_pu = 0x66,
  96                 .bg_vref = 0x8,
  97                 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
  98                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  99         },
 100 };
 101 #else
 102 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
 103         {
 104                 .frequency = 75000000,
 105                 .vcocap = 0x3,
 106                 .ichpmp = 0x1,
 107                 .loadadj = 0x3,
 108                 .termadj = 0x9,
 109                 .tx_pu = 0x40,
 110                 .bg_vref = 0x8,
 111                 .drive_current = { 0x29, 0x29, 0x29, 0x29 },
 112                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 113         }, {
 114                 .frequency = 150000000,
 115                 .vcocap = 0x3,
 116                 .ichpmp = 0x1,
 117                 .loadadj = 0x3,
 118                 .termadj = 0x9,
 119                 .tx_pu = 0x66,
 120                 .bg_vref = 0x8,
 121                 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
 122                 .preemphasis = { 0x01, 0x02, 0x02, 0x02 },
 123         }, {
 124                 .frequency = 300000000,
 125                 .vcocap = 0x3,
 126                 .ichpmp = 0x6,
 127                 .loadadj = 0x3,
 128                 .termadj = 0x9,
 129                 .tx_pu = 0x66,
 130                 .bg_vref = 0xf,
 131                 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
 132                 .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e },
 133         }, {
 134                 .frequency = 600000000,
 135                 .vcocap = 0x3,
 136                 .ichpmp = 0xa,
 137                 .loadadj = 0x3,
 138                 .termadj = 0xb,
 139                 .tx_pu = 0x66,
 140                 .bg_vref = 0xe,
 141                 .drive_current = { 0x35, 0x3e, 0x3e, 0x3e },
 142                 .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f },
 143         },
 144 };
 145 #endif
 146
 147 struct tegra_sor_soc {
 148         bool supports_edp;
 149         bool supports_lvds;
 150         bool supports_hdmi;
 151         bool supports_dp;
 152
 153         const struct tegra_sor_hdmi_settings *settings;
 154         unsigned int num_settings;
 155
 156         const u8 *xbar_cfg;
 157 };
 158
 159 struct tegra_sor;
 160
 161 struct tegra_sor_ops {
 162         const char *name;
 163         int (*probe)(struct tegra_sor *sor);
 164         int (*remove)(struct tegra_sor *sor);
 165 };
 166
 167 struct tegra_sor {
 168         struct host1x_client client;
 169         struct tegra_output output;
 170         struct device *dev;
 171
 172         const struct tegra_sor_soc *soc;
 173         void __iomem *regs;
 174
 175         struct reset_control *rst;
 176         struct clk *clk_parent;
 177         struct clk *clk_brick;
 178         struct clk *clk_safe;
 179         struct clk *clk_src;
 180         struct clk *clk_dp;
 181         struct clk *clk;
 182
 183         struct drm_dp_aux *aux;
 184
 185         struct drm_info_list *debugfs_files;
 186         struct drm_minor *minor;
 187         struct dentry *debugfs;
 188
 189         const struct tegra_sor_ops *ops;
 190
 191         /* for HDMI 2.0 */
 192         struct tegra_sor_hdmi_settings *settings;
 193         unsigned int num_settings;
 194
 195         struct regulator *avdd_io_supply;
 196         struct regulator *vdd_pll_supply;
 197         struct regulator *hdmi_supply;
 198 };
 199
 200 struct tegra_sor_state {
 201         struct drm_connector_state base;
 202
 203         unsigned int bpc;
 204 };
 205
 206 static inline struct tegra_sor_state *
 207 to_sor_state(struct drm_connector_state *state)
 208 {
 209         return container_of(state, struct tegra_sor_state, base);
 210 }
 211
 212 struct tegra_sor_config {
 213         u32 bits_per_pixel;
 214
 215         u32 active_polarity;
 216         u32 active_count;
 217         u32 tu_size;
 218         u32 active_frac;
 219         u32 watermark;
 220
 221         u32 hblank_symbols;
 222         u32 vblank_symbols;
 223 };
 224
 225 static inline struct tegra_sor *
 226 host1x_client_to_sor(struct host1x_client *client)
 227 {
 228         return container_of(client, struct tegra_sor, client);
 229 }
 230
 231 static inline struct tegra_sor *to_sor(struct tegra_output *output)
 232 {
 233         return container_of(output, struct tegra_sor, output);
 234 }
 235
 236 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset)
 237 {
 238         u32 value = readl(sor->regs + (offset << 2));
 239
 240         trace_sor_readl(sor->dev, offset, value);
 241
 242         return value;
 243 }
 244
 245 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value,
 246                                     unsigned int offset)
 247 {
 248         trace_sor_writel(sor->dev, offset, value);
 249         writel(value, sor->regs + (offset << 2));
 250 }
 251
 252 static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent)
 253 {
 254         int err;
 255
 256         clk_disable_unprepare(sor->clk);
 257
 258         err = clk_set_parent(sor->clk, parent);
 259         if (err < 0)
 260                 return err;
 261
 262         err = clk_prepare_enable(sor->clk);
 263         if (err < 0)
 264                 return err;
 265
 266         return 0;
 267 }
 268
 269 struct tegra_clk_sor_brick {
 270         struct clk_hw hw;
 271         struct tegra_sor *sor;
 272 };
 273
 274 static inline struct tegra_clk_sor_brick *to_brick(struct clk_hw *hw)
 275 {
 276         return container_of(hw, struct tegra_clk_sor_brick, hw);
 277 }
 278
 279 static const char * const tegra_clk_sor_brick_parents[] = {
 280         "pll_d2_out0", "pll_dp"
 281 };
 282
 283 static int tegra_clk_sor_brick_set_parent(struct clk_hw *hw, u8 index)
 284 {
 285         struct tegra_clk_sor_brick *brick = to_brick(hw);
 286         struct tegra_sor *sor = brick->sor;
 287         u32 value;
 288
 289         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 290         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
 291
 292         switch (index) {
 293         case 0:
 294                 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
 295                 break;
 296
 297         case 1:
 298                 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
 299                 break;
 300         }
 301
 302         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
 303
 304         return 0;
 305 }
 306
 307 static u8 tegra_clk_sor_brick_get_parent(struct clk_hw *hw)
 308 {
 309         struct tegra_clk_sor_brick *brick = to_brick(hw);
 310         struct tegra_sor *sor = brick->sor;
 311         u8 parent = U8_MAX;
 312         u32 value;
 313
 314         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 315
 316         switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) {
 317         case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK:
 318         case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK:
 319                 parent = 0;
 320                 break;
 321
 322         case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK:
 323         case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK:
 324                 parent = 1;
 325                 break;
 326         }
 327
 328         return parent;
 329 }
 330
 331 static const struct clk_ops tegra_clk_sor_brick_ops = {
 332         .set_parent = tegra_clk_sor_brick_set_parent,
 333         .get_parent = tegra_clk_sor_brick_get_parent,
 334 };
 335
 336 static struct clk *tegra_clk_sor_brick_register(struct tegra_sor *sor,
 337                                                 const char *name)
 338 {
 339         struct tegra_clk_sor_brick *brick;
 340         struct clk_init_data init;
 341         struct clk *clk;
 342
 343         brick = devm_kzalloc(sor->dev, sizeof(*brick), GFP_KERNEL);
 344         if (!brick)
 345                 return ERR_PTR(-ENOMEM);
 346
 347         brick->sor = sor;
 348
 349         init.name = name;
 350         init.flags = 0;
 351         init.parent_names = tegra_clk_sor_brick_parents;
 352         init.num_parents = ARRAY_SIZE(tegra_clk_sor_brick_parents);
 353         init.ops = &tegra_clk_sor_brick_ops;
 354
 355         brick->hw.init = &init;
 356
 357         clk = devm_clk_register(sor->dev, &brick->hw);
 358
 359         return clk;
 360 }
 361
 362 static int tegra_sor_dp_train_fast(struct tegra_sor *sor,
 363                                    struct drm_dp_link *link)
 364 {
 365         unsigned int i;
 366         u8 pattern;
 367         u32 value;
 368         int err;
 369
 370         /* setup lane parameters */
 371         value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) |
 372                 SOR_LANE_DRIVE_CURRENT_LANE2(0x40) |
 373                 SOR_LANE_DRIVE_CURRENT_LANE1(0x40) |
 374                 SOR_LANE_DRIVE_CURRENT_LANE0(0x40);
 375         tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
 376
 377         value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) |
 378                 SOR_LANE_PREEMPHASIS_LANE2(0x0f) |
 379                 SOR_LANE_PREEMPHASIS_LANE1(0x0f) |
 380                 SOR_LANE_PREEMPHASIS_LANE0(0x0f);
 381         tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
 382
 383         value = SOR_LANE_POSTCURSOR_LANE3(0x00) |
 384                 SOR_LANE_POSTCURSOR_LANE2(0x00) |
 385                 SOR_LANE_POSTCURSOR_LANE1(0x00) |
 386                 SOR_LANE_POSTCURSOR_LANE0(0x00);
 387         tegra_sor_writel(sor, value, SOR_LANE_POSTCURSOR0);
 388
 389         /* disable LVDS mode */
 390         tegra_sor_writel(sor, 0, SOR_LVDS);
 391
 392         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
 393         value |= SOR_DP_PADCTL_TX_PU_ENABLE;
 394         value &= ~SOR_DP_PADCTL_TX_PU_MASK;
 395         value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */
 396         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
 397
 398         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
 399         value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
 400                  SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0;
 401         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
 402
 403         usleep_range(10, 100);
 404
 405         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
 406         value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
 407                    SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0);
 408         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
 409
 410         err = drm_dp_aux_prepare(sor->aux, DP_SET_ANSI_8B10B);
 411         if (err < 0)
 412                 return err;
 413
 414         for (i = 0, value = 0; i < link->num_lanes; i++) {
 415                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
 416                                      SOR_DP_TPG_SCRAMBLER_NONE |
 417                                      SOR_DP_TPG_PATTERN_TRAIN1;
 418                 value = (value << 8) | lane;
 419         }
 420
 421         tegra_sor_writel(sor, value, SOR_DP_TPG);
 422
 423         pattern = DP_TRAINING_PATTERN_1;
 424
 425         err = drm_dp_aux_train(sor->aux, link, pattern);
 426         if (err < 0)
 427                 return err;
 428
 429         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
 430         value |= SOR_DP_SPARE_SEQ_ENABLE;
 431         value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
 432         value |= SOR_DP_SPARE_MACRO_SOR_CLK;
 433         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
 434
 435         for (i = 0, value = 0; i < link->num_lanes; i++) {
 436                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
 437                                      SOR_DP_TPG_SCRAMBLER_NONE |
 438                                      SOR_DP_TPG_PATTERN_TRAIN2;
 439                 value = (value << 8) | lane;
 440         }
 441
 442         tegra_sor_writel(sor, value, SOR_DP_TPG);
 443
 444         pattern = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2;
 445
 446         err = drm_dp_aux_train(sor->aux, link, pattern);
 447         if (err < 0)
 448                 return err;
 449
 450         for (i = 0, value = 0; i < link->num_lanes; i++) {
 451                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
 452                                      SOR_DP_TPG_SCRAMBLER_GALIOS |
 453                                      SOR_DP_TPG_PATTERN_NONE;
 454                 value = (value << 8) | lane;
 455         }
 456
 457         tegra_sor_writel(sor, value, SOR_DP_TPG);
 458
 459         pattern = DP_TRAINING_PATTERN_DISABLE;
 460
 461         err = drm_dp_aux_train(sor->aux, link, pattern);
 462         if (err < 0)
 463                 return err;
 464
 465         return 0;
 466 }
 467
 468 static void tegra_sor_dp_term_calibrate(struct tegra_sor *sor)
 469 {
 470         u32 mask = 0x08, adj = 0, value;
 471
 472         /* enable pad calibration logic */
 473         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
 474         value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
 475         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
 476
 477         value = tegra_sor_readl(sor, SOR_PLL1);
 478         value |= SOR_PLL1_TMDS_TERM;
 479         tegra_sor_writel(sor, value, SOR_PLL1);
 480
 481         while (mask) {
 482                 adj |= mask;
 483
 484                 value = tegra_sor_readl(sor, SOR_PLL1);
 485                 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
 486                 value |= SOR_PLL1_TMDS_TERMADJ(adj);
 487                 tegra_sor_writel(sor, value, SOR_PLL1);
 488
 489                 usleep_range(100, 200);
 490
 491                 value = tegra_sor_readl(sor, SOR_PLL1);
 492                 if (value & SOR_PLL1_TERM_COMPOUT)
 493                         adj &= ~mask;
 494
 495                 mask >>= 1;
 496         }
 497
 498         value = tegra_sor_readl(sor, SOR_PLL1);
 499         value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
 500         value |= SOR_PLL1_TMDS_TERMADJ(adj);
 501         tegra_sor_writel(sor, value, SOR_PLL1);
 502
 503         /* disable pad calibration logic */
 504         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
 505         value |= SOR_DP_PADCTL_PAD_CAL_PD;
 506         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
 507 }
 508
 509 static void tegra_sor_super_update(struct tegra_sor *sor)
 510 {
 511         tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
 512         tegra_sor_writel(sor, 1, SOR_SUPER_STATE0);
 513         tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
 514 }
 515
 516 static void tegra_sor_update(struct tegra_sor *sor)
 517 {
 518         tegra_sor_writel(sor, 0, SOR_STATE0);
 519         tegra_sor_writel(sor, 1, SOR_STATE0);
 520         tegra_sor_writel(sor, 0, SOR_STATE0);
 521 }
 522
 523 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout)
 524 {
 525         u32 value;
 526
 527         value = tegra_sor_readl(sor, SOR_PWM_DIV);
 528         value &= ~SOR_PWM_DIV_MASK;
 529         value |= 0x400; /* period */
 530         tegra_sor_writel(sor, value, SOR_PWM_DIV);
 531
 532         value = tegra_sor_readl(sor, SOR_PWM_CTL);
 533         value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK;
 534         value |= 0x400; /* duty cycle */
 535         value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */
 536         value |= SOR_PWM_CTL_TRIGGER;
 537         tegra_sor_writel(sor, value, SOR_PWM_CTL);
 538
 539         timeout = jiffies + msecs_to_jiffies(timeout);
 540
 541         while (time_before(jiffies, timeout)) {
 542                 value = tegra_sor_readl(sor, SOR_PWM_CTL);
 543                 if ((value & SOR_PWM_CTL_TRIGGER) == 0)
 544                         return 0;
 545
 546                 usleep_range(25, 100);
 547         }
 548
 549         return -ETIMEDOUT;
 550 }
 551
 552 static int tegra_sor_attach(struct tegra_sor *sor)
 553 {
 554         unsigned long value, timeout;
 555
 556         /* wake up in normal mode */
 557         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
 558         value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE;
 559         value |= SOR_SUPER_STATE_MODE_NORMAL;
 560         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
 561         tegra_sor_super_update(sor);
 562
 563         /* attach */
 564         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
 565         value |= SOR_SUPER_STATE_ATTACHED;
 566         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
 567         tegra_sor_super_update(sor);
 568
 569         timeout = jiffies + msecs_to_jiffies(250);
 570
 571         while (time_before(jiffies, timeout)) {
 572                 value = tegra_sor_readl(sor, SOR_TEST);
 573                 if ((value & SOR_TEST_ATTACHED) != 0)
 574                         return 0;
 575
 576                 usleep_range(25, 100);
 577         }
 578
 579         return -ETIMEDOUT;
 580 }
 581
 582 static int tegra_sor_wakeup(struct tegra_sor *sor)
 583 {
 584         unsigned long value, timeout;
 585
 586         timeout = jiffies + msecs_to_jiffies(250);
 587
 588         /* wait for head to wake up */
 589         while (time_before(jiffies, timeout)) {
 590                 value = tegra_sor_readl(sor, SOR_TEST);
 591                 value &= SOR_TEST_HEAD_MODE_MASK;
 592
 593                 if (value == SOR_TEST_HEAD_MODE_AWAKE)
 594                         return 0;
 595
 596                 usleep_range(25, 100);
 597         }
 598
 599         return -ETIMEDOUT;
 600 }
 601
 602 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout)
 603 {
 604         u32 value;
 605
 606         value = tegra_sor_readl(sor, SOR_PWR);
 607         value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU;
 608         tegra_sor_writel(sor, value, SOR_PWR);
 609
 610         timeout = jiffies + msecs_to_jiffies(timeout);
 611
 612         while (time_before(jiffies, timeout)) {
 613                 value = tegra_sor_readl(sor, SOR_PWR);
 614                 if ((value & SOR_PWR_TRIGGER) == 0)
 615                         return 0;
 616
 617                 usleep_range(25, 100);
 618         }
 619
 620         return -ETIMEDOUT;
 621 }
 622
 623 struct tegra_sor_params {
 624         /* number of link clocks per line */
 625         unsigned int num_clocks;
 626         /* ratio between input and output */
 627         u64 ratio;
 628         /* precision factor */
 629         u64 precision;
 630
 631         unsigned int active_polarity;
 632         unsigned int active_count;
 633         unsigned int active_frac;
 634         unsigned int tu_size;
 635         unsigned int error;
 636 };
 637
 638 static int tegra_sor_compute_params(struct tegra_sor *sor,
 639                                     struct tegra_sor_params *params,
 640                                     unsigned int tu_size)
 641 {
 642         u64 active_sym, active_count, frac, approx;
 643         u32 active_polarity, active_frac = 0;
 644         const u64 f = params->precision;
 645         s64 error;
 646
 647         active_sym = params->ratio * tu_size;
 648         active_count = div_u64(active_sym, f) * f;
 649         frac = active_sym - active_count;
 650
 651         /* fraction < 0.5 */
 652         if (frac >= (f / 2)) {
 653                 active_polarity = 1;
 654                 frac = f - frac;
 655         } else {
 656                 active_polarity = 0;
 657         }
 658
 659         if (frac != 0) {
 660                 frac = div_u64(f * f,  frac); /* 1/fraction */
 661                 if (frac <= (15 * f)) {
 662                         active_frac = div_u64(frac, f);
 663
 664                         /* round up */
 665                         if (active_polarity)
 666                                 active_frac++;
 667                 } else {
 668                         active_frac = active_polarity ? 1 : 15;
 669                 }
 670         }
 671
 672         if (active_frac == 1)
 673                 active_polarity = 0;
 674
 675         if (active_polarity == 1) {
 676                 if (active_frac) {
 677                         approx = active_count + (active_frac * (f - 1)) * f;
 678                         approx = div_u64(approx, active_frac * f);
 679                 } else {
 680                         approx = active_count + f;
 681                 }
 682         } else {
 683                 if (active_frac)
 684                         approx = active_count + div_u64(f, active_frac);
 685                 else
 686                         approx = active_count;
 687         }
 688
 689         error = div_s64(active_sym - approx, tu_size);
 690         error *= params->num_clocks;
 691
 692         if (error <= 0 && abs(error) < params->error) {
 693                 params->active_count = div_u64(active_count, f);
 694                 params->active_polarity = active_polarity;
 695                 params->active_frac = active_frac;
 696                 params->error = abs(error);
 697                 params->tu_size = tu_size;
 698
 699                 if (error == 0)
 700                         return true;
 701         }
 702
 703         return false;
 704 }
 705
 706 static int tegra_sor_compute_config(struct tegra_sor *sor,
 707                                     const struct drm_display_mode *mode,
 708                                     struct tegra_sor_config *config,
 709                                     struct drm_dp_link *link)
 710 {
 711         const u64 f = 100000, link_rate = link->rate * 1000;
 712         const u64 pclk = mode->clock * 1000;
 713         u64 input, output, watermark, num;
 714         struct tegra_sor_params params;
 715         u32 num_syms_per_line;
 716         unsigned int i;
 717
 718         if (!link_rate || !link->num_lanes || !pclk || !config->bits_per_pixel)
 719                 return -EINVAL;
 720
 721         output = link_rate * 8 * link->num_lanes;
 722         input = pclk * config->bits_per_pixel;
 723
 724         if (input >= output)
 725                 return -ERANGE;
 726
 727         memset(&params, 0, sizeof(params));
 728         params.ratio = div64_u64(input * f, output);
 729         params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk);
 730         params.precision = f;
 731         params.error = 64 * f;
 732         params.tu_size = 64;
 733
 734         for (i = params.tu_size; i >= 32; i--)
 735                 if (tegra_sor_compute_params(sor, &params, i))
 736                         break;
 737
 738         if (params.active_frac == 0) {
 739                 config->active_polarity = 0;
 740                 config->active_count = params.active_count;
 741
 742                 if (!params.active_polarity)
 743                         config->active_count--;
 744
 745                 config->tu_size = params.tu_size;
 746                 config->active_frac = 1;
 747         } else {
 748                 config->active_polarity = params.active_polarity;
 749                 config->active_count = params.active_count;
 750                 config->active_frac = params.active_frac;
 751                 config->tu_size = params.tu_size;
 752         }
 753
 754         dev_dbg(sor->dev,
 755                 "polarity: %d active count: %d tu size: %d active frac: %d\n",
 756                 config->active_polarity, config->active_count,
 757                 config->tu_size, config->active_frac);
 758
 759         watermark = params.ratio * config->tu_size * (f - params.ratio);
 760         watermark = div_u64(watermark, f);
 761
 762         watermark = div_u64(watermark + params.error, f);
 763         config->watermark = watermark + (config->bits_per_pixel / 8) + 2;
 764         num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) *
 765                             (link->num_lanes * 8);
 766
 767         if (config->watermark > 30) {
 768                 config->watermark = 30;
 769                 dev_err(sor->dev,
 770                         "unable to compute TU size, forcing watermark to %u\n",
 771                         config->watermark);
 772         } else if (config->watermark > num_syms_per_line) {
 773                 config->watermark = num_syms_per_line;
 774                 dev_err(sor->dev, "watermark too high, forcing to %u\n",
 775                         config->watermark);
 776         }
 777
 778         /* compute the number of symbols per horizontal blanking interval */
 779         num = ((mode->htotal - mode->hdisplay) - 7) * link_rate;
 780         config->hblank_symbols = div_u64(num, pclk);
 781
 782         if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
 783                 config->hblank_symbols -= 3;
 784
 785         config->hblank_symbols -= 12 / link->num_lanes;
 786
 787         /* compute the number of symbols per vertical blanking interval */
 788         num = (mode->hdisplay - 25) * link_rate;
 789         config->vblank_symbols = div_u64(num, pclk);
 790         config->vblank_symbols -= 36 / link->num_lanes + 4;
 791
 792         dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols,
 793                 config->vblank_symbols);
 794
 795         return 0;
 796 }
 797
 798 static void tegra_sor_apply_config(struct tegra_sor *sor,
 799                                    const struct tegra_sor_config *config)
 800 {
 801         u32 value;
 802
 803         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
 804         value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK;
 805         value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size);
 806         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
 807
 808         value = tegra_sor_readl(sor, SOR_DP_CONFIG0);
 809         value &= ~SOR_DP_CONFIG_WATERMARK_MASK;
 810         value |= SOR_DP_CONFIG_WATERMARK(config->watermark);
 811
 812         value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK;
 813         value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count);
 814
 815         value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK;
 816         value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac);
 817
 818         if (config->active_polarity)
 819                 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
 820         else
 821                 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
 822
 823         value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE;
 824         value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE;
 825         tegra_sor_writel(sor, value, SOR_DP_CONFIG0);
 826
 827         value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS);
 828         value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK;
 829         value |= config->hblank_symbols & 0xffff;
 830         tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);
 831
 832         value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS);
 833         value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK;
 834         value |= config->vblank_symbols & 0xffff;
 835         tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
 836 }
 837
 838 static void tegra_sor_mode_set(struct tegra_sor *sor,
 839                                const struct drm_display_mode *mode,
 840                                struct tegra_sor_state *state)
 841 {
 842         struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc);
 843         unsigned int vbe, vse, hbe, hse, vbs, hbs;
 844         u32 value;
 845
 846         value = tegra_sor_readl(sor, SOR_STATE1);
 847         value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK;
 848         value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
 849         value &= ~SOR_STATE_ASY_OWNER_MASK;
 850
 851         value |= SOR_STATE_ASY_CRC_MODE_COMPLETE |
 852                  SOR_STATE_ASY_OWNER(dc->pipe + 1);
 853
 854         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
 855                 value &= ~SOR_STATE_ASY_HSYNCPOL;
 856
 857         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 858                 value |= SOR_STATE_ASY_HSYNCPOL;
 859
 860         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 861                 value &= ~SOR_STATE_ASY_VSYNCPOL;
 862
 863         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 864                 value |= SOR_STATE_ASY_VSYNCPOL;
 865
 866         switch (state->bpc) {
 867         case 16:
 868                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444;
 869                 break;
 870
 871         case 12:
 872                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444;
 873                 break;
 874
 875         case 10:
 876                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444;
 877                 break;
 878
 879         case 8:
 880                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
 881                 break;
 882
 883         case 6:
 884                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444;
 885                 break;
 886
 887         default:
 888                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
 889                 break;
 890         }
 891
 892         tegra_sor_writel(sor, value, SOR_STATE1);
 893
 894         /*
 895          * TODO: The video timing programming below doesn't seem to match the
 896          * register definitions.
 897          */
 898
 899         value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
 900         tegra_sor_writel(sor, value, SOR_HEAD_STATE1(dc->pipe));
 901
 902         /* sync end = sync width - 1 */
 903         vse = mode->vsync_end - mode->vsync_start - 1;
 904         hse = mode->hsync_end - mode->hsync_start - 1;
 905
 906         value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
 907         tegra_sor_writel(sor, value, SOR_HEAD_STATE2(dc->pipe));
 908
 909         /* blank end = sync end + back porch */
 910         vbe = vse + (mode->vtotal - mode->vsync_end);
 911         hbe = hse + (mode->htotal - mode->hsync_end);
 912
 913         value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
 914         tegra_sor_writel(sor, value, SOR_HEAD_STATE3(dc->pipe));
 915
 916         /* blank start = blank end + active */
 917         vbs = vbe + mode->vdisplay;
 918         hbs = hbe + mode->hdisplay;
 919
 920         value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
 921         tegra_sor_writel(sor, value, SOR_HEAD_STATE4(dc->pipe));
 922
 923         /* XXX interlacing support */
 924         tegra_sor_writel(sor, 0x001, SOR_HEAD_STATE5(dc->pipe));
 925 }
 926
 927 static int tegra_sor_detach(struct tegra_sor *sor)
 928 {
 929         unsigned long value, timeout;
 930
 931         /* switch to safe mode */
 932         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
 933         value &= ~SOR_SUPER_STATE_MODE_NORMAL;
 934         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
 935         tegra_sor_super_update(sor);
 936
 937         timeout = jiffies + msecs_to_jiffies(250);
 938
 939         while (time_before(jiffies, timeout)) {
 940                 value = tegra_sor_readl(sor, SOR_PWR);
 941                 if (value & SOR_PWR_MODE_SAFE)
 942                         break;
 943         }
 944
 945         if ((value & SOR_PWR_MODE_SAFE) == 0)
 946                 return -ETIMEDOUT;
 947
 948         /* go to sleep */
 949         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
 950         value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK;
 951         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
 952         tegra_sor_super_update(sor);
 953
 954         /* detach */
 955         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
 956         value &= ~SOR_SUPER_STATE_ATTACHED;
 957         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
 958         tegra_sor_super_update(sor);
 959
 960         timeout = jiffies + msecs_to_jiffies(250);
 961
 962         while (time_before(jiffies, timeout)) {
 963                 value = tegra_sor_readl(sor, SOR_TEST);
 964                 if ((value & SOR_TEST_ATTACHED) == 0)
 965                         break;
 966
 967                 usleep_range(25, 100);
 968         }
 969
 970         if ((value & SOR_TEST_ATTACHED) != 0)
 971                 return -ETIMEDOUT;
 972
 973         return 0;
 974 }
 975
 976 static int tegra_sor_power_down(struct tegra_sor *sor)
 977 {
 978         unsigned long value, timeout;
 979         int err;
 980
 981         value = tegra_sor_readl(sor, SOR_PWR);
 982         value &= ~SOR_PWR_NORMAL_STATE_PU;
 983         value |= SOR_PWR_TRIGGER;
 984         tegra_sor_writel(sor, value, SOR_PWR);
 985
 986         timeout = jiffies + msecs_to_jiffies(250);
 987
 988         while (time_before(jiffies, timeout)) {
 989                 value = tegra_sor_readl(sor, SOR_PWR);
 990                 if ((value & SOR_PWR_TRIGGER) == 0)
 991                         return 0;
 992
 993                 usleep_range(25, 100);
 994         }
 995
 996         if ((value & SOR_PWR_TRIGGER) != 0)
 997                 return -ETIMEDOUT;
 998
 999         /* switch to safe parent clock */
1000         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1001         if (err < 0)
1002                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1003
1004         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
1005         value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
1006                    SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2);
1007         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
1008
1009         /* stop lane sequencer */
1010         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
1011                 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
1012         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
1013
1014         timeout = jiffies + msecs_to_jiffies(250);
1015
1016         while (time_before(jiffies, timeout)) {
1017                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
1018                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
1019                         break;
1020
1021                 usleep_range(25, 100);
1022         }
1023
1024         if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
1025                 return -ETIMEDOUT;
1026
1027         value = tegra_sor_readl(sor, SOR_PLL2);
1028         value |= SOR_PLL2_PORT_POWERDOWN;
1029         tegra_sor_writel(sor, value, SOR_PLL2);
1030
1031         usleep_range(20, 100);
1032
1033         value = tegra_sor_readl(sor, SOR_PLL0);
1034         value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1035         tegra_sor_writel(sor, value, SOR_PLL0);
1036
1037         value = tegra_sor_readl(sor, SOR_PLL2);
1038         value |= SOR_PLL2_SEQ_PLLCAPPD;
1039         value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1040         tegra_sor_writel(sor, value, SOR_PLL2);
1041
1042         usleep_range(20, 100);
1043
1044         return 0;
1045 }
1046
1047 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout)
1048 {
1049         u32 value;
1050
1051         timeout = jiffies + msecs_to_jiffies(timeout);
1052
1053         while (time_before(jiffies, timeout)) {
1054                 value = tegra_sor_readl(sor, SOR_CRCA);
1055                 if (value & SOR_CRCA_VALID)
1056                         return 0;
1057
1058                 usleep_range(100, 200);
1059         }
1060
1061         return -ETIMEDOUT;
1062 }
1063
1064 static int tegra_sor_show_crc(struct seq_file *s, void *data)
1065 {
1066         struct drm_info_node *node = s->private;
1067         struct tegra_sor *sor = node->info_ent->data;
1068         struct drm_crtc *crtc = sor->output.encoder.crtc;
1069         struct drm_device *drm = node->minor->dev;
1070         int err = 0;
1071         u32 value;
1072
1073         drm_modeset_lock_all(drm);
1074
1075         if (!crtc || !crtc->state->active) {
1076                 err = -EBUSY;
1077                 goto unlock;
1078         }
1079
1080         value = tegra_sor_readl(sor, SOR_STATE1);
1081         value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1082         tegra_sor_writel(sor, value, SOR_STATE1);
1083
1084         value = tegra_sor_readl(sor, SOR_CRC_CNTRL);
1085         value |= SOR_CRC_CNTRL_ENABLE;
1086         tegra_sor_writel(sor, value, SOR_CRC_CNTRL);
1087
1088         value = tegra_sor_readl(sor, SOR_TEST);
1089         value &= ~SOR_TEST_CRC_POST_SERIALIZE;
1090         tegra_sor_writel(sor, value, SOR_TEST);
1091
1092         err = tegra_sor_crc_wait(sor, 100);
1093         if (err < 0)
1094                 goto unlock;
1095
1096         tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA);
1097         value = tegra_sor_readl(sor, SOR_CRCB);
1098
1099         seq_printf(s, "%08x\n", value);
1100
1101 unlock:
1102         drm_modeset_unlock_all(drm);
1103         return err;
1104 }
1105
1106 static int tegra_sor_show_regs(struct seq_file *s, void *data)
1107 {
1108         struct drm_info_node *node = s->private;
1109         struct tegra_sor *sor = node->info_ent->data;
1110         struct drm_crtc *crtc = sor->output.encoder.crtc;
1111         struct drm_device *drm = node->minor->dev;
1112         int err = 0;
1113
1114         drm_modeset_lock_all(drm);
1115
1116         if (!crtc || !crtc->state->active) {
1117                 err = -EBUSY;
1118                 goto unlock;
1119         }
1120
1121 #define DUMP_REG(name)                                          \
1122         seq_printf(s, "%-38s %#05x %08x\n", #name, name,        \
1123                    tegra_sor_readl(sor, name))
1124
1125         DUMP_REG(SOR_CTXSW);
1126         DUMP_REG(SOR_SUPER_STATE0);
1127         DUMP_REG(SOR_SUPER_STATE1);
1128         DUMP_REG(SOR_STATE0);
1129         DUMP_REG(SOR_STATE1);
1130         DUMP_REG(SOR_HEAD_STATE0(0));
1131         DUMP_REG(SOR_HEAD_STATE0(1));
1132         DUMP_REG(SOR_HEAD_STATE1(0));
1133         DUMP_REG(SOR_HEAD_STATE1(1));
1134         DUMP_REG(SOR_HEAD_STATE2(0));
1135         DUMP_REG(SOR_HEAD_STATE2(1));
1136         DUMP_REG(SOR_HEAD_STATE3(0));
1137         DUMP_REG(SOR_HEAD_STATE3(1));
1138         DUMP_REG(SOR_HEAD_STATE4(0));
1139         DUMP_REG(SOR_HEAD_STATE4(1));
1140         DUMP_REG(SOR_HEAD_STATE5(0));
1141         DUMP_REG(SOR_HEAD_STATE5(1));
1142         DUMP_REG(SOR_CRC_CNTRL);
1143         DUMP_REG(SOR_DP_DEBUG_MVID);
1144         DUMP_REG(SOR_CLK_CNTRL);
1145         DUMP_REG(SOR_CAP);
1146         DUMP_REG(SOR_PWR);
1147         DUMP_REG(SOR_TEST);
1148         DUMP_REG(SOR_PLL0);
1149         DUMP_REG(SOR_PLL1);
1150         DUMP_REG(SOR_PLL2);
1151         DUMP_REG(SOR_PLL3);
1152         DUMP_REG(SOR_CSTM);
1153         DUMP_REG(SOR_LVDS);
1154         DUMP_REG(SOR_CRCA);
1155         DUMP_REG(SOR_CRCB);
1156         DUMP_REG(SOR_BLANK);
1157         DUMP_REG(SOR_SEQ_CTL);
1158         DUMP_REG(SOR_LANE_SEQ_CTL);
1159         DUMP_REG(SOR_SEQ_INST(0));
1160         DUMP_REG(SOR_SEQ_INST(1));
1161         DUMP_REG(SOR_SEQ_INST(2));
1162         DUMP_REG(SOR_SEQ_INST(3));
1163         DUMP_REG(SOR_SEQ_INST(4));
1164         DUMP_REG(SOR_SEQ_INST(5));
1165         DUMP_REG(SOR_SEQ_INST(6));
1166         DUMP_REG(SOR_SEQ_INST(7));
1167         DUMP_REG(SOR_SEQ_INST(8));
1168         DUMP_REG(SOR_SEQ_INST(9));
1169         DUMP_REG(SOR_SEQ_INST(10));
1170         DUMP_REG(SOR_SEQ_INST(11));
1171         DUMP_REG(SOR_SEQ_INST(12));
1172         DUMP_REG(SOR_SEQ_INST(13));
1173         DUMP_REG(SOR_SEQ_INST(14));
1174         DUMP_REG(SOR_SEQ_INST(15));
1175         DUMP_REG(SOR_PWM_DIV);
1176         DUMP_REG(SOR_PWM_CTL);
1177         DUMP_REG(SOR_VCRC_A0);
1178         DUMP_REG(SOR_VCRC_A1);
1179         DUMP_REG(SOR_VCRC_B0);
1180         DUMP_REG(SOR_VCRC_B1);
1181         DUMP_REG(SOR_CCRC_A0);
1182         DUMP_REG(SOR_CCRC_A1);
1183         DUMP_REG(SOR_CCRC_B0);
1184         DUMP_REG(SOR_CCRC_B1);
1185         DUMP_REG(SOR_EDATA_A0);
1186         DUMP_REG(SOR_EDATA_A1);
1187         DUMP_REG(SOR_EDATA_B0);
1188         DUMP_REG(SOR_EDATA_B1);
1189         DUMP_REG(SOR_COUNT_A0);
1190         DUMP_REG(SOR_COUNT_A1);
1191         DUMP_REG(SOR_COUNT_B0);
1192         DUMP_REG(SOR_COUNT_B1);
1193         DUMP_REG(SOR_DEBUG_A0);
1194         DUMP_REG(SOR_DEBUG_A1);
1195         DUMP_REG(SOR_DEBUG_B0);
1196         DUMP_REG(SOR_DEBUG_B1);
1197         DUMP_REG(SOR_TRIG);
1198         DUMP_REG(SOR_MSCHECK);
1199         DUMP_REG(SOR_XBAR_CTRL);
1200         DUMP_REG(SOR_XBAR_POL);
1201         DUMP_REG(SOR_DP_LINKCTL0);
1202         DUMP_REG(SOR_DP_LINKCTL1);
1203         DUMP_REG(SOR_LANE_DRIVE_CURRENT0);
1204         DUMP_REG(SOR_LANE_DRIVE_CURRENT1);
1205         DUMP_REG(SOR_LANE4_DRIVE_CURRENT0);
1206         DUMP_REG(SOR_LANE4_DRIVE_CURRENT1);
1207         DUMP_REG(SOR_LANE_PREEMPHASIS0);
1208         DUMP_REG(SOR_LANE_PREEMPHASIS1);
1209         DUMP_REG(SOR_LANE4_PREEMPHASIS0);
1210         DUMP_REG(SOR_LANE4_PREEMPHASIS1);
1211         DUMP_REG(SOR_LANE_POSTCURSOR0);
1212         DUMP_REG(SOR_LANE_POSTCURSOR1);
1213         DUMP_REG(SOR_DP_CONFIG0);
1214         DUMP_REG(SOR_DP_CONFIG1);
1215         DUMP_REG(SOR_DP_MN0);
1216         DUMP_REG(SOR_DP_MN1);
1217         DUMP_REG(SOR_DP_PADCTL0);
1218         DUMP_REG(SOR_DP_PADCTL1);
1219         DUMP_REG(SOR_DP_DEBUG0);
1220         DUMP_REG(SOR_DP_DEBUG1);
1221         DUMP_REG(SOR_DP_SPARE0);
1222         DUMP_REG(SOR_DP_SPARE1);
1223         DUMP_REG(SOR_DP_AUDIO_CTRL);
1224         DUMP_REG(SOR_DP_AUDIO_HBLANK_SYMBOLS);
1225         DUMP_REG(SOR_DP_AUDIO_VBLANK_SYMBOLS);
1226         DUMP_REG(SOR_DP_GENERIC_INFOFRAME_HEADER);
1227         DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK0);
1228         DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK1);
1229         DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK2);
1230         DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK3);
1231         DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK4);
1232         DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK5);
1233         DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK6);
1234         DUMP_REG(SOR_DP_TPG);
1235         DUMP_REG(SOR_DP_TPG_CONFIG);
1236         DUMP_REG(SOR_DP_LQ_CSTM0);
1237         DUMP_REG(SOR_DP_LQ_CSTM1);
1238         DUMP_REG(SOR_DP_LQ_CSTM2);
1239
1240 #undef DUMP_REG
1241
1242 unlock:
1243         drm_modeset_unlock_all(drm);
1244         return err;
1245 }
1246
1247 static const struct drm_info_list debugfs_files[] = {
1248         { "crc", tegra_sor_show_crc, 0, NULL },
1249         { "regs", tegra_sor_show_regs, 0, NULL },
1250 };
1251
1252 static int tegra_sor_debugfs_init(struct tegra_sor *sor,
1253                                   struct drm_minor *minor)
1254 {
1255         const char *name = sor->soc->supports_dp ? "sor1" : "sor";
1256         unsigned int i;
1257         int err;
1258
1259         sor->debugfs = debugfs_create_dir(name, minor->debugfs_root);
1260         if (!sor->debugfs)
1261                 return -ENOMEM;
1262
1263         sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1264                                      GFP_KERNEL);
1265         if (!sor->debugfs_files) {
1266                 err = -ENOMEM;
1267                 goto remove;
1268         }
1269
1270         for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1271                 sor->debugfs_files[i].data = sor;
1272
1273         err = drm_debugfs_create_files(sor->debugfs_files,
1274                                        ARRAY_SIZE(debugfs_files),
1275                                        sor->debugfs, minor);
1276         if (err < 0)
1277                 goto free;
1278
1279         sor->minor = minor;
1280
1281         return 0;
1282
1283 free:
1284         kfree(sor->debugfs_files);
1285         sor->debugfs_files = NULL;
1286 remove:
1287         debugfs_remove_recursive(sor->debugfs);
1288         sor->debugfs = NULL;
1289         return err;
1290 }
1291
1292 static void tegra_sor_debugfs_exit(struct tegra_sor *sor)
1293 {
1294         drm_debugfs_remove_files(sor->debugfs_files, ARRAY_SIZE(debugfs_files),
1295                                  sor->minor);
1296         sor->minor = NULL;
1297
1298         kfree(sor->debugfs_files);
1299         sor->debugfs_files = NULL;
1300
1301         debugfs_remove_recursive(sor->debugfs);
1302         sor->debugfs = NULL;
1303 }
1304
1305 static void tegra_sor_connector_reset(struct drm_connector *connector)
1306 {
1307         struct tegra_sor_state *state;
1308
1309         state = kzalloc(sizeof(*state), GFP_KERNEL);
1310         if (!state)
1311                 return;
1312
1313         if (connector->state) {
1314                 __drm_atomic_helper_connector_destroy_state(connector->state);
1315                 kfree(connector->state);
1316         }
1317
1318         __drm_atomic_helper_connector_reset(connector, &state->base);
1319 }
1320
1321 static enum drm_connector_status
1322 tegra_sor_connector_detect(struct drm_connector *connector, bool force)
1323 {
1324         struct tegra_output *output = connector_to_output(connector);
1325         struct tegra_sor *sor = to_sor(output);
1326
1327         if (sor->aux)
1328                 return drm_dp_aux_detect(sor->aux);
1329
1330         return tegra_output_connector_detect(connector, force);
1331 }
1332
1333 static struct drm_connector_state *
1334 tegra_sor_connector_duplicate_state(struct drm_connector *connector)
1335 {
1336         struct tegra_sor_state *state = to_sor_state(connector->state);
1337         struct tegra_sor_state *copy;
1338
1339         copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
1340         if (!copy)
1341                 return NULL;
1342
1343         __drm_atomic_helper_connector_duplicate_state(connector, &copy->base);
1344
1345         return &copy->base;
1346 }
1347
1348 static const struct drm_connector_funcs tegra_sor_connector_funcs = {
1349         .reset = tegra_sor_connector_reset,
1350         .detect = tegra_sor_connector_detect,
1351         .fill_modes = drm_helper_probe_single_connector_modes,
1352         .destroy = tegra_output_connector_destroy,
1353         .atomic_duplicate_state = tegra_sor_connector_duplicate_state,
1354         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1355 };
1356
1357 static int tegra_sor_connector_get_modes(struct drm_connector *connector)
1358 {
1359         struct tegra_output *output = connector_to_output(connector);
1360         struct tegra_sor *sor = to_sor(output);
1361         int err;
1362
1363         if (sor->aux)
1364                 drm_dp_aux_enable(sor->aux);
1365
1366         err = tegra_output_connector_get_modes(connector);
1367
1368         if (sor->aux)
1369                 drm_dp_aux_disable(sor->aux);
1370
1371         return err;
1372 }
1373
1374 static enum drm_mode_status
1375 tegra_sor_connector_mode_valid(struct drm_connector *connector,
1376                                struct drm_display_mode *mode)
1377 {
1378         /* HDMI 2.0 modes are not yet supported */
1379         if (mode->clock > 340000)
1380                 return MODE_NOCLOCK;
1381
1382         return MODE_OK;
1383 }
1384
1385 static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = {
1386         .get_modes = tegra_sor_connector_get_modes,
1387         .mode_valid = tegra_sor_connector_mode_valid,
1388 };
1389
1390 static const struct drm_encoder_funcs tegra_sor_encoder_funcs = {
1391         .destroy = tegra_output_encoder_destroy,
1392 };
1393
1394 static void tegra_sor_edp_disable(struct drm_encoder *encoder)
1395 {
1396         struct tegra_output *output = encoder_to_output(encoder);
1397         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1398         struct tegra_sor *sor = to_sor(output);
1399         u32 value;
1400         int err;
1401
1402         if (output->panel)
1403                 drm_panel_disable(output->panel);
1404
1405         err = tegra_sor_detach(sor);
1406         if (err < 0)
1407                 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
1408
1409         tegra_sor_writel(sor, 0, SOR_STATE1);
1410         tegra_sor_update(sor);
1411
1412         /*
1413          * The following accesses registers of the display controller, so make
1414          * sure it's only executed when the output is attached to one.
1415          */
1416         if (dc) {
1417                 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1418                 value &= ~SOR_ENABLE;
1419                 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1420
1421                 tegra_dc_commit(dc);
1422         }
1423
1424         err = tegra_sor_power_down(sor);
1425         if (err < 0)
1426                 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
1427
1428         if (sor->aux) {
1429                 err = drm_dp_aux_disable(sor->aux);
1430                 if (err < 0)
1431                         dev_err(sor->dev, "failed to disable DP: %d\n", err);
1432         }
1433
1434         err = tegra_io_rail_power_off(TEGRA_IO_RAIL_LVDS);
1435         if (err < 0)
1436                 dev_err(sor->dev, "failed to power off I/O rail: %d\n", err);
1437
1438         if (output->panel)
1439                 drm_panel_unprepare(output->panel);
1440
1441         pm_runtime_put(sor->dev);
1442 }
1443
1444 #if 0
1445 static int calc_h_ref_to_sync(const struct drm_display_mode *mode,
1446                               unsigned int *value)
1447 {
1448         unsigned int hfp, hsw, hbp, a = 0, b;
1449
1450         hfp = mode->hsync_start - mode->hdisplay;
1451         hsw = mode->hsync_end - mode->hsync_start;
1452         hbp = mode->htotal - mode->hsync_end;
1453
1454         pr_info("hfp: %u, hsw: %u, hbp: %u\n", hfp, hsw, hbp);
1455
1456         b = hfp - 1;
1457
1458         pr_info("a: %u, b: %u\n", a, b);
1459         pr_info("a + hsw + hbp = %u\n", a + hsw + hbp);
1460
1461         if (a + hsw + hbp <= 11) {
1462                 a = 1 + 11 - hsw - hbp;
1463                 pr_info("a: %u\n", a);
1464         }
1465
1466         if (a > b)
1467                 return -EINVAL;
1468
1469         if (hsw < 1)
1470                 return -EINVAL;
1471
1472         if (mode->hdisplay < 16)
1473                 return -EINVAL;
1474
1475         if (value) {
1476                 if (b > a && a % 2)
1477                         *value = a + 1;
1478                 else
1479                         *value = a;
1480         }
1481
1482         return 0;
1483 }
1484 #endif
1485
1486 static void tegra_sor_edp_enable(struct drm_encoder *encoder)
1487 {
1488         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1489         struct tegra_output *output = encoder_to_output(encoder);
1490         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1491         struct tegra_sor *sor = to_sor(output);
1492         struct tegra_sor_config config;
1493         struct tegra_sor_state *state;
1494         struct drm_dp_link link;
1495         u8 rate, lanes;
1496         unsigned int i;
1497         int err = 0;
1498         u32 value;
1499
1500         state = to_sor_state(output->connector.state);
1501
1502         pm_runtime_get_sync(sor->dev);
1503
1504         if (output->panel)
1505                 drm_panel_prepare(output->panel);
1506
1507         err = drm_dp_aux_enable(sor->aux);
1508         if (err < 0)
1509                 dev_err(sor->dev, "failed to enable DP: %d\n", err);
1510
1511         err = drm_dp_link_probe(sor->aux, &link);
1512         if (err < 0) {
1513                 dev_err(sor->dev, "failed to probe eDP link: %d\n", err);
1514                 return;
1515         }
1516
1517         /* switch to safe parent clock */
1518         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1519         if (err < 0)
1520                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1521
1522         memset(&config, 0, sizeof(config));
1523         config.bits_per_pixel = state->bpc * 3;
1524
1525         err = tegra_sor_compute_config(sor, mode, &config, &link);
1526         if (err < 0)
1527                 dev_err(sor->dev, "failed to compute configuration: %d\n", err);
1528
1529         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1530         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
1531         value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
1532         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1533
1534         value = tegra_sor_readl(sor, SOR_PLL2);
1535         value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
1536         tegra_sor_writel(sor, value, SOR_PLL2);
1537         usleep_range(20, 100);
1538
1539         value = tegra_sor_readl(sor, SOR_PLL3);
1540         value |= SOR_PLL3_PLL_VDD_MODE_3V3;
1541         tegra_sor_writel(sor, value, SOR_PLL3);
1542
1543         value = SOR_PLL0_ICHPMP(0xf) | SOR_PLL0_VCOCAP_RST |
1544                 SOR_PLL0_PLLREG_LEVEL_V45 | SOR_PLL0_RESISTOR_EXT;
1545         tegra_sor_writel(sor, value, SOR_PLL0);
1546
1547         value = tegra_sor_readl(sor, SOR_PLL2);
1548         value |= SOR_PLL2_SEQ_PLLCAPPD;
1549         value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1550         value |= SOR_PLL2_LVDS_ENABLE;
1551         tegra_sor_writel(sor, value, SOR_PLL2);
1552
1553         value = SOR_PLL1_TERM_COMPOUT | SOR_PLL1_TMDS_TERM;
1554         tegra_sor_writel(sor, value, SOR_PLL1);
1555
1556         while (true) {
1557                 value = tegra_sor_readl(sor, SOR_PLL2);
1558                 if ((value & SOR_PLL2_SEQ_PLLCAPPD_ENFORCE) == 0)
1559                         break;
1560
1561                 usleep_range(250, 1000);
1562         }
1563
1564         value = tegra_sor_readl(sor, SOR_PLL2);
1565         value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
1566         value &= ~SOR_PLL2_PORT_POWERDOWN;
1567         tegra_sor_writel(sor, value, SOR_PLL2);
1568
1569         /*
1570          * power up
1571          */
1572
1573         /* set safe link bandwidth (1.62 Gbps) */
1574         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1575         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1576         value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62;
1577         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1578
1579         /* step 1 */
1580         value = tegra_sor_readl(sor, SOR_PLL2);
1581         value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL2_PORT_POWERDOWN |
1582                  SOR_PLL2_BANDGAP_POWERDOWN;
1583         tegra_sor_writel(sor, value, SOR_PLL2);
1584
1585         value = tegra_sor_readl(sor, SOR_PLL0);
1586         value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1587         tegra_sor_writel(sor, value, SOR_PLL0);
1588
1589         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
1590         value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
1591         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
1592
1593         /* step 2 */
1594         err = tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS);
1595         if (err < 0)
1596                 dev_err(sor->dev, "failed to power on I/O rail: %d\n", err);
1597
1598         usleep_range(5, 100);
1599
1600         /* step 3 */
1601         value = tegra_sor_readl(sor, SOR_PLL2);
1602         value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
1603         tegra_sor_writel(sor, value, SOR_PLL2);
1604
1605         usleep_range(20, 100);
1606
1607         /* step 4 */
1608         value = tegra_sor_readl(sor, SOR_PLL0);
1609         value &= ~SOR_PLL0_VCOPD;
1610         value &= ~SOR_PLL0_PWR;
1611         tegra_sor_writel(sor, value, SOR_PLL0);
1612
1613         value = tegra_sor_readl(sor, SOR_PLL2);
1614         value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1615         tegra_sor_writel(sor, value, SOR_PLL2);
1616
1617         usleep_range(200, 1000);
1618
1619         /* step 5 */
1620         value = tegra_sor_readl(sor, SOR_PLL2);
1621         value &= ~SOR_PLL2_PORT_POWERDOWN;
1622         tegra_sor_writel(sor, value, SOR_PLL2);
1623
1624         /* XXX not in TRM */
1625         for (value = 0, i = 0; i < 5; i++)
1626                 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) |
1627                          SOR_XBAR_CTRL_LINK1_XSEL(i, i);
1628
1629         tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
1630         tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
1631
1632         /* switch to DP parent clock */
1633         err = tegra_sor_set_parent_clock(sor, sor->clk_dp);
1634         if (err < 0)
1635                 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
1636
1637         /* power DP lanes */
1638         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
1639
1640         if (link.num_lanes <= 2)
1641                 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2);
1642         else
1643                 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2;
1644
1645         if (link.num_lanes <= 1)
1646                 value &= ~SOR_DP_PADCTL_PD_TXD_1;
1647         else
1648                 value |= SOR_DP_PADCTL_PD_TXD_1;
1649
1650         if (link.num_lanes == 0)
1651                 value &= ~SOR_DP_PADCTL_PD_TXD_0;
1652         else
1653                 value |= SOR_DP_PADCTL_PD_TXD_0;
1654
1655         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
1656
1657         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1658         value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
1659         value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes);
1660         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1661
1662         /* start lane sequencer */
1663         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
1664                 SOR_LANE_SEQ_CTL_POWER_STATE_UP;
1665         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
1666
1667         while (true) {
1668                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
1669                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
1670                         break;
1671
1672                 usleep_range(250, 1000);
1673         }
1674
1675         /* set link bandwidth */
1676         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1677         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1678         value |= drm_dp_link_rate_to_bw_code(link.rate) << 2;
1679         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1680
1681         tegra_sor_apply_config(sor, &config);
1682
1683         /* enable link */
1684         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1685         value |= SOR_DP_LINKCTL_ENABLE;
1686         value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
1687         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1688
1689         for (i = 0, value = 0; i < 4; i++) {
1690                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
1691                                      SOR_DP_TPG_SCRAMBLER_GALIOS |
1692                                      SOR_DP_TPG_PATTERN_NONE;
1693                 value = (value << 8) | lane;
1694         }
1695
1696         tegra_sor_writel(sor, value, SOR_DP_TPG);
1697
1698         /* enable pad calibration logic */
1699         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
1700         value |= SOR_DP_PADCTL_PAD_CAL_PD;
1701         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
1702
1703         err = drm_dp_link_probe(sor->aux, &link);
1704         if (err < 0)
1705                 dev_err(sor->dev, "failed to probe eDP link: %d\n", err);
1706
1707         err = drm_dp_link_power_up(sor->aux, &link);
1708         if (err < 0)
1709                 dev_err(sor->dev, "failed to power up eDP link: %d\n", err);
1710
1711         err = drm_dp_link_configure(sor->aux, &link);
1712         if (err < 0)
1713                 dev_err(sor->dev, "failed to configure eDP link: %d\n", err);
1714
1715         rate = drm_dp_link_rate_to_bw_code(link.rate);
1716         lanes = link.num_lanes;
1717
1718         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1719         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1720         value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
1721         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1722
1723         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1724         value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
1725         value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
1726
1727         if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
1728                 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
1729
1730         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1731
1732         /* disable training pattern generator */
1733
1734         for (i = 0; i < link.num_lanes; i++) {
1735                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
1736                                      SOR_DP_TPG_SCRAMBLER_GALIOS |
1737                                      SOR_DP_TPG_PATTERN_NONE;
1738                 value = (value << 8) | lane;
1739         }
1740
1741         tegra_sor_writel(sor, value, SOR_DP_TPG);
1742
1743         err = tegra_sor_dp_train_fast(sor, &link);
1744         if (err < 0)
1745                 dev_err(sor->dev, "DP fast link training failed: %d\n", err);
1746
1747         dev_dbg(sor->dev, "fast link training succeeded\n");
1748
1749         err = tegra_sor_power_up(sor, 250);
1750         if (err < 0)
1751                 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
1752
1753         /* CSTM (LVDS, link A/B, upper) */
1754         value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |
1755                 SOR_CSTM_UPPER;
1756         tegra_sor_writel(sor, value, SOR_CSTM);
1757
1758         /* use DP-A protocol */
1759         value = tegra_sor_readl(sor, SOR_STATE1);
1760         value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
1761         value |= SOR_STATE_ASY_PROTOCOL_DP_A;
1762         tegra_sor_writel(sor, value, SOR_STATE1);
1763
1764         tegra_sor_mode_set(sor, mode, state);
1765
1766         /* PWM setup */
1767         err = tegra_sor_setup_pwm(sor, 250);
1768         if (err < 0)
1769                 dev_err(sor->dev, "failed to setup PWM: %d\n", err);
1770
1771         tegra_sor_update(sor);
1772
1773         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1774         value |= SOR_ENABLE;
1775         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1776
1777         tegra_dc_commit(dc);
1778
1779         err = tegra_sor_attach(sor);
1780         if (err < 0)
1781                 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
1782
1783         err = tegra_sor_wakeup(sor);
1784         if (err < 0)
1785                 dev_err(sor->dev, "failed to enable DC: %d\n", err);
1786
1787         if (output->panel)
1788                 drm_panel_enable(output->panel);
1789 }
1790
1791 static int
1792 tegra_sor_encoder_atomic_check(struct drm_encoder *encoder,
1793                                struct drm_crtc_state *crtc_state,
1794                                struct drm_connector_state *conn_state)
1795 {
1796         struct tegra_output *output = encoder_to_output(encoder);
1797         struct tegra_sor_state *state = to_sor_state(conn_state);
1798         struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1799         unsigned long pclk = crtc_state->mode.clock * 1000;
1800         struct tegra_sor *sor = to_sor(output);
1801         struct drm_display_info *info;
1802         int err;
1803
1804         info = &output->connector.display_info;
1805
1806         err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent,
1807                                          pclk, 0);
1808         if (err < 0) {
1809                 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1810                 return err;
1811         }
1812
1813         switch (info->bpc) {
1814         case 8:
1815         case 6:
1816                 state->bpc = info->bpc;
1817                 break;
1818
1819         default:
1820                 DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc);
1821                 state->bpc = 8;
1822                 break;
1823         }
1824
1825         return 0;
1826 }
1827
1828 static const struct drm_encoder_helper_funcs tegra_sor_edp_helpers = {
1829         .disable = tegra_sor_edp_disable,
1830         .enable = tegra_sor_edp_enable,
1831         .atomic_check = tegra_sor_encoder_atomic_check,
1832 };
1833
1834 static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size)
1835 {
1836         u32 value = 0;
1837         size_t i;
1838
1839         for (i = size; i > 0; i--)
1840                 value = (value << 8) | ptr[i - 1];
1841
1842         return value;
1843 }
1844
1845 static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor,
1846                                           const void *data, size_t size)
1847 {
1848         const u8 *ptr = data;
1849         unsigned long offset;
1850         size_t i, j;
1851         u32 value;
1852
1853         switch (ptr[0]) {
1854         case HDMI_INFOFRAME_TYPE_AVI:
1855                 offset = SOR_HDMI_AVI_INFOFRAME_HEADER;
1856                 break;
1857
1858         case HDMI_INFOFRAME_TYPE_AUDIO:
1859                 offset = SOR_HDMI_AUDIO_INFOFRAME_HEADER;
1860                 break;
1861
1862         case HDMI_INFOFRAME_TYPE_VENDOR:
1863                 offset = SOR_HDMI_VSI_INFOFRAME_HEADER;
1864                 break;
1865
1866         default:
1867                 dev_err(sor->dev, "unsupported infoframe type: %02x\n",
1868                         ptr[0]);
1869                 return;
1870         }
1871
1872         value = INFOFRAME_HEADER_TYPE(ptr[0]) |
1873                 INFOFRAME_HEADER_VERSION(ptr[1]) |
1874                 INFOFRAME_HEADER_LEN(ptr[2]);
1875         tegra_sor_writel(sor, value, offset);
1876         offset++;
1877
1878         /*
1879          * Each subpack contains 7 bytes, divided into:
1880          * - subpack_low: bytes 0 - 3
1881          * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
1882          */
1883         for (i = 3, j = 0; i < size; i += 7, j += 8) {
1884                 size_t rem = size - i, num = min_t(size_t, rem, 4);
1885
1886                 value = tegra_sor_hdmi_subpack(&ptr[i], num);
1887                 tegra_sor_writel(sor, value, offset++);
1888
1889                 num = min_t(size_t, rem - num, 3);
1890
1891                 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num);
1892                 tegra_sor_writel(sor, value, offset++);
1893         }
1894 }
1895
1896 static int
1897 tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor,
1898                                    const struct drm_display_mode *mode)
1899 {
1900         u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
1901         struct hdmi_avi_infoframe frame;
1902         u32 value;
1903         int err;
1904
1905         /* disable AVI infoframe */
1906         value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
1907         value &= ~INFOFRAME_CTRL_SINGLE;
1908         value &= ~INFOFRAME_CTRL_OTHER;
1909         value &= ~INFOFRAME_CTRL_ENABLE;
1910         tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
1911
1912         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false);
1913         if (err < 0) {
1914                 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
1915                 return err;
1916         }
1917
1918         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1919         if (err < 0) {
1920                 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err);
1921                 return err;
1922         }
1923
1924         tegra_sor_hdmi_write_infopack(sor, buffer, err);
1925
1926         /* enable AVI infoframe */
1927         value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
1928         value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
1929         value |= INFOFRAME_CTRL_ENABLE;
1930         tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
1931
1932         return 0;
1933 }
1934
1935 static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor)
1936 {
1937         u32 value;
1938
1939         value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
1940         value &= ~INFOFRAME_CTRL_ENABLE;
1941         tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
1942 }
1943
1944 static struct tegra_sor_hdmi_settings *
1945 tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency)
1946 {
1947         unsigned int i;
1948
1949         for (i = 0; i < sor->num_settings; i++)
1950                 if (frequency <= sor->settings[i].frequency)
1951                         return &sor->settings[i];
1952
1953         return NULL;
1954 }
1955
1956 static void tegra_sor_hdmi_disable(struct drm_encoder *encoder)
1957 {
1958         struct tegra_output *output = encoder_to_output(encoder);
1959         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1960         struct tegra_sor *sor = to_sor(output);
1961         u32 value;
1962         int err;
1963
1964         err = tegra_sor_detach(sor);
1965         if (err < 0)
1966                 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
1967
1968         tegra_sor_writel(sor, 0, SOR_STATE1);
1969         tegra_sor_update(sor);
1970
1971         /* disable display to SOR clock */
1972         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1973         value &= ~SOR1_TIMING_CYA;
1974         value &= ~SOR1_ENABLE;
1975         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1976
1977         tegra_dc_commit(dc);
1978
1979         err = tegra_sor_power_down(sor);
1980         if (err < 0)
1981                 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
1982
1983         err = tegra_io_rail_power_off(TEGRA_IO_RAIL_HDMI);
1984         if (err < 0)
1985                 dev_err(sor->dev, "failed to power off HDMI rail: %d\n", err);
1986
1987         pm_runtime_put(sor->dev);
1988 }
1989
1990 static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
1991 {
1992         struct tegra_output *output = encoder_to_output(encoder);
1993         unsigned int h_ref_to_sync = 1, pulse_start, max_ac;
1994         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1995         struct tegra_sor_hdmi_settings *settings;
1996         struct tegra_sor *sor = to_sor(output);
1997         struct tegra_sor_state *state;
1998         struct drm_display_mode *mode;
1999         unsigned int div, i;
2000         u32 value;
2001         int err;
2002
2003         state = to_sor_state(output->connector.state);
2004         mode = &encoder->crtc->state->adjusted_mode;
2005
2006         pm_runtime_get_sync(sor->dev);
2007
2008         /* switch to safe parent clock */
2009         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2010         if (err < 0)
2011                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2012
2013         div = clk_get_rate(sor->clk) / 1000000 * 4;
2014
2015         err = tegra_io_rail_power_on(TEGRA_IO_RAIL_HDMI);
2016         if (err < 0)
2017                 dev_err(sor->dev, "failed to power on HDMI rail: %d\n", err);
2018
2019         usleep_range(20, 100);
2020
2021         value = tegra_sor_readl(sor, SOR_PLL2);
2022         value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
2023         tegra_sor_writel(sor, value, SOR_PLL2);
2024
2025         usleep_range(20, 100);
2026
2027         value = tegra_sor_readl(sor, SOR_PLL3);
2028         value &= ~SOR_PLL3_PLL_VDD_MODE_3V3;
2029         tegra_sor_writel(sor, value, SOR_PLL3);
2030
2031         value = tegra_sor_readl(sor, SOR_PLL0);
2032         value &= ~SOR_PLL0_VCOPD;
2033         value &= ~SOR_PLL0_PWR;
2034         tegra_sor_writel(sor, value, SOR_PLL0);
2035
2036         value = tegra_sor_readl(sor, SOR_PLL2);
2037         value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
2038         tegra_sor_writel(sor, value, SOR_PLL2);
2039
2040         usleep_range(200, 400);
2041
2042         value = tegra_sor_readl(sor, SOR_PLL2);
2043         value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
2044         value &= ~SOR_PLL2_PORT_POWERDOWN;
2045         tegra_sor_writel(sor, value, SOR_PLL2);
2046
2047         usleep_range(20, 100);
2048
2049         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
2050         value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
2051                  SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2;
2052         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
2053
2054         while (true) {
2055                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2056                 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0)
2057                         break;
2058
2059                 usleep_range(250, 1000);
2060         }
2061
2062         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
2063                 SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5);
2064         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
2065
2066         while (true) {
2067                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2068                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
2069                         break;
2070
2071                 usleep_range(250, 1000);
2072         }
2073
2074         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
2075         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
2076         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
2077
2078         if (mode->clock < 340000)
2079                 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70;
2080         else
2081                 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40;
2082
2083         value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
2084         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2085
2086         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2087         value |= SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2088         value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
2089         value |= SOR_DP_SPARE_SEQ_ENABLE;
2090         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2091
2092         value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) |
2093                 SOR_SEQ_CTL_PD_PC(8) | SOR_SEQ_CTL_PD_PC_ALT(8);
2094         tegra_sor_writel(sor, value, SOR_SEQ_CTL);
2095
2096         value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT |
2097                 SOR_SEQ_INST_WAIT_VSYNC | SOR_SEQ_INST_WAIT(1);
2098         tegra_sor_writel(sor, value, SOR_SEQ_INST(0));
2099         tegra_sor_writel(sor, value, SOR_SEQ_INST(8));
2100
2101         /* program the reference clock */
2102         value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div);
2103         tegra_sor_writel(sor, value, SOR_REFCLK);
2104
2105         /* XXX not in TRM */
2106         for (value = 0, i = 0; i < 5; i++)
2107                 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) |
2108                          SOR_XBAR_CTRL_LINK1_XSEL(i, i);
2109
2110         tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
2111         tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2112
2113         /* switch to parent clock */
2114         err = clk_set_parent(sor->clk_src, sor->clk_parent);
2115         if (err < 0)
2116                 dev_err(sor->dev, "failed to set source clock: %d\n", err);
2117
2118         err = tegra_sor_set_parent_clock(sor, sor->clk_src);
2119         if (err < 0)
2120                 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
2121
2122         value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
2123
2124         /* XXX is this the proper check? */
2125         if (mode->clock < 75000)
2126                 value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED;
2127
2128         tegra_sor_writel(sor, value, SOR_INPUT_CONTROL);
2129
2130         max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32;
2131
2132         value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) |
2133                 SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY);
2134         tegra_sor_writel(sor, value, SOR_HDMI_CTRL);
2135
2136         /* H_PULSE2 setup */
2137         pulse_start = h_ref_to_sync + (mode->hsync_end - mode->hsync_start) +
2138                       (mode->htotal - mode->hsync_end) - 10;
2139
2140         value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE |
2141                 PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL;
2142         tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
2143
2144         value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start);
2145         tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
2146
2147         value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
2148         value |= H_PULSE2_ENABLE;
2149         tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0);
2150
2151         /* infoframe setup */
2152         err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode);
2153         if (err < 0)
2154                 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
2155
2156         /* XXX HDMI audio support not implemented yet */
2157         tegra_sor_hdmi_disable_audio_infoframe(sor);
2158
2159         /* use single TMDS protocol */
2160         value = tegra_sor_readl(sor, SOR_STATE1);
2161         value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2162         value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A;
2163         tegra_sor_writel(sor, value, SOR_STATE1);
2164
2165         /* power up pad calibration */
2166         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
2167         value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
2168         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
2169
2170         /* production settings */
2171         settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000);
2172         if (!settings) {
2173                 dev_err(sor->dev, "no settings for pixel clock %d Hz\n",
2174                         mode->clock * 1000);
2175                 return;
2176         }
2177
2178         value = tegra_sor_readl(sor, SOR_PLL0);
2179         value &= ~SOR_PLL0_ICHPMP_MASK;
2180         value &= ~SOR_PLL0_VCOCAP_MASK;
2181         value |= SOR_PLL0_ICHPMP(settings->ichpmp);
2182         value |= SOR_PLL0_VCOCAP(settings->vcocap);
2183         tegra_sor_writel(sor, value, SOR_PLL0);
2184
2185         tegra_sor_dp_term_calibrate(sor);
2186
2187         value = tegra_sor_readl(sor, SOR_PLL1);
2188         value &= ~SOR_PLL1_LOADADJ_MASK;
2189         value |= SOR_PLL1_LOADADJ(settings->loadadj);
2190         tegra_sor_writel(sor, value, SOR_PLL1);
2191
2192         value = tegra_sor_readl(sor, SOR_PLL3);
2193         value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK;
2194         value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref);
2195         tegra_sor_writel(sor, value, SOR_PLL3);
2196
2197         value = settings->drive_current[0] << 24 |
2198                 settings->drive_current[1] << 16 |
2199                 settings->drive_current[2] <<  8 |
2200                 settings->drive_current[3] <<  0;
2201         tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
2202
2203         value = settings->preemphasis[0] << 24 |
2204                 settings->preemphasis[1] << 16 |
2205                 settings->preemphasis[2] <<  8 |
2206                 settings->preemphasis[3] <<  0;
2207         tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
2208
2209         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
2210         value &= ~SOR_DP_PADCTL_TX_PU_MASK;
2211         value |= SOR_DP_PADCTL_TX_PU_ENABLE;
2212         value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu);
2213         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
2214
2215         /* power down pad calibration */
2216         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
2217         value |= SOR_DP_PADCTL_PAD_CAL_PD;
2218         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
2219
2220         /* miscellaneous display controller settings */
2221         value = VSYNC_H_POSITION(1);
2222         tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS);
2223
2224         value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
2225         value &= ~DITHER_CONTROL_MASK;
2226         value &= ~BASE_COLOR_SIZE_MASK;
2227
2228         switch (state->bpc) {
2229         case 6:
2230                 value |= BASE_COLOR_SIZE_666;
2231                 break;
2232
2233         case 8:
2234                 value |= BASE_COLOR_SIZE_888;
2235                 break;
2236
2237         default:
2238                 WARN(1, "%u bits-per-color not supported\n", state->bpc);
2239                 value |= BASE_COLOR_SIZE_888;
2240                 break;
2241         }
2242
2243         tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL);
2244
2245         err = tegra_sor_power_up(sor, 250);
2246         if (err < 0)
2247                 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2248
2249         /* configure dynamic range of output */
2250         value = tegra_sor_readl(sor, SOR_HEAD_STATE0(dc->pipe));
2251         value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK;
2252         value &= ~SOR_HEAD_STATE_DYNRANGE_MASK;
2253         tegra_sor_writel(sor, value, SOR_HEAD_STATE0(dc->pipe));
2254
2255         /* configure colorspace */
2256         value = tegra_sor_readl(sor, SOR_HEAD_STATE0(dc->pipe));
2257         value &= ~SOR_HEAD_STATE_COLORSPACE_MASK;
2258         value |= SOR_HEAD_STATE_COLORSPACE_RGB;
2259         tegra_sor_writel(sor, value, SOR_HEAD_STATE0(dc->pipe));
2260
2261         tegra_sor_mode_set(sor, mode, state);
2262
2263         tegra_sor_update(sor);
2264
2265         err = tegra_sor_attach(sor);
2266         if (err < 0)
2267                 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2268
2269         /* enable display to SOR clock and generate HDMI preamble */
2270         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2271         value |= SOR1_ENABLE | SOR1_TIMING_CYA;
2272         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2273
2274         tegra_dc_commit(dc);
2275
2276         err = tegra_sor_wakeup(sor);
2277         if (err < 0)
2278                 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2279 }
2280
2281 static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = {
2282         .disable = tegra_sor_hdmi_disable,
2283         .enable = tegra_sor_hdmi_enable,
2284         .atomic_check = tegra_sor_encoder_atomic_check,
2285 };
2286
2287 static int tegra_sor_init(struct host1x_client *client)
2288 {
2289         struct drm_device *drm = dev_get_drvdata(client->parent);
2290         const struct drm_encoder_helper_funcs *helpers = NULL;
2291         struct tegra_sor *sor = host1x_client_to_sor(client);
2292         int connector = DRM_MODE_CONNECTOR_Unknown;
2293         int encoder = DRM_MODE_ENCODER_NONE;
2294         int err;
2295
2296         if (!sor->aux) {
2297                 if (sor->soc->supports_hdmi) {
2298                         connector = DRM_MODE_CONNECTOR_HDMIA;
2299                         encoder = DRM_MODE_ENCODER_TMDS;
2300                         helpers = &tegra_sor_hdmi_helpers;
2301                 } else if (sor->soc->supports_lvds) {
2302                         connector = DRM_MODE_CONNECTOR_LVDS;
2303                         encoder = DRM_MODE_ENCODER_LVDS;
2304                 }
2305         } else {
2306                 if (sor->soc->supports_edp) {
2307                         connector = DRM_MODE_CONNECTOR_eDP;
2308                         encoder = DRM_MODE_ENCODER_TMDS;
2309                         helpers = &tegra_sor_edp_helpers;
2310                 } else if (sor->soc->supports_dp) {
2311                         connector = DRM_MODE_CONNECTOR_DisplayPort;
2312                         encoder = DRM_MODE_ENCODER_TMDS;
2313                 }
2314         }
2315
2316         sor->output.dev = sor->dev;
2317
2318         drm_connector_init(drm, &sor->output.connector,
2319                            &tegra_sor_connector_funcs,
2320                            connector);
2321         drm_connector_helper_add(&sor->output.connector,
2322                                  &tegra_sor_connector_helper_funcs);
2323         sor->output.connector.dpms = DRM_MODE_DPMS_OFF;
2324
2325         drm_encoder_init(drm, &sor->output.encoder, &tegra_sor_encoder_funcs,
2326                          encoder, NULL);
2327         drm_encoder_helper_add(&sor->output.encoder, helpers);
2328
2329         drm_mode_connector_attach_encoder(&sor->output.connector,
2330                                           &sor->output.encoder);
2331         drm_connector_register(&sor->output.connector);
2332
2333         err = tegra_output_init(drm, &sor->output);
2334         if (err < 0) {
2335                 dev_err(client->dev, "failed to initialize output: %d\n", err);
2336                 return err;
2337         }
2338
2339         sor->output.encoder.possible_crtcs = 0x3;
2340
2341         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
2342                 err = tegra_sor_debugfs_init(sor, drm->primary);
2343                 if (err < 0)
2344                         dev_err(sor->dev, "debugfs setup failed: %d\n", err);
2345         }
2346
2347         if (sor->aux) {
2348                 err = drm_dp_aux_attach(sor->aux, &sor->output);
2349                 if (err < 0) {
2350                         dev_err(sor->dev, "failed to attach DP: %d\n", err);
2351                         return err;
2352                 }
2353         }
2354
2355         /*
2356          * XXX: Remove this reset once proper hand-over from firmware to
2357          * kernel is possible.
2358          */
2359         if (sor->rst) {
2360                 err = reset_control_assert(sor->rst);
2361                 if (err < 0) {
2362                         dev_err(sor->dev, "failed to assert SOR reset: %d\n",
2363                                 err);
2364                         return err;
2365                 }
2366         }
2367
2368         err = clk_prepare_enable(sor->clk);
2369         if (err < 0) {
2370                 dev_err(sor->dev, "failed to enable clock: %d\n", err);
2371                 return err;
2372         }
2373
2374         usleep_range(1000, 3000);
2375
2376         if (sor->rst) {
2377                 err = reset_control_deassert(sor->rst);
2378                 if (err < 0) {
2379                         dev_err(sor->dev, "failed to deassert SOR reset: %d\n",
2380                                 err);
2381                         return err;
2382                 }
2383         }
2384
2385         err = clk_prepare_enable(sor->clk_safe);
2386         if (err < 0)
2387                 return err;
2388
2389         err = clk_prepare_enable(sor->clk_dp);
2390         if (err < 0)
2391                 return err;
2392
2393         return 0;
2394 }
2395
2396 static int tegra_sor_exit(struct host1x_client *client)
2397 {
2398         struct tegra_sor *sor = host1x_client_to_sor(client);
2399         int err;
2400
2401         tegra_output_exit(&sor->output);
2402
2403         if (sor->aux) {
2404                 err = drm_dp_aux_detach(sor->aux);
2405                 if (err < 0) {
2406                         dev_err(sor->dev, "failed to detach DP: %d\n", err);
2407                         return err;
2408                 }
2409         }
2410
2411         clk_disable_unprepare(sor->clk_safe);
2412         clk_disable_unprepare(sor->clk_dp);
2413         clk_disable_unprepare(sor->clk);
2414
2415         if (IS_ENABLED(CONFIG_DEBUG_FS))
2416                 tegra_sor_debugfs_exit(sor);
2417
2418         return 0;
2419 }
2420
2421 static const struct host1x_client_ops sor_client_ops = {
2422         .init = tegra_sor_init,
2423         .exit = tegra_sor_exit,
2424 };
2425
2426 static const struct tegra_sor_ops tegra_sor_edp_ops = {
2427         .name = "eDP",
2428 };
2429
2430 static int tegra_sor_hdmi_probe(struct tegra_sor *sor)
2431 {
2432         int err;
2433
2434         sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io");
2435         if (IS_ERR(sor->avdd_io_supply)) {
2436                 dev_err(sor->dev, "cannot get AVDD I/O supply: %ld\n",
2437                         PTR_ERR(sor->avdd_io_supply));
2438                 return PTR_ERR(sor->avdd_io_supply);
2439         }
2440
2441         err = regulator_enable(sor->avdd_io_supply);
2442         if (err < 0) {
2443                 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n",
2444                         err);
2445                 return err;
2446         }
2447
2448         sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-pll");
2449         if (IS_ERR(sor->vdd_pll_supply)) {
2450                 dev_err(sor->dev, "cannot get VDD PLL supply: %ld\n",
2451                         PTR_ERR(sor->vdd_pll_supply));
2452                 return PTR_ERR(sor->vdd_pll_supply);
2453         }
2454
2455         err = regulator_enable(sor->vdd_pll_supply);
2456         if (err < 0) {
2457                 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n",
2458                         err);
2459                 return err;
2460         }
2461
2462         sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi");
2463         if (IS_ERR(sor->hdmi_supply)) {
2464                 dev_err(sor->dev, "cannot get HDMI supply: %ld\n",
2465                         PTR_ERR(sor->hdmi_supply));
2466                 return PTR_ERR(sor->hdmi_supply);
2467         }
2468
2469         err = regulator_enable(sor->hdmi_supply);
2470         if (err < 0) {
2471                 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err);
2472                 return err;
2473         }
2474
2475         return 0;
2476 }
2477
2478 static int tegra_sor_hdmi_remove(struct tegra_sor *sor)
2479 {
2480         regulator_disable(sor->hdmi_supply);
2481         regulator_disable(sor->vdd_pll_supply);
2482         regulator_disable(sor->avdd_io_supply);
2483
2484         return 0;
2485 }
2486
2487 static const struct tegra_sor_ops tegra_sor_hdmi_ops = {
2488         .name = "HDMI",
2489         .probe = tegra_sor_hdmi_probe,
2490         .remove = tegra_sor_hdmi_remove,
2491 };
2492
2493 static const u8 tegra124_sor_xbar_cfg[5] = {
2494         0, 1, 2, 3, 4
2495 };
2496
2497 static const struct tegra_sor_soc tegra124_sor = {
2498         .supports_edp = true,
2499         .supports_lvds = true,
2500         .supports_hdmi = false,
2501         .supports_dp = false,
2502         .xbar_cfg = tegra124_sor_xbar_cfg,
2503 };
2504
2505 static const struct tegra_sor_soc tegra210_sor = {
2506         .supports_edp = true,
2507         .supports_lvds = false,
2508         .supports_hdmi = false,
2509         .supports_dp = false,
2510         .xbar_cfg = tegra124_sor_xbar_cfg,
2511 };
2512
2513 static const u8 tegra210_sor_xbar_cfg[5] = {
2514         2, 1, 0, 3, 4
2515 };
2516
2517 static const struct tegra_sor_soc tegra210_sor1 = {
2518         .supports_edp = false,
2519         .supports_lvds = false,
2520         .supports_hdmi = true,
2521         .supports_dp = true,
2522
2523         .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults),
2524         .settings = tegra210_sor_hdmi_defaults,
2525
2526         .xbar_cfg = tegra210_sor_xbar_cfg,
2527 };
2528
2529 static const struct of_device_id tegra_sor_of_match[] = {
2530         { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 },
2531         { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor },
2532         { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor },
2533         { },
2534 };
2535 MODULE_DEVICE_TABLE(of, tegra_sor_of_match);
2536
2537 static int tegra_sor_probe(struct platform_device *pdev)
2538 {
2539         struct device_node *np;
2540         struct tegra_sor *sor;
2541         struct resource *regs;
2542         int err;
2543
2544         sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL);
2545         if (!sor)
2546                 return -ENOMEM;
2547
2548         sor->soc = of_device_get_match_data(&pdev->dev);
2549         sor->output.dev = sor->dev = &pdev->dev;
2550
2551         sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings,
2552                                      sor->soc->num_settings *
2553                                         sizeof(*sor->settings),
2554                                      GFP_KERNEL);
2555         if (!sor->settings)
2556                 return -ENOMEM;
2557
2558         sor->num_settings = sor->soc->num_settings;
2559
2560         np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0);
2561         if (np) {
2562                 sor->aux = drm_dp_aux_find_by_of_node(np);
2563                 of_node_put(np);
2564
2565                 if (!sor->aux)
2566                         return -EPROBE_DEFER;
2567         }
2568
2569         if (!sor->aux) {
2570                 if (sor->soc->supports_hdmi) {
2571                         sor->ops = &tegra_sor_hdmi_ops;
2572                 } else if (sor->soc->supports_lvds) {
2573                         dev_err(&pdev->dev, "LVDS not supported yet\n");
2574                         return -ENODEV;
2575                 } else {
2576                         dev_err(&pdev->dev, "unknown (non-DP) support\n");
2577                         return -ENODEV;
2578                 }
2579         } else {
2580                 if (sor->soc->supports_edp) {
2581                         sor->ops = &tegra_sor_edp_ops;
2582                 } else if (sor->soc->supports_dp) {
2583                         dev_err(&pdev->dev, "DisplayPort not supported yet\n");
2584                         return -ENODEV;
2585                 } else {
2586                         dev_err(&pdev->dev, "unknown (DP) support\n");
2587                         return -ENODEV;
2588                 }
2589         }
2590
2591         err = tegra_output_probe(&sor->output);
2592         if (err < 0) {
2593                 dev_err(&pdev->dev, "failed to probe output: %d\n", err);
2594                 return err;
2595         }
2596
2597         if (sor->ops && sor->ops->probe) {
2598                 err = sor->ops->probe(sor);
2599                 if (err < 0) {
2600                         dev_err(&pdev->dev, "failed to probe %s: %d\n",
2601                                 sor->ops->name, err);
2602                         goto output;
2603                 }
2604         }
2605
2606         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2607         sor->regs = devm_ioremap_resource(&pdev->dev, regs);
2608         if (IS_ERR(sor->regs)) {
2609                 err = PTR_ERR(sor->regs);
2610                 goto remove;
2611         }
2612
2613         if (!pdev->dev.pm_domain) {
2614                 sor->rst = devm_reset_control_get(&pdev->dev, "sor");
2615                 if (IS_ERR(sor->rst)) {
2616                         err = PTR_ERR(sor->rst);
2617                         dev_err(&pdev->dev, "failed to get reset control: %d\n",
2618                                 err);
2619                         goto remove;
2620                 }
2621         }
2622
2623         sor->clk = devm_clk_get(&pdev->dev, NULL);
2624         if (IS_ERR(sor->clk)) {
2625                 err = PTR_ERR(sor->clk);
2626                 dev_err(&pdev->dev, "failed to get module clock: %d\n", err);
2627                 goto remove;
2628         }
2629
2630         if (sor->soc->supports_hdmi || sor->soc->supports_dp) {
2631                 sor->clk_src = devm_clk_get(&pdev->dev, "source");
2632                 if (IS_ERR(sor->clk_src)) {
2633                         err = PTR_ERR(sor->clk_src);
2634                         dev_err(sor->dev, "failed to get source clock: %d\n",
2635                                 err);
2636                         goto remove;
2637                 }
2638         }
2639
2640         sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
2641         if (IS_ERR(sor->clk_parent)) {
2642                 err = PTR_ERR(sor->clk_parent);
2643                 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err);
2644                 goto remove;
2645         }
2646
2647         sor->clk_safe = devm_clk_get(&pdev->dev, "safe");
2648         if (IS_ERR(sor->clk_safe)) {
2649                 err = PTR_ERR(sor->clk_safe);
2650                 dev_err(&pdev->dev, "failed to get safe clock: %d\n", err);
2651                 goto remove;
2652         }
2653
2654         sor->clk_dp = devm_clk_get(&pdev->dev, "dp");
2655         if (IS_ERR(sor->clk_dp)) {
2656                 err = PTR_ERR(sor->clk_dp);
2657                 dev_err(&pdev->dev, "failed to get DP clock: %d\n", err);
2658                 goto remove;
2659         }
2660
2661         platform_set_drvdata(pdev, sor);
2662         pm_runtime_enable(&pdev->dev);
2663
2664         pm_runtime_get_sync(&pdev->dev);
2665         sor->clk_brick = tegra_clk_sor_brick_register(sor, "sor1_brick");
2666         pm_runtime_put(&pdev->dev);
2667
2668         if (IS_ERR(sor->clk_brick)) {
2669                 err = PTR_ERR(sor->clk_brick);
2670                 dev_err(&pdev->dev, "failed to register SOR clock: %d\n", err);
2671                 goto remove;
2672         }
2673
2674         INIT_LIST_HEAD(&sor->client.list);
2675         sor->client.ops = &sor_client_ops;
2676         sor->client.dev = &pdev->dev;
2677
2678         err = host1x_client_register(&sor->client);
2679         if (err < 0) {
2680                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
2681                         err);
2682                 goto remove;
2683         }
2684
2685         return 0;
2686
2687 remove:
2688         if (sor->ops && sor->ops->remove)
2689                 sor->ops->remove(sor);
2690 output:
2691         tegra_output_remove(&sor->output);
2692         return err;
2693 }
2694
2695 static int tegra_sor_remove(struct platform_device *pdev)
2696 {
2697         struct tegra_sor *sor = platform_get_drvdata(pdev);
2698         int err;
2699
2700         pm_runtime_disable(&pdev->dev);
2701
2702         err = host1x_client_unregister(&sor->client);
2703         if (err < 0) {
2704                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
2705                         err);
2706                 return err;
2707         }
2708
2709         if (sor->ops && sor->ops->remove) {
2710                 err = sor->ops->remove(sor);
2711                 if (err < 0)
2712                         dev_err(&pdev->dev, "failed to remove SOR: %d\n", err);
2713         }
2714
2715         tegra_output_remove(&sor->output);
2716
2717         return 0;
2718 }
2719
2720 #ifdef CONFIG_PM
2721 static int tegra_sor_suspend(struct device *dev)
2722 {
2723         struct tegra_sor *sor = dev_get_drvdata(dev);
2724         int err;
2725
2726         if (sor->rst) {
2727                 err = reset_control_assert(sor->rst);
2728                 if (err < 0) {
2729                         dev_err(dev, "failed to assert reset: %d\n", err);
2730                         return err;
2731                 }
2732         }
2733
2734         usleep_range(1000, 2000);
2735
2736         clk_disable_unprepare(sor->clk);
2737
2738         return 0;
2739 }
2740
2741 static int tegra_sor_resume(struct device *dev)
2742 {
2743         struct tegra_sor *sor = dev_get_drvdata(dev);
2744         int err;
2745
2746         err = clk_prepare_enable(sor->clk);
2747         if (err < 0) {
2748                 dev_err(dev, "failed to enable clock: %d\n", err);
2749                 return err;
2750         }
2751
2752         usleep_range(1000, 2000);
2753
2754         if (sor->rst) {
2755                 err = reset_control_deassert(sor->rst);
2756                 if (err < 0) {
2757                         dev_err(dev, "failed to deassert reset: %d\n", err);
2758                         clk_disable_unprepare(sor->clk);
2759                         return err;
2760                 }
2761         }
2762
2763         return 0;
2764 }
2765 #endif
2766
2767 static const struct dev_pm_ops tegra_sor_pm_ops = {
2768         SET_RUNTIME_PM_OPS(tegra_sor_suspend, tegra_sor_resume, NULL)
2769 };
2770
2771 struct platform_driver tegra_sor_driver = {
2772         .driver = {
2773                 .name = "tegra-sor",
2774                 .of_match_table = tegra_sor_of_match,
2775                 .pm = &tegra_sor_pm_ops,
2776         },
2777         .probe = tegra_sor_probe,
2778         .remove = tegra_sor_remove,
2779 };