Merge branch 'parisc-5.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/deller...
[muen/linux.git] / drivers / i2c / busses / i2c-imx.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  *      Copyright (C) 2002 Motorola GSG-China
4  *
5  * Author:
6  *      Darius Augulis, Teltonika Inc.
7  *
8  * Desc.:
9  *      Implementation of I2C Adapter/Algorithm Driver
10  *      for I2C Bus integrated in Freescale i.MX/MXC processors
11  *
12  *      Derived from Motorola GSG China I2C example driver
13  *
14  *      Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
15  *      Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
16  *      Copyright (C) 2007 RightHand Technologies, Inc.
17  *      Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
18  *
19  *      Copyright 2013 Freescale Semiconductor, Inc.
20  *
21  */
22
23 #include <linux/clk.h>
24 #include <linux/completion.h>
25 #include <linux/delay.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/dmaengine.h>
28 #include <linux/dmapool.h>
29 #include <linux/err.h>
30 #include <linux/errno.h>
31 #include <linux/gpio/consumer.h>
32 #include <linux/i2c.h>
33 #include <linux/init.h>
34 #include <linux/interrupt.h>
35 #include <linux/io.h>
36 #include <linux/kernel.h>
37 #include <linux/module.h>
38 #include <linux/of.h>
39 #include <linux/of_device.h>
40 #include <linux/of_dma.h>
41 #include <linux/pinctrl/consumer.h>
42 #include <linux/platform_data/i2c-imx.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/sched.h>
46 #include <linux/slab.h>
47
48 /* This will be the driver name the kernel reports */
49 #define DRIVER_NAME "imx-i2c"
50
51 /* Default value */
52 #define IMX_I2C_BIT_RATE        100000  /* 100kHz */
53
54 /*
55  * Enable DMA if transfer byte size is bigger than this threshold.
56  * As the hardware request, it must bigger than 4 bytes.\
57  * I have set '16' here, maybe it's not the best but I think it's
58  * the appropriate.
59  */
60 #define DMA_THRESHOLD   16
61 #define DMA_TIMEOUT     1000
62
63 /* IMX I2C registers:
64  * the I2C register offset is different between SoCs,
65  * to provid support for all these chips, split the
66  * register offset into a fixed base address and a
67  * variable shift value, then the full register offset
68  * will be calculated by
69  * reg_off = ( reg_base_addr << reg_shift)
70  */
71 #define IMX_I2C_IADR    0x00    /* i2c slave address */
72 #define IMX_I2C_IFDR    0x01    /* i2c frequency divider */
73 #define IMX_I2C_I2CR    0x02    /* i2c control */
74 #define IMX_I2C_I2SR    0x03    /* i2c status */
75 #define IMX_I2C_I2DR    0x04    /* i2c transfer data */
76
77 #define IMX_I2C_REGSHIFT        2
78 #define VF610_I2C_REGSHIFT      0
79
80 /* Bits of IMX I2C registers */
81 #define I2SR_RXAK       0x01
82 #define I2SR_IIF        0x02
83 #define I2SR_SRW        0x04
84 #define I2SR_IAL        0x10
85 #define I2SR_IBB        0x20
86 #define I2SR_IAAS       0x40
87 #define I2SR_ICF        0x80
88 #define I2CR_DMAEN      0x02
89 #define I2CR_RSTA       0x04
90 #define I2CR_TXAK       0x08
91 #define I2CR_MTX        0x10
92 #define I2CR_MSTA       0x20
93 #define I2CR_IIEN       0x40
94 #define I2CR_IEN        0x80
95
96 /* register bits different operating codes definition:
97  * 1) I2SR: Interrupt flags clear operation differ between SoCs:
98  * - write zero to clear(w0c) INT flag on i.MX,
99  * - but write one to clear(w1c) INT flag on Vybrid.
100  * 2) I2CR: I2C module enable operation also differ between SoCs:
101  * - set I2CR_IEN bit enable the module on i.MX,
102  * - but clear I2CR_IEN bit enable the module on Vybrid.
103  */
104 #define I2SR_CLR_OPCODE_W0C     0x0
105 #define I2SR_CLR_OPCODE_W1C     (I2SR_IAL | I2SR_IIF)
106 #define I2CR_IEN_OPCODE_0       0x0
107 #define I2CR_IEN_OPCODE_1       I2CR_IEN
108
109 #define I2C_PM_TIMEOUT          10 /* ms */
110
111 /*
112  * sorted list of clock divider, register value pairs
113  * taken from table 26-5, p.26-9, Freescale i.MX
114  * Integrated Portable System Processor Reference Manual
115  * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
116  *
117  * Duplicated divider values removed from list
118  */
119 struct imx_i2c_clk_pair {
120         u16     div;
121         u16     val;
122 };
123
124 static struct imx_i2c_clk_pair imx_i2c_clk_div[] = {
125         { 22,   0x20 }, { 24,   0x21 }, { 26,   0x22 }, { 28,   0x23 },
126         { 30,   0x00 }, { 32,   0x24 }, { 36,   0x25 }, { 40,   0x26 },
127         { 42,   0x03 }, { 44,   0x27 }, { 48,   0x28 }, { 52,   0x05 },
128         { 56,   0x29 }, { 60,   0x06 }, { 64,   0x2A }, { 72,   0x2B },
129         { 80,   0x2C }, { 88,   0x09 }, { 96,   0x2D }, { 104,  0x0A },
130         { 112,  0x2E }, { 128,  0x2F }, { 144,  0x0C }, { 160,  0x30 },
131         { 192,  0x31 }, { 224,  0x32 }, { 240,  0x0F }, { 256,  0x33 },
132         { 288,  0x10 }, { 320,  0x34 }, { 384,  0x35 }, { 448,  0x36 },
133         { 480,  0x13 }, { 512,  0x37 }, { 576,  0x14 }, { 640,  0x38 },
134         { 768,  0x39 }, { 896,  0x3A }, { 960,  0x17 }, { 1024, 0x3B },
135         { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
136         { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
137         { 3072, 0x1E }, { 3840, 0x1F }
138 };
139
140 /* Vybrid VF610 clock divider, register value pairs */
141 static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = {
142         { 20,   0x00 }, { 22,   0x01 }, { 24,   0x02 }, { 26,   0x03 },
143         { 28,   0x04 }, { 30,   0x05 }, { 32,   0x09 }, { 34,   0x06 },
144         { 36,   0x0A }, { 40,   0x07 }, { 44,   0x0C }, { 48,   0x0D },
145         { 52,   0x43 }, { 56,   0x0E }, { 60,   0x45 }, { 64,   0x12 },
146         { 68,   0x0F }, { 72,   0x13 }, { 80,   0x14 }, { 88,   0x15 },
147         { 96,   0x19 }, { 104,  0x16 }, { 112,  0x1A }, { 128,  0x17 },
148         { 136,  0x4F }, { 144,  0x1C }, { 160,  0x1D }, { 176,  0x55 },
149         { 192,  0x1E }, { 208,  0x56 }, { 224,  0x22 }, { 228,  0x24 },
150         { 240,  0x1F }, { 256,  0x23 }, { 288,  0x5C }, { 320,  0x25 },
151         { 384,  0x26 }, { 448,  0x2A }, { 480,  0x27 }, { 512,  0x2B },
152         { 576,  0x2C }, { 640,  0x2D }, { 768,  0x31 }, { 896,  0x32 },
153         { 960,  0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
154         { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
155         { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
156         { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
157 };
158
159 enum imx_i2c_type {
160         IMX1_I2C,
161         IMX21_I2C,
162         VF610_I2C,
163 };
164
165 struct imx_i2c_hwdata {
166         enum imx_i2c_type       devtype;
167         unsigned                regshift;
168         struct imx_i2c_clk_pair *clk_div;
169         unsigned                ndivs;
170         unsigned                i2sr_clr_opcode;
171         unsigned                i2cr_ien_opcode;
172 };
173
174 struct imx_i2c_dma {
175         struct dma_chan         *chan_tx;
176         struct dma_chan         *chan_rx;
177         struct dma_chan         *chan_using;
178         struct completion       cmd_complete;
179         dma_addr_t              dma_buf;
180         unsigned int            dma_len;
181         enum dma_transfer_direction dma_transfer_dir;
182         enum dma_data_direction dma_data_dir;
183 };
184
185 struct imx_i2c_struct {
186         struct i2c_adapter      adapter;
187         struct clk              *clk;
188         struct notifier_block   clk_change_nb;
189         void __iomem            *base;
190         wait_queue_head_t       queue;
191         unsigned long           i2csr;
192         unsigned int            disable_delay;
193         int                     stopped;
194         unsigned int            ifdr; /* IMX_I2C_IFDR */
195         unsigned int            cur_clk;
196         unsigned int            bitrate;
197         const struct imx_i2c_hwdata     *hwdata;
198         struct i2c_bus_recovery_info rinfo;
199
200         struct pinctrl *pinctrl;
201         struct pinctrl_state *pinctrl_pins_default;
202         struct pinctrl_state *pinctrl_pins_gpio;
203
204         struct imx_i2c_dma      *dma;
205 };
206
207 static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
208         .devtype                = IMX1_I2C,
209         .regshift               = IMX_I2C_REGSHIFT,
210         .clk_div                = imx_i2c_clk_div,
211         .ndivs                  = ARRAY_SIZE(imx_i2c_clk_div),
212         .i2sr_clr_opcode        = I2SR_CLR_OPCODE_W0C,
213         .i2cr_ien_opcode        = I2CR_IEN_OPCODE_1,
214
215 };
216
217 static const struct imx_i2c_hwdata imx21_i2c_hwdata = {
218         .devtype                = IMX21_I2C,
219         .regshift               = IMX_I2C_REGSHIFT,
220         .clk_div                = imx_i2c_clk_div,
221         .ndivs                  = ARRAY_SIZE(imx_i2c_clk_div),
222         .i2sr_clr_opcode        = I2SR_CLR_OPCODE_W0C,
223         .i2cr_ien_opcode        = I2CR_IEN_OPCODE_1,
224
225 };
226
227 static struct imx_i2c_hwdata vf610_i2c_hwdata = {
228         .devtype                = VF610_I2C,
229         .regshift               = VF610_I2C_REGSHIFT,
230         .clk_div                = vf610_i2c_clk_div,
231         .ndivs                  = ARRAY_SIZE(vf610_i2c_clk_div),
232         .i2sr_clr_opcode        = I2SR_CLR_OPCODE_W1C,
233         .i2cr_ien_opcode        = I2CR_IEN_OPCODE_0,
234
235 };
236
237 static const struct platform_device_id imx_i2c_devtype[] = {
238         {
239                 .name = "imx1-i2c",
240                 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata,
241         }, {
242                 .name = "imx21-i2c",
243                 .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata,
244         }, {
245                 /* sentinel */
246         }
247 };
248 MODULE_DEVICE_TABLE(platform, imx_i2c_devtype);
249
250 static const struct of_device_id i2c_imx_dt_ids[] = {
251         { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, },
252         { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, },
253         { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, },
254         { /* sentinel */ }
255 };
256 MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids);
257
258 static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)
259 {
260         return i2c_imx->hwdata->devtype == IMX1_I2C;
261 }
262
263 static inline void imx_i2c_write_reg(unsigned int val,
264                 struct imx_i2c_struct *i2c_imx, unsigned int reg)
265 {
266         writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
267 }
268
269 static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,
270                 unsigned int reg)
271 {
272         return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
273 }
274
275 /* Functions for DMA support */
276 static int i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
277                                dma_addr_t phy_addr)
278 {
279         struct imx_i2c_dma *dma;
280         struct dma_slave_config dma_sconfig;
281         struct device *dev = &i2c_imx->adapter.dev;
282         int ret;
283
284         dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
285         if (!dma)
286                 return -ENOMEM;
287
288         dma->chan_tx = dma_request_chan(dev, "tx");
289         if (IS_ERR(dma->chan_tx)) {
290                 ret = PTR_ERR(dma->chan_tx);
291                 if (ret != -ENODEV && ret != -EPROBE_DEFER)
292                         dev_err(dev, "can't request DMA tx channel (%d)\n", ret);
293                 goto fail_al;
294         }
295
296         dma_sconfig.dst_addr = phy_addr +
297                                 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
298         dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
299         dma_sconfig.dst_maxburst = 1;
300         dma_sconfig.direction = DMA_MEM_TO_DEV;
301         ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig);
302         if (ret < 0) {
303                 dev_err(dev, "can't configure tx channel (%d)\n", ret);
304                 goto fail_tx;
305         }
306
307         dma->chan_rx = dma_request_chan(dev, "rx");
308         if (IS_ERR(dma->chan_rx)) {
309                 ret = PTR_ERR(dma->chan_rx);
310                 if (ret != -ENODEV && ret != -EPROBE_DEFER)
311                         dev_err(dev, "can't request DMA rx channel (%d)\n", ret);
312                 goto fail_tx;
313         }
314
315         dma_sconfig.src_addr = phy_addr +
316                                 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
317         dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
318         dma_sconfig.src_maxburst = 1;
319         dma_sconfig.direction = DMA_DEV_TO_MEM;
320         ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig);
321         if (ret < 0) {
322                 dev_err(dev, "can't configure rx channel (%d)\n", ret);
323                 goto fail_rx;
324         }
325
326         i2c_imx->dma = dma;
327         init_completion(&dma->cmd_complete);
328         dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n",
329                 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
330
331         return 0;
332
333 fail_rx:
334         dma_release_channel(dma->chan_rx);
335 fail_tx:
336         dma_release_channel(dma->chan_tx);
337 fail_al:
338         devm_kfree(dev, dma);
339         /* return successfully if there is no dma support */
340         return ret == -ENODEV ? 0 : ret;
341 }
342
343 static void i2c_imx_dma_callback(void *arg)
344 {
345         struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg;
346         struct imx_i2c_dma *dma = i2c_imx->dma;
347
348         dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf,
349                         dma->dma_len, dma->dma_data_dir);
350         complete(&dma->cmd_complete);
351 }
352
353 static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx,
354                                         struct i2c_msg *msgs)
355 {
356         struct imx_i2c_dma *dma = i2c_imx->dma;
357         struct dma_async_tx_descriptor *txdesc;
358         struct device *dev = &i2c_imx->adapter.dev;
359         struct device *chan_dev = dma->chan_using->device->dev;
360
361         dma->dma_buf = dma_map_single(chan_dev, msgs->buf,
362                                         dma->dma_len, dma->dma_data_dir);
363         if (dma_mapping_error(chan_dev, dma->dma_buf)) {
364                 dev_err(dev, "DMA mapping failed\n");
365                 goto err_map;
366         }
367
368         txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf,
369                                         dma->dma_len, dma->dma_transfer_dir,
370                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
371         if (!txdesc) {
372                 dev_err(dev, "Not able to get desc for DMA xfer\n");
373                 goto err_desc;
374         }
375
376         reinit_completion(&dma->cmd_complete);
377         txdesc->callback = i2c_imx_dma_callback;
378         txdesc->callback_param = i2c_imx;
379         if (dma_submit_error(dmaengine_submit(txdesc))) {
380                 dev_err(dev, "DMA submit failed\n");
381                 goto err_submit;
382         }
383
384         dma_async_issue_pending(dma->chan_using);
385         return 0;
386
387 err_submit:
388         dmaengine_terminate_all(dma->chan_using);
389 err_desc:
390         dma_unmap_single(chan_dev, dma->dma_buf,
391                         dma->dma_len, dma->dma_data_dir);
392 err_map:
393         return -EINVAL;
394 }
395
396 static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx)
397 {
398         struct imx_i2c_dma *dma = i2c_imx->dma;
399
400         dma->dma_buf = 0;
401         dma->dma_len = 0;
402
403         dma_release_channel(dma->chan_tx);
404         dma->chan_tx = NULL;
405
406         dma_release_channel(dma->chan_rx);
407         dma->chan_rx = NULL;
408
409         dma->chan_using = NULL;
410 }
411
412 static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy)
413 {
414         unsigned long orig_jiffies = jiffies;
415         unsigned int temp;
416
417         dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
418
419         while (1) {
420                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
421
422                 /* check for arbitration lost */
423                 if (temp & I2SR_IAL) {
424                         temp &= ~I2SR_IAL;
425                         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
426                         return -EAGAIN;
427                 }
428
429                 if (for_busy && (temp & I2SR_IBB)) {
430                         i2c_imx->stopped = 0;
431                         break;
432                 }
433                 if (!for_busy && !(temp & I2SR_IBB)) {
434                         i2c_imx->stopped = 1;
435                         break;
436                 }
437                 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
438                         dev_dbg(&i2c_imx->adapter.dev,
439                                 "<%s> I2C bus is busy\n", __func__);
440                         return -ETIMEDOUT;
441                 }
442                 schedule();
443         }
444
445         return 0;
446 }
447
448 static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx)
449 {
450         wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
451
452         if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
453                 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
454                 return -ETIMEDOUT;
455         }
456         dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
457         i2c_imx->i2csr = 0;
458         return 0;
459 }
460
461 static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
462 {
463         if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) {
464                 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
465                 return -ENXIO;  /* No ACK */
466         }
467
468         dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
469         return 0;
470 }
471
472 static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
473                             unsigned int i2c_clk_rate)
474 {
475         struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div;
476         unsigned int div;
477         int i;
478
479         /* Divider value calculation */
480         if (i2c_imx->cur_clk == i2c_clk_rate)
481                 return;
482
483         i2c_imx->cur_clk = i2c_clk_rate;
484
485         div = (i2c_clk_rate + i2c_imx->bitrate - 1) / i2c_imx->bitrate;
486         if (div < i2c_clk_div[0].div)
487                 i = 0;
488         else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div)
489                 i = i2c_imx->hwdata->ndivs - 1;
490         else
491                 for (i = 0; i2c_clk_div[i].div < div; i++)
492                         ;
493
494         /* Store divider value */
495         i2c_imx->ifdr = i2c_clk_div[i].val;
496
497         /*
498          * There dummy delay is calculated.
499          * It should be about one I2C clock period long.
500          * This delay is used in I2C bus disable function
501          * to fix chip hardware bug.
502          */
503         i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div
504                 + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
505
506 #ifdef CONFIG_I2C_DEBUG_BUS
507         dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n",
508                 i2c_clk_rate, div);
509         dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n",
510                 i2c_clk_div[i].val, i2c_clk_div[i].div);
511 #endif
512 }
513
514 static int i2c_imx_clk_notifier_call(struct notifier_block *nb,
515                                      unsigned long action, void *data)
516 {
517         struct clk_notifier_data *ndata = data;
518         struct imx_i2c_struct *i2c_imx = container_of(&ndata->clk,
519                                                       struct imx_i2c_struct,
520                                                       clk);
521
522         if (action & POST_RATE_CHANGE)
523                 i2c_imx_set_clk(i2c_imx, ndata->new_rate);
524
525         return NOTIFY_OK;
526 }
527
528 static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
529 {
530         unsigned int temp = 0;
531         int result;
532
533         dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
534
535         imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR);
536         /* Enable I2C controller */
537         imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
538         imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR);
539
540         /* Wait controller to be stable */
541         usleep_range(50, 150);
542
543         /* Start I2C transaction */
544         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
545         temp |= I2CR_MSTA;
546         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
547         result = i2c_imx_bus_busy(i2c_imx, 1);
548         if (result)
549                 return result;
550
551         temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
552         temp &= ~I2CR_DMAEN;
553         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
554         return result;
555 }
556
557 static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
558 {
559         unsigned int temp = 0;
560
561         if (!i2c_imx->stopped) {
562                 /* Stop I2C transaction */
563                 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
564                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
565                 temp &= ~(I2CR_MSTA | I2CR_MTX);
566                 if (i2c_imx->dma)
567                         temp &= ~I2CR_DMAEN;
568                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
569         }
570         if (is_imx1_i2c(i2c_imx)) {
571                 /*
572                  * This delay caused by an i.MXL hardware bug.
573                  * If no (or too short) delay, no "STOP" bit will be generated.
574                  */
575                 udelay(i2c_imx->disable_delay);
576         }
577
578         if (!i2c_imx->stopped)
579                 i2c_imx_bus_busy(i2c_imx, 0);
580
581         /* Disable I2C controller */
582         temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
583         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
584 }
585
586 static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
587 {
588         struct imx_i2c_struct *i2c_imx = dev_id;
589         unsigned int temp;
590
591         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
592         if (temp & I2SR_IIF) {
593                 /* save status register */
594                 i2c_imx->i2csr = temp;
595                 temp &= ~I2SR_IIF;
596                 temp |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF);
597                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
598                 wake_up(&i2c_imx->queue);
599                 return IRQ_HANDLED;
600         }
601
602         return IRQ_NONE;
603 }
604
605 static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx,
606                                         struct i2c_msg *msgs)
607 {
608         int result;
609         unsigned long time_left;
610         unsigned int temp = 0;
611         unsigned long orig_jiffies = jiffies;
612         struct imx_i2c_dma *dma = i2c_imx->dma;
613         struct device *dev = &i2c_imx->adapter.dev;
614
615         dma->chan_using = dma->chan_tx;
616         dma->dma_transfer_dir = DMA_MEM_TO_DEV;
617         dma->dma_data_dir = DMA_TO_DEVICE;
618         dma->dma_len = msgs->len - 1;
619         result = i2c_imx_dma_xfer(i2c_imx, msgs);
620         if (result)
621                 return result;
622
623         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
624         temp |= I2CR_DMAEN;
625         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
626
627         /*
628          * Write slave address.
629          * The first byte must be transmitted by the CPU.
630          */
631         imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
632         time_left = wait_for_completion_timeout(
633                                 &i2c_imx->dma->cmd_complete,
634                                 msecs_to_jiffies(DMA_TIMEOUT));
635         if (time_left == 0) {
636                 dmaengine_terminate_all(dma->chan_using);
637                 return -ETIMEDOUT;
638         }
639
640         /* Waiting for transfer complete. */
641         while (1) {
642                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
643                 if (temp & I2SR_ICF)
644                         break;
645                 if (time_after(jiffies, orig_jiffies +
646                                 msecs_to_jiffies(DMA_TIMEOUT))) {
647                         dev_dbg(dev, "<%s> Timeout\n", __func__);
648                         return -ETIMEDOUT;
649                 }
650                 schedule();
651         }
652
653         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
654         temp &= ~I2CR_DMAEN;
655         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
656
657         /* The last data byte must be transferred by the CPU. */
658         imx_i2c_write_reg(msgs->buf[msgs->len-1],
659                                 i2c_imx, IMX_I2C_I2DR);
660         result = i2c_imx_trx_complete(i2c_imx);
661         if (result)
662                 return result;
663
664         return i2c_imx_acked(i2c_imx);
665 }
666
667 static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx,
668                         struct i2c_msg *msgs, bool is_lastmsg)
669 {
670         int result;
671         unsigned long time_left;
672         unsigned int temp;
673         unsigned long orig_jiffies = jiffies;
674         struct imx_i2c_dma *dma = i2c_imx->dma;
675         struct device *dev = &i2c_imx->adapter.dev;
676
677
678         dma->chan_using = dma->chan_rx;
679         dma->dma_transfer_dir = DMA_DEV_TO_MEM;
680         dma->dma_data_dir = DMA_FROM_DEVICE;
681         /* The last two data bytes must be transferred by the CPU. */
682         dma->dma_len = msgs->len - 2;
683         result = i2c_imx_dma_xfer(i2c_imx, msgs);
684         if (result)
685                 return result;
686
687         time_left = wait_for_completion_timeout(
688                                 &i2c_imx->dma->cmd_complete,
689                                 msecs_to_jiffies(DMA_TIMEOUT));
690         if (time_left == 0) {
691                 dmaengine_terminate_all(dma->chan_using);
692                 return -ETIMEDOUT;
693         }
694
695         /* waiting for transfer complete. */
696         while (1) {
697                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
698                 if (temp & I2SR_ICF)
699                         break;
700                 if (time_after(jiffies, orig_jiffies +
701                                 msecs_to_jiffies(DMA_TIMEOUT))) {
702                         dev_dbg(dev, "<%s> Timeout\n", __func__);
703                         return -ETIMEDOUT;
704                 }
705                 schedule();
706         }
707
708         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
709         temp &= ~I2CR_DMAEN;
710         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
711
712         /* read n-1 byte data */
713         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
714         temp |= I2CR_TXAK;
715         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
716
717         msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
718         /* read n byte data */
719         result = i2c_imx_trx_complete(i2c_imx);
720         if (result)
721                 return result;
722
723         if (is_lastmsg) {
724                 /*
725                  * It must generate STOP before read I2DR to prevent
726                  * controller from generating another clock cycle
727                  */
728                 dev_dbg(dev, "<%s> clear MSTA\n", __func__);
729                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
730                 temp &= ~(I2CR_MSTA | I2CR_MTX);
731                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
732                 i2c_imx_bus_busy(i2c_imx, 0);
733         } else {
734                 /*
735                  * For i2c master receiver repeat restart operation like:
736                  * read -> repeat MSTA -> read/write
737                  * The controller must set MTX before read the last byte in
738                  * the first read operation, otherwise the first read cost
739                  * one extra clock cycle.
740                  */
741                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
742                 temp |= I2CR_MTX;
743                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
744         }
745         msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
746
747         return 0;
748 }
749
750 static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
751 {
752         int i, result;
753
754         dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
755                 __func__, i2c_8bit_addr_from_msg(msgs));
756
757         /* write slave address */
758         imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
759         result = i2c_imx_trx_complete(i2c_imx);
760         if (result)
761                 return result;
762         result = i2c_imx_acked(i2c_imx);
763         if (result)
764                 return result;
765         dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
766
767         /* write data */
768         for (i = 0; i < msgs->len; i++) {
769                 dev_dbg(&i2c_imx->adapter.dev,
770                         "<%s> write byte: B%d=0x%X\n",
771                         __func__, i, msgs->buf[i]);
772                 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR);
773                 result = i2c_imx_trx_complete(i2c_imx);
774                 if (result)
775                         return result;
776                 result = i2c_imx_acked(i2c_imx);
777                 if (result)
778                         return result;
779         }
780         return 0;
781 }
782
783 static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, bool is_lastmsg)
784 {
785         int i, result;
786         unsigned int temp;
787         int block_data = msgs->flags & I2C_M_RECV_LEN;
788         int use_dma = i2c_imx->dma && msgs->len >= DMA_THRESHOLD && !block_data;
789
790         dev_dbg(&i2c_imx->adapter.dev,
791                 "<%s> write slave address: addr=0x%x\n",
792                 __func__, i2c_8bit_addr_from_msg(msgs));
793
794         /* write slave address */
795         imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
796         result = i2c_imx_trx_complete(i2c_imx);
797         if (result)
798                 return result;
799         result = i2c_imx_acked(i2c_imx);
800         if (result)
801                 return result;
802
803         dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
804
805         /* setup bus to read data */
806         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
807         temp &= ~I2CR_MTX;
808
809         /*
810          * Reset the I2CR_TXAK flag initially for SMBus block read since the
811          * length is unknown
812          */
813         if ((msgs->len - 1) || block_data)
814                 temp &= ~I2CR_TXAK;
815         if (use_dma)
816                 temp |= I2CR_DMAEN;
817         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
818         imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */
819
820         dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
821
822         if (use_dma)
823                 return i2c_imx_dma_read(i2c_imx, msgs, is_lastmsg);
824
825         /* read data */
826         for (i = 0; i < msgs->len; i++) {
827                 u8 len = 0;
828
829                 result = i2c_imx_trx_complete(i2c_imx);
830                 if (result)
831                         return result;
832                 /*
833                  * First byte is the length of remaining packet
834                  * in the SMBus block data read. Add it to
835                  * msgs->len.
836                  */
837                 if ((!i) && block_data) {
838                         len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
839                         if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX))
840                                 return -EPROTO;
841                         dev_dbg(&i2c_imx->adapter.dev,
842                                 "<%s> read length: 0x%X\n",
843                                 __func__, len);
844                         msgs->len += len;
845                 }
846                 if (i == (msgs->len - 1)) {
847                         if (is_lastmsg) {
848                                 /*
849                                  * It must generate STOP before read I2DR to prevent
850                                  * controller from generating another clock cycle
851                                  */
852                                 dev_dbg(&i2c_imx->adapter.dev,
853                                         "<%s> clear MSTA\n", __func__);
854                                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
855                                 temp &= ~(I2CR_MSTA | I2CR_MTX);
856                                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
857                                 i2c_imx_bus_busy(i2c_imx, 0);
858                         } else {
859                                 /*
860                                  * For i2c master receiver repeat restart operation like:
861                                  * read -> repeat MSTA -> read/write
862                                  * The controller must set MTX before read the last byte in
863                                  * the first read operation, otherwise the first read cost
864                                  * one extra clock cycle.
865                                  */
866                                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
867                                 temp |= I2CR_MTX;
868                                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
869                         }
870                 } else if (i == (msgs->len - 2)) {
871                         dev_dbg(&i2c_imx->adapter.dev,
872                                 "<%s> set TXAK\n", __func__);
873                         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
874                         temp |= I2CR_TXAK;
875                         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
876                 }
877                 if ((!i) && block_data)
878                         msgs->buf[0] = len;
879                 else
880                         msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
881                 dev_dbg(&i2c_imx->adapter.dev,
882                         "<%s> read byte: B%d=0x%X\n",
883                         __func__, i, msgs->buf[i]);
884         }
885         return 0;
886 }
887
888 static int i2c_imx_xfer(struct i2c_adapter *adapter,
889                                                 struct i2c_msg *msgs, int num)
890 {
891         unsigned int i, temp;
892         int result;
893         bool is_lastmsg = false;
894         struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
895
896         dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
897
898         result = pm_runtime_get_sync(i2c_imx->adapter.dev.parent);
899         if (result < 0)
900                 goto out;
901
902         /* Start I2C transfer */
903         result = i2c_imx_start(i2c_imx);
904         if (result) {
905                 if (i2c_imx->adapter.bus_recovery_info) {
906                         i2c_recover_bus(&i2c_imx->adapter);
907                         result = i2c_imx_start(i2c_imx);
908                 }
909         }
910
911         if (result)
912                 goto fail0;
913
914         /* read/write data */
915         for (i = 0; i < num; i++) {
916                 if (i == num - 1)
917                         is_lastmsg = true;
918
919                 if (i) {
920                         dev_dbg(&i2c_imx->adapter.dev,
921                                 "<%s> repeated start\n", __func__);
922                         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
923                         temp |= I2CR_RSTA;
924                         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
925                         result = i2c_imx_bus_busy(i2c_imx, 1);
926                         if (result)
927                                 goto fail0;
928                 }
929                 dev_dbg(&i2c_imx->adapter.dev,
930                         "<%s> transfer message: %d\n", __func__, i);
931                 /* write/read data */
932 #ifdef CONFIG_I2C_DEBUG_BUS
933                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
934                 dev_dbg(&i2c_imx->adapter.dev,
935                         "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n",
936                         __func__,
937                         (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
938                         (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
939                         (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
940                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
941                 dev_dbg(&i2c_imx->adapter.dev,
942                         "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n",
943                         __func__,
944                         (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
945                         (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
946                         (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
947                         (temp & I2SR_RXAK ? 1 : 0));
948 #endif
949                 if (msgs[i].flags & I2C_M_RD)
950                         result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg);
951                 else {
952                         if (i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD)
953                                 result = i2c_imx_dma_write(i2c_imx, &msgs[i]);
954                         else
955                                 result = i2c_imx_write(i2c_imx, &msgs[i]);
956                 }
957                 if (result)
958                         goto fail0;
959         }
960
961 fail0:
962         /* Stop I2C transfer */
963         i2c_imx_stop(i2c_imx);
964
965         pm_runtime_mark_last_busy(i2c_imx->adapter.dev.parent);
966         pm_runtime_put_autosuspend(i2c_imx->adapter.dev.parent);
967
968 out:
969         dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
970                 (result < 0) ? "error" : "success msg",
971                         (result < 0) ? result : num);
972         return (result < 0) ? result : num;
973 }
974
975 static void i2c_imx_prepare_recovery(struct i2c_adapter *adap)
976 {
977         struct imx_i2c_struct *i2c_imx;
978
979         i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
980
981         pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_gpio);
982 }
983
984 static void i2c_imx_unprepare_recovery(struct i2c_adapter *adap)
985 {
986         struct imx_i2c_struct *i2c_imx;
987
988         i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
989
990         pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_default);
991 }
992
993 /*
994  * We switch SCL and SDA to their GPIO function and do some bitbanging
995  * for bus recovery. These alternative pinmux settings can be
996  * described in the device tree by a separate pinctrl state "gpio". If
997  * this is missing this is not a big problem, the only implication is
998  * that we can't do bus recovery.
999  */
1000 static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx,
1001                 struct platform_device *pdev)
1002 {
1003         struct i2c_bus_recovery_info *rinfo = &i2c_imx->rinfo;
1004
1005         i2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev);
1006         if (!i2c_imx->pinctrl || IS_ERR(i2c_imx->pinctrl)) {
1007                 dev_info(&pdev->dev, "can't get pinctrl, bus recovery not supported\n");
1008                 return PTR_ERR(i2c_imx->pinctrl);
1009         }
1010
1011         i2c_imx->pinctrl_pins_default = pinctrl_lookup_state(i2c_imx->pinctrl,
1012                         PINCTRL_STATE_DEFAULT);
1013         i2c_imx->pinctrl_pins_gpio = pinctrl_lookup_state(i2c_imx->pinctrl,
1014                         "gpio");
1015         rinfo->sda_gpiod = devm_gpiod_get(&pdev->dev, "sda", GPIOD_IN);
1016         rinfo->scl_gpiod = devm_gpiod_get(&pdev->dev, "scl", GPIOD_OUT_HIGH_OPEN_DRAIN);
1017
1018         if (PTR_ERR(rinfo->sda_gpiod) == -EPROBE_DEFER ||
1019             PTR_ERR(rinfo->scl_gpiod) == -EPROBE_DEFER) {
1020                 return -EPROBE_DEFER;
1021         } else if (IS_ERR(rinfo->sda_gpiod) ||
1022                    IS_ERR(rinfo->scl_gpiod) ||
1023                    IS_ERR(i2c_imx->pinctrl_pins_default) ||
1024                    IS_ERR(i2c_imx->pinctrl_pins_gpio)) {
1025                 dev_dbg(&pdev->dev, "recovery information incomplete\n");
1026                 return 0;
1027         }
1028
1029         dev_dbg(&pdev->dev, "using scl%s for recovery\n",
1030                 rinfo->sda_gpiod ? ",sda" : "");
1031
1032         rinfo->prepare_recovery = i2c_imx_prepare_recovery;
1033         rinfo->unprepare_recovery = i2c_imx_unprepare_recovery;
1034         rinfo->recover_bus = i2c_generic_scl_recovery;
1035         i2c_imx->adapter.bus_recovery_info = rinfo;
1036
1037         return 0;
1038 }
1039
1040 static u32 i2c_imx_func(struct i2c_adapter *adapter)
1041 {
1042         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
1043                 | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
1044 }
1045
1046 static const struct i2c_algorithm i2c_imx_algo = {
1047         .master_xfer    = i2c_imx_xfer,
1048         .functionality  = i2c_imx_func,
1049 };
1050
1051 static int i2c_imx_probe(struct platform_device *pdev)
1052 {
1053         const struct of_device_id *of_id = of_match_device(i2c_imx_dt_ids,
1054                                                            &pdev->dev);
1055         struct imx_i2c_struct *i2c_imx;
1056         struct resource *res;
1057         struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev);
1058         void __iomem *base;
1059         int irq, ret;
1060         dma_addr_t phy_addr;
1061
1062         dev_dbg(&pdev->dev, "<%s>\n", __func__);
1063
1064         irq = platform_get_irq(pdev, 0);
1065         if (irq < 0) {
1066                 dev_err(&pdev->dev, "can't get irq number\n");
1067                 return irq;
1068         }
1069
1070         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1071         base = devm_ioremap_resource(&pdev->dev, res);
1072         if (IS_ERR(base))
1073                 return PTR_ERR(base);
1074
1075         phy_addr = (dma_addr_t)res->start;
1076         i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL);
1077         if (!i2c_imx)
1078                 return -ENOMEM;
1079
1080         if (of_id)
1081                 i2c_imx->hwdata = of_id->data;
1082         else
1083                 i2c_imx->hwdata = (struct imx_i2c_hwdata *)
1084                                 platform_get_device_id(pdev)->driver_data;
1085
1086         /* Setup i2c_imx driver structure */
1087         strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));
1088         i2c_imx->adapter.owner          = THIS_MODULE;
1089         i2c_imx->adapter.algo           = &i2c_imx_algo;
1090         i2c_imx->adapter.dev.parent     = &pdev->dev;
1091         i2c_imx->adapter.nr             = pdev->id;
1092         i2c_imx->adapter.dev.of_node    = pdev->dev.of_node;
1093         i2c_imx->base                   = base;
1094
1095         /* Get I2C clock */
1096         i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
1097         if (IS_ERR(i2c_imx->clk)) {
1098                 if (PTR_ERR(i2c_imx->clk) != -EPROBE_DEFER)
1099                         dev_err(&pdev->dev, "can't get I2C clock\n");
1100                 return PTR_ERR(i2c_imx->clk);
1101         }
1102
1103         ret = clk_prepare_enable(i2c_imx->clk);
1104         if (ret) {
1105                 dev_err(&pdev->dev, "can't enable I2C clock, ret=%d\n", ret);
1106                 return ret;
1107         }
1108
1109         /* Request IRQ */
1110         ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, IRQF_SHARED,
1111                                 pdev->name, i2c_imx);
1112         if (ret) {
1113                 dev_err(&pdev->dev, "can't claim irq %d\n", irq);
1114                 goto clk_disable;
1115         }
1116
1117         /* Init queue */
1118         init_waitqueue_head(&i2c_imx->queue);
1119
1120         /* Set up adapter data */
1121         i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
1122
1123         /* Set up platform driver data */
1124         platform_set_drvdata(pdev, i2c_imx);
1125
1126         pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT);
1127         pm_runtime_use_autosuspend(&pdev->dev);
1128         pm_runtime_set_active(&pdev->dev);
1129         pm_runtime_enable(&pdev->dev);
1130
1131         ret = pm_runtime_get_sync(&pdev->dev);
1132         if (ret < 0)
1133                 goto rpm_disable;
1134
1135         /* Set up clock divider */
1136         i2c_imx->bitrate = IMX_I2C_BIT_RATE;
1137         ret = of_property_read_u32(pdev->dev.of_node,
1138                                    "clock-frequency", &i2c_imx->bitrate);
1139         if (ret < 0 && pdata && pdata->bitrate)
1140                 i2c_imx->bitrate = pdata->bitrate;
1141         i2c_imx->clk_change_nb.notifier_call = i2c_imx_clk_notifier_call;
1142         clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb);
1143         i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk));
1144
1145         /* Set up chip registers to defaults */
1146         imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
1147                         i2c_imx, IMX_I2C_I2CR);
1148         imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
1149
1150         /* Init optional bus recovery function */
1151         ret = i2c_imx_init_recovery_info(i2c_imx, pdev);
1152         /* Give it another chance if pinctrl used is not ready yet */
1153         if (ret == -EPROBE_DEFER)
1154                 goto clk_notifier_unregister;
1155
1156         /* Add I2C adapter */
1157         ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
1158         if (ret < 0)
1159                 goto clk_notifier_unregister;
1160
1161         pm_runtime_mark_last_busy(&pdev->dev);
1162         pm_runtime_put_autosuspend(&pdev->dev);
1163
1164         dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
1165         dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res);
1166         dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
1167                 i2c_imx->adapter.name);
1168
1169         /* Init DMA config if supported */
1170         ret = i2c_imx_dma_request(i2c_imx, phy_addr);
1171         if (ret < 0)
1172                 goto clk_notifier_unregister;
1173
1174         dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
1175         return 0;   /* Return OK */
1176
1177 clk_notifier_unregister:
1178         clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);
1179 rpm_disable:
1180         pm_runtime_put_noidle(&pdev->dev);
1181         pm_runtime_disable(&pdev->dev);
1182         pm_runtime_set_suspended(&pdev->dev);
1183         pm_runtime_dont_use_autosuspend(&pdev->dev);
1184
1185 clk_disable:
1186         clk_disable_unprepare(i2c_imx->clk);
1187         return ret;
1188 }
1189
1190 static int i2c_imx_remove(struct platform_device *pdev)
1191 {
1192         struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
1193         int ret;
1194
1195         ret = pm_runtime_get_sync(&pdev->dev);
1196         if (ret < 0)
1197                 return ret;
1198
1199         /* remove adapter */
1200         dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
1201         i2c_del_adapter(&i2c_imx->adapter);
1202
1203         if (i2c_imx->dma)
1204                 i2c_imx_dma_free(i2c_imx);
1205
1206         /* setup chip registers to defaults */
1207         imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
1208         imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR);
1209         imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR);
1210         imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR);
1211
1212         clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);
1213         clk_disable_unprepare(i2c_imx->clk);
1214
1215         pm_runtime_put_noidle(&pdev->dev);
1216         pm_runtime_disable(&pdev->dev);
1217
1218         return 0;
1219 }
1220
1221 #ifdef CONFIG_PM
1222 static int i2c_imx_runtime_suspend(struct device *dev)
1223 {
1224         struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
1225
1226         clk_disable(i2c_imx->clk);
1227
1228         return 0;
1229 }
1230
1231 static int i2c_imx_runtime_resume(struct device *dev)
1232 {
1233         struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
1234         int ret;
1235
1236         ret = clk_enable(i2c_imx->clk);
1237         if (ret)
1238                 dev_err(dev, "can't enable I2C clock, ret=%d\n", ret);
1239
1240         return ret;
1241 }
1242
1243 static const struct dev_pm_ops i2c_imx_pm_ops = {
1244         SET_RUNTIME_PM_OPS(i2c_imx_runtime_suspend,
1245                            i2c_imx_runtime_resume, NULL)
1246 };
1247 #define I2C_IMX_PM_OPS (&i2c_imx_pm_ops)
1248 #else
1249 #define I2C_IMX_PM_OPS NULL
1250 #endif /* CONFIG_PM */
1251
1252 static struct platform_driver i2c_imx_driver = {
1253         .probe = i2c_imx_probe,
1254         .remove = i2c_imx_remove,
1255         .driver = {
1256                 .name = DRIVER_NAME,
1257                 .pm = I2C_IMX_PM_OPS,
1258                 .of_match_table = i2c_imx_dt_ids,
1259         },
1260         .id_table = imx_i2c_devtype,
1261 };
1262
1263 static int __init i2c_adap_imx_init(void)
1264 {
1265         return platform_driver_register(&i2c_imx_driver);
1266 }
1267 subsys_initcall(i2c_adap_imx_init);
1268
1269 static void __exit i2c_adap_imx_exit(void)
1270 {
1271         platform_driver_unregister(&i2c_imx_driver);
1272 }
1273 module_exit(i2c_adap_imx_exit);
1274
1275 MODULE_LICENSE("GPL");
1276 MODULE_AUTHOR("Darius Augulis");
1277 MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
1278 MODULE_ALIAS("platform:" DRIVER_NAME);