Merge tag 'for-linus-unmerged' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma...
[muen/linux.git] / drivers / infiniband / hw / mlx5 / qp.c
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32
33 #include <linux/module.h>
34 #include <rdma/ib_umem.h>
35 #include <rdma/ib_cache.h>
36 #include <rdma/ib_user_verbs.h>
37 #include <linux/mlx5/fs.h>
38 #include "mlx5_ib.h"
39 #include "ib_rep.h"
40
41 /* not supported currently */
42 static int wq_signature;
43
44 enum {
45         MLX5_IB_ACK_REQ_FREQ    = 8,
46 };
47
48 enum {
49         MLX5_IB_DEFAULT_SCHED_QUEUE     = 0x83,
50         MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
51         MLX5_IB_LINK_TYPE_IB            = 0,
52         MLX5_IB_LINK_TYPE_ETH           = 1
53 };
54
55 enum {
56         MLX5_IB_SQ_STRIDE       = 6,
57 };
58
59 static const u32 mlx5_ib_opcode[] = {
60         [IB_WR_SEND]                            = MLX5_OPCODE_SEND,
61         [IB_WR_LSO]                             = MLX5_OPCODE_LSO,
62         [IB_WR_SEND_WITH_IMM]                   = MLX5_OPCODE_SEND_IMM,
63         [IB_WR_RDMA_WRITE]                      = MLX5_OPCODE_RDMA_WRITE,
64         [IB_WR_RDMA_WRITE_WITH_IMM]             = MLX5_OPCODE_RDMA_WRITE_IMM,
65         [IB_WR_RDMA_READ]                       = MLX5_OPCODE_RDMA_READ,
66         [IB_WR_ATOMIC_CMP_AND_SWP]              = MLX5_OPCODE_ATOMIC_CS,
67         [IB_WR_ATOMIC_FETCH_AND_ADD]            = MLX5_OPCODE_ATOMIC_FA,
68         [IB_WR_SEND_WITH_INV]                   = MLX5_OPCODE_SEND_INVAL,
69         [IB_WR_LOCAL_INV]                       = MLX5_OPCODE_UMR,
70         [IB_WR_REG_MR]                          = MLX5_OPCODE_UMR,
71         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = MLX5_OPCODE_ATOMIC_MASKED_CS,
72         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = MLX5_OPCODE_ATOMIC_MASKED_FA,
73         [MLX5_IB_WR_UMR]                        = MLX5_OPCODE_UMR,
74 };
75
76 struct mlx5_wqe_eth_pad {
77         u8 rsvd0[16];
78 };
79
80 enum raw_qp_set_mask_map {
81         MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID         = 1UL << 0,
82         MLX5_RAW_QP_RATE_LIMIT                  = 1UL << 1,
83 };
84
85 struct mlx5_modify_raw_qp_param {
86         u16 operation;
87
88         u32 set_mask; /* raw_qp_set_mask_map */
89
90         struct mlx5_rate_limit rl;
91
92         u8 rq_q_ctr_id;
93 };
94
95 static void get_cqs(enum ib_qp_type qp_type,
96                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
97                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
98
99 static int is_qp0(enum ib_qp_type qp_type)
100 {
101         return qp_type == IB_QPT_SMI;
102 }
103
104 static int is_sqp(enum ib_qp_type qp_type)
105 {
106         return is_qp0(qp_type) || is_qp1(qp_type);
107 }
108
109 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
110 {
111         return mlx5_buf_offset(&qp->buf, offset);
112 }
113
114 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
115 {
116         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
117 }
118
119 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
120 {
121         return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
122 }
123
124 /**
125  * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
126  *
127  * @qp: QP to copy from.
128  * @send: copy from the send queue when non-zero, use the receive queue
129  *        otherwise.
130  * @wqe_index:  index to start copying from. For send work queues, the
131  *              wqe_index is in units of MLX5_SEND_WQE_BB.
132  *              For receive work queue, it is the number of work queue
133  *              element in the queue.
134  * @buffer: destination buffer.
135  * @length: maximum number of bytes to copy.
136  *
137  * Copies at least a single WQE, but may copy more data.
138  *
139  * Return: the number of bytes copied, or an error code.
140  */
141 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
142                           void *buffer, u32 length,
143                           struct mlx5_ib_qp_base *base)
144 {
145         struct ib_device *ibdev = qp->ibqp.device;
146         struct mlx5_ib_dev *dev = to_mdev(ibdev);
147         struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
148         size_t offset;
149         size_t wq_end;
150         struct ib_umem *umem = base->ubuffer.umem;
151         u32 first_copy_length;
152         int wqe_length;
153         int ret;
154
155         if (wq->wqe_cnt == 0) {
156                 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
157                             qp->ibqp.qp_type);
158                 return -EINVAL;
159         }
160
161         offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
162         wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
163
164         if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
165                 return -EINVAL;
166
167         if (offset > umem->length ||
168             (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
169                 return -EINVAL;
170
171         first_copy_length = min_t(u32, offset + length, wq_end) - offset;
172         ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
173         if (ret)
174                 return ret;
175
176         if (send) {
177                 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
178                 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
179
180                 wqe_length = ds * MLX5_WQE_DS_UNITS;
181         } else {
182                 wqe_length = 1 << wq->wqe_shift;
183         }
184
185         if (wqe_length <= first_copy_length)
186                 return first_copy_length;
187
188         ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
189                                 wqe_length - first_copy_length);
190         if (ret)
191                 return ret;
192
193         return wqe_length;
194 }
195
196 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
197 {
198         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
199         struct ib_event event;
200
201         if (type == MLX5_EVENT_TYPE_PATH_MIG) {
202                 /* This event is only valid for trans_qps */
203                 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
204         }
205
206         if (ibqp->event_handler) {
207                 event.device     = ibqp->device;
208                 event.element.qp = ibqp;
209                 switch (type) {
210                 case MLX5_EVENT_TYPE_PATH_MIG:
211                         event.event = IB_EVENT_PATH_MIG;
212                         break;
213                 case MLX5_EVENT_TYPE_COMM_EST:
214                         event.event = IB_EVENT_COMM_EST;
215                         break;
216                 case MLX5_EVENT_TYPE_SQ_DRAINED:
217                         event.event = IB_EVENT_SQ_DRAINED;
218                         break;
219                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
220                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
221                         break;
222                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
223                         event.event = IB_EVENT_QP_FATAL;
224                         break;
225                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
226                         event.event = IB_EVENT_PATH_MIG_ERR;
227                         break;
228                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
229                         event.event = IB_EVENT_QP_REQ_ERR;
230                         break;
231                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
232                         event.event = IB_EVENT_QP_ACCESS_ERR;
233                         break;
234                 default:
235                         pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
236                         return;
237                 }
238
239                 ibqp->event_handler(&event, ibqp->qp_context);
240         }
241 }
242
243 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
244                        int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
245 {
246         int wqe_size;
247         int wq_size;
248
249         /* Sanity check RQ size before proceeding */
250         if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
251                 return -EINVAL;
252
253         if (!has_rq) {
254                 qp->rq.max_gs = 0;
255                 qp->rq.wqe_cnt = 0;
256                 qp->rq.wqe_shift = 0;
257                 cap->max_recv_wr = 0;
258                 cap->max_recv_sge = 0;
259         } else {
260                 if (ucmd) {
261                         qp->rq.wqe_cnt = ucmd->rq_wqe_count;
262                         qp->rq.wqe_shift = ucmd->rq_wqe_shift;
263                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
264                         qp->rq.max_post = qp->rq.wqe_cnt;
265                 } else {
266                         wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
267                         wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
268                         wqe_size = roundup_pow_of_two(wqe_size);
269                         wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
270                         wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
271                         qp->rq.wqe_cnt = wq_size / wqe_size;
272                         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
273                                 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
274                                             wqe_size,
275                                             MLX5_CAP_GEN(dev->mdev,
276                                                          max_wqe_sz_rq));
277                                 return -EINVAL;
278                         }
279                         qp->rq.wqe_shift = ilog2(wqe_size);
280                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
281                         qp->rq.max_post = qp->rq.wqe_cnt;
282                 }
283         }
284
285         return 0;
286 }
287
288 static int sq_overhead(struct ib_qp_init_attr *attr)
289 {
290         int size = 0;
291
292         switch (attr->qp_type) {
293         case IB_QPT_XRC_INI:
294                 size += sizeof(struct mlx5_wqe_xrc_seg);
295                 /* fall through */
296         case IB_QPT_RC:
297                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
298                         max(sizeof(struct mlx5_wqe_atomic_seg) +
299                             sizeof(struct mlx5_wqe_raddr_seg),
300                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
301                             sizeof(struct mlx5_mkey_seg));
302                 break;
303
304         case IB_QPT_XRC_TGT:
305                 return 0;
306
307         case IB_QPT_UC:
308                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
309                         max(sizeof(struct mlx5_wqe_raddr_seg),
310                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
311                             sizeof(struct mlx5_mkey_seg));
312                 break;
313
314         case IB_QPT_UD:
315                 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
316                         size += sizeof(struct mlx5_wqe_eth_pad) +
317                                 sizeof(struct mlx5_wqe_eth_seg);
318                 /* fall through */
319         case IB_QPT_SMI:
320         case MLX5_IB_QPT_HW_GSI:
321                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
322                         sizeof(struct mlx5_wqe_datagram_seg);
323                 break;
324
325         case MLX5_IB_QPT_REG_UMR:
326                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
327                         sizeof(struct mlx5_wqe_umr_ctrl_seg) +
328                         sizeof(struct mlx5_mkey_seg);
329                 break;
330
331         default:
332                 return -EINVAL;
333         }
334
335         return size;
336 }
337
338 static int calc_send_wqe(struct ib_qp_init_attr *attr)
339 {
340         int inl_size = 0;
341         int size;
342
343         size = sq_overhead(attr);
344         if (size < 0)
345                 return size;
346
347         if (attr->cap.max_inline_data) {
348                 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
349                         attr->cap.max_inline_data;
350         }
351
352         size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
353         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
354             ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
355                         return MLX5_SIG_WQE_SIZE;
356         else
357                 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
358 }
359
360 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
361 {
362         int max_sge;
363
364         if (attr->qp_type == IB_QPT_RC)
365                 max_sge = (min_t(int, wqe_size, 512) -
366                            sizeof(struct mlx5_wqe_ctrl_seg) -
367                            sizeof(struct mlx5_wqe_raddr_seg)) /
368                         sizeof(struct mlx5_wqe_data_seg);
369         else if (attr->qp_type == IB_QPT_XRC_INI)
370                 max_sge = (min_t(int, wqe_size, 512) -
371                            sizeof(struct mlx5_wqe_ctrl_seg) -
372                            sizeof(struct mlx5_wqe_xrc_seg) -
373                            sizeof(struct mlx5_wqe_raddr_seg)) /
374                         sizeof(struct mlx5_wqe_data_seg);
375         else
376                 max_sge = (wqe_size - sq_overhead(attr)) /
377                         sizeof(struct mlx5_wqe_data_seg);
378
379         return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
380                      sizeof(struct mlx5_wqe_data_seg));
381 }
382
383 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
384                         struct mlx5_ib_qp *qp)
385 {
386         int wqe_size;
387         int wq_size;
388
389         if (!attr->cap.max_send_wr)
390                 return 0;
391
392         wqe_size = calc_send_wqe(attr);
393         mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
394         if (wqe_size < 0)
395                 return wqe_size;
396
397         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
398                 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
399                             wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
400                 return -EINVAL;
401         }
402
403         qp->max_inline_data = wqe_size - sq_overhead(attr) -
404                               sizeof(struct mlx5_wqe_inline_seg);
405         attr->cap.max_inline_data = qp->max_inline_data;
406
407         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
408                 qp->signature_en = true;
409
410         wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
411         qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
412         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
413                 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
414                             attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
415                             qp->sq.wqe_cnt,
416                             1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
417                 return -ENOMEM;
418         }
419         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
420         qp->sq.max_gs = get_send_sge(attr, wqe_size);
421         if (qp->sq.max_gs < attr->cap.max_send_sge)
422                 return -ENOMEM;
423
424         attr->cap.max_send_sge = qp->sq.max_gs;
425         qp->sq.max_post = wq_size / wqe_size;
426         attr->cap.max_send_wr = qp->sq.max_post;
427
428         return wq_size;
429 }
430
431 static int set_user_buf_size(struct mlx5_ib_dev *dev,
432                             struct mlx5_ib_qp *qp,
433                             struct mlx5_ib_create_qp *ucmd,
434                             struct mlx5_ib_qp_base *base,
435                             struct ib_qp_init_attr *attr)
436 {
437         int desc_sz = 1 << qp->sq.wqe_shift;
438
439         if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
440                 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
441                              desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
442                 return -EINVAL;
443         }
444
445         if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
446                 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
447                              ucmd->sq_wqe_count, ucmd->sq_wqe_count);
448                 return -EINVAL;
449         }
450
451         qp->sq.wqe_cnt = ucmd->sq_wqe_count;
452
453         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
454                 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
455                              qp->sq.wqe_cnt,
456                              1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
457                 return -EINVAL;
458         }
459
460         if (attr->qp_type == IB_QPT_RAW_PACKET ||
461             qp->flags & MLX5_IB_QP_UNDERLAY) {
462                 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
463                 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
464         } else {
465                 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
466                                          (qp->sq.wqe_cnt << 6);
467         }
468
469         return 0;
470 }
471
472 static int qp_has_rq(struct ib_qp_init_attr *attr)
473 {
474         if (attr->qp_type == IB_QPT_XRC_INI ||
475             attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
476             attr->qp_type == MLX5_IB_QPT_REG_UMR ||
477             !attr->cap.max_recv_wr)
478                 return 0;
479
480         return 1;
481 }
482
483 static int first_med_bfreg(void)
484 {
485         return 1;
486 }
487
488 enum {
489         /* this is the first blue flame register in the array of bfregs assigned
490          * to a processes. Since we do not use it for blue flame but rather
491          * regular 64 bit doorbells, we do not need a lock for maintaiing
492          * "odd/even" order
493          */
494         NUM_NON_BLUE_FLAME_BFREGS = 1,
495 };
496
497 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
498 {
499         return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
500 }
501
502 static int num_med_bfreg(struct mlx5_ib_dev *dev,
503                          struct mlx5_bfreg_info *bfregi)
504 {
505         int n;
506
507         n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
508             NUM_NON_BLUE_FLAME_BFREGS;
509
510         return n >= 0 ? n : 0;
511 }
512
513 static int first_hi_bfreg(struct mlx5_ib_dev *dev,
514                           struct mlx5_bfreg_info *bfregi)
515 {
516         int med;
517
518         med = num_med_bfreg(dev, bfregi);
519         return ++med;
520 }
521
522 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
523                                   struct mlx5_bfreg_info *bfregi)
524 {
525         int i;
526
527         for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
528                 if (!bfregi->count[i]) {
529                         bfregi->count[i]++;
530                         return i;
531                 }
532         }
533
534         return -ENOMEM;
535 }
536
537 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
538                                  struct mlx5_bfreg_info *bfregi)
539 {
540         int minidx = first_med_bfreg();
541         int i;
542
543         for (i = first_med_bfreg(); i < first_hi_bfreg(dev, bfregi); i++) {
544                 if (bfregi->count[i] < bfregi->count[minidx])
545                         minidx = i;
546                 if (!bfregi->count[minidx])
547                         break;
548         }
549
550         bfregi->count[minidx]++;
551         return minidx;
552 }
553
554 static int alloc_bfreg(struct mlx5_ib_dev *dev,
555                        struct mlx5_bfreg_info *bfregi,
556                        enum mlx5_ib_latency_class lat)
557 {
558         int bfregn = -EINVAL;
559
560         mutex_lock(&bfregi->lock);
561         switch (lat) {
562         case MLX5_IB_LATENCY_CLASS_LOW:
563                 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
564                 bfregn = 0;
565                 bfregi->count[bfregn]++;
566                 break;
567
568         case MLX5_IB_LATENCY_CLASS_MEDIUM:
569                 if (bfregi->ver < 2)
570                         bfregn = -ENOMEM;
571                 else
572                         bfregn = alloc_med_class_bfreg(dev, bfregi);
573                 break;
574
575         case MLX5_IB_LATENCY_CLASS_HIGH:
576                 if (bfregi->ver < 2)
577                         bfregn = -ENOMEM;
578                 else
579                         bfregn = alloc_high_class_bfreg(dev, bfregi);
580                 break;
581         }
582         mutex_unlock(&bfregi->lock);
583
584         return bfregn;
585 }
586
587 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
588 {
589         mutex_lock(&bfregi->lock);
590         bfregi->count[bfregn]--;
591         mutex_unlock(&bfregi->lock);
592 }
593
594 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
595 {
596         switch (state) {
597         case IB_QPS_RESET:      return MLX5_QP_STATE_RST;
598         case IB_QPS_INIT:       return MLX5_QP_STATE_INIT;
599         case IB_QPS_RTR:        return MLX5_QP_STATE_RTR;
600         case IB_QPS_RTS:        return MLX5_QP_STATE_RTS;
601         case IB_QPS_SQD:        return MLX5_QP_STATE_SQD;
602         case IB_QPS_SQE:        return MLX5_QP_STATE_SQER;
603         case IB_QPS_ERR:        return MLX5_QP_STATE_ERR;
604         default:                return -1;
605         }
606 }
607
608 static int to_mlx5_st(enum ib_qp_type type)
609 {
610         switch (type) {
611         case IB_QPT_RC:                 return MLX5_QP_ST_RC;
612         case IB_QPT_UC:                 return MLX5_QP_ST_UC;
613         case IB_QPT_UD:                 return MLX5_QP_ST_UD;
614         case MLX5_IB_QPT_REG_UMR:       return MLX5_QP_ST_REG_UMR;
615         case IB_QPT_XRC_INI:
616         case IB_QPT_XRC_TGT:            return MLX5_QP_ST_XRC;
617         case IB_QPT_SMI:                return MLX5_QP_ST_QP0;
618         case MLX5_IB_QPT_HW_GSI:        return MLX5_QP_ST_QP1;
619         case MLX5_IB_QPT_DCI:           return MLX5_QP_ST_DCI;
620         case IB_QPT_RAW_IPV6:           return MLX5_QP_ST_RAW_IPV6;
621         case IB_QPT_RAW_PACKET:
622         case IB_QPT_RAW_ETHERTYPE:      return MLX5_QP_ST_RAW_ETHERTYPE;
623         case IB_QPT_MAX:
624         default:                return -EINVAL;
625         }
626 }
627
628 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
629                              struct mlx5_ib_cq *recv_cq);
630 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
631                                struct mlx5_ib_cq *recv_cq);
632
633 static int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
634                                struct mlx5_bfreg_info *bfregi, int bfregn,
635                                bool dyn_bfreg)
636 {
637         int bfregs_per_sys_page;
638         int index_of_sys_page;
639         int offset;
640
641         bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
642                                 MLX5_NON_FP_BFREGS_PER_UAR;
643         index_of_sys_page = bfregn / bfregs_per_sys_page;
644
645         if (dyn_bfreg) {
646                 index_of_sys_page += bfregi->num_static_sys_pages;
647                 if (bfregn > bfregi->num_dyn_bfregs ||
648                     bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
649                         mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
650                         return -EINVAL;
651                 }
652         }
653
654         offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
655         return bfregi->sys_pages[index_of_sys_page] + offset;
656 }
657
658 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
659                             struct ib_pd *pd,
660                             unsigned long addr, size_t size,
661                             struct ib_umem **umem,
662                             int *npages, int *page_shift, int *ncont,
663                             u32 *offset)
664 {
665         int err;
666
667         *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
668         if (IS_ERR(*umem)) {
669                 mlx5_ib_dbg(dev, "umem_get failed\n");
670                 return PTR_ERR(*umem);
671         }
672
673         mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
674
675         err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
676         if (err) {
677                 mlx5_ib_warn(dev, "bad offset\n");
678                 goto err_umem;
679         }
680
681         mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
682                     addr, size, *npages, *page_shift, *ncont, *offset);
683
684         return 0;
685
686 err_umem:
687         ib_umem_release(*umem);
688         *umem = NULL;
689
690         return err;
691 }
692
693 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
694                             struct mlx5_ib_rwq *rwq)
695 {
696         struct mlx5_ib_ucontext *context;
697
698         if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
699                 atomic_dec(&dev->delay_drop.rqs_cnt);
700
701         context = to_mucontext(pd->uobject->context);
702         mlx5_ib_db_unmap_user(context, &rwq->db);
703         if (rwq->umem)
704                 ib_umem_release(rwq->umem);
705 }
706
707 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
708                           struct mlx5_ib_rwq *rwq,
709                           struct mlx5_ib_create_wq *ucmd)
710 {
711         struct mlx5_ib_ucontext *context;
712         int page_shift = 0;
713         int npages;
714         u32 offset = 0;
715         int ncont = 0;
716         int err;
717
718         if (!ucmd->buf_addr)
719                 return -EINVAL;
720
721         context = to_mucontext(pd->uobject->context);
722         rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
723                                rwq->buf_size, 0, 0);
724         if (IS_ERR(rwq->umem)) {
725                 mlx5_ib_dbg(dev, "umem_get failed\n");
726                 err = PTR_ERR(rwq->umem);
727                 return err;
728         }
729
730         mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
731                            &ncont, NULL);
732         err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
733                                      &rwq->rq_page_offset);
734         if (err) {
735                 mlx5_ib_warn(dev, "bad offset\n");
736                 goto err_umem;
737         }
738
739         rwq->rq_num_pas = ncont;
740         rwq->page_shift = page_shift;
741         rwq->log_page_size =  page_shift - MLX5_ADAPTER_PAGE_SHIFT;
742         rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
743
744         mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
745                     (unsigned long long)ucmd->buf_addr, rwq->buf_size,
746                     npages, page_shift, ncont, offset);
747
748         err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
749         if (err) {
750                 mlx5_ib_dbg(dev, "map failed\n");
751                 goto err_umem;
752         }
753
754         rwq->create_type = MLX5_WQ_USER;
755         return 0;
756
757 err_umem:
758         ib_umem_release(rwq->umem);
759         return err;
760 }
761
762 static int adjust_bfregn(struct mlx5_ib_dev *dev,
763                          struct mlx5_bfreg_info *bfregi, int bfregn)
764 {
765         return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
766                                 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
767 }
768
769 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
770                           struct mlx5_ib_qp *qp, struct ib_udata *udata,
771                           struct ib_qp_init_attr *attr,
772                           u32 **in,
773                           struct mlx5_ib_create_qp_resp *resp, int *inlen,
774                           struct mlx5_ib_qp_base *base)
775 {
776         struct mlx5_ib_ucontext *context;
777         struct mlx5_ib_create_qp ucmd;
778         struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
779         int page_shift = 0;
780         int uar_index = 0;
781         int npages;
782         u32 offset = 0;
783         int bfregn;
784         int ncont = 0;
785         __be64 *pas;
786         void *qpc;
787         int err;
788
789         err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
790         if (err) {
791                 mlx5_ib_dbg(dev, "copy failed\n");
792                 return err;
793         }
794
795         context = to_mucontext(pd->uobject->context);
796         if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) {
797                 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
798                                                 ucmd.bfreg_index, true);
799                 if (uar_index < 0)
800                         return uar_index;
801
802                 bfregn = MLX5_IB_INVALID_BFREG;
803         } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) {
804                 /*
805                  * TBD: should come from the verbs when we have the API
806                  */
807                 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
808                 bfregn = MLX5_CROSS_CHANNEL_BFREG;
809         }
810         else {
811                 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_HIGH);
812                 if (bfregn < 0) {
813                         mlx5_ib_dbg(dev, "failed to allocate low latency BFREG\n");
814                         mlx5_ib_dbg(dev, "reverting to medium latency\n");
815                         bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_MEDIUM);
816                         if (bfregn < 0) {
817                                 mlx5_ib_dbg(dev, "failed to allocate medium latency BFREG\n");
818                                 mlx5_ib_dbg(dev, "reverting to high latency\n");
819                                 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_LOW);
820                                 if (bfregn < 0) {
821                                         mlx5_ib_warn(dev, "bfreg allocation failed\n");
822                                         return bfregn;
823                                 }
824                         }
825                 }
826         }
827
828         mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
829         if (bfregn != MLX5_IB_INVALID_BFREG)
830                 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
831                                                 false);
832
833         qp->rq.offset = 0;
834         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
835         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
836
837         err = set_user_buf_size(dev, qp, &ucmd, base, attr);
838         if (err)
839                 goto err_bfreg;
840
841         if (ucmd.buf_addr && ubuffer->buf_size) {
842                 ubuffer->buf_addr = ucmd.buf_addr;
843                 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
844                                        ubuffer->buf_size,
845                                        &ubuffer->umem, &npages, &page_shift,
846                                        &ncont, &offset);
847                 if (err)
848                         goto err_bfreg;
849         } else {
850                 ubuffer->umem = NULL;
851         }
852
853         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
854                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
855         *in = kvzalloc(*inlen, GFP_KERNEL);
856         if (!*in) {
857                 err = -ENOMEM;
858                 goto err_umem;
859         }
860
861         pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
862         if (ubuffer->umem)
863                 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
864
865         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
866
867         MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
868         MLX5_SET(qpc, qpc, page_offset, offset);
869
870         MLX5_SET(qpc, qpc, uar_page, uar_index);
871         if (bfregn != MLX5_IB_INVALID_BFREG)
872                 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
873         else
874                 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
875         qp->bfregn = bfregn;
876
877         err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
878         if (err) {
879                 mlx5_ib_dbg(dev, "map failed\n");
880                 goto err_free;
881         }
882
883         err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
884         if (err) {
885                 mlx5_ib_dbg(dev, "copy failed\n");
886                 goto err_unmap;
887         }
888         qp->create_type = MLX5_QP_USER;
889
890         return 0;
891
892 err_unmap:
893         mlx5_ib_db_unmap_user(context, &qp->db);
894
895 err_free:
896         kvfree(*in);
897
898 err_umem:
899         if (ubuffer->umem)
900                 ib_umem_release(ubuffer->umem);
901
902 err_bfreg:
903         if (bfregn != MLX5_IB_INVALID_BFREG)
904                 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
905         return err;
906 }
907
908 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
909                             struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base)
910 {
911         struct mlx5_ib_ucontext *context;
912
913         context = to_mucontext(pd->uobject->context);
914         mlx5_ib_db_unmap_user(context, &qp->db);
915         if (base->ubuffer.umem)
916                 ib_umem_release(base->ubuffer.umem);
917
918         /*
919          * Free only the BFREGs which are handled by the kernel.
920          * BFREGs of UARs allocated dynamically are handled by user.
921          */
922         if (qp->bfregn != MLX5_IB_INVALID_BFREG)
923                 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
924 }
925
926 static int create_kernel_qp(struct mlx5_ib_dev *dev,
927                             struct ib_qp_init_attr *init_attr,
928                             struct mlx5_ib_qp *qp,
929                             u32 **in, int *inlen,
930                             struct mlx5_ib_qp_base *base)
931 {
932         int uar_index;
933         void *qpc;
934         int err;
935
936         if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
937                                         IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
938                                         IB_QP_CREATE_IPOIB_UD_LSO |
939                                         IB_QP_CREATE_NETIF_QP |
940                                         mlx5_ib_create_qp_sqpn_qp1()))
941                 return -EINVAL;
942
943         if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
944                 qp->bf.bfreg = &dev->fp_bfreg;
945         else
946                 qp->bf.bfreg = &dev->bfreg;
947
948         /* We need to divide by two since each register is comprised of
949          * two buffers of identical size, namely odd and even
950          */
951         qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
952         uar_index = qp->bf.bfreg->index;
953
954         err = calc_sq_size(dev, init_attr, qp);
955         if (err < 0) {
956                 mlx5_ib_dbg(dev, "err %d\n", err);
957                 return err;
958         }
959
960         qp->rq.offset = 0;
961         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
962         base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
963
964         err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
965         if (err) {
966                 mlx5_ib_dbg(dev, "err %d\n", err);
967                 return err;
968         }
969
970         qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
971         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
972                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
973         *in = kvzalloc(*inlen, GFP_KERNEL);
974         if (!*in) {
975                 err = -ENOMEM;
976                 goto err_buf;
977         }
978
979         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
980         MLX5_SET(qpc, qpc, uar_page, uar_index);
981         MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
982
983         /* Set "fast registration enabled" for all kernel QPs */
984         MLX5_SET(qpc, qpc, fre, 1);
985         MLX5_SET(qpc, qpc, rlky, 1);
986
987         if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
988                 MLX5_SET(qpc, qpc, deth_sqpn, 1);
989                 qp->flags |= MLX5_IB_QP_SQPN_QP1;
990         }
991
992         mlx5_fill_page_array(&qp->buf,
993                              (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
994
995         err = mlx5_db_alloc(dev->mdev, &qp->db);
996         if (err) {
997                 mlx5_ib_dbg(dev, "err %d\n", err);
998                 goto err_free;
999         }
1000
1001         qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1002                                      sizeof(*qp->sq.wrid), GFP_KERNEL);
1003         qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
1004                                         sizeof(*qp->sq.wr_data), GFP_KERNEL);
1005         qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1006                                      sizeof(*qp->rq.wrid), GFP_KERNEL);
1007         qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
1008                                        sizeof(*qp->sq.w_list), GFP_KERNEL);
1009         qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
1010                                          sizeof(*qp->sq.wqe_head), GFP_KERNEL);
1011
1012         if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1013             !qp->sq.w_list || !qp->sq.wqe_head) {
1014                 err = -ENOMEM;
1015                 goto err_wrid;
1016         }
1017         qp->create_type = MLX5_QP_KERNEL;
1018
1019         return 0;
1020
1021 err_wrid:
1022         kvfree(qp->sq.wqe_head);
1023         kvfree(qp->sq.w_list);
1024         kvfree(qp->sq.wrid);
1025         kvfree(qp->sq.wr_data);
1026         kvfree(qp->rq.wrid);
1027         mlx5_db_free(dev->mdev, &qp->db);
1028
1029 err_free:
1030         kvfree(*in);
1031
1032 err_buf:
1033         mlx5_buf_free(dev->mdev, &qp->buf);
1034         return err;
1035 }
1036
1037 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1038 {
1039         kvfree(qp->sq.wqe_head);
1040         kvfree(qp->sq.w_list);
1041         kvfree(qp->sq.wrid);
1042         kvfree(qp->sq.wr_data);
1043         kvfree(qp->rq.wrid);
1044         mlx5_db_free(dev->mdev, &qp->db);
1045         mlx5_buf_free(dev->mdev, &qp->buf);
1046 }
1047
1048 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1049 {
1050         if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1051             (attr->qp_type == MLX5_IB_QPT_DCI) ||
1052             (attr->qp_type == IB_QPT_XRC_INI))
1053                 return MLX5_SRQ_RQ;
1054         else if (!qp->has_rq)
1055                 return MLX5_ZERO_LEN_RQ;
1056         else
1057                 return MLX5_NON_ZERO_RQ;
1058 }
1059
1060 static int is_connected(enum ib_qp_type qp_type)
1061 {
1062         if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1063                 return 1;
1064
1065         return 0;
1066 }
1067
1068 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1069                                     struct mlx5_ib_qp *qp,
1070                                     struct mlx5_ib_sq *sq, u32 tdn)
1071 {
1072         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1073         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1074
1075         MLX5_SET(tisc, tisc, transport_domain, tdn);
1076         if (qp->flags & MLX5_IB_QP_UNDERLAY)
1077                 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1078
1079         return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1080 }
1081
1082 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1083                                       struct mlx5_ib_sq *sq)
1084 {
1085         mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1086 }
1087
1088 static void destroy_flow_rule_vport_sq(struct mlx5_ib_dev *dev,
1089                                        struct mlx5_ib_sq *sq)
1090 {
1091         if (sq->flow_rule)
1092                 mlx5_del_flow_rules(sq->flow_rule);
1093 }
1094
1095 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1096                                    struct mlx5_ib_sq *sq, void *qpin,
1097                                    struct ib_pd *pd)
1098 {
1099         struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1100         __be64 *pas;
1101         void *in;
1102         void *sqc;
1103         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1104         void *wq;
1105         int inlen;
1106         int err;
1107         int page_shift = 0;
1108         int npages;
1109         int ncont = 0;
1110         u32 offset = 0;
1111
1112         err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1113                                &sq->ubuffer.umem, &npages, &page_shift,
1114                                &ncont, &offset);
1115         if (err)
1116                 return err;
1117
1118         inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1119         in = kvzalloc(inlen, GFP_KERNEL);
1120         if (!in) {
1121                 err = -ENOMEM;
1122                 goto err_umem;
1123         }
1124
1125         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1126         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1127         if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1128                 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
1129         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1130         MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1131         MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1132         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1133         MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1134         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1135             MLX5_CAP_ETH(dev->mdev, swp))
1136                 MLX5_SET(sqc, sqc, allow_swp, 1);
1137
1138         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1139         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1140         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1141         MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1142         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1143         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1144         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1145         MLX5_SET(wq, wq, log_wq_pg_sz,  page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1146         MLX5_SET(wq, wq, page_offset, offset);
1147
1148         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1149         mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1150
1151         err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1152
1153         kvfree(in);
1154
1155         if (err)
1156                 goto err_umem;
1157
1158         err = create_flow_rule_vport_sq(dev, sq);
1159         if (err)
1160                 goto err_flow;
1161
1162         return 0;
1163
1164 err_flow:
1165         mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1166
1167 err_umem:
1168         ib_umem_release(sq->ubuffer.umem);
1169         sq->ubuffer.umem = NULL;
1170
1171         return err;
1172 }
1173
1174 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1175                                      struct mlx5_ib_sq *sq)
1176 {
1177         destroy_flow_rule_vport_sq(dev, sq);
1178         mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1179         ib_umem_release(sq->ubuffer.umem);
1180 }
1181
1182 static size_t get_rq_pas_size(void *qpc)
1183 {
1184         u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1185         u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1186         u32 log_rq_size   = MLX5_GET(qpc, qpc, log_rq_size);
1187         u32 page_offset   = MLX5_GET(qpc, qpc, page_offset);
1188         u32 po_quanta     = 1 << (log_page_size - 6);
1189         u32 rq_sz         = 1 << (log_rq_size + 4 + log_rq_stride);
1190         u32 page_size     = 1 << log_page_size;
1191         u32 rq_sz_po      = rq_sz + (page_offset * po_quanta);
1192         u32 rq_num_pas    = (rq_sz_po + page_size - 1) / page_size;
1193
1194         return rq_num_pas * sizeof(u64);
1195 }
1196
1197 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1198                                    struct mlx5_ib_rq *rq, void *qpin,
1199                                    size_t qpinlen)
1200 {
1201         struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1202         __be64 *pas;
1203         __be64 *qp_pas;
1204         void *in;
1205         void *rqc;
1206         void *wq;
1207         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1208         size_t rq_pas_size = get_rq_pas_size(qpc);
1209         size_t inlen;
1210         int err;
1211
1212         if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas))
1213                 return -EINVAL;
1214
1215         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1216         in = kvzalloc(inlen, GFP_KERNEL);
1217         if (!in)
1218                 return -ENOMEM;
1219
1220         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1221         if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1222                 MLX5_SET(rqc, rqc, vsd, 1);
1223         MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1224         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1225         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1226         MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1227         MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1228
1229         if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1230                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1231
1232         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1233         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1234         if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1235                 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1236         MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1237         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1238         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1239         MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1240         MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1241         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1242
1243         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1244         qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1245         memcpy(pas, qp_pas, rq_pas_size);
1246
1247         err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1248
1249         kvfree(in);
1250
1251         return err;
1252 }
1253
1254 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1255                                      struct mlx5_ib_rq *rq)
1256 {
1257         mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1258 }
1259
1260 static bool tunnel_offload_supported(struct mlx5_core_dev *dev)
1261 {
1262         return  (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) ||
1263                  MLX5_CAP_ETH(dev, tunnel_stateless_gre) ||
1264                  MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx));
1265 }
1266
1267 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1268                                     struct mlx5_ib_rq *rq, u32 tdn,
1269                                     bool tunnel_offload_en)
1270 {
1271         u32 *in;
1272         void *tirc;
1273         int inlen;
1274         int err;
1275
1276         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1277         in = kvzalloc(inlen, GFP_KERNEL);
1278         if (!in)
1279                 return -ENOMEM;
1280
1281         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1282         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1283         MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1284         MLX5_SET(tirc, tirc, transport_domain, tdn);
1285         if (tunnel_offload_en)
1286                 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1287
1288         if (dev->rep)
1289                 MLX5_SET(tirc, tirc, self_lb_block,
1290                          MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_);
1291
1292         err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1293
1294         kvfree(in);
1295
1296         return err;
1297 }
1298
1299 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1300                                       struct mlx5_ib_rq *rq)
1301 {
1302         mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1303 }
1304
1305 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1306                                 u32 *in, size_t inlen,
1307                                 struct ib_pd *pd)
1308 {
1309         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1310         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1311         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1312         struct ib_uobject *uobj = pd->uobject;
1313         struct ib_ucontext *ucontext = uobj->context;
1314         struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1315         int err;
1316         u32 tdn = mucontext->tdn;
1317
1318         if (qp->sq.wqe_cnt) {
1319                 err = create_raw_packet_qp_tis(dev, qp, sq, tdn);
1320                 if (err)
1321                         return err;
1322
1323                 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1324                 if (err)
1325                         goto err_destroy_tis;
1326
1327                 sq->base.container_mibqp = qp;
1328                 sq->base.mqp.event = mlx5_ib_qp_event;
1329         }
1330
1331         if (qp->rq.wqe_cnt) {
1332                 rq->base.container_mibqp = qp;
1333
1334                 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1335                         rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
1336                 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING)
1337                         rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
1338                 err = create_raw_packet_qp_rq(dev, rq, in, inlen);
1339                 if (err)
1340                         goto err_destroy_sq;
1341
1342
1343                 err = create_raw_packet_qp_tir(dev, rq, tdn,
1344                                                qp->tunnel_offload_en);
1345                 if (err)
1346                         goto err_destroy_rq;
1347         }
1348
1349         qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1350                                                      rq->base.mqp.qpn;
1351
1352         return 0;
1353
1354 err_destroy_rq:
1355         destroy_raw_packet_qp_rq(dev, rq);
1356 err_destroy_sq:
1357         if (!qp->sq.wqe_cnt)
1358                 return err;
1359         destroy_raw_packet_qp_sq(dev, sq);
1360 err_destroy_tis:
1361         destroy_raw_packet_qp_tis(dev, sq);
1362
1363         return err;
1364 }
1365
1366 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1367                                   struct mlx5_ib_qp *qp)
1368 {
1369         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1370         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1371         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1372
1373         if (qp->rq.wqe_cnt) {
1374                 destroy_raw_packet_qp_tir(dev, rq);
1375                 destroy_raw_packet_qp_rq(dev, rq);
1376         }
1377
1378         if (qp->sq.wqe_cnt) {
1379                 destroy_raw_packet_qp_sq(dev, sq);
1380                 destroy_raw_packet_qp_tis(dev, sq);
1381         }
1382 }
1383
1384 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1385                                     struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1386 {
1387         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1388         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1389
1390         sq->sq = &qp->sq;
1391         rq->rq = &qp->rq;
1392         sq->doorbell = &qp->db;
1393         rq->doorbell = &qp->db;
1394 }
1395
1396 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1397 {
1398         mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1399 }
1400
1401 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1402                                  struct ib_pd *pd,
1403                                  struct ib_qp_init_attr *init_attr,
1404                                  struct ib_udata *udata)
1405 {
1406         struct ib_uobject *uobj = pd->uobject;
1407         struct ib_ucontext *ucontext = uobj->context;
1408         struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1409         struct mlx5_ib_create_qp_resp resp = {};
1410         int inlen;
1411         int err;
1412         u32 *in;
1413         void *tirc;
1414         void *hfso;
1415         u32 selected_fields = 0;
1416         u32 outer_l4;
1417         size_t min_resp_len;
1418         u32 tdn = mucontext->tdn;
1419         struct mlx5_ib_create_qp_rss ucmd = {};
1420         size_t required_cmd_sz;
1421
1422         if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1423                 return -EOPNOTSUPP;
1424
1425         if (init_attr->create_flags || init_attr->send_cq)
1426                 return -EINVAL;
1427
1428         min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
1429         if (udata->outlen < min_resp_len)
1430                 return -EINVAL;
1431
1432         required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags);
1433         if (udata->inlen < required_cmd_sz) {
1434                 mlx5_ib_dbg(dev, "invalid inlen\n");
1435                 return -EINVAL;
1436         }
1437
1438         if (udata->inlen > sizeof(ucmd) &&
1439             !ib_is_udata_cleared(udata, sizeof(ucmd),
1440                                  udata->inlen - sizeof(ucmd))) {
1441                 mlx5_ib_dbg(dev, "inlen is not supported\n");
1442                 return -EOPNOTSUPP;
1443         }
1444
1445         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1446                 mlx5_ib_dbg(dev, "copy failed\n");
1447                 return -EFAULT;
1448         }
1449
1450         if (ucmd.comp_mask) {
1451                 mlx5_ib_dbg(dev, "invalid comp mask\n");
1452                 return -EOPNOTSUPP;
1453         }
1454
1455         if (ucmd.flags & ~MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1456                 mlx5_ib_dbg(dev, "invalid flags\n");
1457                 return -EOPNOTSUPP;
1458         }
1459
1460         if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS &&
1461             !tunnel_offload_supported(dev->mdev)) {
1462                 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n");
1463                 return -EOPNOTSUPP;
1464         }
1465
1466         if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1467             !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1468                 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1469                 return -EOPNOTSUPP;
1470         }
1471
1472         err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
1473         if (err) {
1474                 mlx5_ib_dbg(dev, "copy failed\n");
1475                 return -EINVAL;
1476         }
1477
1478         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1479         in = kvzalloc(inlen, GFP_KERNEL);
1480         if (!in)
1481                 return -ENOMEM;
1482
1483         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1484         MLX5_SET(tirc, tirc, disp_type,
1485                  MLX5_TIRC_DISP_TYPE_INDIRECT);
1486         MLX5_SET(tirc, tirc, indirect_table,
1487                  init_attr->rwq_ind_tbl->ind_tbl_num);
1488         MLX5_SET(tirc, tirc, transport_domain, tdn);
1489
1490         hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1491
1492         if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1493                 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1494
1495         if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1496                 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1497         else
1498                 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1499
1500         switch (ucmd.rx_hash_function) {
1501         case MLX5_RX_HASH_FUNC_TOEPLITZ:
1502         {
1503                 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1504                 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1505
1506                 if (len != ucmd.rx_key_len) {
1507                         err = -EINVAL;
1508                         goto err;
1509                 }
1510
1511                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1512                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1513                 memcpy(rss_key, ucmd.rx_hash_key, len);
1514                 break;
1515         }
1516         default:
1517                 err = -EOPNOTSUPP;
1518                 goto err;
1519         }
1520
1521         if (!ucmd.rx_hash_fields_mask) {
1522                 /* special case when this TIR serves as steering entry without hashing */
1523                 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1524                         goto create_tir;
1525                 err = -EINVAL;
1526                 goto err;
1527         }
1528
1529         if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1530              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1531              ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1532              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1533                 err = -EINVAL;
1534                 goto err;
1535         }
1536
1537         /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1538         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1539             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1540                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1541                          MLX5_L3_PROT_TYPE_IPV4);
1542         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1543                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1544                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1545                          MLX5_L3_PROT_TYPE_IPV6);
1546
1547         outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1548                     (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 |
1549                    ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1550                     (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 |
1551                    (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2;
1552
1553         /* Check that only one l4 protocol is set */
1554         if (outer_l4 & (outer_l4 - 1)) {
1555                 err = -EINVAL;
1556                 goto err;
1557         }
1558
1559         /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1560         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1561             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1562                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1563                          MLX5_L4_PROT_TYPE_TCP);
1564         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1565                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1566                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1567                          MLX5_L4_PROT_TYPE_UDP);
1568
1569         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1570             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1571                 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1572
1573         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1574             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1575                 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1576
1577         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1578             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1579                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1580
1581         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1582             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1583                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1584
1585         if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI)
1586                 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI;
1587
1588         MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1589
1590 create_tir:
1591         if (dev->rep)
1592                 MLX5_SET(tirc, tirc, self_lb_block,
1593                          MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_);
1594
1595         err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1596
1597         if (err)
1598                 goto err;
1599
1600         kvfree(in);
1601         /* qpn is reserved for that QP */
1602         qp->trans_qp.base.mqp.qpn = 0;
1603         qp->flags |= MLX5_IB_QP_RSS;
1604         return 0;
1605
1606 err:
1607         kvfree(in);
1608         return err;
1609 }
1610
1611 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1612                             struct ib_qp_init_attr *init_attr,
1613                             struct ib_udata *udata, struct mlx5_ib_qp *qp)
1614 {
1615         struct mlx5_ib_resources *devr = &dev->devr;
1616         int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1617         struct mlx5_core_dev *mdev = dev->mdev;
1618         struct mlx5_ib_create_qp_resp resp;
1619         struct mlx5_ib_cq *send_cq;
1620         struct mlx5_ib_cq *recv_cq;
1621         unsigned long flags;
1622         u32 uidx = MLX5_IB_DEFAULT_UIDX;
1623         struct mlx5_ib_create_qp ucmd;
1624         struct mlx5_ib_qp_base *base;
1625         int mlx5_st;
1626         void *qpc;
1627         u32 *in;
1628         int err;
1629
1630         mutex_init(&qp->mutex);
1631         spin_lock_init(&qp->sq.lock);
1632         spin_lock_init(&qp->rq.lock);
1633
1634         mlx5_st = to_mlx5_st(init_attr->qp_type);
1635         if (mlx5_st < 0)
1636                 return -EINVAL;
1637
1638         if (init_attr->rwq_ind_tbl) {
1639                 if (!udata)
1640                         return -ENOSYS;
1641
1642                 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1643                 return err;
1644         }
1645
1646         if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1647                 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1648                         mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1649                         return -EINVAL;
1650                 } else {
1651                         qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1652                 }
1653         }
1654
1655         if (init_attr->create_flags &
1656                         (IB_QP_CREATE_CROSS_CHANNEL |
1657                          IB_QP_CREATE_MANAGED_SEND |
1658                          IB_QP_CREATE_MANAGED_RECV)) {
1659                 if (!MLX5_CAP_GEN(mdev, cd)) {
1660                         mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1661                         return -EINVAL;
1662                 }
1663                 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1664                         qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1665                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1666                         qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1667                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1668                         qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1669         }
1670
1671         if (init_attr->qp_type == IB_QPT_UD &&
1672             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1673                 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1674                         mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1675                         return -EOPNOTSUPP;
1676                 }
1677
1678         if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1679                 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1680                         mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1681                         return -EOPNOTSUPP;
1682                 }
1683                 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1684                     !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1685                         mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1686                         return -EOPNOTSUPP;
1687                 }
1688                 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1689         }
1690
1691         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1692                 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1693
1694         if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
1695                 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1696                       MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
1697                     (init_attr->qp_type != IB_QPT_RAW_PACKET))
1698                         return -EOPNOTSUPP;
1699                 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
1700         }
1701
1702         if (pd && pd->uobject) {
1703                 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1704                         mlx5_ib_dbg(dev, "copy failed\n");
1705                         return -EFAULT;
1706                 }
1707
1708                 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1709                                         &ucmd, udata->inlen, &uidx);
1710                 if (err)
1711                         return err;
1712
1713                 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1714                 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1715                 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1716                         if (init_attr->qp_type != IB_QPT_RAW_PACKET ||
1717                             !tunnel_offload_supported(mdev)) {
1718                                 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n");
1719                                 return -EOPNOTSUPP;
1720                         }
1721                         qp->tunnel_offload_en = true;
1722                 }
1723
1724                 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) {
1725                         if (init_attr->qp_type != IB_QPT_UD ||
1726                             (MLX5_CAP_GEN(dev->mdev, port_type) !=
1727                              MLX5_CAP_PORT_TYPE_IB) ||
1728                             !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) {
1729                                 mlx5_ib_dbg(dev, "Source QP option isn't supported\n");
1730                                 return -EOPNOTSUPP;
1731                         }
1732
1733                         qp->flags |= MLX5_IB_QP_UNDERLAY;
1734                         qp->underlay_qpn = init_attr->source_qpn;
1735                 }
1736         } else {
1737                 qp->wq_sig = !!wq_signature;
1738         }
1739
1740         base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1741                 qp->flags & MLX5_IB_QP_UNDERLAY) ?
1742                &qp->raw_packet_qp.rq.base :
1743                &qp->trans_qp.base;
1744
1745         qp->has_rq = qp_has_rq(init_attr);
1746         err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1747                           qp, (pd && pd->uobject) ? &ucmd : NULL);
1748         if (err) {
1749                 mlx5_ib_dbg(dev, "err %d\n", err);
1750                 return err;
1751         }
1752
1753         if (pd) {
1754                 if (pd->uobject) {
1755                         __u32 max_wqes =
1756                                 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1757                         mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1758                         if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1759                             ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1760                                 mlx5_ib_dbg(dev, "invalid rq params\n");
1761                                 return -EINVAL;
1762                         }
1763                         if (ucmd.sq_wqe_count > max_wqes) {
1764                                 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1765                                             ucmd.sq_wqe_count, max_wqes);
1766                                 return -EINVAL;
1767                         }
1768                         if (init_attr->create_flags &
1769                             mlx5_ib_create_qp_sqpn_qp1()) {
1770                                 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1771                                 return -EINVAL;
1772                         }
1773                         err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1774                                              &resp, &inlen, base);
1775                         if (err)
1776                                 mlx5_ib_dbg(dev, "err %d\n", err);
1777                 } else {
1778                         err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1779                                                base);
1780                         if (err)
1781                                 mlx5_ib_dbg(dev, "err %d\n", err);
1782                 }
1783
1784                 if (err)
1785                         return err;
1786         } else {
1787                 in = kvzalloc(inlen, GFP_KERNEL);
1788                 if (!in)
1789                         return -ENOMEM;
1790
1791                 qp->create_type = MLX5_QP_EMPTY;
1792         }
1793
1794         if (is_sqp(init_attr->qp_type))
1795                 qp->port = init_attr->port_num;
1796
1797         qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1798
1799         MLX5_SET(qpc, qpc, st, mlx5_st);
1800         MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1801
1802         if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
1803                 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
1804         else
1805                 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1806
1807
1808         if (qp->wq_sig)
1809                 MLX5_SET(qpc, qpc, wq_signature, 1);
1810
1811         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1812                 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1813
1814         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
1815                 MLX5_SET(qpc, qpc, cd_master, 1);
1816         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
1817                 MLX5_SET(qpc, qpc, cd_slave_send, 1);
1818         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
1819                 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1820
1821         if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1822                 int rcqe_sz;
1823                 int scqe_sz;
1824
1825                 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1826                 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1827
1828                 if (rcqe_sz == 128)
1829                         MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1830                 else
1831                         MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
1832
1833                 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1834                         if (scqe_sz == 128)
1835                                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1836                         else
1837                                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1838                 }
1839         }
1840
1841         if (qp->rq.wqe_cnt) {
1842                 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1843                 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
1844         }
1845
1846         MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
1847
1848         if (qp->sq.wqe_cnt) {
1849                 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
1850         } else {
1851                 MLX5_SET(qpc, qpc, no_sq, 1);
1852                 if (init_attr->srq &&
1853                     init_attr->srq->srq_type == IB_SRQT_TM)
1854                         MLX5_SET(qpc, qpc, offload_type,
1855                                  MLX5_QPC_OFFLOAD_TYPE_RNDV);
1856         }
1857
1858         /* Set default resources */
1859         switch (init_attr->qp_type) {
1860         case IB_QPT_XRC_TGT:
1861                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1862                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1863                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1864                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
1865                 break;
1866         case IB_QPT_XRC_INI:
1867                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1868                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1869                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1870                 break;
1871         default:
1872                 if (init_attr->srq) {
1873                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1874                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
1875                 } else {
1876                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1877                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
1878                 }
1879         }
1880
1881         if (init_attr->send_cq)
1882                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
1883
1884         if (init_attr->recv_cq)
1885                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
1886
1887         MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
1888
1889         /* 0xffffff means we ask to work with cqe version 0 */
1890         if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
1891                 MLX5_SET(qpc, qpc, user_index, uidx);
1892
1893         /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1894         if (init_attr->qp_type == IB_QPT_UD &&
1895             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
1896                 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1897                 qp->flags |= MLX5_IB_QP_LSO;
1898         }
1899
1900         if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
1901                 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
1902                         mlx5_ib_dbg(dev, "scatter end padding is not supported\n");
1903                         err = -EOPNOTSUPP;
1904                         goto err;
1905                 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1906                         MLX5_SET(qpc, qpc, end_padding_mode,
1907                                  MLX5_WQ_END_PAD_MODE_ALIGN);
1908                 } else {
1909                         qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING;
1910                 }
1911         }
1912
1913         if (inlen < 0) {
1914                 err = -EINVAL;
1915                 goto err;
1916         }
1917
1918         if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1919             qp->flags & MLX5_IB_QP_UNDERLAY) {
1920                 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1921                 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1922                 err = create_raw_packet_qp(dev, qp, in, inlen, pd);
1923         } else {
1924                 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1925         }
1926
1927         if (err) {
1928                 mlx5_ib_dbg(dev, "create qp failed\n");
1929                 goto err_create;
1930         }
1931
1932         kvfree(in);
1933
1934         base->container_mibqp = qp;
1935         base->mqp.event = mlx5_ib_qp_event;
1936
1937         get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1938                 &send_cq, &recv_cq);
1939         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1940         mlx5_ib_lock_cqs(send_cq, recv_cq);
1941         /* Maintain device to QPs access, needed for further handling via reset
1942          * flow
1943          */
1944         list_add_tail(&qp->qps_list, &dev->qp_list);
1945         /* Maintain CQ to QPs access, needed for further handling via reset flow
1946          */
1947         if (send_cq)
1948                 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1949         if (recv_cq)
1950                 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1951         mlx5_ib_unlock_cqs(send_cq, recv_cq);
1952         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1953
1954         return 0;
1955
1956 err_create:
1957         if (qp->create_type == MLX5_QP_USER)
1958                 destroy_qp_user(dev, pd, qp, base);
1959         else if (qp->create_type == MLX5_QP_KERNEL)
1960                 destroy_qp_kernel(dev, qp);
1961
1962 err:
1963         kvfree(in);
1964         return err;
1965 }
1966
1967 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1968         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1969 {
1970         if (send_cq) {
1971                 if (recv_cq) {
1972                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
1973                                 spin_lock(&send_cq->lock);
1974                                 spin_lock_nested(&recv_cq->lock,
1975                                                  SINGLE_DEPTH_NESTING);
1976                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1977                                 spin_lock(&send_cq->lock);
1978                                 __acquire(&recv_cq->lock);
1979                         } else {
1980                                 spin_lock(&recv_cq->lock);
1981                                 spin_lock_nested(&send_cq->lock,
1982                                                  SINGLE_DEPTH_NESTING);
1983                         }
1984                 } else {
1985                         spin_lock(&send_cq->lock);
1986                         __acquire(&recv_cq->lock);
1987                 }
1988         } else if (recv_cq) {
1989                 spin_lock(&recv_cq->lock);
1990                 __acquire(&send_cq->lock);
1991         } else {
1992                 __acquire(&send_cq->lock);
1993                 __acquire(&recv_cq->lock);
1994         }
1995 }
1996
1997 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1998         __releases(&send_cq->lock) __releases(&recv_cq->lock)
1999 {
2000         if (send_cq) {
2001                 if (recv_cq) {
2002                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
2003                                 spin_unlock(&recv_cq->lock);
2004                                 spin_unlock(&send_cq->lock);
2005                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2006                                 __release(&recv_cq->lock);
2007                                 spin_unlock(&send_cq->lock);
2008                         } else {
2009                                 spin_unlock(&send_cq->lock);
2010                                 spin_unlock(&recv_cq->lock);
2011                         }
2012                 } else {
2013                         __release(&recv_cq->lock);
2014                         spin_unlock(&send_cq->lock);
2015                 }
2016         } else if (recv_cq) {
2017                 __release(&send_cq->lock);
2018                 spin_unlock(&recv_cq->lock);
2019         } else {
2020                 __release(&recv_cq->lock);
2021                 __release(&send_cq->lock);
2022         }
2023 }
2024
2025 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
2026 {
2027         return to_mpd(qp->ibqp.pd);
2028 }
2029
2030 static void get_cqs(enum ib_qp_type qp_type,
2031                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
2032                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
2033 {
2034         switch (qp_type) {
2035         case IB_QPT_XRC_TGT:
2036                 *send_cq = NULL;
2037                 *recv_cq = NULL;
2038                 break;
2039         case MLX5_IB_QPT_REG_UMR:
2040         case IB_QPT_XRC_INI:
2041                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2042                 *recv_cq = NULL;
2043                 break;
2044
2045         case IB_QPT_SMI:
2046         case MLX5_IB_QPT_HW_GSI:
2047         case IB_QPT_RC:
2048         case IB_QPT_UC:
2049         case IB_QPT_UD:
2050         case IB_QPT_RAW_IPV6:
2051         case IB_QPT_RAW_ETHERTYPE:
2052         case IB_QPT_RAW_PACKET:
2053                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2054                 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
2055                 break;
2056
2057         case IB_QPT_MAX:
2058         default:
2059                 *send_cq = NULL;
2060                 *recv_cq = NULL;
2061                 break;
2062         }
2063 }
2064
2065 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2066                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2067                                 u8 lag_tx_affinity);
2068
2069 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
2070 {
2071         struct mlx5_ib_cq *send_cq, *recv_cq;
2072         struct mlx5_ib_qp_base *base;
2073         unsigned long flags;
2074         int err;
2075
2076         if (qp->ibqp.rwq_ind_tbl) {
2077                 destroy_rss_raw_qp_tir(dev, qp);
2078                 return;
2079         }
2080
2081         base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2082                 qp->flags & MLX5_IB_QP_UNDERLAY) ?
2083                &qp->raw_packet_qp.rq.base :
2084                &qp->trans_qp.base;
2085
2086         if (qp->state != IB_QPS_RESET) {
2087                 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
2088                     !(qp->flags & MLX5_IB_QP_UNDERLAY)) {
2089                         err = mlx5_core_qp_modify(dev->mdev,
2090                                                   MLX5_CMD_OP_2RST_QP, 0,
2091                                                   NULL, &base->mqp);
2092                 } else {
2093                         struct mlx5_modify_raw_qp_param raw_qp_param = {
2094                                 .operation = MLX5_CMD_OP_2RST_QP
2095                         };
2096
2097                         err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
2098                 }
2099                 if (err)
2100                         mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
2101                                      base->mqp.qpn);
2102         }
2103
2104         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2105                 &send_cq, &recv_cq);
2106
2107         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2108         mlx5_ib_lock_cqs(send_cq, recv_cq);
2109         /* del from lists under both locks above to protect reset flow paths */
2110         list_del(&qp->qps_list);
2111         if (send_cq)
2112                 list_del(&qp->cq_send_list);
2113
2114         if (recv_cq)
2115                 list_del(&qp->cq_recv_list);
2116
2117         if (qp->create_type == MLX5_QP_KERNEL) {
2118                 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2119                                    qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2120                 if (send_cq != recv_cq)
2121                         __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2122                                            NULL);
2123         }
2124         mlx5_ib_unlock_cqs(send_cq, recv_cq);
2125         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2126
2127         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2128             qp->flags & MLX5_IB_QP_UNDERLAY) {
2129                 destroy_raw_packet_qp(dev, qp);
2130         } else {
2131                 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
2132                 if (err)
2133                         mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2134                                      base->mqp.qpn);
2135         }
2136
2137         if (qp->create_type == MLX5_QP_KERNEL)
2138                 destroy_qp_kernel(dev, qp);
2139         else if (qp->create_type == MLX5_QP_USER)
2140                 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base);
2141 }
2142
2143 static const char *ib_qp_type_str(enum ib_qp_type type)
2144 {
2145         switch (type) {
2146         case IB_QPT_SMI:
2147                 return "IB_QPT_SMI";
2148         case IB_QPT_GSI:
2149                 return "IB_QPT_GSI";
2150         case IB_QPT_RC:
2151                 return "IB_QPT_RC";
2152         case IB_QPT_UC:
2153                 return "IB_QPT_UC";
2154         case IB_QPT_UD:
2155                 return "IB_QPT_UD";
2156         case IB_QPT_RAW_IPV6:
2157                 return "IB_QPT_RAW_IPV6";
2158         case IB_QPT_RAW_ETHERTYPE:
2159                 return "IB_QPT_RAW_ETHERTYPE";
2160         case IB_QPT_XRC_INI:
2161                 return "IB_QPT_XRC_INI";
2162         case IB_QPT_XRC_TGT:
2163                 return "IB_QPT_XRC_TGT";
2164         case IB_QPT_RAW_PACKET:
2165                 return "IB_QPT_RAW_PACKET";
2166         case MLX5_IB_QPT_REG_UMR:
2167                 return "MLX5_IB_QPT_REG_UMR";
2168         case IB_QPT_DRIVER:
2169                 return "IB_QPT_DRIVER";
2170         case IB_QPT_MAX:
2171         default:
2172                 return "Invalid QP type";
2173         }
2174 }
2175
2176 static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd,
2177                                         struct ib_qp_init_attr *attr,
2178                                         struct mlx5_ib_create_qp *ucmd)
2179 {
2180         struct mlx5_ib_qp *qp;
2181         int err = 0;
2182         u32 uidx = MLX5_IB_DEFAULT_UIDX;
2183         void *dctc;
2184
2185         if (!attr->srq || !attr->recv_cq)
2186                 return ERR_PTR(-EINVAL);
2187
2188         err = get_qp_user_index(to_mucontext(pd->uobject->context),
2189                                 ucmd, sizeof(*ucmd), &uidx);
2190         if (err)
2191                 return ERR_PTR(err);
2192
2193         qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2194         if (!qp)
2195                 return ERR_PTR(-ENOMEM);
2196
2197         qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
2198         if (!qp->dct.in) {
2199                 err = -ENOMEM;
2200                 goto err_free;
2201         }
2202
2203         dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
2204         qp->qp_sub_type = MLX5_IB_QPT_DCT;
2205         MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn);
2206         MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn);
2207         MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn);
2208         MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key);
2209         MLX5_SET(dctc, dctc, user_index, uidx);
2210
2211         qp->state = IB_QPS_RESET;
2212
2213         return &qp->ibqp;
2214 err_free:
2215         kfree(qp);
2216         return ERR_PTR(err);
2217 }
2218
2219 static int set_mlx_qp_type(struct mlx5_ib_dev *dev,
2220                            struct ib_qp_init_attr *init_attr,
2221                            struct mlx5_ib_create_qp *ucmd,
2222                            struct ib_udata *udata)
2223 {
2224         enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI };
2225         int err;
2226
2227         if (!udata)
2228                 return -EINVAL;
2229
2230         if (udata->inlen < sizeof(*ucmd)) {
2231                 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n");
2232                 return -EINVAL;
2233         }
2234         err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd));
2235         if (err)
2236                 return err;
2237
2238         if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) {
2239                 init_attr->qp_type = MLX5_IB_QPT_DCI;
2240         } else {
2241                 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) {
2242                         init_attr->qp_type = MLX5_IB_QPT_DCT;
2243                 } else {
2244                         mlx5_ib_dbg(dev, "Invalid QP flags\n");
2245                         return -EINVAL;
2246                 }
2247         }
2248
2249         if (!MLX5_CAP_GEN(dev->mdev, dct)) {
2250                 mlx5_ib_dbg(dev, "DC transport is not supported\n");
2251                 return -EOPNOTSUPP;
2252         }
2253
2254         return 0;
2255 }
2256
2257 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
2258                                 struct ib_qp_init_attr *verbs_init_attr,
2259                                 struct ib_udata *udata)
2260 {
2261         struct mlx5_ib_dev *dev;
2262         struct mlx5_ib_qp *qp;
2263         u16 xrcdn = 0;
2264         int err;
2265         struct ib_qp_init_attr mlx_init_attr;
2266         struct ib_qp_init_attr *init_attr = verbs_init_attr;
2267
2268         if (pd) {
2269                 dev = to_mdev(pd->device);
2270
2271                 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2272                         if (!pd->uobject) {
2273                                 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2274                                 return ERR_PTR(-EINVAL);
2275                         } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2276                                 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2277                                 return ERR_PTR(-EINVAL);
2278                         }
2279                 }
2280         } else {
2281                 /* being cautious here */
2282                 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2283                     init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2284                         pr_warn("%s: no PD for transport %s\n", __func__,
2285                                 ib_qp_type_str(init_attr->qp_type));
2286                         return ERR_PTR(-EINVAL);
2287                 }
2288                 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2289         }
2290
2291         if (init_attr->qp_type == IB_QPT_DRIVER) {
2292                 struct mlx5_ib_create_qp ucmd;
2293
2294                 init_attr = &mlx_init_attr;
2295                 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr));
2296                 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata);
2297                 if (err)
2298                         return ERR_PTR(err);
2299
2300                 if (init_attr->qp_type == MLX5_IB_QPT_DCI) {
2301                         if (init_attr->cap.max_recv_wr ||
2302                             init_attr->cap.max_recv_sge) {
2303                                 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n");
2304                                 return ERR_PTR(-EINVAL);
2305                         }
2306                 } else {
2307                         return mlx5_ib_create_dct(pd, init_attr, &ucmd);
2308                 }
2309         }
2310
2311         switch (init_attr->qp_type) {
2312         case IB_QPT_XRC_TGT:
2313         case IB_QPT_XRC_INI:
2314                 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
2315                         mlx5_ib_dbg(dev, "XRC not supported\n");
2316                         return ERR_PTR(-ENOSYS);
2317                 }
2318                 init_attr->recv_cq = NULL;
2319                 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2320                         xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2321                         init_attr->send_cq = NULL;
2322                 }
2323
2324                 /* fall through */
2325         case IB_QPT_RAW_PACKET:
2326         case IB_QPT_RC:
2327         case IB_QPT_UC:
2328         case IB_QPT_UD:
2329         case IB_QPT_SMI:
2330         case MLX5_IB_QPT_HW_GSI:
2331         case MLX5_IB_QPT_REG_UMR:
2332         case MLX5_IB_QPT_DCI:
2333                 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2334                 if (!qp)
2335                         return ERR_PTR(-ENOMEM);
2336
2337                 err = create_qp_common(dev, pd, init_attr, udata, qp);
2338                 if (err) {
2339                         mlx5_ib_dbg(dev, "create_qp_common failed\n");
2340                         kfree(qp);
2341                         return ERR_PTR(err);
2342                 }
2343
2344                 if (is_qp0(init_attr->qp_type))
2345                         qp->ibqp.qp_num = 0;
2346                 else if (is_qp1(init_attr->qp_type))
2347                         qp->ibqp.qp_num = 1;
2348                 else
2349                         qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2350
2351                 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2352                             qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2353                             init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2354                             init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
2355
2356                 qp->trans_qp.xrcdn = xrcdn;
2357
2358                 break;
2359
2360         case IB_QPT_GSI:
2361                 return mlx5_ib_gsi_create_qp(pd, init_attr);
2362
2363         case IB_QPT_RAW_IPV6:
2364         case IB_QPT_RAW_ETHERTYPE:
2365         case IB_QPT_MAX:
2366         default:
2367                 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2368                             init_attr->qp_type);
2369                 /* Don't support raw QPs */
2370                 return ERR_PTR(-EINVAL);
2371         }
2372
2373         if (verbs_init_attr->qp_type == IB_QPT_DRIVER)
2374                 qp->qp_sub_type = init_attr->qp_type;
2375
2376         return &qp->ibqp;
2377 }
2378
2379 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp)
2380 {
2381         struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device);
2382
2383         if (mqp->state == IB_QPS_RTR) {
2384                 int err;
2385
2386                 err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct);
2387                 if (err) {
2388                         mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err);
2389                         return err;
2390                 }
2391         }
2392
2393         kfree(mqp->dct.in);
2394         kfree(mqp);
2395         return 0;
2396 }
2397
2398 int mlx5_ib_destroy_qp(struct ib_qp *qp)
2399 {
2400         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2401         struct mlx5_ib_qp *mqp = to_mqp(qp);
2402
2403         if (unlikely(qp->qp_type == IB_QPT_GSI))
2404                 return mlx5_ib_gsi_destroy_qp(qp);
2405
2406         if (mqp->qp_sub_type == MLX5_IB_QPT_DCT)
2407                 return mlx5_ib_destroy_dct(mqp);
2408
2409         destroy_qp_common(dev, mqp);
2410
2411         kfree(mqp);
2412
2413         return 0;
2414 }
2415
2416 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2417                                    int attr_mask)
2418 {
2419         u32 hw_access_flags = 0;
2420         u8 dest_rd_atomic;
2421         u32 access_flags;
2422
2423         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2424                 dest_rd_atomic = attr->max_dest_rd_atomic;
2425         else
2426                 dest_rd_atomic = qp->trans_qp.resp_depth;
2427
2428         if (attr_mask & IB_QP_ACCESS_FLAGS)
2429                 access_flags = attr->qp_access_flags;
2430         else
2431                 access_flags = qp->trans_qp.atomic_rd_en;
2432
2433         if (!dest_rd_atomic)
2434                 access_flags &= IB_ACCESS_REMOTE_WRITE;
2435
2436         if (access_flags & IB_ACCESS_REMOTE_READ)
2437                 hw_access_flags |= MLX5_QP_BIT_RRE;
2438         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2439                 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2440         if (access_flags & IB_ACCESS_REMOTE_WRITE)
2441                 hw_access_flags |= MLX5_QP_BIT_RWE;
2442
2443         return cpu_to_be32(hw_access_flags);
2444 }
2445
2446 enum {
2447         MLX5_PATH_FLAG_FL       = 1 << 0,
2448         MLX5_PATH_FLAG_FREE_AR  = 1 << 1,
2449         MLX5_PATH_FLAG_COUNTER  = 1 << 2,
2450 };
2451
2452 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2453 {
2454         if (rate == IB_RATE_PORT_CURRENT) {
2455                 return 0;
2456         } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
2457                 return -EINVAL;
2458         } else {
2459                 while (rate != IB_RATE_2_5_GBPS &&
2460                        !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2461                          MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2462                         --rate;
2463         }
2464
2465         return rate + MLX5_STAT_RATE_OFFSET;
2466 }
2467
2468 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2469                                       struct mlx5_ib_sq *sq, u8 sl)
2470 {
2471         void *in;
2472         void *tisc;
2473         int inlen;
2474         int err;
2475
2476         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2477         in = kvzalloc(inlen, GFP_KERNEL);
2478         if (!in)
2479                 return -ENOMEM;
2480
2481         MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2482
2483         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2484         MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2485
2486         err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2487
2488         kvfree(in);
2489
2490         return err;
2491 }
2492
2493 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2494                                          struct mlx5_ib_sq *sq, u8 tx_affinity)
2495 {
2496         void *in;
2497         void *tisc;
2498         int inlen;
2499         int err;
2500
2501         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2502         in = kvzalloc(inlen, GFP_KERNEL);
2503         if (!in)
2504                 return -ENOMEM;
2505
2506         MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2507
2508         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2509         MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2510
2511         err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2512
2513         kvfree(in);
2514
2515         return err;
2516 }
2517
2518 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2519                          const struct rdma_ah_attr *ah,
2520                          struct mlx5_qp_path *path, u8 port, int attr_mask,
2521                          u32 path_flags, const struct ib_qp_attr *attr,
2522                          bool alt)
2523 {
2524         const struct ib_global_route *grh = rdma_ah_read_grh(ah);
2525         int err;
2526         enum ib_gid_type gid_type;
2527         u8 ah_flags = rdma_ah_get_ah_flags(ah);
2528         u8 sl = rdma_ah_get_sl(ah);
2529
2530         if (attr_mask & IB_QP_PKEY_INDEX)
2531                 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2532                                                      attr->pkey_index);
2533
2534         if (ah_flags & IB_AH_GRH) {
2535                 if (grh->sgid_index >=
2536                     dev->mdev->port_caps[port - 1].gid_table_len) {
2537                         pr_err("sgid_index (%u) too large. max is %d\n",
2538                                grh->sgid_index,
2539                                dev->mdev->port_caps[port - 1].gid_table_len);
2540                         return -EINVAL;
2541                 }
2542         }
2543
2544         if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
2545                 if (!(ah_flags & IB_AH_GRH))
2546                         return -EINVAL;
2547                 err = mlx5_get_roce_gid_type(dev, port, grh->sgid_index,
2548                                              &gid_type);
2549                 if (err)
2550                         return err;
2551                 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2552                 if (qp->ibqp.qp_type == IB_QPT_RC ||
2553                     qp->ibqp.qp_type == IB_QPT_UC ||
2554                     qp->ibqp.qp_type == IB_QPT_XRC_INI ||
2555                     qp->ibqp.qp_type == IB_QPT_XRC_TGT)
2556                         path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
2557                                                                   grh->sgid_index);
2558                 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
2559                 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
2560                         path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
2561         } else {
2562                 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2563                 path->fl_free_ar |=
2564                         (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2565                 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
2566                 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
2567                 if (ah_flags & IB_AH_GRH)
2568                         path->grh_mlid  |= 1 << 7;
2569                 path->dci_cfi_prio_sl = sl & 0xf;
2570         }
2571
2572         if (ah_flags & IB_AH_GRH) {
2573                 path->mgid_index = grh->sgid_index;
2574                 path->hop_limit  = grh->hop_limit;
2575                 path->tclass_flowlabel =
2576                         cpu_to_be32((grh->traffic_class << 20) |
2577                                     (grh->flow_label));
2578                 memcpy(path->rgid, grh->dgid.raw, 16);
2579         }
2580
2581         err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
2582         if (err < 0)
2583                 return err;
2584         path->static_rate = err;
2585         path->port = port;
2586
2587         if (attr_mask & IB_QP_TIMEOUT)
2588                 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2589
2590         if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2591                 return modify_raw_packet_eth_prio(dev->mdev,
2592                                                   &qp->raw_packet_qp.sq,
2593                                                   sl & 0xf);
2594
2595         return 0;
2596 }
2597
2598 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2599         [MLX5_QP_STATE_INIT] = {
2600                 [MLX5_QP_STATE_INIT] = {
2601                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2602                                           MLX5_QP_OPTPAR_RAE            |
2603                                           MLX5_QP_OPTPAR_RWE            |
2604                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2605                                           MLX5_QP_OPTPAR_PRI_PORT,
2606                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
2607                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2608                                           MLX5_QP_OPTPAR_PRI_PORT,
2609                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2610                                           MLX5_QP_OPTPAR_Q_KEY          |
2611                                           MLX5_QP_OPTPAR_PRI_PORT,
2612                 },
2613                 [MLX5_QP_STATE_RTR] = {
2614                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2615                                           MLX5_QP_OPTPAR_RRE            |
2616                                           MLX5_QP_OPTPAR_RAE            |
2617                                           MLX5_QP_OPTPAR_RWE            |
2618                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2619                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2620                                           MLX5_QP_OPTPAR_RWE            |
2621                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2622                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2623                                           MLX5_QP_OPTPAR_Q_KEY,
2624                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX    |
2625                                            MLX5_QP_OPTPAR_Q_KEY,
2626                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2627                                           MLX5_QP_OPTPAR_RRE            |
2628                                           MLX5_QP_OPTPAR_RAE            |
2629                                           MLX5_QP_OPTPAR_RWE            |
2630                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2631                 },
2632         },
2633         [MLX5_QP_STATE_RTR] = {
2634                 [MLX5_QP_STATE_RTS] = {
2635                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2636                                           MLX5_QP_OPTPAR_RRE            |
2637                                           MLX5_QP_OPTPAR_RAE            |
2638                                           MLX5_QP_OPTPAR_RWE            |
2639                                           MLX5_QP_OPTPAR_PM_STATE       |
2640                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
2641                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2642                                           MLX5_QP_OPTPAR_RWE            |
2643                                           MLX5_QP_OPTPAR_PM_STATE,
2644                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2645                 },
2646         },
2647         [MLX5_QP_STATE_RTS] = {
2648                 [MLX5_QP_STATE_RTS] = {
2649                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2650                                           MLX5_QP_OPTPAR_RAE            |
2651                                           MLX5_QP_OPTPAR_RWE            |
2652                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
2653                                           MLX5_QP_OPTPAR_PM_STATE       |
2654                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2655                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
2656                                           MLX5_QP_OPTPAR_PM_STATE       |
2657                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2658                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY          |
2659                                           MLX5_QP_OPTPAR_SRQN           |
2660                                           MLX5_QP_OPTPAR_CQN_RCV,
2661                 },
2662         },
2663         [MLX5_QP_STATE_SQER] = {
2664                 [MLX5_QP_STATE_RTS] = {
2665                         [MLX5_QP_ST_UD]  = MLX5_QP_OPTPAR_Q_KEY,
2666                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
2667                         [MLX5_QP_ST_UC]  = MLX5_QP_OPTPAR_RWE,
2668                         [MLX5_QP_ST_RC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT   |
2669                                            MLX5_QP_OPTPAR_RWE           |
2670                                            MLX5_QP_OPTPAR_RAE           |
2671                                            MLX5_QP_OPTPAR_RRE,
2672                 },
2673         },
2674 };
2675
2676 static int ib_nr_to_mlx5_nr(int ib_mask)
2677 {
2678         switch (ib_mask) {
2679         case IB_QP_STATE:
2680                 return 0;
2681         case IB_QP_CUR_STATE:
2682                 return 0;
2683         case IB_QP_EN_SQD_ASYNC_NOTIFY:
2684                 return 0;
2685         case IB_QP_ACCESS_FLAGS:
2686                 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2687                         MLX5_QP_OPTPAR_RAE;
2688         case IB_QP_PKEY_INDEX:
2689                 return MLX5_QP_OPTPAR_PKEY_INDEX;
2690         case IB_QP_PORT:
2691                 return MLX5_QP_OPTPAR_PRI_PORT;
2692         case IB_QP_QKEY:
2693                 return MLX5_QP_OPTPAR_Q_KEY;
2694         case IB_QP_AV:
2695                 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2696                         MLX5_QP_OPTPAR_PRI_PORT;
2697         case IB_QP_PATH_MTU:
2698                 return 0;
2699         case IB_QP_TIMEOUT:
2700                 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2701         case IB_QP_RETRY_CNT:
2702                 return MLX5_QP_OPTPAR_RETRY_COUNT;
2703         case IB_QP_RNR_RETRY:
2704                 return MLX5_QP_OPTPAR_RNR_RETRY;
2705         case IB_QP_RQ_PSN:
2706                 return 0;
2707         case IB_QP_MAX_QP_RD_ATOMIC:
2708                 return MLX5_QP_OPTPAR_SRA_MAX;
2709         case IB_QP_ALT_PATH:
2710                 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2711         case IB_QP_MIN_RNR_TIMER:
2712                 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2713         case IB_QP_SQ_PSN:
2714                 return 0;
2715         case IB_QP_MAX_DEST_RD_ATOMIC:
2716                 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2717                         MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2718         case IB_QP_PATH_MIG_STATE:
2719                 return MLX5_QP_OPTPAR_PM_STATE;
2720         case IB_QP_CAP:
2721                 return 0;
2722         case IB_QP_DEST_QPN:
2723                 return 0;
2724         }
2725         return 0;
2726 }
2727
2728 static int ib_mask_to_mlx5_opt(int ib_mask)
2729 {
2730         int result = 0;
2731         int i;
2732
2733         for (i = 0; i < 8 * sizeof(int); i++) {
2734                 if ((1 << i) & ib_mask)
2735                         result |= ib_nr_to_mlx5_nr(1 << i);
2736         }
2737
2738         return result;
2739 }
2740
2741 static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2742                                    struct mlx5_ib_rq *rq, int new_state,
2743                                    const struct mlx5_modify_raw_qp_param *raw_qp_param)
2744 {
2745         void *in;
2746         void *rqc;
2747         int inlen;
2748         int err;
2749
2750         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2751         in = kvzalloc(inlen, GFP_KERNEL);
2752         if (!in)
2753                 return -ENOMEM;
2754
2755         MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2756
2757         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2758         MLX5_SET(rqc, rqc, state, new_state);
2759
2760         if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2761                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
2762                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
2763                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
2764                         MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2765                 } else
2766                         pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n",
2767                                      dev->ib_dev.name);
2768         }
2769
2770         err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
2771         if (err)
2772                 goto out;
2773
2774         rq->state = new_state;
2775
2776 out:
2777         kvfree(in);
2778         return err;
2779 }
2780
2781 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2782                                    struct mlx5_ib_sq *sq,
2783                                    int new_state,
2784                                    const struct mlx5_modify_raw_qp_param *raw_qp_param)
2785 {
2786         struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
2787         struct mlx5_rate_limit old_rl = ibqp->rl;
2788         struct mlx5_rate_limit new_rl = old_rl;
2789         bool new_rate_added = false;
2790         u16 rl_index = 0;
2791         void *in;
2792         void *sqc;
2793         int inlen;
2794         int err;
2795
2796         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2797         in = kvzalloc(inlen, GFP_KERNEL);
2798         if (!in)
2799                 return -ENOMEM;
2800
2801         MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2802
2803         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2804         MLX5_SET(sqc, sqc, state, new_state);
2805
2806         if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
2807                 if (new_state != MLX5_SQC_STATE_RDY)
2808                         pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
2809                                 __func__);
2810                 else
2811                         new_rl = raw_qp_param->rl;
2812         }
2813
2814         if (!mlx5_rl_are_equal(&old_rl, &new_rl)) {
2815                 if (new_rl.rate) {
2816                         err = mlx5_rl_add_rate(dev, &rl_index, &new_rl);
2817                         if (err) {
2818                                 pr_err("Failed configuring rate limit(err %d): \
2819                                        rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
2820                                        err, new_rl.rate, new_rl.max_burst_sz,
2821                                        new_rl.typical_pkt_sz);
2822
2823                                 goto out;
2824                         }
2825                         new_rate_added = true;
2826                 }
2827
2828                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
2829                 /* index 0 means no limit */
2830                 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
2831         }
2832
2833         err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
2834         if (err) {
2835                 /* Remove new rate from table if failed */
2836                 if (new_rate_added)
2837                         mlx5_rl_remove_rate(dev, &new_rl);
2838                 goto out;
2839         }
2840
2841         /* Only remove the old rate after new rate was set */
2842         if ((old_rl.rate &&
2843              !mlx5_rl_are_equal(&old_rl, &new_rl)) ||
2844             (new_state != MLX5_SQC_STATE_RDY))
2845                 mlx5_rl_remove_rate(dev, &old_rl);
2846
2847         ibqp->rl = new_rl;
2848         sq->state = new_state;
2849
2850 out:
2851         kvfree(in);
2852         return err;
2853 }
2854
2855 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2856                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2857                                 u8 tx_affinity)
2858 {
2859         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2860         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2861         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2862         int modify_rq = !!qp->rq.wqe_cnt;
2863         int modify_sq = !!qp->sq.wqe_cnt;
2864         int rq_state;
2865         int sq_state;
2866         int err;
2867
2868         switch (raw_qp_param->operation) {
2869         case MLX5_CMD_OP_RST2INIT_QP:
2870                 rq_state = MLX5_RQC_STATE_RDY;
2871                 sq_state = MLX5_SQC_STATE_RDY;
2872                 break;
2873         case MLX5_CMD_OP_2ERR_QP:
2874                 rq_state = MLX5_RQC_STATE_ERR;
2875                 sq_state = MLX5_SQC_STATE_ERR;
2876                 break;
2877         case MLX5_CMD_OP_2RST_QP:
2878                 rq_state = MLX5_RQC_STATE_RST;
2879                 sq_state = MLX5_SQC_STATE_RST;
2880                 break;
2881         case MLX5_CMD_OP_RTR2RTS_QP:
2882         case MLX5_CMD_OP_RTS2RTS_QP:
2883                 if (raw_qp_param->set_mask ==
2884                     MLX5_RAW_QP_RATE_LIMIT) {
2885                         modify_rq = 0;
2886                         sq_state = sq->state;
2887                 } else {
2888                         return raw_qp_param->set_mask ? -EINVAL : 0;
2889                 }
2890                 break;
2891         case MLX5_CMD_OP_INIT2INIT_QP:
2892         case MLX5_CMD_OP_INIT2RTR_QP:
2893                 if (raw_qp_param->set_mask)
2894                         return -EINVAL;
2895                 else
2896                         return 0;
2897         default:
2898                 WARN_ON(1);
2899                 return -EINVAL;
2900         }
2901
2902         if (modify_rq) {
2903                 err =  modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param);
2904                 if (err)
2905                         return err;
2906         }
2907
2908         if (modify_sq) {
2909                 if (tx_affinity) {
2910                         err = modify_raw_packet_tx_affinity(dev->mdev, sq,
2911                                                             tx_affinity);
2912                         if (err)
2913                                 return err;
2914                 }
2915
2916                 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param);
2917         }
2918
2919         return 0;
2920 }
2921
2922 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2923                                const struct ib_qp_attr *attr, int attr_mask,
2924                                enum ib_qp_state cur_state, enum ib_qp_state new_state,
2925                                const struct mlx5_ib_modify_qp *ucmd)
2926 {
2927         static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2928                 [MLX5_QP_STATE_RST] = {
2929                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2930                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2931                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_RST2INIT_QP,
2932                 },
2933                 [MLX5_QP_STATE_INIT]  = {
2934                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2935                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2936                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_INIT2INIT_QP,
2937                         [MLX5_QP_STATE_RTR]     = MLX5_CMD_OP_INIT2RTR_QP,
2938                 },
2939                 [MLX5_QP_STATE_RTR]   = {
2940                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2941                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2942                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTR2RTS_QP,
2943                 },
2944                 [MLX5_QP_STATE_RTS]   = {
2945                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2946                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2947                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTS2RTS_QP,
2948                 },
2949                 [MLX5_QP_STATE_SQD] = {
2950                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2951                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2952                 },
2953                 [MLX5_QP_STATE_SQER] = {
2954                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2955                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2956                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_SQERR2RTS_QP,
2957                 },
2958                 [MLX5_QP_STATE_ERR] = {
2959                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2960                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2961                 }
2962         };
2963
2964         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2965         struct mlx5_ib_qp *qp = to_mqp(ibqp);
2966         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
2967         struct mlx5_ib_cq *send_cq, *recv_cq;
2968         struct mlx5_qp_context *context;
2969         struct mlx5_ib_pd *pd;
2970         struct mlx5_ib_port *mibport = NULL;
2971         enum mlx5_qp_state mlx5_cur, mlx5_new;
2972         enum mlx5_qp_optpar optpar;
2973         int mlx5_st;
2974         int err;
2975         u16 op;
2976         u8 tx_affinity = 0;
2977
2978         mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ?
2979                              qp->qp_sub_type : ibqp->qp_type);
2980         if (mlx5_st < 0)
2981                 return -EINVAL;
2982
2983         context = kzalloc(sizeof(*context), GFP_KERNEL);
2984         if (!context)
2985                 return -ENOMEM;
2986
2987         context->flags = cpu_to_be32(mlx5_st << 16);
2988
2989         if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2990                 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2991         } else {
2992                 switch (attr->path_mig_state) {
2993                 case IB_MIG_MIGRATED:
2994                         context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2995                         break;
2996                 case IB_MIG_REARM:
2997                         context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2998                         break;
2999                 case IB_MIG_ARMED:
3000                         context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
3001                         break;
3002                 }
3003         }
3004
3005         if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
3006                 if ((ibqp->qp_type == IB_QPT_RC) ||
3007                     (ibqp->qp_type == IB_QPT_UD &&
3008                      !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
3009                     (ibqp->qp_type == IB_QPT_UC) ||
3010                     (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
3011                     (ibqp->qp_type == IB_QPT_XRC_INI) ||
3012                     (ibqp->qp_type == IB_QPT_XRC_TGT)) {
3013                         if (mlx5_lag_is_active(dev->mdev)) {
3014                                 u8 p = mlx5_core_native_port_num(dev->mdev);
3015                                 tx_affinity = (unsigned int)atomic_add_return(1,
3016                                                 &dev->roce[p].next_port) %
3017                                                 MLX5_MAX_PORTS + 1;
3018                                 context->flags |= cpu_to_be32(tx_affinity << 24);
3019                         }
3020                 }
3021         }
3022
3023         if (is_sqp(ibqp->qp_type)) {
3024                 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
3025         } else if ((ibqp->qp_type == IB_QPT_UD &&
3026                     !(qp->flags & MLX5_IB_QP_UNDERLAY)) ||
3027                    ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
3028                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
3029         } else if (attr_mask & IB_QP_PATH_MTU) {
3030                 if (attr->path_mtu < IB_MTU_256 ||
3031                     attr->path_mtu > IB_MTU_4096) {
3032                         mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
3033                         err = -EINVAL;
3034                         goto out;
3035                 }
3036                 context->mtu_msgmax = (attr->path_mtu << 5) |
3037                                       (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
3038         }
3039
3040         if (attr_mask & IB_QP_DEST_QPN)
3041                 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
3042
3043         if (attr_mask & IB_QP_PKEY_INDEX)
3044                 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
3045
3046         /* todo implement counter_index functionality */
3047
3048         if (is_sqp(ibqp->qp_type))
3049                 context->pri_path.port = qp->port;
3050
3051         if (attr_mask & IB_QP_PORT)
3052                 context->pri_path.port = attr->port_num;
3053
3054         if (attr_mask & IB_QP_AV) {
3055                 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
3056                                     attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
3057                                     attr_mask, 0, attr, false);
3058                 if (err)
3059                         goto out;
3060         }
3061
3062         if (attr_mask & IB_QP_TIMEOUT)
3063                 context->pri_path.ackto_lt |= attr->timeout << 3;
3064
3065         if (attr_mask & IB_QP_ALT_PATH) {
3066                 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
3067                                     &context->alt_path,
3068                                     attr->alt_port_num,
3069                                     attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
3070                                     0, attr, true);
3071                 if (err)
3072                         goto out;
3073         }
3074
3075         pd = get_pd(qp);
3076         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
3077                 &send_cq, &recv_cq);
3078
3079         context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
3080         context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
3081         context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
3082         context->params1  = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
3083
3084         if (attr_mask & IB_QP_RNR_RETRY)
3085                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
3086
3087         if (attr_mask & IB_QP_RETRY_CNT)
3088                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
3089
3090         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
3091                 if (attr->max_rd_atomic)
3092                         context->params1 |=
3093                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
3094         }
3095
3096         if (attr_mask & IB_QP_SQ_PSN)
3097                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
3098
3099         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
3100                 if (attr->max_dest_rd_atomic)
3101                         context->params2 |=
3102                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
3103         }
3104
3105         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
3106                 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
3107
3108         if (attr_mask & IB_QP_MIN_RNR_TIMER)
3109                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
3110
3111         if (attr_mask & IB_QP_RQ_PSN)
3112                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
3113
3114         if (attr_mask & IB_QP_QKEY)
3115                 context->qkey = cpu_to_be32(attr->qkey);
3116
3117         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3118                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
3119
3120         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3121                 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
3122                                qp->port) - 1;
3123
3124                 /* Underlay port should be used - index 0 function per port */
3125                 if (qp->flags & MLX5_IB_QP_UNDERLAY)
3126                         port_num = 0;
3127
3128                 mibport = &dev->port[port_num];
3129                 context->qp_counter_set_usr_page |=
3130                         cpu_to_be32((u32)(mibport->cnts.set_id) << 24);
3131         }
3132
3133         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3134                 context->sq_crq_size |= cpu_to_be16(1 << 4);
3135
3136         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
3137                 context->deth_sqpn = cpu_to_be32(1);
3138
3139         mlx5_cur = to_mlx5_state(cur_state);
3140         mlx5_new = to_mlx5_state(new_state);
3141
3142         if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
3143             !optab[mlx5_cur][mlx5_new]) {
3144                 err = -EINVAL;
3145                 goto out;
3146         }
3147
3148         op = optab[mlx5_cur][mlx5_new];
3149         optpar = ib_mask_to_mlx5_opt(attr_mask);
3150         optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
3151
3152         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
3153             qp->flags & MLX5_IB_QP_UNDERLAY) {
3154                 struct mlx5_modify_raw_qp_param raw_qp_param = {};
3155
3156                 raw_qp_param.operation = op;
3157                 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3158                         raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id;
3159                         raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
3160                 }
3161
3162                 if (attr_mask & IB_QP_RATE_LIMIT) {
3163                         raw_qp_param.rl.rate = attr->rate_limit;
3164
3165                         if (ucmd->burst_info.max_burst_sz) {
3166                                 if (attr->rate_limit &&
3167                                     MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) {
3168                                         raw_qp_param.rl.max_burst_sz =
3169                                                 ucmd->burst_info.max_burst_sz;
3170                                 } else {
3171                                         err = -EINVAL;
3172                                         goto out;
3173                                 }
3174                         }
3175
3176                         if (ucmd->burst_info.typical_pkt_sz) {