Merge tag 'iommu-updates-v4.17' of git://git.kernel.org/pub/scm/linux/kernel/git...
[muen/linux.git] / drivers / irqchip / irq-gic-v3-its.c
1 /*
2  * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
3  * Author: Marc Zyngier <marc.zyngier@arm.com>
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License version 2 as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
16  */
17
18 #include <linux/acpi.h>
19 #include <linux/acpi_iort.h>
20 #include <linux/bitmap.h>
21 #include <linux/cpu.h>
22 #include <linux/delay.h>
23 #include <linux/dma-iommu.h>
24 #include <linux/interrupt.h>
25 #include <linux/irqdomain.h>
26 #include <linux/log2.h>
27 #include <linux/mm.h>
28 #include <linux/msi.h>
29 #include <linux/of.h>
30 #include <linux/of_address.h>
31 #include <linux/of_irq.h>
32 #include <linux/of_pci.h>
33 #include <linux/of_platform.h>
34 #include <linux/percpu.h>
35 #include <linux/slab.h>
36 #include <linux/syscore_ops.h>
37
38 #include <linux/irqchip.h>
39 #include <linux/irqchip/arm-gic-v3.h>
40 #include <linux/irqchip/arm-gic-v4.h>
41
42 #include <asm/cputype.h>
43 #include <asm/exception.h>
44
45 #include "irq-gic-common.h"
46
47 #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING           (1ULL << 0)
48 #define ITS_FLAGS_WORKAROUND_CAVIUM_22375       (1ULL << 1)
49 #define ITS_FLAGS_WORKAROUND_CAVIUM_23144       (1ULL << 2)
50 #define ITS_FLAGS_SAVE_SUSPEND_STATE            (1ULL << 3)
51
52 #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING     (1 << 0)
53
54 static u32 lpi_id_bits;
55
56 /*
57  * We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to
58  * deal with (one configuration byte per interrupt). PENDBASE has to
59  * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
60  */
61 #define LPI_NRBITS              lpi_id_bits
62 #define LPI_PROPBASE_SZ         ALIGN(BIT(LPI_NRBITS), SZ_64K)
63 #define LPI_PENDBASE_SZ         ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
64
65 #define LPI_PROP_DEFAULT_PRIO   0xa0
66
67 /*
68  * Collection structure - just an ID, and a redistributor address to
69  * ping. We use one per CPU as a bag of interrupts assigned to this
70  * CPU.
71  */
72 struct its_collection {
73         u64                     target_address;
74         u16                     col_id;
75 };
76
77 /*
78  * The ITS_BASER structure - contains memory information, cached
79  * value of BASER register configuration and ITS page size.
80  */
81 struct its_baser {
82         void            *base;
83         u64             val;
84         u32             order;
85         u32             psz;
86 };
87
88 struct its_device;
89
90 /*
91  * The ITS structure - contains most of the infrastructure, with the
92  * top-level MSI domain, the command queue, the collections, and the
93  * list of devices writing to it.
94  */
95 struct its_node {
96         raw_spinlock_t          lock;
97         struct list_head        entry;
98         void __iomem            *base;
99         phys_addr_t             phys_base;
100         struct its_cmd_block    *cmd_base;
101         struct its_cmd_block    *cmd_write;
102         struct its_baser        tables[GITS_BASER_NR_REGS];
103         struct its_collection   *collections;
104         struct fwnode_handle    *fwnode_handle;
105         u64                     (*get_msi_base)(struct its_device *its_dev);
106         u64                     cbaser_save;
107         u32                     ctlr_save;
108         struct list_head        its_device_list;
109         u64                     flags;
110         unsigned long           list_nr;
111         u32                     ite_size;
112         u32                     device_ids;
113         int                     numa_node;
114         unsigned int            msi_domain_flags;
115         u32                     pre_its_base; /* for Socionext Synquacer */
116         bool                    is_v4;
117         int                     vlpi_redist_offset;
118 };
119
120 #define ITS_ITT_ALIGN           SZ_256
121
122 /* The maximum number of VPEID bits supported by VLPI commands */
123 #define ITS_MAX_VPEID_BITS      (16)
124 #define ITS_MAX_VPEID           (1 << (ITS_MAX_VPEID_BITS))
125
126 /* Convert page order to size in bytes */
127 #define PAGE_ORDER_TO_SIZE(o)   (PAGE_SIZE << (o))
128
129 struct event_lpi_map {
130         unsigned long           *lpi_map;
131         u16                     *col_map;
132         irq_hw_number_t         lpi_base;
133         int                     nr_lpis;
134         struct mutex            vlpi_lock;
135         struct its_vm           *vm;
136         struct its_vlpi_map     *vlpi_maps;
137         int                     nr_vlpis;
138 };
139
140 /*
141  * The ITS view of a device - belongs to an ITS, owns an interrupt
142  * translation table, and a list of interrupts.  If it some of its
143  * LPIs are injected into a guest (GICv4), the event_map.vm field
144  * indicates which one.
145  */
146 struct its_device {
147         struct list_head        entry;
148         struct its_node         *its;
149         struct event_lpi_map    event_map;
150         void                    *itt;
151         u32                     nr_ites;
152         u32                     device_id;
153 };
154
155 static struct {
156         raw_spinlock_t          lock;
157         struct its_device       *dev;
158         struct its_vpe          **vpes;
159         int                     next_victim;
160 } vpe_proxy;
161
162 static LIST_HEAD(its_nodes);
163 static DEFINE_SPINLOCK(its_lock);
164 static struct rdists *gic_rdists;
165 static struct irq_domain *its_parent;
166
167 static unsigned long its_list_map;
168 static u16 vmovp_seq_num;
169 static DEFINE_RAW_SPINLOCK(vmovp_lock);
170
171 static DEFINE_IDA(its_vpeid_ida);
172
173 #define gic_data_rdist()                (raw_cpu_ptr(gic_rdists->rdist))
174 #define gic_data_rdist_rd_base()        (gic_data_rdist()->rd_base)
175 #define gic_data_rdist_vlpi_base()      (gic_data_rdist_rd_base() + SZ_128K)
176
177 static struct its_collection *dev_event_to_col(struct its_device *its_dev,
178                                                u32 event)
179 {
180         struct its_node *its = its_dev->its;
181
182         return its->collections + its_dev->event_map.col_map[event];
183 }
184
185 /*
186  * ITS command descriptors - parameters to be encoded in a command
187  * block.
188  */
189 struct its_cmd_desc {
190         union {
191                 struct {
192                         struct its_device *dev;
193                         u32 event_id;
194                 } its_inv_cmd;
195
196                 struct {
197                         struct its_device *dev;
198                         u32 event_id;
199                 } its_clear_cmd;
200
201                 struct {
202                         struct its_device *dev;
203                         u32 event_id;
204                 } its_int_cmd;
205
206                 struct {
207                         struct its_device *dev;
208                         int valid;
209                 } its_mapd_cmd;
210
211                 struct {
212                         struct its_collection *col;
213                         int valid;
214                 } its_mapc_cmd;
215
216                 struct {
217                         struct its_device *dev;
218                         u32 phys_id;
219                         u32 event_id;
220                 } its_mapti_cmd;
221
222                 struct {
223                         struct its_device *dev;
224                         struct its_collection *col;
225                         u32 event_id;
226                 } its_movi_cmd;
227
228                 struct {
229                         struct its_device *dev;
230                         u32 event_id;
231                 } its_discard_cmd;
232
233                 struct {
234                         struct its_collection *col;
235                 } its_invall_cmd;
236
237                 struct {
238                         struct its_vpe *vpe;
239                 } its_vinvall_cmd;
240
241                 struct {
242                         struct its_vpe *vpe;
243                         struct its_collection *col;
244                         bool valid;
245                 } its_vmapp_cmd;
246
247                 struct {
248                         struct its_vpe *vpe;
249                         struct its_device *dev;
250                         u32 virt_id;
251                         u32 event_id;
252                         bool db_enabled;
253                 } its_vmapti_cmd;
254
255                 struct {
256                         struct its_vpe *vpe;
257                         struct its_device *dev;
258                         u32 event_id;
259                         bool db_enabled;
260                 } its_vmovi_cmd;
261
262                 struct {
263                         struct its_vpe *vpe;
264                         struct its_collection *col;
265                         u16 seq_num;
266                         u16 its_list;
267                 } its_vmovp_cmd;
268         };
269 };
270
271 /*
272  * The ITS command block, which is what the ITS actually parses.
273  */
274 struct its_cmd_block {
275         u64     raw_cmd[4];
276 };
277
278 #define ITS_CMD_QUEUE_SZ                SZ_64K
279 #define ITS_CMD_QUEUE_NR_ENTRIES        (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block))
280
281 typedef struct its_collection *(*its_cmd_builder_t)(struct its_node *,
282                                                     struct its_cmd_block *,
283                                                     struct its_cmd_desc *);
284
285 typedef struct its_vpe *(*its_cmd_vbuilder_t)(struct its_node *,
286                                               struct its_cmd_block *,
287                                               struct its_cmd_desc *);
288
289 static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l)
290 {
291         u64 mask = GENMASK_ULL(h, l);
292         *raw_cmd &= ~mask;
293         *raw_cmd |= (val << l) & mask;
294 }
295
296 static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
297 {
298         its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0);
299 }
300
301 static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
302 {
303         its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32);
304 }
305
306 static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
307 {
308         its_mask_encode(&cmd->raw_cmd[1], id, 31, 0);
309 }
310
311 static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
312 {
313         its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32);
314 }
315
316 static void its_encode_size(struct its_cmd_block *cmd, u8 size)
317 {
318         its_mask_encode(&cmd->raw_cmd[1], size, 4, 0);
319 }
320
321 static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
322 {
323         its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 51, 8);
324 }
325
326 static void its_encode_valid(struct its_cmd_block *cmd, int valid)
327 {
328         its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63);
329 }
330
331 static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
332 {
333         its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 51, 16);
334 }
335
336 static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
337 {
338         its_mask_encode(&cmd->raw_cmd[2], col, 15, 0);
339 }
340
341 static void its_encode_vpeid(struct its_cmd_block *cmd, u16 vpeid)
342 {
343         its_mask_encode(&cmd->raw_cmd[1], vpeid, 47, 32);
344 }
345
346 static void its_encode_virt_id(struct its_cmd_block *cmd, u32 virt_id)
347 {
348         its_mask_encode(&cmd->raw_cmd[2], virt_id, 31, 0);
349 }
350
351 static void its_encode_db_phys_id(struct its_cmd_block *cmd, u32 db_phys_id)
352 {
353         its_mask_encode(&cmd->raw_cmd[2], db_phys_id, 63, 32);
354 }
355
356 static void its_encode_db_valid(struct its_cmd_block *cmd, bool db_valid)
357 {
358         its_mask_encode(&cmd->raw_cmd[2], db_valid, 0, 0);
359 }
360
361 static void its_encode_seq_num(struct its_cmd_block *cmd, u16 seq_num)
362 {
363         its_mask_encode(&cmd->raw_cmd[0], seq_num, 47, 32);
364 }
365
366 static void its_encode_its_list(struct its_cmd_block *cmd, u16 its_list)
367 {
368         its_mask_encode(&cmd->raw_cmd[1], its_list, 15, 0);
369 }
370
371 static void its_encode_vpt_addr(struct its_cmd_block *cmd, u64 vpt_pa)
372 {
373         its_mask_encode(&cmd->raw_cmd[3], vpt_pa >> 16, 51, 16);
374 }
375
376 static void its_encode_vpt_size(struct its_cmd_block *cmd, u8 vpt_size)
377 {
378         its_mask_encode(&cmd->raw_cmd[3], vpt_size, 4, 0);
379 }
380
381 static inline void its_fixup_cmd(struct its_cmd_block *cmd)
382 {
383         /* Let's fixup BE commands */
384         cmd->raw_cmd[0] = cpu_to_le64(cmd->raw_cmd[0]);
385         cmd->raw_cmd[1] = cpu_to_le64(cmd->raw_cmd[1]);
386         cmd->raw_cmd[2] = cpu_to_le64(cmd->raw_cmd[2]);
387         cmd->raw_cmd[3] = cpu_to_le64(cmd->raw_cmd[3]);
388 }
389
390 static struct its_collection *its_build_mapd_cmd(struct its_node *its,
391                                                  struct its_cmd_block *cmd,
392                                                  struct its_cmd_desc *desc)
393 {
394         unsigned long itt_addr;
395         u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites);
396
397         itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt);
398         itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN);
399
400         its_encode_cmd(cmd, GITS_CMD_MAPD);
401         its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id);
402         its_encode_size(cmd, size - 1);
403         its_encode_itt(cmd, itt_addr);
404         its_encode_valid(cmd, desc->its_mapd_cmd.valid);
405
406         its_fixup_cmd(cmd);
407
408         return NULL;
409 }
410
411 static struct its_collection *its_build_mapc_cmd(struct its_node *its,
412                                                  struct its_cmd_block *cmd,
413                                                  struct its_cmd_desc *desc)
414 {
415         its_encode_cmd(cmd, GITS_CMD_MAPC);
416         its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
417         its_encode_target(cmd, desc->its_mapc_cmd.col->target_address);
418         its_encode_valid(cmd, desc->its_mapc_cmd.valid);
419
420         its_fixup_cmd(cmd);
421
422         return desc->its_mapc_cmd.col;
423 }
424
425 static struct its_collection *its_build_mapti_cmd(struct its_node *its,
426                                                   struct its_cmd_block *cmd,
427                                                   struct its_cmd_desc *desc)
428 {
429         struct its_collection *col;
430
431         col = dev_event_to_col(desc->its_mapti_cmd.dev,
432                                desc->its_mapti_cmd.event_id);
433
434         its_encode_cmd(cmd, GITS_CMD_MAPTI);
435         its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id);
436         its_encode_event_id(cmd, desc->its_mapti_cmd.event_id);
437         its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id);
438         its_encode_collection(cmd, col->col_id);
439
440         its_fixup_cmd(cmd);
441
442         return col;
443 }
444
445 static struct its_collection *its_build_movi_cmd(struct its_node *its,
446                                                  struct its_cmd_block *cmd,
447                                                  struct its_cmd_desc *desc)
448 {
449         struct its_collection *col;
450
451         col = dev_event_to_col(desc->its_movi_cmd.dev,
452                                desc->its_movi_cmd.event_id);
453
454         its_encode_cmd(cmd, GITS_CMD_MOVI);
455         its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id);
456         its_encode_event_id(cmd, desc->its_movi_cmd.event_id);
457         its_encode_collection(cmd, desc->its_movi_cmd.col->col_id);
458
459         its_fixup_cmd(cmd);
460
461         return col;
462 }
463
464 static struct its_collection *its_build_discard_cmd(struct its_node *its,
465                                                     struct its_cmd_block *cmd,
466                                                     struct its_cmd_desc *desc)
467 {
468         struct its_collection *col;
469
470         col = dev_event_to_col(desc->its_discard_cmd.dev,
471                                desc->its_discard_cmd.event_id);
472
473         its_encode_cmd(cmd, GITS_CMD_DISCARD);
474         its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id);
475         its_encode_event_id(cmd, desc->its_discard_cmd.event_id);
476
477         its_fixup_cmd(cmd);
478
479         return col;
480 }
481
482 static struct its_collection *its_build_inv_cmd(struct its_node *its,
483                                                 struct its_cmd_block *cmd,
484                                                 struct its_cmd_desc *desc)
485 {
486         struct its_collection *col;
487
488         col = dev_event_to_col(desc->its_inv_cmd.dev,
489                                desc->its_inv_cmd.event_id);
490
491         its_encode_cmd(cmd, GITS_CMD_INV);
492         its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
493         its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
494
495         its_fixup_cmd(cmd);
496
497         return col;
498 }
499
500 static struct its_collection *its_build_int_cmd(struct its_node *its,
501                                                 struct its_cmd_block *cmd,
502                                                 struct its_cmd_desc *desc)
503 {
504         struct its_collection *col;
505
506         col = dev_event_to_col(desc->its_int_cmd.dev,
507                                desc->its_int_cmd.event_id);
508
509         its_encode_cmd(cmd, GITS_CMD_INT);
510         its_encode_devid(cmd, desc->its_int_cmd.dev->device_id);
511         its_encode_event_id(cmd, desc->its_int_cmd.event_id);
512
513         its_fixup_cmd(cmd);
514
515         return col;
516 }
517
518 static struct its_collection *its_build_clear_cmd(struct its_node *its,
519                                                   struct its_cmd_block *cmd,
520                                                   struct its_cmd_desc *desc)
521 {
522         struct its_collection *col;
523
524         col = dev_event_to_col(desc->its_clear_cmd.dev,
525                                desc->its_clear_cmd.event_id);
526
527         its_encode_cmd(cmd, GITS_CMD_CLEAR);
528         its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id);
529         its_encode_event_id(cmd, desc->its_clear_cmd.event_id);
530
531         its_fixup_cmd(cmd);
532
533         return col;
534 }
535
536 static struct its_collection *its_build_invall_cmd(struct its_node *its,
537                                                    struct its_cmd_block *cmd,
538                                                    struct its_cmd_desc *desc)
539 {
540         its_encode_cmd(cmd, GITS_CMD_INVALL);
541         its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
542
543         its_fixup_cmd(cmd);
544
545         return NULL;
546 }
547
548 static struct its_vpe *its_build_vinvall_cmd(struct its_node *its,
549                                              struct its_cmd_block *cmd,
550                                              struct its_cmd_desc *desc)
551 {
552         its_encode_cmd(cmd, GITS_CMD_VINVALL);
553         its_encode_vpeid(cmd, desc->its_vinvall_cmd.vpe->vpe_id);
554
555         its_fixup_cmd(cmd);
556
557         return desc->its_vinvall_cmd.vpe;
558 }
559
560 static struct its_vpe *its_build_vmapp_cmd(struct its_node *its,
561                                            struct its_cmd_block *cmd,
562                                            struct its_cmd_desc *desc)
563 {
564         unsigned long vpt_addr;
565         u64 target;
566
567         vpt_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->vpt_page));
568         target = desc->its_vmapp_cmd.col->target_address + its->vlpi_redist_offset;
569
570         its_encode_cmd(cmd, GITS_CMD_VMAPP);
571         its_encode_vpeid(cmd, desc->its_vmapp_cmd.vpe->vpe_id);
572         its_encode_valid(cmd, desc->its_vmapp_cmd.valid);
573         its_encode_target(cmd, target);
574         its_encode_vpt_addr(cmd, vpt_addr);
575         its_encode_vpt_size(cmd, LPI_NRBITS - 1);
576
577         its_fixup_cmd(cmd);
578
579         return desc->its_vmapp_cmd.vpe;
580 }
581
582 static struct its_vpe *its_build_vmapti_cmd(struct its_node *its,
583                                             struct its_cmd_block *cmd,
584                                             struct its_cmd_desc *desc)
585 {
586         u32 db;
587
588         if (desc->its_vmapti_cmd.db_enabled)
589                 db = desc->its_vmapti_cmd.vpe->vpe_db_lpi;
590         else
591                 db = 1023;
592
593         its_encode_cmd(cmd, GITS_CMD_VMAPTI);
594         its_encode_devid(cmd, desc->its_vmapti_cmd.dev->device_id);
595         its_encode_vpeid(cmd, desc->its_vmapti_cmd.vpe->vpe_id);
596         its_encode_event_id(cmd, desc->its_vmapti_cmd.event_id);
597         its_encode_db_phys_id(cmd, db);
598         its_encode_virt_id(cmd, desc->its_vmapti_cmd.virt_id);
599
600         its_fixup_cmd(cmd);
601
602         return desc->its_vmapti_cmd.vpe;
603 }
604
605 static struct its_vpe *its_build_vmovi_cmd(struct its_node *its,
606                                            struct its_cmd_block *cmd,
607                                            struct its_cmd_desc *desc)
608 {
609         u32 db;
610
611         if (desc->its_vmovi_cmd.db_enabled)
612                 db = desc->its_vmovi_cmd.vpe->vpe_db_lpi;
613         else
614                 db = 1023;
615
616         its_encode_cmd(cmd, GITS_CMD_VMOVI);
617         its_encode_devid(cmd, desc->its_vmovi_cmd.dev->device_id);
618         its_encode_vpeid(cmd, desc->its_vmovi_cmd.vpe->vpe_id);
619         its_encode_event_id(cmd, desc->its_vmovi_cmd.event_id);
620         its_encode_db_phys_id(cmd, db);
621         its_encode_db_valid(cmd, true);
622
623         its_fixup_cmd(cmd);
624
625         return desc->its_vmovi_cmd.vpe;
626 }
627
628 static struct its_vpe *its_build_vmovp_cmd(struct its_node *its,
629                                            struct its_cmd_block *cmd,
630                                            struct its_cmd_desc *desc)
631 {
632         u64 target;
633
634         target = desc->its_vmovp_cmd.col->target_address + its->vlpi_redist_offset;
635         its_encode_cmd(cmd, GITS_CMD_VMOVP);
636         its_encode_seq_num(cmd, desc->its_vmovp_cmd.seq_num);
637         its_encode_its_list(cmd, desc->its_vmovp_cmd.its_list);
638         its_encode_vpeid(cmd, desc->its_vmovp_cmd.vpe->vpe_id);
639         its_encode_target(cmd, target);
640
641         its_fixup_cmd(cmd);
642
643         return desc->its_vmovp_cmd.vpe;
644 }
645
646 static u64 its_cmd_ptr_to_offset(struct its_node *its,
647                                  struct its_cmd_block *ptr)
648 {
649         return (ptr - its->cmd_base) * sizeof(*ptr);
650 }
651
652 static int its_queue_full(struct its_node *its)
653 {
654         int widx;
655         int ridx;
656
657         widx = its->cmd_write - its->cmd_base;
658         ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block);
659
660         /* This is incredibly unlikely to happen, unless the ITS locks up. */
661         if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx)
662                 return 1;
663
664         return 0;
665 }
666
667 static struct its_cmd_block *its_allocate_entry(struct its_node *its)
668 {
669         struct its_cmd_block *cmd;
670         u32 count = 1000000;    /* 1s! */
671
672         while (its_queue_full(its)) {
673                 count--;
674                 if (!count) {
675                         pr_err_ratelimited("ITS queue not draining\n");
676                         return NULL;
677                 }
678                 cpu_relax();
679                 udelay(1);
680         }
681
682         cmd = its->cmd_write++;
683
684         /* Handle queue wrapping */
685         if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES))
686                 its->cmd_write = its->cmd_base;
687
688         /* Clear command  */
689         cmd->raw_cmd[0] = 0;
690         cmd->raw_cmd[1] = 0;
691         cmd->raw_cmd[2] = 0;
692         cmd->raw_cmd[3] = 0;
693
694         return cmd;
695 }
696
697 static struct its_cmd_block *its_post_commands(struct its_node *its)
698 {
699         u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write);
700
701         writel_relaxed(wr, its->base + GITS_CWRITER);
702
703         return its->cmd_write;
704 }
705
706 static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd)
707 {
708         /*
709          * Make sure the commands written to memory are observable by
710          * the ITS.
711          */
712         if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING)
713                 gic_flush_dcache_to_poc(cmd, sizeof(*cmd));
714         else
715                 dsb(ishst);
716 }
717
718 static int its_wait_for_range_completion(struct its_node *its,
719                                          struct its_cmd_block *from,
720                                          struct its_cmd_block *to)
721 {
722         u64 rd_idx, from_idx, to_idx;
723         u32 count = 1000000;    /* 1s! */
724
725         from_idx = its_cmd_ptr_to_offset(its, from);
726         to_idx = its_cmd_ptr_to_offset(its, to);
727
728         while (1) {
729                 rd_idx = readl_relaxed(its->base + GITS_CREADR);
730
731                 /* Direct case */
732                 if (from_idx < to_idx && rd_idx >= to_idx)
733                         break;
734
735                 /* Wrapped case */
736                 if (from_idx >= to_idx && rd_idx >= to_idx && rd_idx < from_idx)
737                         break;
738
739                 count--;
740                 if (!count) {
741                         pr_err_ratelimited("ITS queue timeout (%llu %llu %llu)\n",
742                                            from_idx, to_idx, rd_idx);
743                         return -1;
744                 }
745                 cpu_relax();
746                 udelay(1);
747         }
748
749         return 0;
750 }
751
752 /* Warning, macro hell follows */
753 #define BUILD_SINGLE_CMD_FUNC(name, buildtype, synctype, buildfn)       \
754 void name(struct its_node *its,                                         \
755           buildtype builder,                                            \
756           struct its_cmd_desc *desc)                                    \
757 {                                                                       \
758         struct its_cmd_block *cmd, *sync_cmd, *next_cmd;                \
759         synctype *sync_obj;                                             \
760         unsigned long flags;                                            \
761                                                                         \
762         raw_spin_lock_irqsave(&its->lock, flags);                       \
763                                                                         \
764         cmd = its_allocate_entry(its);                                  \
765         if (!cmd) {             /* We're soooooo screewed... */         \
766                 raw_spin_unlock_irqrestore(&its->lock, flags);          \
767                 return;                                                 \
768         }                                                               \
769         sync_obj = builder(its, cmd, desc);                             \
770         its_flush_cmd(its, cmd);                                        \
771                                                                         \
772         if (sync_obj) {                                                 \
773                 sync_cmd = its_allocate_entry(its);                     \
774                 if (!sync_cmd)                                          \
775                         goto post;                                      \
776                                                                         \
777                 buildfn(its, sync_cmd, sync_obj);                       \
778                 its_flush_cmd(its, sync_cmd);                           \
779         }                                                               \
780                                                                         \
781 post:                                                                   \
782         next_cmd = its_post_commands(its);                              \
783         raw_spin_unlock_irqrestore(&its->lock, flags);                  \
784                                                                         \
785         if (its_wait_for_range_completion(its, cmd, next_cmd))          \
786                 pr_err_ratelimited("ITS cmd %ps failed\n", builder);    \
787 }
788
789 static void its_build_sync_cmd(struct its_node *its,
790                                struct its_cmd_block *sync_cmd,
791                                struct its_collection *sync_col)
792 {
793         its_encode_cmd(sync_cmd, GITS_CMD_SYNC);
794         its_encode_target(sync_cmd, sync_col->target_address);
795
796         its_fixup_cmd(sync_cmd);
797 }
798
799 static BUILD_SINGLE_CMD_FUNC(its_send_single_command, its_cmd_builder_t,
800                              struct its_collection, its_build_sync_cmd)
801
802 static void its_build_vsync_cmd(struct its_node *its,
803                                 struct its_cmd_block *sync_cmd,
804                                 struct its_vpe *sync_vpe)
805 {
806         its_encode_cmd(sync_cmd, GITS_CMD_VSYNC);
807         its_encode_vpeid(sync_cmd, sync_vpe->vpe_id);
808
809         its_fixup_cmd(sync_cmd);
810 }
811
812 static BUILD_SINGLE_CMD_FUNC(its_send_single_vcommand, its_cmd_vbuilder_t,
813                              struct its_vpe, its_build_vsync_cmd)
814
815 static void its_send_int(struct its_device *dev, u32 event_id)
816 {
817         struct its_cmd_desc desc;
818
819         desc.its_int_cmd.dev = dev;
820         desc.its_int_cmd.event_id = event_id;
821
822         its_send_single_command(dev->its, its_build_int_cmd, &desc);
823 }
824
825 static void its_send_clear(struct its_device *dev, u32 event_id)
826 {
827         struct its_cmd_desc desc;
828
829         desc.its_clear_cmd.dev = dev;
830         desc.its_clear_cmd.event_id = event_id;
831
832         its_send_single_command(dev->its, its_build_clear_cmd, &desc);
833 }
834
835 static void its_send_inv(struct its_device *dev, u32 event_id)
836 {
837         struct its_cmd_desc desc;
838
839         desc.its_inv_cmd.dev = dev;
840         desc.its_inv_cmd.event_id = event_id;
841
842         its_send_single_command(dev->its, its_build_inv_cmd, &desc);
843 }
844
845 static void its_send_mapd(struct its_device *dev, int valid)
846 {
847         struct its_cmd_desc desc;
848
849         desc.its_mapd_cmd.dev = dev;
850         desc.its_mapd_cmd.valid = !!valid;
851
852         its_send_single_command(dev->its, its_build_mapd_cmd, &desc);
853 }
854
855 static void its_send_mapc(struct its_node *its, struct its_collection *col,
856                           int valid)
857 {
858         struct its_cmd_desc desc;
859
860         desc.its_mapc_cmd.col = col;
861         desc.its_mapc_cmd.valid = !!valid;
862
863         its_send_single_command(its, its_build_mapc_cmd, &desc);
864 }
865
866 static void its_send_mapti(struct its_device *dev, u32 irq_id, u32 id)
867 {
868         struct its_cmd_desc desc;
869
870         desc.its_mapti_cmd.dev = dev;
871         desc.its_mapti_cmd.phys_id = irq_id;
872         desc.its_mapti_cmd.event_id = id;
873
874         its_send_single_command(dev->its, its_build_mapti_cmd, &desc);
875 }
876
877 static void its_send_movi(struct its_device *dev,
878                           struct its_collection *col, u32 id)
879 {
880         struct its_cmd_desc desc;
881
882         desc.its_movi_cmd.dev = dev;
883         desc.its_movi_cmd.col = col;
884         desc.its_movi_cmd.event_id = id;
885
886         its_send_single_command(dev->its, its_build_movi_cmd, &desc);
887 }
888
889 static void its_send_discard(struct its_device *dev, u32 id)
890 {
891         struct its_cmd_desc desc;
892
893         desc.its_discard_cmd.dev = dev;
894         desc.its_discard_cmd.event_id = id;
895
896         its_send_single_command(dev->its, its_build_discard_cmd, &desc);
897 }
898
899 static void its_send_invall(struct its_node *its, struct its_collection *col)
900 {
901         struct its_cmd_desc desc;
902
903         desc.its_invall_cmd.col = col;
904
905         its_send_single_command(its, its_build_invall_cmd, &desc);
906 }
907
908 static void its_send_vmapti(struct its_device *dev, u32 id)
909 {
910         struct its_vlpi_map *map = &dev->event_map.vlpi_maps[id];
911         struct its_cmd_desc desc;
912
913         desc.its_vmapti_cmd.vpe = map->vpe;
914         desc.its_vmapti_cmd.dev = dev;
915         desc.its_vmapti_cmd.virt_id = map->vintid;
916         desc.its_vmapti_cmd.event_id = id;
917         desc.its_vmapti_cmd.db_enabled = map->db_enabled;
918
919         its_send_single_vcommand(dev->its, its_build_vmapti_cmd, &desc);
920 }
921
922 static void its_send_vmovi(struct its_device *dev, u32 id)
923 {
924         struct its_vlpi_map *map = &dev->event_map.vlpi_maps[id];
925         struct its_cmd_desc desc;
926
927         desc.its_vmovi_cmd.vpe = map->vpe;
928         desc.its_vmovi_cmd.dev = dev;
929         desc.its_vmovi_cmd.event_id = id;
930         desc.its_vmovi_cmd.db_enabled = map->db_enabled;
931
932         its_send_single_vcommand(dev->its, its_build_vmovi_cmd, &desc);
933 }
934
935 static void its_send_vmapp(struct its_node *its,
936                            struct its_vpe *vpe, bool valid)
937 {
938         struct its_cmd_desc desc;
939
940         desc.its_vmapp_cmd.vpe = vpe;
941         desc.its_vmapp_cmd.valid = valid;
942         desc.its_vmapp_cmd.col = &its->collections[vpe->col_idx];
943
944         its_send_single_vcommand(its, its_build_vmapp_cmd, &desc);
945 }
946
947 static void its_send_vmovp(struct its_vpe *vpe)
948 {
949         struct its_cmd_desc desc;
950         struct its_node *its;
951         unsigned long flags;
952         int col_id = vpe->col_idx;
953
954         desc.its_vmovp_cmd.vpe = vpe;
955         desc.its_vmovp_cmd.its_list = (u16)its_list_map;
956
957         if (!its_list_map) {
958                 its = list_first_entry(&its_nodes, struct its_node, entry);
959                 desc.its_vmovp_cmd.seq_num = 0;
960                 desc.its_vmovp_cmd.col = &its->collections[col_id];
961                 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
962                 return;
963         }
964
965         /*
966          * Yet another marvel of the architecture. If using the
967          * its_list "feature", we need to make sure that all ITSs
968          * receive all VMOVP commands in the same order. The only way
969          * to guarantee this is to make vmovp a serialization point.
970          *
971          * Wall <-- Head.
972          */
973         raw_spin_lock_irqsave(&vmovp_lock, flags);
974
975         desc.its_vmovp_cmd.seq_num = vmovp_seq_num++;
976
977         /* Emit VMOVPs */
978         list_for_each_entry(its, &its_nodes, entry) {
979                 if (!its->is_v4)
980                         continue;
981
982                 if (!vpe->its_vm->vlpi_count[its->list_nr])
983                         continue;
984
985                 desc.its_vmovp_cmd.col = &its->collections[col_id];
986                 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
987         }
988
989         raw_spin_unlock_irqrestore(&vmovp_lock, flags);
990 }
991
992 static void its_send_vinvall(struct its_node *its, struct its_vpe *vpe)
993 {
994         struct its_cmd_desc desc;
995
996         desc.its_vinvall_cmd.vpe = vpe;
997         its_send_single_vcommand(its, its_build_vinvall_cmd, &desc);
998 }
999
1000 /*
1001  * irqchip functions - assumes MSI, mostly.
1002  */
1003
1004 static inline u32 its_get_event_id(struct irq_data *d)
1005 {
1006         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1007         return d->hwirq - its_dev->event_map.lpi_base;
1008 }
1009
1010 static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)
1011 {
1012         irq_hw_number_t hwirq;
1013         struct page *prop_page;
1014         u8 *cfg;
1015
1016         if (irqd_is_forwarded_to_vcpu(d)) {
1017                 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1018                 u32 event = its_get_event_id(d);
1019                 struct its_vlpi_map *map;
1020
1021                 prop_page = its_dev->event_map.vm->vprop_page;
1022                 map = &its_dev->event_map.vlpi_maps[event];
1023                 hwirq = map->vintid;
1024
1025                 /* Remember the updated property */
1026                 map->properties &= ~clr;
1027                 map->properties |= set | LPI_PROP_GROUP1;
1028         } else {
1029                 prop_page = gic_rdists->prop_page;
1030                 hwirq = d->hwirq;
1031         }
1032
1033         cfg = page_address(prop_page) + hwirq - 8192;
1034         *cfg &= ~clr;
1035         *cfg |= set | LPI_PROP_GROUP1;
1036
1037         /*
1038          * Make the above write visible to the redistributors.
1039          * And yes, we're flushing exactly: One. Single. Byte.
1040          * Humpf...
1041          */
1042         if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
1043                 gic_flush_dcache_to_poc(cfg, sizeof(*cfg));
1044         else
1045                 dsb(ishst);
1046 }
1047
1048 static void lpi_update_config(struct irq_data *d, u8 clr, u8 set)
1049 {
1050         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1051
1052         lpi_write_config(d, clr, set);
1053         its_send_inv(its_dev, its_get_event_id(d));
1054 }
1055
1056 static void its_vlpi_set_doorbell(struct irq_data *d, bool enable)
1057 {
1058         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1059         u32 event = its_get_event_id(d);
1060
1061         if (its_dev->event_map.vlpi_maps[event].db_enabled == enable)
1062                 return;
1063
1064         its_dev->event_map.vlpi_maps[event].db_enabled = enable;
1065
1066         /*
1067          * More fun with the architecture:
1068          *
1069          * Ideally, we'd issue a VMAPTI to set the doorbell to its LPI
1070          * value or to 1023, depending on the enable bit. But that
1071          * would be issueing a mapping for an /existing/ DevID+EventID
1072          * pair, which is UNPREDICTABLE. Instead, let's issue a VMOVI
1073          * to the /same/ vPE, using this opportunity to adjust the
1074          * doorbell. Mouahahahaha. We loves it, Precious.
1075          */
1076         its_send_vmovi(its_dev, event);
1077 }
1078
1079 static void its_mask_irq(struct irq_data *d)
1080 {
1081         if (irqd_is_forwarded_to_vcpu(d))
1082                 its_vlpi_set_doorbell(d, false);
1083
1084         lpi_update_config(d, LPI_PROP_ENABLED, 0);
1085 }
1086
1087 static void its_unmask_irq(struct irq_data *d)
1088 {
1089         if (irqd_is_forwarded_to_vcpu(d))
1090                 its_vlpi_set_doorbell(d, true);
1091
1092         lpi_update_config(d, 0, LPI_PROP_ENABLED);
1093 }
1094
1095 static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
1096                             bool force)
1097 {
1098         unsigned int cpu;
1099         const struct cpumask *cpu_mask = cpu_online_mask;
1100         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1101         struct its_collection *target_col;
1102         u32 id = its_get_event_id(d);
1103
1104         /* A forwarded interrupt should use irq_set_vcpu_affinity */
1105         if (irqd_is_forwarded_to_vcpu(d))
1106                 return -EINVAL;
1107
1108        /* lpi cannot be routed to a redistributor that is on a foreign node */
1109         if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
1110                 if (its_dev->its->numa_node >= 0) {
1111                         cpu_mask = cpumask_of_node(its_dev->its->numa_node);
1112                         if (!cpumask_intersects(mask_val, cpu_mask))
1113                                 return -EINVAL;
1114                 }
1115         }
1116
1117         cpu = cpumask_any_and(mask_val, cpu_mask);
1118
1119         if (cpu >= nr_cpu_ids)
1120                 return -EINVAL;
1121
1122         /* don't set the affinity when the target cpu is same as current one */
1123         if (cpu != its_dev->event_map.col_map[id]) {
1124                 target_col = &its_dev->its->collections[cpu];
1125                 its_send_movi(its_dev, target_col, id);
1126                 its_dev->event_map.col_map[id] = cpu;
1127                 irq_data_update_effective_affinity(d, cpumask_of(cpu));
1128         }
1129
1130         return IRQ_SET_MASK_OK_DONE;
1131 }
1132
1133 static u64 its_irq_get_msi_base(struct its_device *its_dev)
1134 {
1135         struct its_node *its = its_dev->its;
1136
1137         return its->phys_base + GITS_TRANSLATER;
1138 }
1139
1140 static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
1141 {
1142         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1143         struct its_node *its;
1144         u64 addr;
1145
1146         its = its_dev->its;
1147         addr = its->get_msi_base(its_dev);
1148
1149         msg->address_lo         = lower_32_bits(addr);
1150         msg->address_hi         = upper_32_bits(addr);
1151         msg->data               = its_get_event_id(d);
1152
1153         iommu_dma_map_msi_msg(d->irq, msg);
1154 }
1155
1156 static int its_irq_set_irqchip_state(struct irq_data *d,
1157                                      enum irqchip_irq_state which,
1158                                      bool state)
1159 {
1160         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1161         u32 event = its_get_event_id(d);
1162
1163         if (which != IRQCHIP_STATE_PENDING)
1164                 return -EINVAL;
1165
1166         if (state)
1167                 its_send_int(its_dev, event);
1168         else
1169                 its_send_clear(its_dev, event);
1170
1171         return 0;
1172 }
1173
1174 static void its_map_vm(struct its_node *its, struct its_vm *vm)
1175 {
1176         unsigned long flags;
1177
1178         /* Not using the ITS list? Everything is always mapped. */
1179         if (!its_list_map)
1180                 return;
1181
1182         raw_spin_lock_irqsave(&vmovp_lock, flags);
1183
1184         /*
1185          * If the VM wasn't mapped yet, iterate over the vpes and get
1186          * them mapped now.
1187          */
1188         vm->vlpi_count[its->list_nr]++;
1189
1190         if (vm->vlpi_count[its->list_nr] == 1) {
1191                 int i;
1192
1193                 for (i = 0; i < vm->nr_vpes; i++) {
1194                         struct its_vpe *vpe = vm->vpes[i];
1195                         struct irq_data *d = irq_get_irq_data(vpe->irq);
1196
1197                         /* Map the VPE to the first possible CPU */
1198                         vpe->col_idx = cpumask_first(cpu_online_mask);
1199                         its_send_vmapp(its, vpe, true);
1200                         its_send_vinvall(its, vpe);
1201                         irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
1202                 }
1203         }
1204
1205         raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1206 }
1207
1208 static void its_unmap_vm(struct its_node *its, struct its_vm *vm)
1209 {
1210         unsigned long flags;
1211
1212         /* Not using the ITS list? Everything is always mapped. */
1213         if (!its_list_map)
1214                 return;
1215
1216         raw_spin_lock_irqsave(&vmovp_lock, flags);
1217
1218         if (!--vm->vlpi_count[its->list_nr]) {
1219                 int i;
1220
1221                 for (i = 0; i < vm->nr_vpes; i++)
1222                         its_send_vmapp(its, vm->vpes[i], false);
1223         }
1224
1225         raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1226 }
1227
1228 static int its_vlpi_map(struct irq_data *d, struct its_cmd_info *info)
1229 {
1230         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1231         u32 event = its_get_event_id(d);
1232         int ret = 0;
1233
1234         if (!info->map)
1235                 return -EINVAL;
1236
1237         mutex_lock(&its_dev->event_map.vlpi_lock);
1238
1239         if (!its_dev->event_map.vm) {
1240                 struct its_vlpi_map *maps;
1241
1242                 maps = kzalloc(sizeof(*maps) * its_dev->event_map.nr_lpis,
1243                                GFP_KERNEL);
1244                 if (!maps) {
1245                         ret = -ENOMEM;
1246                         goto out;
1247                 }
1248
1249                 its_dev->event_map.vm = info->map->vm;
1250                 its_dev->event_map.vlpi_maps = maps;
1251         } else if (its_dev->event_map.vm != info->map->vm) {
1252                 ret = -EINVAL;
1253                 goto out;
1254         }
1255
1256         /* Get our private copy of the mapping information */
1257         its_dev->event_map.vlpi_maps[event] = *info->map;
1258
1259         if (irqd_is_forwarded_to_vcpu(d)) {
1260                 /* Already mapped, move it around */
1261                 its_send_vmovi(its_dev, event);
1262         } else {
1263                 /* Ensure all the VPEs are mapped on this ITS */
1264                 its_map_vm(its_dev->its, info->map->vm);
1265
1266                 /*
1267                  * Flag the interrupt as forwarded so that we can
1268                  * start poking the virtual property table.
1269                  */
1270                 irqd_set_forwarded_to_vcpu(d);
1271
1272                 /* Write out the property to the prop table */
1273                 lpi_write_config(d, 0xff, info->map->properties);
1274
1275                 /* Drop the physical mapping */
1276                 its_send_discard(its_dev, event);
1277
1278                 /* and install the virtual one */
1279                 its_send_vmapti(its_dev, event);
1280
1281                 /* Increment the number of VLPIs */
1282                 its_dev->event_map.nr_vlpis++;
1283         }
1284
1285 out:
1286         mutex_unlock(&its_dev->event_map.vlpi_lock);
1287         return ret;
1288 }
1289
1290 static int its_vlpi_get(struct irq_data *d, struct its_cmd_info *info)
1291 {
1292         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1293         u32 event = its_get_event_id(d);
1294         int ret = 0;
1295
1296         mutex_lock(&its_dev->event_map.vlpi_lock);
1297
1298         if (!its_dev->event_map.vm ||
1299             !its_dev->event_map.vlpi_maps[event].vm) {
1300                 ret = -EINVAL;
1301                 goto out;
1302         }
1303
1304         /* Copy our mapping information to the incoming request */
1305         *info->map = its_dev->event_map.vlpi_maps[event];
1306
1307 out:
1308         mutex_unlock(&its_dev->event_map.vlpi_lock);
1309         return ret;
1310 }
1311
1312 static int its_vlpi_unmap(struct irq_data *d)
1313 {
1314         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1315         u32 event = its_get_event_id(d);
1316         int ret = 0;
1317
1318         mutex_lock(&its_dev->event_map.vlpi_lock);
1319
1320         if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) {
1321                 ret = -EINVAL;
1322                 goto out;
1323         }
1324
1325         /* Drop the virtual mapping */
1326         its_send_discard(its_dev, event);
1327
1328         /* and restore the physical one */
1329         irqd_clr_forwarded_to_vcpu(d);
1330         its_send_mapti(its_dev, d->hwirq, event);
1331         lpi_update_config(d, 0xff, (LPI_PROP_DEFAULT_PRIO |
1332                                     LPI_PROP_ENABLED |
1333                                     LPI_PROP_GROUP1));
1334
1335         /* Potentially unmap the VM from this ITS */
1336         its_unmap_vm(its_dev->its, its_dev->event_map.vm);
1337
1338         /*
1339          * Drop the refcount and make the device available again if
1340          * this was the last VLPI.
1341          */
1342         if (!--its_dev->event_map.nr_vlpis) {
1343                 its_dev->event_map.vm = NULL;
1344                 kfree(its_dev->event_map.vlpi_maps);
1345         }
1346
1347 out:
1348         mutex_unlock(&its_dev->event_map.vlpi_lock);
1349         return ret;
1350 }
1351
1352 static int its_vlpi_prop_update(struct irq_data *d, struct its_cmd_info *info)
1353 {
1354         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1355
1356         if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d))
1357                 return -EINVAL;
1358
1359         if (info->cmd_type == PROP_UPDATE_AND_INV_VLPI)
1360                 lpi_update_config(d, 0xff, info->config);
1361         else
1362                 lpi_write_config(d, 0xff, info->config);
1363         its_vlpi_set_doorbell(d, !!(info->config & LPI_PROP_ENABLED));
1364
1365         return 0;
1366 }
1367
1368 static int its_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
1369 {
1370         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1371         struct its_cmd_info *info = vcpu_info;
1372
1373         /* Need a v4 ITS */
1374         if (!its_dev->its->is_v4)
1375                 return -EINVAL;
1376
1377         /* Unmap request? */
1378         if (!info)
1379                 return its_vlpi_unmap(d);
1380
1381         switch (info->cmd_type) {
1382         case MAP_VLPI:
1383                 return its_vlpi_map(d, info);
1384
1385         case GET_VLPI:
1386                 return its_vlpi_get(d, info);
1387
1388         case PROP_UPDATE_VLPI:
1389         case PROP_UPDATE_AND_INV_VLPI:
1390                 return its_vlpi_prop_update(d, info);
1391
1392         default:
1393                 return -EINVAL;
1394         }
1395 }
1396
1397 static struct irq_chip its_irq_chip = {
1398         .name                   = "ITS",
1399         .irq_mask               = its_mask_irq,
1400         .irq_unmask             = its_unmask_irq,
1401         .irq_eoi                = irq_chip_eoi_parent,
1402         .irq_set_affinity       = its_set_affinity,
1403         .irq_compose_msi_msg    = its_irq_compose_msi_msg,
1404         .irq_set_irqchip_state  = its_irq_set_irqchip_state,
1405         .irq_set_vcpu_affinity  = its_irq_set_vcpu_affinity,
1406 };
1407
1408 /*
1409  * How we allocate LPIs:
1410  *
1411  * The GIC has id_bits bits for interrupt identifiers. From there, we
1412  * must subtract 8192 which are reserved for SGIs/PPIs/SPIs. Then, as
1413  * we allocate LPIs by chunks of 32, we can shift the whole thing by 5
1414  * bits to the right.
1415  *
1416  * This gives us (((1UL << id_bits) - 8192) >> 5) possible allocations.
1417  */
1418 #define IRQS_PER_CHUNK_SHIFT    5
1419 #define IRQS_PER_CHUNK          (1UL << IRQS_PER_CHUNK_SHIFT)
1420 #define ITS_MAX_LPI_NRBITS      16 /* 64K LPIs */
1421
1422 static unsigned long *lpi_bitmap;
1423 static u32 lpi_chunks;
1424 static DEFINE_SPINLOCK(lpi_lock);
1425
1426 static int its_lpi_to_chunk(int lpi)
1427 {
1428         return (lpi - 8192) >> IRQS_PER_CHUNK_SHIFT;
1429 }
1430
1431 static int its_chunk_to_lpi(int chunk)
1432 {
1433         return (chunk << IRQS_PER_CHUNK_SHIFT) + 8192;
1434 }
1435
1436 static int __init its_lpi_init(u32 id_bits)
1437 {
1438         lpi_chunks = its_lpi_to_chunk(1UL << id_bits);
1439
1440         lpi_bitmap = kzalloc(BITS_TO_LONGS(lpi_chunks) * sizeof(long),
1441                              GFP_KERNEL);
1442         if (!lpi_bitmap) {
1443                 lpi_chunks = 0;
1444                 return -ENOMEM;
1445         }
1446
1447         pr_info("ITS: Allocated %d chunks for LPIs\n", (int)lpi_chunks);
1448         return 0;
1449 }
1450
1451 static unsigned long *its_lpi_alloc_chunks(int nr_irqs, int *base, int *nr_ids)
1452 {
1453         unsigned long *bitmap = NULL;
1454         int chunk_id;
1455         int nr_chunks;
1456         int i;
1457
1458         nr_chunks = DIV_ROUND_UP(nr_irqs, IRQS_PER_CHUNK);
1459
1460         spin_lock(&lpi_lock);
1461
1462         do {
1463                 chunk_id = bitmap_find_next_zero_area(lpi_bitmap, lpi_chunks,
1464                                                       0, nr_chunks, 0);
1465                 if (chunk_id < lpi_chunks)
1466                         break;
1467
1468                 nr_chunks--;
1469         } while (nr_chunks > 0);
1470
1471         if (!nr_chunks)
1472                 goto out;
1473
1474         bitmap = kzalloc(BITS_TO_LONGS(nr_chunks * IRQS_PER_CHUNK) * sizeof (long),
1475                          GFP_ATOMIC);
1476         if (!bitmap)
1477                 goto out;
1478
1479         for (i = 0; i < nr_chunks; i++)
1480                 set_bit(chunk_id + i, lpi_bitmap);
1481
1482         *base = its_chunk_to_lpi(chunk_id);
1483         *nr_ids = nr_chunks * IRQS_PER_CHUNK;
1484
1485 out:
1486         spin_unlock(&lpi_lock);
1487
1488         if (!bitmap)
1489                 *base = *nr_ids = 0;
1490
1491         return bitmap;
1492 }
1493
1494 static void its_lpi_free_chunks(unsigned long *bitmap, int base, int nr_ids)
1495 {
1496         int lpi;
1497
1498         spin_lock(&lpi_lock);
1499
1500         for (lpi = base; lpi < (base + nr_ids); lpi += IRQS_PER_CHUNK) {
1501                 int chunk = its_lpi_to_chunk(lpi);
1502
1503                 BUG_ON(chunk > lpi_chunks);
1504                 if (test_bit(chunk, lpi_bitmap)) {
1505                         clear_bit(chunk, lpi_bitmap);
1506                 } else {
1507                         pr_err("Bad LPI chunk %d\n", chunk);
1508                 }
1509         }
1510
1511         spin_unlock(&lpi_lock);
1512
1513         kfree(bitmap);
1514 }
1515
1516 static struct page *its_allocate_prop_table(gfp_t gfp_flags)
1517 {
1518         struct page *prop_page;
1519
1520         prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
1521         if (!prop_page)
1522                 return NULL;
1523
1524         /* Priority 0xa0, Group-1, disabled */
1525         memset(page_address(prop_page),
1526                LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1,
1527                LPI_PROPBASE_SZ);
1528
1529         /* Make sure the GIC will observe the written configuration */
1530         gic_flush_dcache_to_poc(page_address(prop_page), LPI_PROPBASE_SZ);
1531
1532         return prop_page;
1533 }
1534
1535 static void its_free_prop_table(struct page *prop_page)
1536 {
1537         free_pages((unsigned long)page_address(prop_page),
1538                    get_order(LPI_PROPBASE_SZ));
1539 }
1540
1541 static int __init its_alloc_lpi_tables(void)
1542 {
1543         phys_addr_t paddr;
1544
1545         lpi_id_bits = min_t(u32, gic_rdists->id_bits, ITS_MAX_LPI_NRBITS);
1546         gic_rdists->prop_page = its_allocate_prop_table(GFP_NOWAIT);
1547         if (!gic_rdists->prop_page) {
1548                 pr_err("Failed to allocate PROPBASE\n");
1549                 return -ENOMEM;
1550         }
1551
1552         paddr = page_to_phys(gic_rdists->prop_page);
1553         pr_info("GIC: using LPI property table @%pa\n", &paddr);
1554
1555         return its_lpi_init(lpi_id_bits);
1556 }
1557
1558 static const char *its_base_type_string[] = {
1559         [GITS_BASER_TYPE_DEVICE]        = "Devices",
1560         [GITS_BASER_TYPE_VCPU]          = "Virtual CPUs",
1561         [GITS_BASER_TYPE_RESERVED3]     = "Reserved (3)",
1562         [GITS_BASER_TYPE_COLLECTION]    = "Interrupt Collections",
1563         [GITS_BASER_TYPE_RESERVED5]     = "Reserved (5)",
1564         [GITS_BASER_TYPE_RESERVED6]     = "Reserved (6)",
1565         [GITS_BASER_TYPE_RESERVED7]     = "Reserved (7)",
1566 };
1567
1568 static u64 its_read_baser(struct its_node *its, struct its_baser *baser)
1569 {
1570         u32 idx = baser - its->tables;
1571
1572         return gits_read_baser(its->base + GITS_BASER + (idx << 3));
1573 }
1574
1575 static void its_write_baser(struct its_node *its, struct its_baser *baser,
1576                             u64 val)
1577 {
1578         u32 idx = baser - its->tables;
1579
1580         gits_write_baser(val, its->base + GITS_BASER + (idx << 3));
1581         baser->val = its_read_baser(its, baser);
1582 }
1583
1584 static int its_setup_baser(struct its_node *its, struct its_baser *baser,
1585                            u64 cache, u64 shr, u32 psz, u32 order,
1586                            bool indirect)
1587 {
1588         u64 val = its_read_baser(its, baser);
1589         u64 esz = GITS_BASER_ENTRY_SIZE(val);
1590         u64 type = GITS_BASER_TYPE(val);
1591         u64 baser_phys, tmp;
1592         u32 alloc_pages;
1593         void *base;
1594
1595 retry_alloc_baser:
1596         alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
1597         if (alloc_pages > GITS_BASER_PAGES_MAX) {
1598                 pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n",
1599                         &its->phys_base, its_base_type_string[type],
1600                         alloc_pages, GITS_BASER_PAGES_MAX);
1601                 alloc_pages = GITS_BASER_PAGES_MAX;
1602                 order = get_order(GITS_BASER_PAGES_MAX * psz);
1603         }
1604
1605         base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
1606         if (!base)
1607                 return -ENOMEM;
1608
1609         baser_phys = virt_to_phys(base);
1610
1611         /* Check if the physical address of the memory is above 48bits */
1612         if (IS_ENABLED(CONFIG_ARM64_64K_PAGES) && (baser_phys >> 48)) {
1613
1614                 /* 52bit PA is supported only when PageSize=64K */
1615                 if (psz != SZ_64K) {
1616                         pr_err("ITS: no 52bit PA support when psz=%d\n", psz);
1617                         free_pages((unsigned long)base, order);
1618                         return -ENXIO;
1619                 }
1620
1621                 /* Convert 52bit PA to 48bit field */
1622                 baser_phys = GITS_BASER_PHYS_52_to_48(baser_phys);
1623         }
1624
1625 retry_baser:
1626         val = (baser_phys                                        |
1627                 (type << GITS_BASER_TYPE_SHIFT)                  |
1628                 ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT)       |
1629                 ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT)    |
1630                 cache                                            |
1631                 shr                                              |
1632                 GITS_BASER_VALID);
1633
1634         val |=  indirect ? GITS_BASER_INDIRECT : 0x0;
1635
1636         switch (psz) {
1637         case SZ_4K:
1638                 val |= GITS_BASER_PAGE_SIZE_4K;
1639                 break;
1640         case SZ_16K:
1641                 val |= GITS_BASER_PAGE_SIZE_16K;
1642                 break;
1643         case SZ_64K:
1644                 val |= GITS_BASER_PAGE_SIZE_64K;
1645                 break;
1646         }
1647
1648         its_write_baser(its, baser, val);
1649         tmp = baser->val;
1650
1651         if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
1652                 /*
1653                  * Shareability didn't stick. Just use
1654                  * whatever the read reported, which is likely
1655                  * to be the only thing this redistributor
1656                  * supports. If that's zero, make it
1657                  * non-cacheable as well.
1658                  */
1659                 shr = tmp & GITS_BASER_SHAREABILITY_MASK;
1660                 if (!shr) {
1661                         cache = GITS_BASER_nC;
1662                         gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
1663                 }
1664                 goto retry_baser;
1665         }
1666
1667         if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) {
1668                 /*
1669                  * Page size didn't stick. Let's try a smaller
1670                  * size and retry. If we reach 4K, then
1671                  * something is horribly wrong...
1672                  */
1673                 free_pages((unsigned long)base, order);
1674                 baser->base = NULL;
1675
1676                 switch (psz) {
1677                 case SZ_16K:
1678                         psz = SZ_4K;
1679                         goto retry_alloc_baser;
1680                 case SZ_64K:
1681                         psz = SZ_16K;
1682                         goto retry_alloc_baser;
1683                 }
1684         }
1685
1686         if (val != tmp) {
1687                 pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n",
1688                        &its->phys_base, its_base_type_string[type],
1689                        val, tmp);
1690                 free_pages((unsigned long)base, order);
1691                 return -ENXIO;
1692         }
1693
1694         baser->order = order;
1695         baser->base = base;
1696         baser->psz = psz;
1697         tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz;
1698
1699         pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n",
1700                 &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp),
1701                 its_base_type_string[type],
1702                 (unsigned long)virt_to_phys(base),
1703                 indirect ? "indirect" : "flat", (int)esz,
1704                 psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);
1705
1706         return 0;
1707 }
1708
1709 static bool its_parse_indirect_baser(struct its_node *its,
1710                                      struct its_baser *baser,
1711                                      u32 psz, u32 *order, u32 ids)
1712 {
1713         u64 tmp = its_read_baser(its, baser);
1714         u64 type = GITS_BASER_TYPE(tmp);
1715         u64 esz = GITS_BASER_ENTRY_SIZE(tmp);
1716         u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb;
1717         u32 new_order = *order;
1718         bool indirect = false;
1719
1720         /* No need to enable Indirection if memory requirement < (psz*2)bytes */
1721         if ((esz << ids) > (psz * 2)) {
1722                 /*
1723                  * Find out whether hw supports a single or two-level table by
1724                  * table by reading bit at offset '62' after writing '1' to it.
1725                  */
1726                 its_write_baser(its, baser, val | GITS_BASER_INDIRECT);
1727                 indirect = !!(baser->val & GITS_BASER_INDIRECT);
1728
1729                 if (indirect) {
1730                         /*
1731                          * The size of the lvl2 table is equal to ITS page size
1732                          * which is 'psz'. For computing lvl1 table size,
1733                          * subtract ID bits that sparse lvl2 table from 'ids'
1734                          * which is reported by ITS hardware times lvl1 table
1735                          * entry size.
1736                          */
1737                         ids -= ilog2(psz / (int)esz);
1738                         esz = GITS_LVL1_ENTRY_SIZE;
1739                 }
1740         }
1741
1742         /*
1743          * Allocate as many entries as required to fit the
1744          * range of device IDs that the ITS can grok... The ID
1745          * space being incredibly sparse, this results in a
1746          * massive waste of memory if two-level device table
1747          * feature is not supported by hardware.
1748          */
1749         new_order = max_t(u32, get_order(esz << ids), new_order);
1750         if (new_order >= MAX_ORDER) {
1751                 new_order = MAX_ORDER - 1;
1752                 ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz);
1753                 pr_warn("ITS@%pa: %s Table too large, reduce ids %u->%u\n",
1754                         &its->phys_base, its_base_type_string[type],
1755                         its->device_ids, ids);
1756         }
1757
1758         *order = new_order;
1759
1760         return indirect;
1761 }
1762
1763 static void its_free_tables(struct its_node *its)
1764 {
1765         int i;
1766
1767         for (i = 0; i < GITS_BASER_NR_REGS; i++) {
1768                 if (its->tables[i].base) {
1769                         free_pages((unsigned long)its->tables[i].base,
1770                                    its->tables[i].order);
1771                         its->tables[i].base = NULL;
1772                 }
1773         }
1774 }
1775
1776 static int its_alloc_tables(struct its_node *its)
1777 {
1778         u64 shr = GITS_BASER_InnerShareable;
1779         u64 cache = GITS_BASER_RaWaWb;
1780         u32 psz = SZ_64K;
1781         int err, i;
1782
1783         if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375)
1784                 /* erratum 24313: ignore memory access type */
1785                 cache = GITS_BASER_nCnB;
1786
1787         for (i = 0; i < GITS_BASER_NR_REGS; i++) {
1788                 struct its_baser *baser = its->tables + i;
1789                 u64 val = its_read_baser(its, baser);
1790                 u64 type = GITS_BASER_TYPE(val);
1791                 u32 order = get_order(psz);
1792                 bool indirect = false;
1793
1794                 switch (type) {
1795                 case GITS_BASER_TYPE_NONE:
1796                         continue;
1797
1798                 case GITS_BASER_TYPE_DEVICE:
1799                         indirect = its_parse_indirect_baser(its, baser,
1800                                                             psz, &order,
1801                                                             its->device_ids);
1802                 case GITS_BASER_TYPE_VCPU:
1803                         indirect = its_parse_indirect_baser(its, baser,
1804                                                             psz, &order,
1805                                                             ITS_MAX_VPEID_BITS);
1806                         break;
1807                 }
1808
1809                 err = its_setup_baser(its, baser, cache, shr, psz, order, indirect);
1810                 if (err < 0) {
1811                         its_free_tables(its);
1812                         return err;
1813                 }
1814
1815                 /* Update settings which will be used for next BASERn */
1816                 psz = baser->psz;
1817                 cache = baser->val & GITS_BASER_CACHEABILITY_MASK;
1818                 shr = baser->val & GITS_BASER_SHAREABILITY_MASK;
1819         }
1820
1821         return 0;
1822 }
1823
1824 static int its_alloc_collections(struct its_node *its)
1825 {
1826         its->collections = kzalloc(nr_cpu_ids * sizeof(*its->collections),
1827                                    GFP_KERNEL);
1828         if (!its->collections)
1829                 return -ENOMEM;
1830
1831         return 0;
1832 }
1833
1834 static struct page *its_allocate_pending_table(gfp_t gfp_flags)
1835 {
1836         struct page *pend_page;
1837         /*
1838          * The pending pages have to be at least 64kB aligned,
1839          * hence the 'max(LPI_PENDBASE_SZ, SZ_64K)' below.
1840          */
1841         pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
1842                                 get_order(max_t(u32, LPI_PENDBASE_SZ, SZ_64K)));
1843         if (!pend_page)
1844                 return NULL;
1845
1846         /* Make sure the GIC will observe the zero-ed page */
1847         gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ);
1848
1849         return pend_page;
1850 }
1851
1852 static void its_free_pending_table(struct page *pt)
1853 {
1854         free_pages((unsigned long)page_address(pt),
1855                    get_order(max_t(u32, LPI_PENDBASE_SZ, SZ_64K)));
1856 }
1857
1858 static void its_cpu_init_lpis(void)
1859 {
1860         void __iomem *rbase = gic_data_rdist_rd_base();
1861         struct page *pend_page;
1862         u64 val, tmp;
1863
1864         /* If we didn't allocate the pending table yet, do it now */
1865         pend_page = gic_data_rdist()->pend_page;
1866         if (!pend_page) {
1867                 phys_addr_t paddr;
1868
1869                 pend_page = its_allocate_pending_table(GFP_NOWAIT);
1870                 if (!pend_page) {
1871                         pr_err("Failed to allocate PENDBASE for CPU%d\n",
1872                                smp_processor_id());
1873                         return;
1874                 }
1875
1876                 paddr = page_to_phys(pend_page);
1877                 pr_info("CPU%d: using LPI pending table @%pa\n",
1878                         smp_processor_id(), &paddr);
1879                 gic_data_rdist()->pend_page = pend_page;
1880         }
1881
1882         /* set PROPBASE */
1883         val = (page_to_phys(gic_rdists->prop_page) |
1884                GICR_PROPBASER_InnerShareable |
1885                GICR_PROPBASER_RaWaWb |
1886                ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
1887
1888         gicr_write_propbaser(val, rbase + GICR_PROPBASER);
1889         tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
1890
1891         if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
1892                 if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
1893                         /*
1894                          * The HW reports non-shareable, we must
1895                          * remove the cacheability attributes as
1896                          * well.
1897                          */
1898                         val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
1899                                  GICR_PROPBASER_CACHEABILITY_MASK);
1900                         val |= GICR_PROPBASER_nC;
1901                         gicr_write_propbaser(val, rbase + GICR_PROPBASER);
1902                 }
1903                 pr_info_once("GIC: using cache flushing for LPI property table\n");
1904                 gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
1905         }
1906
1907         /* set PENDBASE */
1908         val = (page_to_phys(pend_page) |
1909                GICR_PENDBASER_InnerShareable |
1910                GICR_PENDBASER_RaWaWb);
1911
1912         gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
1913         tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
1914
1915         if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
1916                 /*
1917                  * The HW reports non-shareable, we must remove the
1918                  * cacheability attributes as well.
1919                  */
1920                 val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
1921                          GICR_PENDBASER_CACHEABILITY_MASK);
1922                 val |= GICR_PENDBASER_nC;
1923                 gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
1924         }
1925
1926         /* Enable LPIs */
1927         val = readl_relaxed(rbase + GICR_CTLR);
1928         val |= GICR_CTLR_ENABLE_LPIS;
1929         writel_relaxed(val, rbase + GICR_CTLR);
1930
1931         /* Make sure the GIC has seen the above */
1932         dsb(sy);
1933 }
1934
1935 static void its_cpu_init_collection(struct its_node *its)
1936 {
1937         int cpu = smp_processor_id();
1938         u64 target;
1939
1940         /* avoid cross node collections and its mapping */
1941         if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
1942                 struct device_node *cpu_node;
1943
1944                 cpu_node = of_get_cpu_node(cpu, NULL);
1945                 if (its->numa_node != NUMA_NO_NODE &&
1946                         its->numa_node != of_node_to_nid(cpu_node))
1947                         return;
1948         }
1949
1950         /*
1951          * We now have to bind each collection to its target
1952          * redistributor.
1953          */
1954         if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
1955                 /*
1956                  * This ITS wants the physical address of the
1957                  * redistributor.
1958                  */
1959                 target = gic_data_rdist()->phys_base;
1960         } else {
1961                 /* This ITS wants a linear CPU number. */
1962                 target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
1963                 target = GICR_TYPER_CPU_NUMBER(target) << 16;
1964         }
1965
1966         /* Perform collection mapping */
1967         its->collections[cpu].target_address = target;
1968         its->collections[cpu].col_id = cpu;
1969
1970         its_send_mapc(its, &its->collections[cpu], 1);
1971         its_send_invall(its, &its->collections[cpu]);
1972 }
1973
1974 static void its_cpu_init_collections(void)
1975 {
1976         struct its_node *its;
1977
1978         spin_lock(&its_lock);
1979
1980         list_for_each_entry(its, &its_nodes, entry)
1981                 its_cpu_init_collection(its);
1982
1983         spin_unlock(&its_lock);
1984 }
1985
1986 static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
1987 {
1988         struct its_device *its_dev = NULL, *tmp;
1989         unsigned long flags;
1990
1991         raw_spin_lock_irqsave(&its->lock, flags);
1992
1993         list_for_each_entry(tmp, &its->its_device_list, entry) {
1994                 if (tmp->device_id == dev_id) {
1995                         its_dev = tmp;
1996                         break;
1997                 }
1998         }
1999
2000         raw_spin_unlock_irqrestore(&its->lock, flags);
2001
2002         return its_dev;
2003 }
2004
2005 static struct its_baser *its_get_baser(struct its_node *its, u32 type)
2006 {
2007         int i;
2008
2009         for (i = 0; i < GITS_BASER_NR_REGS; i++) {
2010                 if (GITS_BASER_TYPE(its->tables[i].val) == type)
2011                         return &its->tables[i];
2012         }
2013
2014         return NULL;
2015 }
2016
2017 static bool its_alloc_table_entry(struct its_baser *baser, u32 id)
2018 {
2019         struct page *page;
2020         u32 esz, idx;
2021         __le64 *table;
2022
2023         /* Don't allow device id that exceeds single, flat table limit */
2024         esz = GITS_BASER_ENTRY_SIZE(baser->val);
2025         if (!(baser->val & GITS_BASER_INDIRECT))
2026                 return (id < (PAGE_ORDER_TO_SIZE(baser->order) / esz));
2027
2028         /* Compute 1st level table index & check if that exceeds table limit */
2029         idx = id >> ilog2(baser->psz / esz);
2030         if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE))
2031                 return false;
2032
2033         table = baser->base;
2034
2035         /* Allocate memory for 2nd level table */
2036         if (!table[idx]) {
2037                 page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(baser->psz));
2038                 if (!page)
2039                         return false;
2040
2041                 /* Flush Lvl2 table to PoC if hw doesn't support coherency */
2042                 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
2043                         gic_flush_dcache_to_poc(page_address(page), baser->psz);
2044
2045                 table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID);
2046
2047                 /* Flush Lvl1 entry to PoC if hw doesn't support coherency */
2048                 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
2049                         gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE);
2050
2051                 /* Ensure updated table contents are visible to ITS hardware */
2052                 dsb(sy);
2053         }
2054
2055         return true;
2056 }
2057
2058 static bool its_alloc_device_table(struct its_node *its, u32 dev_id)
2059 {
2060         struct its_baser *baser;
2061
2062         baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE);
2063
2064         /* Don't allow device id that exceeds ITS hardware limit */
2065         if (!baser)
2066                 return (ilog2(dev_id) < its->device_ids);
2067
2068         return its_alloc_table_entry(baser, dev_id);
2069 }
2070
2071 static bool its_alloc_vpe_table(u32 vpe_id)
2072 {
2073         struct its_node *its;
2074
2075         /*
2076          * Make sure the L2 tables are allocated on *all* v4 ITSs. We
2077          * could try and only do it on ITSs corresponding to devices
2078          * that have interrupts targeted at this VPE, but the
2079          * complexity becomes crazy (and you have tons of memory
2080          * anyway, right?).
2081          */
2082         list_for_each_entry(its, &its_nodes, entry) {
2083                 struct its_baser *baser;
2084
2085                 if (!its->is_v4)
2086                         continue;
2087
2088                 baser = its_get_baser(its, GITS_BASER_TYPE_VCPU);
2089                 if (!baser)
2090                         return false;
2091
2092                 if (!its_alloc_table_entry(baser, vpe_id))
2093                         return false;
2094         }
2095
2096         return true;
2097 }
2098
2099 static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
2100                                             int nvecs, bool alloc_lpis)
2101 {
2102         struct its_device *dev;
2103         unsigned long *lpi_map = NULL;
2104         unsigned long flags;
2105         u16 *col_map = NULL;
2106         void *itt;
2107         int lpi_base;
2108         int nr_lpis;
2109         int nr_ites;
2110         int sz;
2111
2112         if (!its_alloc_device_table(its, dev_id))
2113                 return NULL;
2114
2115         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2116         /*
2117          * We allocate at least one chunk worth of LPIs bet device,
2118          * and thus that many ITEs. The device may require less though.
2119          */
2120         nr_ites = max(IRQS_PER_CHUNK, roundup_pow_of_two(nvecs));
2121         sz = nr_ites * its->ite_size;
2122         sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
2123         itt = kzalloc(sz, GFP_KERNEL);
2124         if (alloc_lpis) {
2125                 lpi_map = its_lpi_alloc_chunks(nvecs, &lpi_base, &nr_lpis);
2126                 if (lpi_map)
2127                         col_map = kzalloc(sizeof(*col_map) * nr_lpis,
2128                                           GFP_KERNEL);
2129         } else {
2130                 col_map = kzalloc(sizeof(*col_map) * nr_ites, GFP_KERNEL);
2131                 nr_lpis = 0;
2132                 lpi_base = 0;
2133         }
2134
2135         if (!dev || !itt ||  !col_map || (!lpi_map && alloc_lpis)) {
2136                 kfree(dev);
2137                 kfree(itt);
2138                 kfree(lpi_map);
2139                 kfree(col_map);
2140                 return NULL;
2141         }
2142
2143         gic_flush_dcache_to_poc(itt, sz);
2144
2145         dev->its = its;
2146         dev->itt = itt;
2147         dev->nr_ites = nr_ites;
2148         dev->event_map.lpi_map = lpi_map;
2149         dev->event_map.col_map = col_map;
2150         dev->event_map.lpi_base = lpi_base;
2151         dev->event_map.nr_lpis = nr_lpis;
2152         mutex_init(&dev->event_map.vlpi_lock);
2153         dev->device_id = dev_id;
2154         INIT_LIST_HEAD(&dev->entry);
2155
2156         raw_spin_lock_irqsave(&its->lock, flags);
2157         list_add(&dev->entry, &its->its_device_list);
2158         raw_spin_unlock_irqrestore(&its->lock, flags);
2159
2160         /* Map device to its ITT */
2161         its_send_mapd(dev, 1);
2162
2163         return dev;
2164 }
2165
2166 static void its_free_device(struct its_device *its_dev)
2167 {
2168         unsigned long flags;
2169
2170         raw_spin_lock_irqsave(&its_dev->its->lock, flags);
2171         list_del(&its_dev->entry);
2172         raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
2173         kfree(its_dev->itt);
2174         kfree(its_dev);
2175 }
2176
2177 static int its_alloc_device_irq(struct its_device *dev, irq_hw_number_t *hwirq)
2178 {
2179         int idx;
2180
2181         idx = find_first_zero_bit(dev->event_map.lpi_map,
2182                                   dev->event_map.nr_lpis);
2183         if (idx == dev->event_map.nr_lpis)
2184                 return -ENOSPC;
2185
2186         *hwirq = dev->event_map.lpi_base + idx;
2187         set_bit(idx, dev->event_map.lpi_map);
2188
2189         return 0;
2190 }
2191
2192 static int its_msi_prepare(struct irq_domain *domain, struct device *dev,
2193                            int nvec, msi_alloc_info_t *info)
2194 {
2195         struct its_node *its;
2196         struct its_device *its_dev;
2197         struct msi_domain_info *msi_info;
2198         u32 dev_id;
2199
2200         /*
2201          * We ignore "dev" entierely, and rely on the dev_id that has
2202          * been passed via the scratchpad. This limits this domain's
2203          * usefulness to upper layers that definitely know that they
2204          * are built on top of the ITS.
2205          */
2206         dev_id = info->scratchpad[0].ul;
2207
2208         msi_info = msi_get_domain_info(domain);
2209         its = msi_info->data;
2210
2211         if (!gic_rdists->has_direct_lpi &&
2212             vpe_proxy.dev &&
2213             vpe_proxy.dev->its == its &&
2214             dev_id == vpe_proxy.dev->device_id) {
2215                 /* Bad luck. Get yourself a better implementation */
2216                 WARN_ONCE(1, "DevId %x clashes with GICv4 VPE proxy device\n",
2217                           dev_id);
2218                 return -EINVAL;
2219         }
2220
2221         its_dev = its_find_device(its, dev_id);
2222         if (its_dev) {
2223                 /*
2224                  * We already have seen this ID, probably through
2225                  * another alias (PCI bridge of some sort). No need to
2226                  * create the device.
2227                  */
2228                 pr_debug("Reusing ITT for devID %x\n", dev_id);
2229                 goto out;
2230         }
2231
2232         its_dev = its_create_device(its, dev_id, nvec, true);
2233         if (!its_dev)
2234                 return -ENOMEM;
2235
2236         pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec));
2237 out:
2238         info->scratchpad[0].ptr = its_dev;
2239         return 0;
2240 }
2241
2242 static struct msi_domain_ops its_msi_domain_ops = {
2243         .msi_prepare    = its_msi_prepare,
2244 };
2245
2246 static int its_irq_gic_domain_alloc(struct irq_domain *domain,
2247                                     unsigned int virq,
2248                                     irq_hw_number_t hwirq)
2249 {
2250         struct irq_fwspec fwspec;
2251
2252         if (irq_domain_get_of_node(domain->parent)) {
2253                 fwspec.fwnode = domain->parent->fwnode;
2254                 fwspec.param_count = 3;
2255                 fwspec.param[0] = GIC_IRQ_TYPE_LPI;
2256                 fwspec.param[1] = hwirq;
2257                 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
2258         } else if (is_fwnode_irqchip(domain->parent->fwnode)) {
2259                 fwspec.fwnode = domain->parent->fwnode;
2260                 fwspec.param_count = 2;
2261                 fwspec.param[0] = hwirq;
2262                 fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
2263         } else {
2264                 return -EINVAL;
2265         }
2266
2267         return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
2268 }
2269
2270 static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
2271                                 unsigned int nr_irqs, void *args)
2272 {
2273         msi_alloc_info_t *info = args;
2274         struct its_device *its_dev = info->scratchpad[0].ptr;
2275         irq_hw_number_t hwirq;
2276         int err;
2277         int i;
2278
2279         for (i = 0; i < nr_irqs; i++) {
2280                 err = its_alloc_device_irq(its_dev, &hwirq);
2281                 if (err)
2282                         return err;
2283
2284                 err = its_irq_gic_domain_alloc(domain, virq + i, hwirq);
2285                 if (err)
2286                         return err;
2287
2288                 irq_domain_set_hwirq_and_chip(domain, virq + i,
2289                                               hwirq, &its_irq_chip, its_dev);
2290                 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq + i)));
2291                 pr_debug("ID:%d pID:%d vID:%d\n",
2292                          (int)(hwirq - its_dev->event_map.lpi_base),
2293                          (int) hwirq, virq + i);
2294         }
2295
2296         return 0;
2297 }
2298
2299 static int its_irq_domain_activate(struct irq_domain *domain,
2300                                    struct irq_data *d, bool reserve)
2301 {
2302         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2303         u32 event = its_get_event_id(d);
2304         const struct cpumask *cpu_mask = cpu_online_mask;
2305         int cpu;
2306
2307         /* get the cpu_mask of local node */
2308         if (its_dev->its->numa_node >= 0)
2309                 cpu_mask = cpumask_of_node(its_dev->its->numa_node);
2310
2311         /* Bind the LPI to the first possible CPU */
2312         cpu = cpumask_first(cpu_mask);
2313         its_dev->event_map.col_map[event] = cpu;
2314         irq_data_update_effective_affinity(d, cpumask_of(cpu));
2315
2316         /* Map the GIC IRQ and event to the device */
2317         its_send_mapti(its_dev, d->hwirq, event);
2318         return 0;
2319 }
2320
2321 static void its_irq_domain_deactivate(struct irq_domain *domain,
2322                                       struct irq_data *d)
2323 {
2324         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2325         u32 event = its_get_event_id(d);
2326
2327         /* Stop the delivery of interrupts */
2328         its_send_discard(its_dev, event);
2329 }
2330
2331 static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,
2332                                 unsigned int nr_irqs)
2333 {
2334         struct irq_data *d = irq_domain_get_irq_data(domain, virq);
2335         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2336         int i;
2337
2338         for (i = 0; i < nr_irqs; i++) {
2339                 struct irq_data *data = irq_domain_get_irq_data(domain,
2340                                                                 virq + i);
2341                 u32 event = its_get_event_id(data);
2342
2343                 /* Mark interrupt index as unused */
2344                 clear_bit(event, its_dev->event_map.lpi_map);
2345
2346                 /* Nuke the entry in the domain */
2347                 irq_domain_reset_irq_data(data);
2348         }
2349
2350         /* If all interrupts have been freed, start mopping the floor */
2351         if (bitmap_empty(its_dev->event_map.lpi_map,
2352                          its_dev->event_map.nr_lpis)) {
2353                 its_lpi_free_chunks(its_dev->event_map.lpi_map,
2354                                     its_dev->event_map.lpi_base,
2355                                     its_dev->event_map.nr_lpis);
2356                 kfree(its_dev->event_map.col_map);
2357
2358                 /* Unmap device/itt */
2359                 its_send_mapd(its_dev, 0);
2360                 its_free_device(its_dev);
2361         }
2362
2363         irq_domain_free_irqs_parent(domain, virq, nr_irqs);
2364 }
2365
2366 static const struct irq_domain_ops its_domain_ops = {
2367         .alloc                  = its_irq_domain_alloc,
2368         .free                   = its_irq_domain_free,
2369         .activate               = its_irq_domain_activate,
2370         .deactivate             = its_irq_domain_deactivate,
2371 };
2372
2373 /*
2374  * This is insane.
2375  *
2376  * If a GICv4 doesn't implement Direct LPIs (which is extremely
2377  * likely), the only way to perform an invalidate is to use a fake
2378  * device to issue an INV command, implying that the LPI has first
2379  * been mapped to some event on that device. Since this is not exactly
2380  * cheap, we try to keep that mapping around as long as possible, and
2381  * only issue an UNMAP if we're short on available slots.
2382  *
2383  * Broken by design(tm).
2384  */
2385 static void its_vpe_db_proxy_unmap_locked(struct its_vpe *vpe)
2386 {
2387         /* Already unmapped? */
2388         if (vpe->vpe_proxy_event == -1)
2389                 return;
2390
2391         its_send_discard(vpe_proxy.dev, vpe->vpe_proxy_event);
2392         vpe_proxy.vpes[vpe->vpe_proxy_event] = NULL;
2393
2394         /*
2395          * We don't track empty slots at all, so let's move the
2396          * next_victim pointer if we can quickly reuse that slot
2397          * instead of nuking an existing entry. Not clear that this is
2398          * always a win though, and this might just generate a ripple
2399          * effect... Let's just hope VPEs don't migrate too often.
2400          */
2401         if (vpe_proxy.vpes[vpe_proxy.next_victim])
2402                 vpe_proxy.next_victim = vpe->vpe_proxy_event;
2403
2404         vpe->vpe_proxy_event = -1;
2405 }
2406
2407 static void its_vpe_db_proxy_unmap(struct its_vpe *vpe)
2408 {
2409         if (!gic_rdists->has_direct_lpi) {
2410                 unsigned long flags;
2411
2412                 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
2413                 its_vpe_db_proxy_unmap_locked(vpe);
2414                 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
2415         }
2416 }
2417
2418 static void its_vpe_db_proxy_map_locked(struct its_vpe *vpe)
2419 {
2420         /* Already mapped? */
2421         if (vpe->vpe_proxy_event != -1)
2422                 return;
2423
2424         /* This slot was already allocated. Kick the other VPE out. */
2425         if (vpe_proxy.vpes[vpe_proxy.next_victim])
2426                 its_vpe_db_proxy_unmap_locked(vpe_proxy.vpes[vpe_proxy.next_victim]);
2427
2428         /* Map the new VPE instead */
2429         vpe_proxy.vpes[vpe_proxy.next_victim] = vpe;
2430         vpe->vpe_proxy_event = vpe_proxy.next_victim;
2431         vpe_proxy.next_victim = (vpe_proxy.next_victim + 1) % vpe_proxy.dev->nr_ites;
2432
2433         vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = vpe->col_idx;
2434         its_send_mapti(vpe_proxy.dev, vpe->vpe_db_lpi, vpe->vpe_proxy_event);
2435 }
2436
2437 static void its_vpe_db_proxy_move(struct its_vpe *vpe, int from, int to)
2438 {
2439         unsigned long flags;
2440         struct its_collection *target_col;
2441
2442         if (gic_rdists->has_direct_lpi) {
2443                 void __iomem *rdbase;
2444
2445                 rdbase = per_cpu_ptr(gic_rdists->rdist, from)->rd_base;
2446                 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
2447                 while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
2448                         cpu_relax();
2449
2450                 return;
2451         }
2452
2453         raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
2454
2455         its_vpe_db_proxy_map_locked(vpe);
2456
2457         target_col = &vpe_proxy.dev->its->collections[to];
2458         its_send_movi(vpe_proxy.dev, target_col, vpe->vpe_proxy_event);
2459         vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = to;
2460
2461         raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
2462 }
2463
2464 static int its_vpe_set_affinity(struct irq_data *d,
2465                                 const struct cpumask *mask_val,
2466                                 bool force)
2467 {
2468         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2469         int cpu = cpumask_first(mask_val);
2470
2471         /*
2472          * Changing affinity is mega expensive, so let's be as lazy as
2473          * we can and only do it if we really have to. Also, if mapped
2474          * into the proxy device, we need to move the doorbell
2475          * interrupt to its new location.
2476          */
2477         if (vpe->col_idx != cpu) {
2478                 int from = vpe->col_idx;
2479
2480                 vpe->col_idx = cpu;
2481                 its_send_vmovp(vpe);
2482                 its_vpe_db_proxy_move(vpe, from, cpu);
2483         }
2484
2485         irq_data_update_effective_affinity(d, cpumask_of(cpu));
2486
2487         return IRQ_SET_MASK_OK_DONE;
2488 }
2489
2490 static void its_vpe_schedule(struct its_vpe *vpe)
2491 {
2492         void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2493         u64 val;
2494
2495         /* Schedule the VPE */
2496         val  = virt_to_phys(page_address(vpe->its_vm->vprop_page)) &
2497                 GENMASK_ULL(51, 12);
2498         val |= (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
2499         val |= GICR_VPROPBASER_RaWb;
2500         val |= GICR_VPROPBASER_InnerShareable;
2501         gits_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2502
2503         val  = virt_to_phys(page_address(vpe->vpt_page)) &
2504                 GENMASK_ULL(51, 16);
2505         val |= GICR_VPENDBASER_RaWaWb;
2506         val |= GICR_VPENDBASER_NonShareable;
2507         /*
2508          * There is no good way of finding out if the pending table is
2509          * empty as we can race against the doorbell interrupt very
2510          * easily. So in the end, vpe->pending_last is only an
2511          * indication that the vcpu has something pending, not one
2512          * that the pending table is empty. A good implementation
2513          * would be able to read its coarse map pretty quickly anyway,
2514          * making this a tolerable issue.
2515          */
2516         val |= GICR_VPENDBASER_PendingLast;
2517         val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0;
2518         val |= GICR_VPENDBASER_Valid;
2519         gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
2520 }
2521
2522 static void its_vpe_deschedule(struct its_vpe *vpe)
2523 {
2524         void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2525         u32 count = 1000000;    /* 1s! */
2526         bool clean;
2527         u64 val;
2528
2529         /* We're being scheduled out */
2530         val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
2531         val &= ~GICR_VPENDBASER_Valid;
2532         gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
2533
2534         do {
2535                 val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
2536                 clean = !(val & GICR_VPENDBASER_Dirty);
2537                 if (!clean) {
2538                         count--;
2539                         cpu_relax();
2540                         udelay(1);
2541                 }
2542         } while (!clean && count);
2543
2544         if (unlikely(!clean && !count)) {
2545                 pr_err_ratelimited("ITS virtual pending table not cleaning\n");
2546                 vpe->idai = false;
2547                 vpe->pending_last = true;
2548         } else {
2549                 vpe->idai = !!(val & GICR_VPENDBASER_IDAI);
2550                 vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);
2551         }
2552 }
2553
2554 static void its_vpe_invall(struct its_vpe *vpe)
2555 {
2556         struct its_node *its;
2557
2558         list_for_each_entry(its, &its_nodes, entry) {
2559                 if (!its->is_v4)
2560                         continue;
2561
2562                 if (its_list_map && !vpe->its_vm->vlpi_count[its->list_nr])
2563                         continue;
2564
2565                 /*
2566                  * Sending a VINVALL to a single ITS is enough, as all
2567                  * we need is to reach the redistributors.
2568                  */
2569                 its_send_vinvall(its, vpe);
2570                 return;
2571         }
2572 }
2573
2574 static int its_vpe_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
2575 {
2576         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2577         struct its_cmd_info *info = vcpu_info;
2578
2579         switch (info->cmd_type) {
2580         case SCHEDULE_VPE:
2581                 its_vpe_schedule(vpe);
2582                 return 0;
2583
2584         case DESCHEDULE_VPE:
2585                 its_vpe_deschedule(vpe);
2586                 return 0;
2587
2588         case INVALL_VPE:
2589                 its_vpe_invall(vpe);
2590                 return 0;
2591
2592         default:
2593                 return -EINVAL;
2594         }
2595 }
2596
2597 static void its_vpe_send_cmd(struct its_vpe *vpe,
2598                              void (*cmd)(struct its_device *, u32))
2599 {
2600         unsigned long flags;
2601
2602         raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
2603
2604         its_vpe_db_proxy_map_locked(vpe);
2605         cmd(vpe_proxy.dev, vpe->vpe_proxy_event);
2606
2607         raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
2608 }
2609
2610 static void its_vpe_send_inv(struct irq_data *d)
2611 {
2612         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2613
2614         if (gic_rdists->has_direct_lpi) {
2615                 void __iomem *rdbase;
2616
2617                 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
2618                 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_INVLPIR);
2619                 while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
2620                         cpu_relax();
2621         } else {
2622                 its_vpe_send_cmd(vpe, its_send_inv);
2623         }
2624 }
2625
2626 static void its_vpe_mask_irq(struct irq_data *d)
2627 {
2628         /*
2629          * We need to unmask the LPI, which is described by the parent
2630          * irq_data. Instead of calling into the parent (which won't
2631          * exactly do the right thing, let's simply use the
2632          * parent_data pointer. Yes, I'm naughty.
2633          */
2634         lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0);
2635         its_vpe_send_inv(d);
2636 }
2637
2638 static void its_vpe_unmask_irq(struct irq_data *d)
2639 {
2640         /* Same hack as above... */
2641         lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED);
2642         its_vpe_send_inv(d);
2643 }
2644
2645 static int its_vpe_set_irqchip_state(struct irq_data *d,
2646                                      enum irqchip_irq_state which,
2647                                      bool state)
2648 {
2649         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2650
2651         if (which != IRQCHIP_STATE_PENDING)
2652                 return -EINVAL;
2653
2654         if (gic_rdists->has_direct_lpi) {
2655                 void __iomem *rdbase;
2656
2657                 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
2658                 if (state) {
2659                         gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_SETLPIR);
2660                 } else {
2661                         gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
2662                         while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
2663                                 cpu_relax();
2664                 }
2665         } else {
2666                 if (state)
2667                         its_vpe_send_cmd(vpe, its_send_int);
2668                 else
2669                         its_vpe_send_cmd(vpe, its_send_clear);
2670         }
2671
2672         return 0;
2673 }
2674
2675 static struct irq_chip its_vpe_irq_chip = {
2676         .name                   = "GICv4-vpe",
2677         .irq_mask               = its_vpe_mask_irq,
2678         .irq_unmask             = its_vpe_unmask_irq,
2679         .irq_eoi                = irq_chip_eoi_parent,
2680         .irq_set_affinity       = its_vpe_set_affinity,
2681         .irq_set_irqchip_state  = its_vpe_set_irqchip_state,
2682         .irq_set_vcpu_affinity  = its_vpe_set_vcpu_affinity,
2683 };
2684
2685 static int its_vpe_id_alloc(void)
2686 {
2687         return ida_simple_get(&its_vpeid_ida, 0, ITS_MAX_VPEID, GFP_KERNEL);
2688 }
2689
2690 static void its_vpe_id_free(u16 id)
2691 {
2692         ida_simple_remove(&its_vpeid_ida, id);
2693 }
2694
2695 static int its_vpe_init(struct its_vpe *vpe)
2696 {
2697         struct page *vpt_page;
2698         int vpe_id;
2699
2700         /* Allocate vpe_id */
2701         vpe_id = its_vpe_id_alloc();
2702         if (vpe_id < 0)
2703                 return vpe_id;
2704
2705         /* Allocate VPT */
2706         vpt_page = its_allocate_pending_table(GFP_KERNEL);
2707         if (!vpt_page) {
2708                 its_vpe_id_free(vpe_id);
2709                 return -ENOMEM;
2710         }
2711
2712         if (!its_alloc_vpe_table(vpe_id)) {
2713                 its_vpe_id_free(vpe_id);
2714                 its_free_pending_table(vpe->vpt_page);
2715                 return -ENOMEM;
2716         }
2717
2718         vpe->vpe_id = vpe_id;
2719         vpe->vpt_page = vpt_page;
2720         vpe->vpe_proxy_event = -1;
2721
2722         return 0;
2723 }
2724
2725 static void its_vpe_teardown(struct its_vpe *vpe)
2726 {
2727         its_vpe_db_proxy_unmap(vpe);
2728         its_vpe_id_free(vpe->vpe_id);
2729         its_free_pending_table(vpe->vpt_page);
2730 }
2731
2732 static void its_vpe_irq_domain_free(struct irq_domain *domain,
2733                                     unsigned int virq,
2734                                     unsigned int nr_irqs)
2735 {
2736         struct its_vm *vm = domain->host_data;
2737         int i;
2738
2739         irq_domain_free_irqs_parent(domain, virq, nr_irqs);
2740
2741         for (i = 0; i < nr_irqs; i++) {
2742                 struct irq_data *data = irq_domain_get_irq_data(domain,
2743                                                                 virq + i);
2744                 struct its_vpe *vpe = irq_data_get_irq_chip_data(data);
2745
2746                 BUG_ON(vm != vpe->its_vm);
2747
2748                 clear_bit(data->hwirq, vm->db_bitmap);
2749                 its_vpe_teardown(vpe);
2750                 irq_domain_reset_irq_data(data);
2751         }
2752
2753         if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) {
2754                 its_lpi_free_chunks(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis);
2755                 its_free_prop_table(vm->vprop_page);
2756         }
2757 }
2758
2759 static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
2760                                     unsigned int nr_irqs, void *args)
2761 {
2762         struct its_vm *vm = args;
2763         unsigned long *bitmap;
2764         struct page *vprop_page;
2765         int base, nr_ids, i, err = 0;
2766
2767         BUG_ON(!vm);
2768
2769         bitmap = its_lpi_alloc_chunks(nr_irqs, &base, &nr_ids);
2770         if (!bitmap)
2771                 return -ENOMEM;
2772
2773         if (nr_ids < nr_irqs) {
2774                 its_lpi_free_chunks(bitmap, base, nr_ids);
2775                 return -ENOMEM;
2776         }
2777
2778         vprop_page = its_allocate_prop_table(GFP_KERNEL);
2779         if (!vprop_page) {
2780                 its_lpi_free_chunks(bitmap, base, nr_ids);
2781                 return -ENOMEM;
2782         }
2783
2784         vm->db_bitmap = bitmap;
2785         vm->db_lpi_base = base;
2786         vm->nr_db_lpis = nr_ids;
2787         vm->vprop_page = vprop_page;
2788
2789         for (i = 0; i < nr_irqs; i++) {
2790                 vm->vpes[i]->vpe_db_lpi = base + i;
2791                 err = its_vpe_init(vm->vpes[i]);
2792                 if (err)
2793                         break;
2794                 err = its_irq_gic_domain_alloc(domain, virq + i,
2795                                                vm->vpes[i]->vpe_db_lpi);
2796                 if (err)
2797                         break;
2798                 irq_domain_set_hwirq_and_chip(domain, virq + i, i,
2799                                               &its_vpe_irq_chip, vm->vpes[i]);
2800                 set_bit(i, bitmap);
2801         }
2802
2803         if (err) {
2804                 if (i > 0)
2805                         its_vpe_irq_domain_free(domain, virq, i - 1);
2806
2807                 its_lpi_free_chunks(bitmap, base, nr_ids);
2808                 its_free_prop_table(vprop_page);
2809         }
2810
2811         return err;
2812 }
2813
2814 static int its_vpe_irq_domain_activate(struct irq_domain *domain,
2815                                        struct irq_data *d, bool reserve)
2816 {
2817         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2818         struct its_node *its;
2819
2820         /* If we use the list map, we issue VMAPP on demand... */
2821         if (its_list_map)
2822                 return 0;
2823
2824         /* Map the VPE to the first possible CPU */
2825         vpe->col_idx = cpumask_first(cpu_online_mask);
2826
2827         list_for_each_entry(its, &its_nodes, entry) {
2828                 if (!its->is_v4)
2829                         continue;
2830
2831                 its_send_vmapp(its, vpe, true);
2832                 its_send_vinvall(its, vpe);
2833         }
2834
2835         irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
2836
2837         return 0;
2838 }
2839
2840 static void its_vpe_irq_domain_deactivate(struct irq_domain *domain,
2841                                           struct irq_data *d)
2842 {
2843         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2844         struct its_node *its;
2845
2846         /*
2847          * If we use the list map, we unmap the VPE once no VLPIs are
2848          * associated with the VM.
2849          */
2850         if (its_list_map)
2851                 return;
2852
2853         list_for_each_entry(its, &its_nodes, entry) {
2854                 if (!its->is_v4)
2855                         continue;
2856
2857                 its_send_vmapp(its, vpe, false);
2858         }
2859 }
2860
2861 static const struct irq_domain_ops its_vpe_domain_ops = {
2862         .alloc                  = its_vpe_irq_domain_alloc,
2863         .free                   = its_vpe_irq_domain_free,
2864         .activate               = its_vpe_irq_domain_activate,
2865         .deactivate             = its_vpe_irq_domain_deactivate,
2866 };
2867
2868 static int its_force_quiescent(void __iomem *base)
2869 {
2870         u32 count = 1000000;    /* 1s */
2871         u32 val;
2872
2873         val = readl_relaxed(base + GITS_CTLR);
2874         /*
2875          * GIC architecture specification requires the ITS to be both
2876          * disabled and quiescent for writes to GITS_BASER<n> or
2877          * GITS_CBASER to not have UNPREDICTABLE results.
2878          */
2879         if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE))
2880                 return 0;
2881
2882         /* Disable the generation of all interrupts to this ITS */
2883         val &= ~(GITS_CTLR_ENABLE | GITS_CTLR_ImDe);
2884         writel_relaxed(val, base + GITS_CTLR);
2885
2886         /* Poll GITS_CTLR and wait until ITS becomes quiescent */
2887         while (1) {
2888                 val = readl_relaxed(base + GITS_CTLR);
2889                 if (val & GITS_CTLR_QUIESCENT)
2890                         return 0;
2891
2892                 count--;
2893                 if (!count)
2894                         return -EBUSY;
2895
2896                 cpu_relax();
2897                 udelay(1);
2898         }
2899 }
2900
2901 static bool __maybe_unused its_enable_quirk_cavium_22375(void *data)
2902 {
2903         struct its_node *its = data;
2904
2905         /* erratum 22375: only alloc 8MB table size */
2906         its->device_ids = 0x14;         /* 20 bits, 8MB */
2907         its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375;
2908
2909         return true;
2910 }
2911
2912 static bool __maybe_unused its_enable_quirk_cavium_23144(void *data)
2913 {
2914         struct its_node *its = data;
2915
2916         its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144;
2917
2918         return true;
2919 }
2920
2921 static bool __maybe_unused its_enable_quirk_qdf2400_e0065(void *data)
2922 {
2923         struct its_node *its = data;
2924
2925         /* On QDF2400, the size of the ITE is 16Bytes */
2926         its->ite_size = 16;
2927
2928         return true;
2929 }
2930
2931 static u64 its_irq_get_msi_base_pre_its(struct its_device *its_dev)
2932 {
2933         struct its_node *its = its_dev->its;
2934
2935         /*
2936          * The Socionext Synquacer SoC has a so-called 'pre-ITS',
2937          * which maps 32-bit writes targeted at a separate window of
2938          * size '4 << device_id_bits' onto writes to GITS_TRANSLATER
2939          * with device ID taken from bits [device_id_bits + 1:2] of
2940          * the window offset.
2941          */
2942         return its->pre_its_base + (its_dev->device_id << 2);
2943 }
2944
2945 static bool __maybe_unused its_enable_quirk_socionext_synquacer(void *data)
2946 {
2947         struct its_node *its = data;
2948         u32 pre_its_window[2];
2949         u32 ids;
2950
2951         if (!fwnode_property_read_u32_array(its->fwnode_handle,
2952                                            "socionext,synquacer-pre-its",
2953                                            pre_its_window,
2954                                            ARRAY_SIZE(pre_its_window))) {
2955
2956                 its->pre_its_base = pre_its_window[0];
2957                 its->get_msi_base = its_irq_get_msi_base_pre_its;
2958
2959                 ids = ilog2(pre_its_window[1]) - 2;
2960                 if (its->device_ids > ids)
2961                         its->device_ids = ids;
2962
2963                 /* the pre-ITS breaks isolation, so disable MSI remapping */
2964                 its->msi_domain_flags &= ~IRQ_DOMAIN_FLAG_MSI_REMAP;
2965                 return true;
2966         }
2967         return false;
2968 }
2969
2970 static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data)
2971 {
2972         struct its_node *its = data;
2973
2974         /*
2975          * Hip07 insists on using the wrong address for the VLPI
2976          * page. Trick it into doing the right thing...
2977          */
2978         its->vlpi_redist_offset = SZ_128K;
2979         return true;
2980 }
2981
2982 static const struct gic_quirk its_quirks[] = {
2983 #ifdef CONFIG_CAVIUM_ERRATUM_22375
2984         {
2985                 .desc   = "ITS: Cavium errata 22375, 24313",
2986                 .iidr   = 0xa100034c,   /* ThunderX pass 1.x */
2987                 .mask   = 0xffff0fff,
2988                 .init   = its_enable_quirk_cavium_22375,
2989         },
2990 #endif
2991 #ifdef CONFIG_CAVIUM_ERRATUM_23144
2992         {
2993                 .desc   = "ITS: Cavium erratum 23144",
2994                 .iidr   = 0xa100034c,   /* ThunderX pass 1.x */
2995                 .mask   = 0xffff0fff,
2996                 .init   = its_enable_quirk_cavium_23144,
2997         },
2998 #endif
2999 #ifdef CONFIG_QCOM_QDF2400_ERRATUM_0065
3000         {
3001                 .desc   = "ITS: QDF2400 erratum 0065",
3002                 .iidr   = 0x00001070, /* QDF2400 ITS rev 1.x */
3003                 .mask   = 0xffffffff,
3004                 .init   = its_enable_quirk_qdf2400_e0065,
3005         },
3006 #endif
3007 #ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS
3008         {
3009                 /*
3010                  * The Socionext Synquacer SoC incorporates ARM's own GIC-500
3011                  * implementation, but with a 'pre-ITS' added that requires
3012                  * special handling in software.
3013                  */
3014                 .desc   = "ITS: Socionext Synquacer pre-ITS",
3015                 .iidr   = 0x0001143b,
3016                 .mask   = 0xffffffff,
3017                 .init   = its_enable_quirk_socionext_synquacer,
3018         },
3019 #endif
3020 #ifdef CONFIG_HISILICON_ERRATUM_161600802
3021         {
3022                 .desc   = "ITS: Hip07 erratum 161600802",
3023                 .iidr   = 0x00000004,
3024                 .mask   = 0xffffffff,
3025                 .init   = its_enable_quirk_hip07_161600802,
3026         },
3027 #endif
3028         {
3029         }
3030 };
3031
3032 static void its_enable_quirks(struct its_node *its)
3033 {
3034         u32 iidr = readl_relaxed(its->base + GITS_IIDR);
3035
3036         gic_enable_quirks(iidr, its_quirks, its);
3037 }
3038
3039 static int its_save_disable(void)
3040 {
3041         struct its_node *its;
3042         int err = 0;
3043
3044         spin_lock(&its_lock);
3045         list_for_each_entry(its, &its_nodes, entry) {
3046                 void __iomem *base;
3047
3048                 if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
3049                         continue;
3050
3051                 base = its->base;
3052                 its->ctlr_save = readl_relaxed(base + GITS_CTLR);
3053                 err = its_force_quiescent(base);
3054                 if (err) {
3055                         pr_err("ITS@%pa: failed to quiesce: %d\n",
3056                                &its->phys_base, err);
3057                         writel_relaxed(its->ctlr_save, base + GITS_CTLR);
3058                         goto err;
3059                 }
3060
3061                 its->cbaser_save = gits_read_cbaser(base + GITS_CBASER);
3062         }
3063
3064 err:
3065         if (err) {
3066                 list_for_each_entry_continue_reverse(its, &its_nodes, entry) {
3067                         void __iomem *base;
3068
3069                         if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
3070                                 continue;
3071
3072                         base = its->base;
3073                         writel_relaxed(its->ctlr_save, base + GITS_CTLR);
3074                 }
3075         }
3076         spin_unlock(&its_lock);
3077
3078         return err;
3079 }
3080
3081 static void its_restore_enable(void)
3082 {
3083         struct its_node *its;
3084         int ret;
3085
3086         spin_lock(&its_lock);
3087         list_for_each_entry(its, &its_nodes, entry) {
3088                 void __iomem *base;
3089                 int i;
3090
3091                 if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
3092                         continue;
3093
3094                 base = its->base;
3095
3096                 /*
3097                  * Make sure that the ITS is disabled. If it fails to quiesce,
3098                  * don't restore it since writing to CBASER or BASER<n>
3099                  * registers is undefined according to the GIC v3 ITS
3100                  * Specification.
3101                  */
3102                 ret = its_force_quiescent(base);
3103                 if (ret) {
3104                         pr_err("ITS@%pa: failed to quiesce on resume: %d\n",
3105                                &its->phys_base, ret);
3106                         continue;
3107                 }
3108
3109                 gits_write_cbaser(its->cbaser_save, base + GITS_CBASER);
3110
3111                 /*
3112                  * Writing CBASER resets CREADR to 0, so make CWRITER and
3113                  * cmd_write line up with it.
3114                  */
3115                 its->cmd_write = its->cmd_base;
3116                 gits_write_cwriter(0, base + GITS_CWRITER);
3117
3118                 /* Restore GITS_BASER from the value cache. */
3119                 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
3120                         struct its_baser *baser = &its->tables[i];
3121
3122                         if (!(baser->val & GITS_BASER_VALID))
3123                                 continue;
3124
3125                         its_write_baser(its, baser, baser->val);
3126                 }
3127                 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
3128
3129                 /*
3130                  * Reinit the collection if it's stored in the ITS. This is
3131                  * indicated by the col_id being less than the HCC field.
3132                  * CID < HCC as specified in the GIC v3 Documentation.
3133                  */
3134                 if (its->collections[smp_processor_id()].col_id <
3135                     GITS_TYPER_HCC(gic_read_typer(base + GITS_TYPER)))
3136                         its_cpu_init_collection(its);
3137         }
3138         spin_unlock(&its_lock);
3139 }
3140
3141 static struct syscore_ops its_syscore_ops = {
3142         .suspend = its_save_disable,
3143         .resume = its_restore_enable,
3144 };
3145
3146 static int its_init_domain(struct fwnode_handle *handle, struct its_node *its)
3147 {
3148         struct irq_domain *inner_domain;
3149         struct msi_domain_info *info;
3150
3151         info = kzalloc(sizeof(*info), GFP_KERNEL);
3152         if (!info)
3153                 return -ENOMEM;
3154
3155         inner_domain = irq_domain_create_tree(handle, &its_domain_ops, its);
3156         if (!inner_domain) {
3157                 kfree(info);
3158                 return -ENOMEM;
3159         }
3160
3161         inner_domain->parent = its_parent;
3162         irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS);
3163         inner_domain->flags |= its->msi_domain_flags;
3164         info->ops = &its_msi_domain_ops;
3165         info->data = its;
3166         inner_domain->host_data = info;
3167
3168         return 0;
3169 }
3170
3171 static int its_init_vpe_domain(void)
3172 {
3173         struct its_node *its;
3174         u32 devid;
3175         int entries;
3176
3177         if (gic_rdists->has_direct_lpi) {
3178                 pr_info("ITS: Using DirectLPI for VPE invalidation\n");
3179                 return 0;
3180         }
3181
3182         /* Any ITS will do, even if not v4 */
3183         its = list_first_entry(&its_nodes, struct its_node, entry);
3184
3185         entries = roundup_pow_of_two(nr_cpu_ids);
3186         vpe_proxy.vpes = kzalloc(sizeof(*vpe_proxy.vpes) * entries,
3187                                  GFP_KERNEL);
3188         if (!vpe_proxy.vpes) {
3189                 pr_err("ITS: Can't allocate GICv4 proxy device array\n");
3190                 return -ENOMEM;
3191         }
3192
3193         /* Use the last possible DevID */
3194         devid = GENMASK(its->device_ids - 1, 0);
3195         vpe_proxy.dev = its_create_device(its, devid, entries, false);
3196         if (!vpe_proxy.dev) {
3197                 kfree(vpe_proxy.vpes);
3198                 pr_err("ITS: Can't allocate GICv4 proxy device\n");
3199                 return -ENOMEM;
3200         }
3201
3202         BUG_ON(entries > vpe_proxy.dev->nr_ites);
3203
3204         raw_spin_lock_init(&vpe_proxy.lock);
3205         vpe_proxy.next_victim = 0;
3206         pr_info("ITS: Allocated DevID %x as GICv4 proxy device (%d slots)\n",
3207                 devid, vpe_proxy.dev->nr_ites);
3208
3209         return 0;
3210 }
3211
3212 static int __init its_compute_its_list_map(struct resource *res,
3213                                            void __iomem *its_base)
3214 {
3215         int its_number;
3216         u32 ctlr;
3217
3218         /*
3219          * This is assumed to be done early enough that we're
3220          * guaranteed to be single-threaded, hence no
3221          * locking. Should this change, we should address
3222          * this.
3223          */
3224         its_number = find_first_zero_bit(&its_list_map, GICv4_ITS_LIST_MAX);
3225         if (its_number >= GICv4_ITS_LIST_MAX) {
3226                 pr_err("ITS@%pa: No ITSList entry available!\n",
3227                        &res->start);
3228                 return -EINVAL;
3229         }
3230
3231         ctlr = readl_relaxed(its_base + GITS_CTLR);
3232         ctlr &= ~GITS_CTLR_ITS_NUMBER;
3233         ctlr |= its_number << GITS_CTLR_ITS_NUMBER_SHIFT;
3234         writel_relaxed(ctlr, its_base + GITS_CTLR);
3235         ctlr = readl_relaxed(its_base + GITS_CTLR);
3236         if ((ctlr & GITS_CTLR_ITS_NUMBER) != (its_number << GITS_CTLR_ITS_NUMBER_SHIFT)) {
3237                 its_number = ctlr & GITS_CTLR_ITS_NUMBER;
3238                 its_number >>= GITS_CTLR_ITS_NUMBER_SHIFT;
3239         }
3240
3241         if (test_and_set_bit(its_number, &its_list_map)) {
3242                 pr_err("ITS@%pa: Duplicate ITSList entry %d\n",
3243                        &res->start, its_number);
3244                 return -EINVAL;
3245         }
3246
3247         return its_number;
3248 }
3249
3250 static int __init its_probe_one(struct resource *res,
3251                                 struct fwnode_handle *handle, int numa_node)
3252 {
3253         struct its_node *its;
3254         void __iomem *its_base;
3255         u32 val, ctlr;
3256         u64 baser, tmp, typer;
3257         int err;
3258
3259         its_base = ioremap(res->start, resource_size(res));
3260         if (!its_base) {
3261                 pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start);
3262                 return -ENOMEM;
3263         }
3264
3265         val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK;
3266         if (val != 0x30 && val != 0x40) {
3267                 pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start);
3268                 err = -ENODEV;
3269                 goto out_unmap;
3270         }
3271
3272         err = its_force_quiescent(its_base);
3273         if (err) {
3274                 pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start);
3275                 goto out_unmap;
3276         }
3277
3278         pr_info("ITS %pR\n", res);
3279
3280         its = kzalloc(sizeof(*its), GFP_KERNEL);
3281         if (!its) {
3282                 err = -ENOMEM;
3283                 goto out_unmap;
3284         }
3285
3286         raw_spin_lock_init(&its->lock);
3287         INIT_LIST_HEAD(&its->entry);
3288         INIT_LIST_HEAD(&its->its_device_list);
3289         typer = gic_read_typer(its_base + GITS_TYPER);
3290         its->base = its_base;
3291         its->phys_base = res->start;
3292         its->ite_size = GITS_TYPER_ITT_ENTRY_SIZE(typer);
3293         its->device_ids = GITS_TYPER_DEVBITS(typer);
3294         its->is_v4 = !!(typer & GITS_TYPER_VLPIS);
3295         if (its->is_v4) {
3296                 if (!(typer & GITS_TYPER_VMOVP)) {
3297                         err = its_compute_its_list_map(res, its_base);
3298                         if (err < 0)
3299                                 goto out_free_its;
3300
3301                         its->list_nr = err;
3302
3303                         pr_info("ITS@%pa: Using ITS number %d\n",
3304                                 &res->start, err);
3305                 } else {
3306                         pr_info("ITS@%pa: Single VMOVP capable\n", &res->start);
3307                 }
3308         }
3309
3310         its->numa_node = numa_node;
3311
3312         its->cmd_base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
3313                                                 get_order(ITS_CMD_QUEUE_SZ));
3314         if (!its->cmd_base) {
3315                 err = -ENOMEM;
3316                 goto out_free_its;
3317         }
3318         its->cmd_write = its->cmd_base;
3319         its->fwnode_handle = handle;
3320         its->get_msi_base = its_irq_get_msi_base;
3321         its->msi_domain_flags = IRQ_DOMAIN_FLAG_MSI_REMAP;
3322
3323         its_enable_quirks(its);
3324
3325         err = its_alloc_tables(its);
3326         if (err)
3327                 goto out_free_cmd;
3328
3329         err = its_alloc_collections(its);
3330         if (err)
3331                 goto out_free_tables;
3332
3333         baser = (virt_to_phys(its->cmd_base)    |
3334                  GITS_CBASER_RaWaWb             |
3335                  GITS_CBASER_InnerShareable     |
3336                  (ITS_CMD_QUEUE_SZ / SZ_4K - 1) |
3337                  GITS_CBASER_VALID);
3338
3339         gits_write_cbaser(baser, its->base + GITS_CBASER);
3340         tmp = gits_read_cbaser(its->base + GITS_CBASER);
3341
3342         if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
3343                 if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
3344                         /*
3345                          * The HW reports non-shareable, we must
3346                          * remove the cacheability attributes as
3347                          * well.
3348                          */
3349                         baser &= ~(GITS_CBASER_SHAREABILITY_MASK |
3350                                    GITS_CBASER_CACHEABILITY_MASK);
3351                         baser |= GITS_CBASER_nC;
3352                         gits_write_cbaser(baser, its->base + GITS_CBASER);
3353                 }
3354                 pr_info("ITS: using cache flushing for cmd queue\n");
3355                 its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
3356         }
3357
3358         gits_write_cwriter(0, its->base + GITS_CWRITER);
3359         ctlr = readl_relaxed(its->base