irqchip/gic-v3: Allow interrupt to be configured as wake-up sources
[muen/linux.git] / drivers / irqchip / irq-gic-v3.c
1 /*
2  * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
3  * Author: Marc Zyngier <marc.zyngier@arm.com>
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License version 2 as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
16  */
17
18 #define pr_fmt(fmt)     "GICv3: " fmt
19
20 #include <linux/acpi.h>
21 #include <linux/cpu.h>
22 #include <linux/cpu_pm.h>
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/irqdomain.h>
26 #include <linux/of.h>
27 #include <linux/of_address.h>
28 #include <linux/of_irq.h>
29 #include <linux/percpu.h>
30 #include <linux/slab.h>
31
32 #include <linux/irqchip.h>
33 #include <linux/irqchip/arm-gic-common.h>
34 #include <linux/irqchip/arm-gic-v3.h>
35 #include <linux/irqchip/irq-partition-percpu.h>
36
37 #include <asm/cputype.h>
38 #include <asm/exception.h>
39 #include <asm/smp_plat.h>
40 #include <asm/virt.h>
41
42 #include "irq-gic-common.h"
43
44 struct redist_region {
45         void __iomem            *redist_base;
46         phys_addr_t             phys_base;
47         bool                    single_redist;
48 };
49
50 struct gic_chip_data {
51         struct fwnode_handle    *fwnode;
52         void __iomem            *dist_base;
53         struct redist_region    *redist_regions;
54         struct rdists           rdists;
55         struct irq_domain       *domain;
56         u64                     redist_stride;
57         u32                     nr_redist_regions;
58         bool                    has_rss;
59         unsigned int            irq_nr;
60         struct partition_desc   *ppi_descs[16];
61 };
62
63 static struct gic_chip_data gic_data __read_mostly;
64 static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
65
66 static struct gic_kvm_info gic_v3_kvm_info;
67 static DEFINE_PER_CPU(bool, has_rss);
68
69 #define MPIDR_RS(mpidr)                 (((mpidr) & 0xF0UL) >> 4)
70 #define gic_data_rdist()                (this_cpu_ptr(gic_data.rdists.rdist))
71 #define gic_data_rdist_rd_base()        (gic_data_rdist()->rd_base)
72 #define gic_data_rdist_sgi_base()       (gic_data_rdist_rd_base() + SZ_64K)
73
74 /* Our default, arbitrary priority value. Linux only uses one anyway. */
75 #define DEFAULT_PMR_VALUE       0xf0
76
77 static inline unsigned int gic_irq(struct irq_data *d)
78 {
79         return d->hwirq;
80 }
81
82 static inline int gic_irq_in_rdist(struct irq_data *d)
83 {
84         return gic_irq(d) < 32;
85 }
86
87 static inline void __iomem *gic_dist_base(struct irq_data *d)
88 {
89         if (gic_irq_in_rdist(d))        /* SGI+PPI -> SGI_base for this CPU */
90                 return gic_data_rdist_sgi_base();
91
92         if (d->hwirq <= 1023)           /* SPI -> dist_base */
93                 return gic_data.dist_base;
94
95         return NULL;
96 }
97
98 static void gic_do_wait_for_rwp(void __iomem *base)
99 {
100         u32 count = 1000000;    /* 1s! */
101
102         while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) {
103                 count--;
104                 if (!count) {
105                         pr_err_ratelimited("RWP timeout, gone fishing\n");
106                         return;
107                 }
108                 cpu_relax();
109                 udelay(1);
110         };
111 }
112
113 /* Wait for completion of a distributor change */
114 static void gic_dist_wait_for_rwp(void)
115 {
116         gic_do_wait_for_rwp(gic_data.dist_base);
117 }
118
119 /* Wait for completion of a redistributor change */
120 static void gic_redist_wait_for_rwp(void)
121 {
122         gic_do_wait_for_rwp(gic_data_rdist_rd_base());
123 }
124
125 #ifdef CONFIG_ARM64
126
127 static u64 __maybe_unused gic_read_iar(void)
128 {
129         if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154))
130                 return gic_read_iar_cavium_thunderx();
131         else
132                 return gic_read_iar_common();
133 }
134 #endif
135
136 static void gic_enable_redist(bool enable)
137 {
138         void __iomem *rbase;
139         u32 count = 1000000;    /* 1s! */
140         u32 val;
141
142         rbase = gic_data_rdist_rd_base();
143
144         val = readl_relaxed(rbase + GICR_WAKER);
145         if (enable)
146                 /* Wake up this CPU redistributor */
147                 val &= ~GICR_WAKER_ProcessorSleep;
148         else
149                 val |= GICR_WAKER_ProcessorSleep;
150         writel_relaxed(val, rbase + GICR_WAKER);
151
152         if (!enable) {          /* Check that GICR_WAKER is writeable */
153                 val = readl_relaxed(rbase + GICR_WAKER);
154                 if (!(val & GICR_WAKER_ProcessorSleep))
155                         return; /* No PM support in this redistributor */
156         }
157
158         while (--count) {
159                 val = readl_relaxed(rbase + GICR_WAKER);
160                 if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep))
161                         break;
162                 cpu_relax();
163                 udelay(1);
164         };
165         if (!count)
166                 pr_err_ratelimited("redistributor failed to %s...\n",
167                                    enable ? "wakeup" : "sleep");
168 }
169
170 /*
171  * Routines to disable, enable, EOI and route interrupts
172  */
173 static int gic_peek_irq(struct irq_data *d, u32 offset)
174 {
175         u32 mask = 1 << (gic_irq(d) % 32);
176         void __iomem *base;
177
178         if (gic_irq_in_rdist(d))
179                 base = gic_data_rdist_sgi_base();
180         else
181                 base = gic_data.dist_base;
182
183         return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask);
184 }
185
186 static void gic_poke_irq(struct irq_data *d, u32 offset)
187 {
188         u32 mask = 1 << (gic_irq(d) % 32);
189         void (*rwp_wait)(void);
190         void __iomem *base;
191
192         if (gic_irq_in_rdist(d)) {
193                 base = gic_data_rdist_sgi_base();
194                 rwp_wait = gic_redist_wait_for_rwp;
195         } else {
196                 base = gic_data.dist_base;
197                 rwp_wait = gic_dist_wait_for_rwp;
198         }
199
200         writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4);
201         rwp_wait();
202 }
203
204 static void gic_mask_irq(struct irq_data *d)
205 {
206         gic_poke_irq(d, GICD_ICENABLER);
207 }
208
209 static void gic_eoimode1_mask_irq(struct irq_data *d)
210 {
211         gic_mask_irq(d);
212         /*
213          * When masking a forwarded interrupt, make sure it is
214          * deactivated as well.
215          *
216          * This ensures that an interrupt that is getting
217          * disabled/masked will not get "stuck", because there is
218          * noone to deactivate it (guest is being terminated).
219          */
220         if (irqd_is_forwarded_to_vcpu(d))
221                 gic_poke_irq(d, GICD_ICACTIVER);
222 }
223
224 static void gic_unmask_irq(struct irq_data *d)
225 {
226         gic_poke_irq(d, GICD_ISENABLER);
227 }
228
229 static int gic_irq_set_irqchip_state(struct irq_data *d,
230                                      enum irqchip_irq_state which, bool val)
231 {
232         u32 reg;
233
234         if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */
235                 return -EINVAL;
236
237         switch (which) {
238         case IRQCHIP_STATE_PENDING:
239                 reg = val ? GICD_ISPENDR : GICD_ICPENDR;
240                 break;
241
242         case IRQCHIP_STATE_ACTIVE:
243                 reg = val ? GICD_ISACTIVER : GICD_ICACTIVER;
244                 break;
245
246         case IRQCHIP_STATE_MASKED:
247                 reg = val ? GICD_ICENABLER : GICD_ISENABLER;
248                 break;
249
250         default:
251                 return -EINVAL;
252         }
253
254         gic_poke_irq(d, reg);
255         return 0;
256 }
257
258 static int gic_irq_get_irqchip_state(struct irq_data *d,
259                                      enum irqchip_irq_state which, bool *val)
260 {
261         if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */
262                 return -EINVAL;
263
264         switch (which) {
265         case IRQCHIP_STATE_PENDING:
266                 *val = gic_peek_irq(d, GICD_ISPENDR);
267                 break;
268
269         case IRQCHIP_STATE_ACTIVE:
270                 *val = gic_peek_irq(d, GICD_ISACTIVER);
271                 break;
272
273         case IRQCHIP_STATE_MASKED:
274                 *val = !gic_peek_irq(d, GICD_ISENABLER);
275                 break;
276
277         default:
278                 return -EINVAL;
279         }
280
281         return 0;
282 }
283
284 static void gic_eoi_irq(struct irq_data *d)
285 {
286         gic_write_eoir(gic_irq(d));
287 }
288
289 static void gic_eoimode1_eoi_irq(struct irq_data *d)
290 {
291         /*
292          * No need to deactivate an LPI, or an interrupt that
293          * is is getting forwarded to a vcpu.
294          */
295         if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d))
296                 return;
297         gic_write_dir(gic_irq(d));
298 }
299
300 static int gic_set_type(struct irq_data *d, unsigned int type)
301 {
302         unsigned int irq = gic_irq(d);
303         void (*rwp_wait)(void);
304         void __iomem *base;
305
306         /* Interrupt configuration for SGIs can't be changed */
307         if (irq < 16)
308                 return -EINVAL;
309
310         /* SPIs have restrictions on the supported types */
311         if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
312                          type != IRQ_TYPE_EDGE_RISING)
313                 return -EINVAL;
314
315         if (gic_irq_in_rdist(d)) {
316                 base = gic_data_rdist_sgi_base();
317                 rwp_wait = gic_redist_wait_for_rwp;
318         } else {
319                 base = gic_data.dist_base;
320                 rwp_wait = gic_dist_wait_for_rwp;
321         }
322
323         return gic_configure_irq(irq, type, base, rwp_wait);
324 }
325
326 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
327 {
328         if (vcpu)
329                 irqd_set_forwarded_to_vcpu(d);
330         else
331                 irqd_clr_forwarded_to_vcpu(d);
332         return 0;
333 }
334
335 static u64 gic_mpidr_to_affinity(unsigned long mpidr)
336 {
337         u64 aff;
338
339         aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 |
340                MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
341                MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8  |
342                MPIDR_AFFINITY_LEVEL(mpidr, 0));
343
344         return aff;
345 }
346
347 static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
348 {
349         u32 irqnr;
350
351         do {
352                 irqnr = gic_read_iar();
353
354                 if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) {
355                         int err;
356
357                         if (static_branch_likely(&supports_deactivate_key))
358                                 gic_write_eoir(irqnr);
359                         else
360                                 isb();
361
362                         err = handle_domain_irq(gic_data.domain, irqnr, regs);
363                         if (err) {
364                                 WARN_ONCE(true, "Unexpected interrupt received!\n");
365                                 if (static_branch_likely(&supports_deactivate_key)) {
366                                         if (irqnr < 8192)
367                                                 gic_write_dir(irqnr);
368                                 } else {
369                                         gic_write_eoir(irqnr);
370                                 }
371                         }
372                         continue;
373                 }
374                 if (irqnr < 16) {
375                         gic_write_eoir(irqnr);
376                         if (static_branch_likely(&supports_deactivate_key))
377                                 gic_write_dir(irqnr);
378 #ifdef CONFIG_SMP
379                         /*
380                          * Unlike GICv2, we don't need an smp_rmb() here.
381                          * The control dependency from gic_read_iar to
382                          * the ISB in gic_write_eoir is enough to ensure
383                          * that any shared data read by handle_IPI will
384                          * be read after the ACK.
385                          */
386                         handle_IPI(irqnr, regs);
387 #else
388                         WARN_ONCE(true, "Unexpected SGI received!\n");
389 #endif
390                         continue;
391                 }
392         } while (irqnr != ICC_IAR1_EL1_SPURIOUS);
393 }
394
395 static void __init gic_dist_init(void)
396 {
397         unsigned int i;
398         u64 affinity;
399         void __iomem *base = gic_data.dist_base;
400
401         /* Disable the distributor */
402         writel_relaxed(0, base + GICD_CTLR);
403         gic_dist_wait_for_rwp();
404
405         /*
406          * Configure SPIs as non-secure Group-1. This will only matter
407          * if the GIC only has a single security state. This will not
408          * do the right thing if the kernel is running in secure mode,
409          * but that's not the intended use case anyway.
410          */
411         for (i = 32; i < gic_data.irq_nr; i += 32)
412                 writel_relaxed(~0, base + GICD_IGROUPR + i / 8);
413
414         gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp);
415
416         /* Enable distributor with ARE, Group1 */
417         writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1,
418                        base + GICD_CTLR);
419
420         /*
421          * Set all global interrupts to the boot CPU only. ARE must be
422          * enabled.
423          */
424         affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id()));
425         for (i = 32; i < gic_data.irq_nr; i++)
426                 gic_write_irouter(affinity, base + GICD_IROUTER + i * 8);
427 }
428
429 static int gic_iterate_rdists(int (*fn)(struct redist_region *, void __iomem *))
430 {
431         int ret = -ENODEV;
432         int i;
433
434         for (i = 0; i < gic_data.nr_redist_regions; i++) {
435                 void __iomem *ptr = gic_data.redist_regions[i].redist_base;
436                 u64 typer;
437                 u32 reg;
438
439                 reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK;
440                 if (reg != GIC_PIDR2_ARCH_GICv3 &&
441                     reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */
442                         pr_warn("No redistributor present @%p\n", ptr);
443                         break;
444                 }
445
446                 do {
447                         typer = gic_read_typer(ptr + GICR_TYPER);
448                         ret = fn(gic_data.redist_regions + i, ptr);
449                         if (!ret)
450                                 return 0;
451
452                         if (gic_data.redist_regions[i].single_redist)
453                                 break;
454
455                         if (gic_data.redist_stride) {
456                                 ptr += gic_data.redist_stride;
457                         } else {
458                                 ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */
459                                 if (typer & GICR_TYPER_VLPIS)
460                                         ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */
461                         }
462                 } while (!(typer & GICR_TYPER_LAST));
463         }
464
465         return ret ? -ENODEV : 0;
466 }
467
468 static int __gic_populate_rdist(struct redist_region *region, void __iomem *ptr)
469 {
470         unsigned long mpidr = cpu_logical_map(smp_processor_id());
471         u64 typer;
472         u32 aff;
473
474         /*
475          * Convert affinity to a 32bit value that can be matched to
476          * GICR_TYPER bits [63:32].
477          */
478         aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 |
479                MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
480                MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
481                MPIDR_AFFINITY_LEVEL(mpidr, 0));
482
483         typer = gic_read_typer(ptr + GICR_TYPER);
484         if ((typer >> 32) == aff) {
485                 u64 offset = ptr - region->redist_base;
486                 gic_data_rdist_rd_base() = ptr;
487                 gic_data_rdist()->phys_base = region->phys_base + offset;
488
489                 pr_info("CPU%d: found redistributor %lx region %d:%pa\n",
490                         smp_processor_id(), mpidr,
491                         (int)(region - gic_data.redist_regions),
492                         &gic_data_rdist()->phys_base);
493                 return 0;
494         }
495
496         /* Try next one */
497         return 1;
498 }
499
500 static int gic_populate_rdist(void)
501 {
502         if (gic_iterate_rdists(__gic_populate_rdist) == 0)
503                 return 0;
504
505         /* We couldn't even deal with ourselves... */
506         WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n",
507              smp_processor_id(),
508              (unsigned long)cpu_logical_map(smp_processor_id()));
509         return -ENODEV;
510 }
511
512 static int __gic_update_vlpi_properties(struct redist_region *region,
513                                         void __iomem *ptr)
514 {
515         u64 typer = gic_read_typer(ptr + GICR_TYPER);
516         gic_data.rdists.has_vlpis &= !!(typer & GICR_TYPER_VLPIS);
517         gic_data.rdists.has_direct_lpi &= !!(typer & GICR_TYPER_DirectLPIS);
518
519         return 1;
520 }
521
522 static void gic_update_vlpi_properties(void)
523 {
524         gic_iterate_rdists(__gic_update_vlpi_properties);
525         pr_info("%sVLPI support, %sdirect LPI support\n",
526                 !gic_data.rdists.has_vlpis ? "no " : "",
527                 !gic_data.rdists.has_direct_lpi ? "no " : "");
528 }
529
530 static void gic_cpu_sys_reg_init(void)
531 {
532         int i, cpu = smp_processor_id();
533         u64 mpidr = cpu_logical_map(cpu);
534         u64 need_rss = MPIDR_RS(mpidr);
535         bool group0;
536         u32 val, pribits;
537
538         /*
539          * Need to check that the SRE bit has actually been set. If
540          * not, it means that SRE is disabled at EL2. We're going to
541          * die painfully, and there is nothing we can do about it.
542          *
543          * Kindly inform the luser.
544          */
545         if (!gic_enable_sre())
546                 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
547
548         pribits = gic_read_ctlr();
549         pribits &= ICC_CTLR_EL1_PRI_BITS_MASK;
550         pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT;
551         pribits++;
552
553         /*
554          * Let's find out if Group0 is under control of EL3 or not by
555          * setting the highest possible, non-zero priority in PMR.
556          *
557          * If SCR_EL3.FIQ is set, the priority gets shifted down in
558          * order for the CPU interface to set bit 7, and keep the
559          * actual priority in the non-secure range. In the process, it
560          * looses the least significant bit and the actual priority
561          * becomes 0x80. Reading it back returns 0, indicating that
562          * we're don't have access to Group0.
563          */
564         write_gicreg(BIT(8 - pribits), ICC_PMR_EL1);
565         val = read_gicreg(ICC_PMR_EL1);
566         group0 = val != 0;
567
568         /* Set priority mask register */
569         write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1);
570
571         /*
572          * Some firmwares hand over to the kernel with the BPR changed from
573          * its reset value (and with a value large enough to prevent
574          * any pre-emptive interrupts from working at all). Writing a zero
575          * to BPR restores is reset value.
576          */
577         gic_write_bpr1(0);
578
579         if (static_branch_likely(&supports_deactivate_key)) {
580                 /* EOI drops priority only (mode 1) */
581                 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop);
582         } else {
583                 /* EOI deactivates interrupt too (mode 0) */
584                 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir);
585         }
586
587         /* Always whack Group0 before Group1 */
588         if (group0) {
589                 switch(pribits) {
590                 case 8:
591                 case 7:
592                         write_gicreg(0, ICC_AP0R3_EL1);
593                         write_gicreg(0, ICC_AP0R2_EL1);
594                 case 6:
595                         write_gicreg(0, ICC_AP0R1_EL1);
596                 case 5:
597                 case 4:
598                         write_gicreg(0, ICC_AP0R0_EL1);
599                 }
600
601                 isb();
602         }
603
604         switch(pribits) {
605         case 8:
606         case 7:
607                 write_gicreg(0, ICC_AP1R3_EL1);
608                 write_gicreg(0, ICC_AP1R2_EL1);
609         case 6:
610                 write_gicreg(0, ICC_AP1R1_EL1);
611         case 5:
612         case 4:
613                 write_gicreg(0, ICC_AP1R0_EL1);
614         }
615
616         isb();
617
618         /* ... and let's hit the road... */
619         gic_write_grpen1(1);
620
621         /* Keep the RSS capability status in per_cpu variable */
622         per_cpu(has_rss, cpu) = !!(gic_read_ctlr() & ICC_CTLR_EL1_RSS);
623
624         /* Check all the CPUs have capable of sending SGIs to other CPUs */
625         for_each_online_cpu(i) {
626                 bool have_rss = per_cpu(has_rss, i) && per_cpu(has_rss, cpu);
627
628                 need_rss |= MPIDR_RS(cpu_logical_map(i));
629                 if (need_rss && (!have_rss))
630                         pr_crit("CPU%d (%lx) can't SGI CPU%d (%lx), no RSS\n",
631                                 cpu, (unsigned long)mpidr,
632                                 i, (unsigned long)cpu_logical_map(i));
633         }
634
635         /**
636          * GIC spec says, when ICC_CTLR_EL1.RSS==1 and GICD_TYPER.RSS==0,
637          * writing ICC_ASGI1R_EL1 register with RS != 0 is a CONSTRAINED
638          * UNPREDICTABLE choice of :
639          *   - The write is ignored.
640          *   - The RS field is treated as 0.
641          */
642         if (need_rss && (!gic_data.has_rss))
643                 pr_crit_once("RSS is required but GICD doesn't support it\n");
644 }
645
646 static bool gicv3_nolpi;
647
648 static int __init gicv3_nolpi_cfg(char *buf)
649 {
650         return strtobool(buf, &gicv3_nolpi);
651 }
652 early_param("irqchip.gicv3_nolpi", gicv3_nolpi_cfg);
653
654 static int gic_dist_supports_lpis(void)
655 {
656         return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS) && !gicv3_nolpi;
657 }
658
659 static void gic_cpu_init(void)
660 {
661         void __iomem *rbase;
662
663         /* Register ourselves with the rest of the world */
664         if (gic_populate_rdist())
665                 return;
666
667         gic_enable_redist(true);
668
669         rbase = gic_data_rdist_sgi_base();
670
671         /* Configure SGIs/PPIs as non-secure Group-1 */
672         writel_relaxed(~0, rbase + GICR_IGROUPR0);
673
674         gic_cpu_config(rbase, gic_redist_wait_for_rwp);
675
676         /* Give LPIs a spin */
677         if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
678                 its_cpu_init();
679
680         /* initialise system registers */
681         gic_cpu_sys_reg_init();
682 }
683
684 #ifdef CONFIG_SMP
685
686 #define MPIDR_TO_SGI_RS(mpidr)  (MPIDR_RS(mpidr) << ICC_SGI1R_RS_SHIFT)
687 #define MPIDR_TO_SGI_CLUSTER_ID(mpidr)  ((mpidr) & ~0xFUL)
688
689 static int gic_starting_cpu(unsigned int cpu)
690 {
691         gic_cpu_init();
692         return 0;
693 }
694
695 static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask,
696                                    unsigned long cluster_id)
697 {
698         int next_cpu, cpu = *base_cpu;
699         unsigned long mpidr = cpu_logical_map(cpu);
700         u16 tlist = 0;
701
702         while (cpu < nr_cpu_ids) {
703                 tlist |= 1 << (mpidr & 0xf);
704
705                 next_cpu = cpumask_next(cpu, mask);
706                 if (next_cpu >= nr_cpu_ids)
707                         goto out;
708                 cpu = next_cpu;
709
710                 mpidr = cpu_logical_map(cpu);
711
712                 if (cluster_id != MPIDR_TO_SGI_CLUSTER_ID(mpidr)) {
713                         cpu--;
714                         goto out;
715                 }
716         }
717 out:
718         *base_cpu = cpu;
719         return tlist;
720 }
721
722 #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \
723         (MPIDR_AFFINITY_LEVEL(cluster_id, level) \
724                 << ICC_SGI1R_AFFINITY_## level ##_SHIFT)
725
726 static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq)
727 {
728         u64 val;
729
730         val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3)     |
731                MPIDR_TO_SGI_AFFINITY(cluster_id, 2)     |
732                irq << ICC_SGI1R_SGI_ID_SHIFT            |
733                MPIDR_TO_SGI_AFFINITY(cluster_id, 1)     |
734                MPIDR_TO_SGI_RS(cluster_id)              |
735                tlist << ICC_SGI1R_TARGET_LIST_SHIFT);
736
737         pr_devel("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val);
738         gic_write_sgi1r(val);
739 }
740
741 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
742 {
743         int cpu;
744
745         if (WARN_ON(irq >= 16))
746                 return;
747
748         /*
749          * Ensure that stores to Normal memory are visible to the
750          * other CPUs before issuing the IPI.
751          */
752         wmb();
753
754         for_each_cpu(cpu, mask) {
755                 u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu));
756                 u16 tlist;
757
758                 tlist = gic_compute_target_list(&cpu, mask, cluster_id);
759                 gic_send_sgi(cluster_id, tlist, irq);
760         }
761
762         /* Force the above writes to ICC_SGI1R_EL1 to be executed */
763         isb();
764 }
765
766 static void gic_smp_init(void)
767 {
768         set_smp_cross_call(gic_raise_softirq);
769         cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING,
770                                   "irqchip/arm/gicv3:starting",
771                                   gic_starting_cpu, NULL);
772 }
773
774 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
775                             bool force)
776 {
777         unsigned int cpu;
778         void __iomem *reg;
779         int enabled;
780         u64 val;
781
782         if (force)
783                 cpu = cpumask_first(mask_val);
784         else
785                 cpu = cpumask_any_and(mask_val, cpu_online_mask);
786
787         if (cpu >= nr_cpu_ids)
788                 return -EINVAL;
789
790         if (gic_irq_in_rdist(d))
791                 return -EINVAL;
792
793         /* If interrupt was enabled, disable it first */
794         enabled = gic_peek_irq(d, GICD_ISENABLER);
795         if (enabled)
796                 gic_mask_irq(d);
797
798         reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8);
799         val = gic_mpidr_to_affinity(cpu_logical_map(cpu));
800
801         gic_write_irouter(val, reg);
802
803         /*
804          * If the interrupt was enabled, enabled it again. Otherwise,
805          * just wait for the distributor to have digested our changes.
806          */
807         if (enabled)
808                 gic_unmask_irq(d);
809         else
810                 gic_dist_wait_for_rwp();
811
812         irq_data_update_effective_affinity(d, cpumask_of(cpu));
813
814         return IRQ_SET_MASK_OK_DONE;
815 }
816 #else
817 #define gic_set_affinity        NULL
818 #define gic_smp_init()          do { } while(0)
819 #endif
820
821 #ifdef CONFIG_CPU_PM
822 /* Check whether it's single security state view */
823 static bool gic_dist_security_disabled(void)
824 {
825         return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS;
826 }
827
828 static int gic_cpu_pm_notifier(struct notifier_block *self,
829                                unsigned long cmd, void *v)
830 {
831         if (cmd == CPU_PM_EXIT) {
832                 if (gic_dist_security_disabled())
833                         gic_enable_redist(true);
834                 gic_cpu_sys_reg_init();
835         } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) {
836                 gic_write_grpen1(0);
837                 gic_enable_redist(false);
838         }
839         return NOTIFY_OK;
840 }
841
842 static struct notifier_block gic_cpu_pm_notifier_block = {
843         .notifier_call = gic_cpu_pm_notifier,
844 };
845
846 static void gic_cpu_pm_init(void)
847 {
848         cpu_pm_register_notifier(&gic_cpu_pm_notifier_block);
849 }
850
851 #else
852 static inline void gic_cpu_pm_init(void) { }
853 #endif /* CONFIG_CPU_PM */
854
855 static struct irq_chip gic_chip = {
856         .name                   = "GICv3",
857         .irq_mask               = gic_mask_irq,
858         .irq_unmask             = gic_unmask_irq,
859         .irq_eoi                = gic_eoi_irq,
860         .irq_set_type           = gic_set_type,
861         .irq_set_affinity       = gic_set_affinity,
862         .irq_get_irqchip_state  = gic_irq_get_irqchip_state,
863         .irq_set_irqchip_state  = gic_irq_set_irqchip_state,
864         .flags                  = IRQCHIP_SET_TYPE_MASKED |
865                                   IRQCHIP_SKIP_SET_WAKE |
866                                   IRQCHIP_MASK_ON_SUSPEND,
867 };
868
869 static struct irq_chip gic_eoimode1_chip = {
870         .name                   = "GICv3",
871         .irq_mask               = gic_eoimode1_mask_irq,
872         .irq_unmask             = gic_unmask_irq,
873         .irq_eoi                = gic_eoimode1_eoi_irq,
874         .irq_set_type           = gic_set_type,
875         .irq_set_affinity       = gic_set_affinity,
876         .irq_get_irqchip_state  = gic_irq_get_irqchip_state,
877         .irq_set_irqchip_state  = gic_irq_set_irqchip_state,
878         .irq_set_vcpu_affinity  = gic_irq_set_vcpu_affinity,
879         .flags                  = IRQCHIP_SET_TYPE_MASKED |
880                                   IRQCHIP_SKIP_SET_WAKE |
881                                   IRQCHIP_MASK_ON_SUSPEND,
882 };
883
884 #define GIC_ID_NR       (1U << GICD_TYPER_ID_BITS(gic_data.rdists.gicd_typer))
885
886 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
887                               irq_hw_number_t hw)
888 {
889         struct irq_chip *chip = &gic_chip;
890
891         if (static_branch_likely(&supports_deactivate_key))
892                 chip = &gic_eoimode1_chip;
893
894         /* SGIs are private to the core kernel */
895         if (hw < 16)
896                 return -EPERM;
897         /* Nothing here */
898         if (hw >= gic_data.irq_nr && hw < 8192)
899                 return -EPERM;
900         /* Off limits */
901         if (hw >= GIC_ID_NR)
902                 return -EPERM;
903
904         /* PPIs */
905         if (hw < 32) {
906                 irq_set_percpu_devid(irq);
907                 irq_domain_set_info(d, irq, hw, chip, d->host_data,
908                                     handle_percpu_devid_irq, NULL, NULL);
909                 irq_set_status_flags(irq, IRQ_NOAUTOEN);
910         }
911         /* SPIs */
912         if (hw >= 32 && hw < gic_data.irq_nr) {
913                 irq_domain_set_info(d, irq, hw, chip, d->host_data,
914                                     handle_fasteoi_irq, NULL, NULL);
915                 irq_set_probe(irq);
916                 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq)));
917         }
918         /* LPIs */
919         if (hw >= 8192 && hw < GIC_ID_NR) {
920                 if (!gic_dist_supports_lpis())
921                         return -EPERM;
922                 irq_domain_set_info(d, irq, hw, chip, d->host_data,
923                                     handle_fasteoi_irq, NULL, NULL);
924         }
925
926         return 0;
927 }
928
929 #define GIC_IRQ_TYPE_PARTITION  (GIC_IRQ_TYPE_LPI + 1)
930
931 static int gic_irq_domain_translate(struct irq_domain *d,
932                                     struct irq_fwspec *fwspec,
933                                     unsigned long *hwirq,
934                                     unsigned int *type)
935 {
936         if (is_of_node(fwspec->fwnode)) {
937                 if (fwspec->param_count < 3)
938                         return -EINVAL;
939
940                 switch (fwspec->param[0]) {
941                 case 0:                 /* SPI */
942                         *hwirq = fwspec->param[1] + 32;
943                         break;
944                 case 1:                 /* PPI */
945                 case GIC_IRQ_TYPE_PARTITION:
946                         *hwirq = fwspec->param[1] + 16;
947                         break;
948                 case GIC_IRQ_TYPE_LPI:  /* LPI */
949                         *hwirq = fwspec->param[1];
950                         break;
951                 default:
952                         return -EINVAL;
953                 }
954
955                 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
956
957                 /*
958                  * Make it clear that broken DTs are... broken.
959                  * Partitionned PPIs are an unfortunate exception.
960                  */
961                 WARN_ON(*type == IRQ_TYPE_NONE &&
962                         fwspec->param[0] != GIC_IRQ_TYPE_PARTITION);
963                 return 0;
964         }
965
966         if (is_fwnode_irqchip(fwspec->fwnode)) {
967                 if(fwspec->param_count != 2)
968                         return -EINVAL;
969
970                 *hwirq = fwspec->param[0];
971                 *type = fwspec->param[1];
972
973                 WARN_ON(*type == IRQ_TYPE_NONE);
974                 return 0;
975         }
976
977         return -EINVAL;
978 }
979
980 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
981                                 unsigned int nr_irqs, void *arg)
982 {
983         int i, ret;
984         irq_hw_number_t hwirq;
985         unsigned int type = IRQ_TYPE_NONE;
986         struct irq_fwspec *fwspec = arg;
987
988         ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type);
989         if (ret)
990                 return ret;
991
992         for (i = 0; i < nr_irqs; i++) {
993                 ret = gic_irq_domain_map(domain, virq + i, hwirq + i);
994                 if (ret)
995                         return ret;
996         }
997
998         return 0;
999 }
1000
1001 static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq,
1002                                 unsigned int nr_irqs)
1003 {
1004         int i;
1005
1006         for (i = 0; i < nr_irqs; i++) {
1007                 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
1008                 irq_set_handler(virq + i, NULL);
1009                 irq_domain_reset_irq_data(d);
1010         }
1011 }
1012
1013 static int gic_irq_domain_select(struct irq_domain *d,
1014                                  struct irq_fwspec *fwspec,
1015                                  enum irq_domain_bus_token bus_token)
1016 {
1017         /* Not for us */
1018         if (fwspec->fwnode != d->fwnode)
1019                 return 0;
1020
1021         /* If this is not DT, then we have a single domain */
1022         if (!is_of_node(fwspec->fwnode))
1023                 return 1;
1024
1025         /*
1026          * If this is a PPI and we have a 4th (non-null) parameter,
1027          * then we need to match the partition domain.
1028          */
1029         if (fwspec->param_count >= 4 &&
1030             fwspec->param[0] == 1 && fwspec->param[3] != 0)
1031                 return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]);
1032
1033         return d == gic_data.domain;
1034 }
1035
1036 static const struct irq_domain_ops gic_irq_domain_ops = {
1037         .translate = gic_irq_domain_translate,
1038         .alloc = gic_irq_domain_alloc,
1039         .free = gic_irq_domain_free,
1040         .select = gic_irq_domain_select,
1041 };
1042
1043 static int partition_domain_translate(struct irq_domain *d,
1044                                       struct irq_fwspec *fwspec,
1045                                       unsigned long *hwirq,
1046                                       unsigned int *type)
1047 {
1048         struct device_node *np;
1049         int ret;
1050
1051         np = of_find_node_by_phandle(fwspec->param[3]);
1052         if (WARN_ON(!np))
1053                 return -EINVAL;
1054
1055         ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]],
1056                                      of_node_to_fwnode(np));
1057         if (ret < 0)
1058                 return ret;
1059
1060         *hwirq = ret;
1061         *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
1062
1063         return 0;
1064 }
1065
1066 static const struct irq_domain_ops partition_domain_ops = {
1067         .translate = partition_domain_translate,
1068         .select = gic_irq_domain_select,
1069 };
1070
1071 static int __init gic_init_bases(void __iomem *dist_base,
1072                                  struct redist_region *rdist_regs,
1073                                  u32 nr_redist_regions,
1074                                  u64 redist_stride,
1075                                  struct fwnode_handle *handle)
1076 {
1077         u32 typer;
1078         int gic_irqs;
1079         int err;
1080
1081         if (!is_hyp_mode_available())
1082                 static_branch_disable(&supports_deactivate_key);
1083
1084         if (static_branch_likely(&supports_deactivate_key))
1085                 pr_info("GIC: Using split EOI/Deactivate mode\n");
1086
1087         gic_data.fwnode = handle;
1088         gic_data.dist_base = dist_base;
1089         gic_data.redist_regions = rdist_regs;
1090         gic_data.nr_redist_regions = nr_redist_regions;
1091         gic_data.redist_stride = redist_stride;
1092
1093         /*
1094          * Find out how many interrupts are supported.
1095          * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI)
1096          */
1097         typer = readl_relaxed(gic_data.dist_base + GICD_TYPER);
1098         gic_data.rdists.gicd_typer = typer;
1099         gic_irqs = GICD_TYPER_IRQS(typer);
1100         if (gic_irqs > 1020)
1101                 gic_irqs = 1020;
1102         gic_data.irq_nr = gic_irqs;
1103
1104         gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops,
1105                                                  &gic_data);
1106         irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED);
1107         gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist));
1108         gic_data.rdists.has_vlpis = true;
1109         gic_data.rdists.has_direct_lpi = true;
1110
1111         if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) {
1112                 err = -ENOMEM;
1113                 goto out_free;
1114         }
1115
1116         gic_data.has_rss = !!(typer & GICD_TYPER_RSS);
1117         pr_info("Distributor has %sRange Selector support\n",
1118                 gic_data.has_rss ? "" : "no ");
1119
1120         if (typer & GICD_TYPER_MBIS) {
1121                 err = mbi_init(handle, gic_data.domain);
1122                 if (err)
1123                         pr_err("Failed to initialize MBIs\n");
1124         }
1125
1126         set_handle_irq(gic_handle_irq);
1127
1128         gic_update_vlpi_properties();
1129
1130         if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
1131                 its_init(handle, &gic_data.rdists, gic_data.domain);
1132
1133         gic_smp_init();
1134         gic_dist_init();
1135         gic_cpu_init();
1136         gic_cpu_pm_init();
1137
1138         return 0;
1139
1140 out_free:
1141         if (gic_data.domain)
1142                 irq_domain_remove(gic_data.domain);
1143         free_percpu(gic_data.rdists.rdist);
1144         return err;
1145 }
1146
1147 static int __init gic_validate_dist_version(void __iomem *dist_base)
1148 {
1149         u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
1150
1151         if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4)
1152                 return -ENODEV;
1153
1154         return 0;
1155 }
1156
1157 /* Create all possible partitions at boot time */
1158 static void __init gic_populate_ppi_partitions(struct device_node *gic_node)
1159 {
1160         struct device_node *parts_node, *child_part;
1161         int part_idx = 0, i;
1162         int nr_parts;
1163         struct partition_affinity *parts;
1164
1165         parts_node = of_get_child_by_name(gic_node, "ppi-partitions");
1166         if (!parts_node)
1167                 return;
1168
1169         nr_parts = of_get_child_count(parts_node);
1170
1171         if (!nr_parts)
1172                 goto out_put_node;
1173
1174         parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL);
1175         if (WARN_ON(!parts))
1176                 goto out_put_node;
1177
1178         for_each_child_of_node(parts_node, child_part) {
1179                 struct partition_affinity *part;
1180                 int n;
1181
1182                 part = &parts[part_idx];
1183
1184                 part->partition_id = of_node_to_fwnode(child_part);
1185
1186                 pr_info("GIC: PPI partition %s[%d] { ",
1187                         child_part->name, part_idx);
1188
1189                 n = of_property_count_elems_of_size(child_part, "affinity",
1190                                                     sizeof(u32));
1191                 WARN_ON(n <= 0);
1192
1193                 for (i = 0; i < n; i++) {
1194                         int err, cpu;
1195                         u32 cpu_phandle;
1196                         struct device_node *cpu_node;
1197
1198                         err = of_property_read_u32_index(child_part, "affinity",
1199                                                          i, &cpu_phandle);
1200                         if (WARN_ON(err))
1201                                 continue;
1202
1203                         cpu_node = of_find_node_by_phandle(cpu_phandle);
1204                         if (WARN_ON(!cpu_node))
1205                                 continue;
1206
1207                         cpu = of_cpu_node_to_id(cpu_node);
1208                         if (WARN_ON(cpu < 0))
1209                                 continue;
1210
1211                         pr_cont("%pOF[%d] ", cpu_node, cpu);
1212
1213                         cpumask_set_cpu(cpu, &part->mask);
1214                 }
1215
1216                 pr_cont("}\n");
1217                 part_idx++;
1218         }
1219
1220         for (i = 0; i < 16; i++) {
1221                 unsigned int irq;
1222                 struct partition_desc *desc;
1223                 struct irq_fwspec ppi_fwspec = {
1224                         .fwnode         = gic_data.fwnode,
1225                         .param_count    = 3,
1226                         .param          = {
1227                                 [0]     = GIC_IRQ_TYPE_PARTITION,
1228                                 [1]     = i,
1229                                 [2]     = IRQ_TYPE_NONE,
1230                         },
1231                 };
1232
1233                 irq = irq_create_fwspec_mapping(&ppi_fwspec);
1234                 if (WARN_ON(!irq))
1235                         continue;
1236                 desc = partition_create_desc(gic_data.fwnode, parts, nr_parts,
1237                                              irq, &partition_domain_ops);
1238                 if (WARN_ON(!desc))
1239                         continue;
1240
1241                 gic_data.ppi_descs[i] = desc;
1242         }
1243
1244 out_put_node:
1245         of_node_put(parts_node);
1246 }
1247
1248 static void __init gic_of_setup_kvm_info(struct device_node *node)
1249 {
1250         int ret;
1251         struct resource r;
1252         u32 gicv_idx;
1253
1254         gic_v3_kvm_info.type = GIC_V3;
1255
1256         gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0);
1257         if (!gic_v3_kvm_info.maint_irq)
1258                 return;
1259
1260         if (of_property_read_u32(node, "#redistributor-regions",
1261                                  &gicv_idx))
1262                 gicv_idx = 1;
1263
1264         gicv_idx += 3;  /* Also skip GICD, GICC, GICH */
1265         ret = of_address_to_resource(node, gicv_idx, &r);
1266         if (!ret)
1267                 gic_v3_kvm_info.vcpu = r;
1268
1269         gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis;
1270         gic_set_kvm_info(&gic_v3_kvm_info);
1271 }
1272
1273 static int __init gic_of_init(struct device_node *node, struct device_node *parent)
1274 {
1275         void __iomem *dist_base;
1276         struct redist_region *rdist_regs;
1277         u64 redist_stride;
1278         u32 nr_redist_regions;
1279         int err, i;
1280
1281         dist_base = of_iomap(node, 0);
1282         if (!dist_base) {
1283                 pr_err("%pOF: unable to map gic dist registers\n", node);
1284                 return -ENXIO;
1285         }
1286
1287         err = gic_validate_dist_version(dist_base);
1288         if (err) {
1289                 pr_err("%pOF: no distributor detected, giving up\n", node);
1290                 goto out_unmap_dist;
1291         }
1292
1293         if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions))
1294                 nr_redist_regions = 1;
1295
1296         rdist_regs = kcalloc(nr_redist_regions, sizeof(*rdist_regs),
1297                              GFP_KERNEL);
1298         if (!rdist_regs) {
1299                 err = -ENOMEM;
1300                 goto out_unmap_dist;
1301         }
1302
1303         for (i = 0; i < nr_redist_regions; i++) {
1304                 struct resource res;
1305                 int ret;
1306
1307                 ret = of_address_to_resource(node, 1 + i, &res);
1308                 rdist_regs[i].redist_base = of_iomap(node, 1 + i);
1309                 if (ret || !rdist_regs[i].redist_base) {
1310                         pr_err("%pOF: couldn't map region %d\n", node, i);
1311                         err = -ENODEV;
1312                         goto out_unmap_rdist;
1313                 }
1314                 rdist_regs[i].phys_base = res.start;
1315         }
1316
1317         if (of_property_read_u64(node, "redistributor-stride", &redist_stride))
1318                 redist_stride = 0;
1319
1320         err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions,
1321                              redist_stride, &node->fwnode);
1322         if (err)
1323                 goto out_unmap_rdist;
1324
1325         gic_populate_ppi_partitions(node);
1326
1327         if (static_branch_likely(&supports_deactivate_key))
1328                 gic_of_setup_kvm_info(node);
1329         return 0;
1330
1331 out_unmap_rdist:
1332         for (i = 0; i < nr_redist_regions; i++)
1333                 if (rdist_regs[i].redist_base)
1334                         iounmap(rdist_regs[i].redist_base);
1335         kfree(rdist_regs);
1336 out_unmap_dist:
1337         iounmap(dist_base);
1338         return err;
1339 }
1340
1341 IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
1342
1343 #ifdef CONFIG_ACPI
1344 static struct
1345 {
1346         void __iomem *dist_base;
1347         struct redist_region *redist_regs;
1348         u32 nr_redist_regions;
1349         bool single_redist;
1350         u32 maint_irq;
1351         int maint_irq_mode;
1352         phys_addr_t vcpu_base;
1353 } acpi_data __initdata;
1354
1355 static void __init
1356 gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base)
1357 {
1358         static int count = 0;
1359
1360         acpi_data.redist_regs[count].phys_base = phys_base;
1361         acpi_data.redist_regs[count].redist_base = redist_base;
1362         acpi_data.redist_regs[count].single_redist = acpi_data.single_redist;
1363         count++;
1364 }
1365
1366 static int __init
1367 gic_acpi_parse_madt_redist(struct acpi_subtable_header *header,
1368                            const unsigned long end)
1369 {
1370         struct acpi_madt_generic_redistributor *redist =
1371                         (struct acpi_madt_generic_redistributor *)header;
1372         void __iomem *redist_base;
1373
1374         redist_base = ioremap(redist->base_address, redist->length);
1375         if (!redist_base) {
1376                 pr_err("Couldn't map GICR region @%llx\n", redist->base_address);
1377                 return -ENOMEM;
1378         }
1379
1380         gic_acpi_register_redist(redist->base_address, redist_base);
1381         return 0;
1382 }
1383
1384 static int __init
1385 gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header,
1386                          const unsigned long end)
1387 {
1388         struct acpi_madt_generic_interrupt *gicc =
1389                                 (struct acpi_madt_generic_interrupt *)header;
1390         u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
1391         u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2;
1392         void __iomem *redist_base;
1393
1394         /* GICC entry which has !ACPI_MADT_ENABLED is not unusable so skip */
1395         if (!(gicc->flags & ACPI_MADT_ENABLED))
1396                 return 0;
1397
1398         redist_base = ioremap(gicc->gicr_base_address, size);
1399         if (!redist_base)
1400                 return -ENOMEM;
1401
1402         gic_acpi_register_redist(gicc->gicr_base_address, redist_base);
1403         return 0;
1404 }
1405
1406 static int __init gic_acpi_collect_gicr_base(void)
1407 {
1408         acpi_tbl_entry_handler redist_parser;
1409         enum acpi_madt_type type;
1410
1411         if (acpi_data.single_redist) {
1412                 type = ACPI_MADT_TYPE_GENERIC_INTERRUPT;
1413                 redist_parser = gic_acpi_parse_madt_gicc;
1414         } else {
1415                 type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR;
1416                 redist_parser = gic_acpi_parse_madt_redist;
1417         }
1418
1419         /* Collect redistributor base addresses in GICR entries */
1420         if (acpi_table_parse_madt(type, redist_parser, 0) > 0)
1421                 return 0;
1422
1423         pr_info("No valid GICR entries exist\n");
1424         return -ENODEV;
1425 }
1426
1427 static int __init gic_acpi_match_gicr(struct acpi_subtable_header *header,
1428                                   const unsigned long end)
1429 {
1430         /* Subtable presence means that redist exists, that's it */
1431         return 0;
1432 }
1433
1434 static int __init gic_acpi_match_gicc(struct acpi_subtable_header *header,
1435                                       const unsigned long end)
1436 {
1437         struct acpi_madt_generic_interrupt *gicc =
1438                                 (struct acpi_madt_generic_interrupt *)header;
1439
1440         /*
1441          * If GICC is enabled and has valid gicr base address, then it means
1442          * GICR base is presented via GICC
1443          */
1444         if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address)
1445                 return 0;
1446
1447         /*
1448          * It's perfectly valid firmware can pass disabled GICC entry, driver
1449          * should not treat as errors, skip the entry instead of probe fail.
1450          */
1451         if (!(gicc->flags & ACPI_MADT_ENABLED))
1452                 return 0;
1453
1454         return -ENODEV;
1455 }
1456
1457 static int __init gic_acpi_count_gicr_regions(void)
1458 {
1459         int count;
1460
1461         /*
1462          * Count how many redistributor regions we have. It is not allowed
1463          * to mix redistributor description, GICR and GICC subtables have to be
1464          * mutually exclusive.
1465          */
1466         count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
1467                                       gic_acpi_match_gicr, 0);
1468         if (count > 0) {
1469                 acpi_data.single_redist = false;
1470                 return count;
1471         }
1472
1473         count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
1474                                       gic_acpi_match_gicc, 0);
1475         if (count > 0)
1476                 acpi_data.single_redist = true;
1477
1478         return count;
1479 }
1480
1481 static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header,
1482                                            struct acpi_probe_entry *ape)
1483 {
1484         struct acpi_madt_generic_distributor *dist;
1485         int count;
1486
1487         dist = (struct acpi_madt_generic_distributor *)header;
1488         if (dist->version != ape->driver_data)
1489                 return false;
1490
1491         /* We need to do that exercise anyway, the sooner the better */
1492         count = gic_acpi_count_gicr_regions();
1493         if (count <= 0)
1494                 return false;
1495
1496         acpi_data.nr_redist_regions = count;
1497         return true;
1498 }
1499
1500 static int __init gic_acpi_parse_virt_madt_gicc(struct acpi_subtable_header *header,
1501                                                 const unsigned long end)
1502 {
1503         struct acpi_madt_generic_interrupt *gicc =
1504                 (struct acpi_madt_generic_interrupt *)header;
1505         int maint_irq_mode;
1506         static int first_madt = true;
1507
1508         /* Skip unusable CPUs */
1509         if (!(gicc->flags & ACPI_MADT_ENABLED))
1510                 return 0;
1511
1512         maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ?
1513                 ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE;
1514
1515         if (first_madt) {
1516                 first_madt = false;
1517
1518                 acpi_data.maint_irq = gicc->vgic_interrupt;
1519                 acpi_data.maint_irq_mode = maint_irq_mode;
1520                 acpi_data.vcpu_base = gicc->gicv_base_address;
1521
1522                 return 0;
1523         }
1524
1525         /*
1526          * The maintenance interrupt and GICV should be the same for every CPU
1527          */
1528         if ((acpi_data.maint_irq != gicc->vgic_interrupt) ||
1529             (acpi_data.maint_irq_mode != maint_irq_mode) ||
1530             (acpi_data.vcpu_base != gicc->gicv_base_address))
1531                 return -EINVAL;
1532
1533         return 0;
1534 }
1535
1536 static bool __init gic_acpi_collect_virt_info(void)
1537 {
1538         int count;
1539
1540         count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
1541                                       gic_acpi_parse_virt_madt_gicc, 0);
1542
1543         return (count > 0);
1544 }
1545
1546 #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K)
1547 #define ACPI_GICV2_VCTRL_MEM_SIZE       (SZ_4K)
1548 #define ACPI_GICV2_VCPU_MEM_SIZE        (SZ_8K)
1549
1550 static void __init gic_acpi_setup_kvm_info(void)
1551 {
1552         int irq;
1553
1554         if (!gic_acpi_collect_virt_info()) {
1555                 pr_warn("Unable to get hardware information used for virtualization\n");
1556                 return;
1557         }
1558
1559         gic_v3_kvm_info.type = GIC_V3;
1560
1561         irq = acpi_register_gsi(NULL, acpi_data.maint_irq,
1562                                 acpi_data.maint_irq_mode,
1563                                 ACPI_ACTIVE_HIGH);
1564         if (irq <= 0)
1565                 return;
1566
1567         gic_v3_kvm_info.maint_irq = irq;
1568
1569         if (acpi_data.vcpu_base) {
1570                 struct resource *vcpu = &gic_v3_kvm_info.vcpu;
1571
1572                 vcpu->flags = IORESOURCE_MEM;
1573                 vcpu->start = acpi_data.vcpu_base;
1574                 vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1;
1575         }
1576
1577         gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis;
1578         gic_set_kvm_info(&gic_v3_kvm_info);
1579 }
1580
1581 static int __init
1582 gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end)
1583 {
1584         struct acpi_madt_generic_distributor *dist;
1585         struct fwnode_handle *domain_handle;
1586         size_t size;
1587         int i, err;
1588
1589         /* Get distributor base address */
1590         dist = (struct acpi_madt_generic_distributor *)header;
1591         acpi_data.dist_base = ioremap(dist->base_address,
1592                                       ACPI_GICV3_DIST_MEM_SIZE);
1593         if (!acpi_data.dist_base) {
1594                 pr_err("Unable to map GICD registers\n");
1595                 return -ENOMEM;
1596         }
1597
1598         err = gic_validate_dist_version(acpi_data.dist_base);
1599         if (err) {
1600                 pr_err("No distributor detected at @%p, giving up\n",
1601                        acpi_data.dist_base);
1602                 goto out_dist_unmap;
1603         }
1604
1605         size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions;
1606         acpi_data.redist_regs = kzalloc(size, GFP_KERNEL);
1607         if (!acpi_data.redist_regs) {
1608                 err = -ENOMEM;
1609                 goto out_dist_unmap;
1610         }
1611
1612         err = gic_acpi_collect_gicr_base();
1613         if (err)
1614                 goto out_redist_unmap;
1615
1616         domain_handle = irq_domain_alloc_fwnode(acpi_data.dist_base);
1617         if (!domain_handle) {
1618                 err = -ENOMEM;
1619                 goto out_redist_unmap;
1620         }
1621
1622         err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs,
1623                              acpi_data.nr_redist_regions, 0, domain_handle);
1624         if (err)
1625                 goto out_fwhandle_free;
1626
1627         acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
1628
1629         if (static_branch_likely(&supports_deactivate_key))
1630                 gic_acpi_setup_kvm_info();
1631
1632         return 0;
1633
1634 out_fwhandle_free:
1635         irq_domain_free_fwnode(domain_handle);
1636 out_redist_unmap:
1637         for (i = 0; i < acpi_data.nr_redist_regions; i++)
1638                 if (acpi_data.redist_regs[i].redist_base)
1639                         iounmap(acpi_data.redist_regs[i].redist_base);
1640         kfree(acpi_data.redist_regs);
1641 out_dist_unmap:
1642         iounmap(acpi_data.dist_base);
1643         return err;
1644 }
1645 IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1646                      acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3,
1647                      gic_acpi_init);
1648 IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1649                      acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4,
1650                      gic_acpi_init);
1651 IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1652                      acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE,
1653                      gic_acpi_init);
1654 #endif